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[2620:137:e000::1:20]) by mx.google.com with ESMTP id eb2-20020a056a004c8200b006870f6fd899si48191pfb.166.2023.08.09.14.05.08; Wed, 09 Aug 2023 14:05:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kFe8H2xU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231960AbjHITrH (ORCPT + 99 others); Wed, 9 Aug 2023 15:47:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229488AbjHITrG (ORCPT ); Wed, 9 Aug 2023 15:47:06 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D13AF10DC; Wed, 9 Aug 2023 12:47:05 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379Jkvc9082645; Wed, 9 Aug 2023 14:46:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610417; bh=lYYkJgSjotdn9z630Q0bdw52E8CRoYe6AJCa/q+uOtg=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=kFe8H2xU/CfP87buBNNpE3+4M4y7LYnDUWDU50TE3MvwJ2Aa3z0u9blC5f9S3TLZB BxcHbKn8VWtkN5WvDDElqeDr1ubcsPlnl8wYDTImGdzbjQ8yogjyZz60BHS96Oipxg jvgI3vTyabatY3DT1RksSrrBFBylgsSlT5WqUSWo= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379JkvmN024692 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:46:57 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:46:57 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:46:56 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379JkuWW022680; Wed, 9 Aug 2023 14:46:56 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:19 +0530 Subject: [PATCH v6 1/7] arm64: dts: ti: k3-j7200-som-p0: Add TP6594 family PMICs MIME-Version: 1.0 Message-ID: <20230810-tps6594-v6-1-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5070; i=j-luthra@ti.com; h=from:subject:message-id; bh=x9uvfuO+UnW37axEg5ZLexDGBu/GJiHMCE5eHVtsQg8=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0tdVUGbjwsXBezXNhpVIJyqTtI5r6DrqO1c IEyEznoOquJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtLQAKCRBD3pH5JJpx RaioEAChIIHejBkgMxWkKccAuoWGM24wQMfDwj+9QOMpr0EcWvCxZi7qtrmDchYkGfgk8zFXwMq 8HEvBN+KDWzTfv7Y9ltzKjT4qmrc2iakEN7yDUCH9GWbqZMWPfFaqDS4/374+cy0IdMXJoByhEf C1BvxgfwefL5AYMOcZ9ly23isLxa95YuhY5HGP8npqCwz328QsEo0h6oJTGE7bfCM5nLnbGyQKC UGwW8BX27uB7G5ijhky7dvYcPwLPBRXJrceZDIGka6w3bU3hv4mRyDWxO9OGsWGp4bf1Bd3U+/E IeglY43xgd4TxHi1ncXVoQvODnGXzj10f/3CfYo0ITsM6MZI51diOZpUNfyeVsbxTuyW6tRYYYG aqTXJsDn+7BCUjNxr98eGl28eX0C19kkP4BlZGU/gB5/+5Tab3gOOjI7Yaq2Xwotgc/Ud6FB7Rf EVqb5gm2DEuOb4u+fEbpbEIBb05cxeWCdJjiFaaW4XFPu0m63pjuCIxKaeqzvU45IibXzR8uPZG etmj5DZ4AhiiBA9/uAT59A+vAEx6XEHI/+bE0pVP/VWdmAF12so8RyhI8rDeJr26GAVeRb/i7Nk 5RBy6bWolBxkzhjBz/1ixVGNWbRXocI0DSbOJtg3nR/+5AhwIL7KXThQDVbIMKTFogV4HfnSWe9 Pf+hUzHg/+6USRA== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773787024877984672 X-GMAIL-MSGID: 1773787024877984672 From: Esteban Blanc This patch adds support for TPS6594 PMIC family on wakup I2C0 bus. Theses devices provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 157 ++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index b37f4f88ece4..51ed611585dd 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -127,6 +127,14 @@ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ }; }; +&wkup_pmx3 { + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < @@ -264,6 +272,155 @@ eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; }; + + tps659414: pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + ti,primary-pmic; + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <84 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1-supply = <&vsys_3v3>; + buck2-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + bucka1: buck1 { + regulator-name = "vda_mcu_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka2: buck2 { + regulator-name = "vdd_mcuio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name = "vdd_mcu_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name = "vdd_ddr_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name = "vdd_phyio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name = "vdd1_lpddr4_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name = "vda_dll_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name = "vdd_wk_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name = "vda_pll_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + lp876441: pmic@4c { + compatible = "ti,lp8764-q1"; + reg = <0x4c>; + system-power-controller; + interrupt-parent = <&wkup_gpio0>; + interrupts = <84 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1-supply = <&vsys_3v3>; + buck2-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + + regulators: regulators { + buckb1: buck1 { + regulator-name = "vdd_cpu_avs"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + buckb2: buck2 { + regulator-name = "vdd_ram_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb3: buck3 { + regulator-name = "vdd_core_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb4: buck4 { + regulator-name = "vdd_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &ospi0 { From patchwork Wed Aug 9 19:46:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 133573 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp37027vqi; Wed, 9 Aug 2023 15:09:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH1y+UXEhIKp8P/3M1Lercq64fJUV0GgA+MYAhHhxaVhAdiyZVSvOt4V5p09u9lNPJho+XM X-Received: by 2002:a17:902:ea02:b0:1bc:e6a:205f with SMTP id s2-20020a170902ea0200b001bc0e6a205fmr484537plg.20.1691618976402; Wed, 09 Aug 2023 15:09:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691618976; cv=none; d=google.com; s=arc-20160816; b=rlSEsiFBZWnYEQ5R8rr1qygJzqbdSLWjDHGpxeU9/SwP1k5ZXcCCFUD+a4Q1wUKX/T nUFkk7WFNKa9zIY+PbZHTyQqWE6nJ3klcVOR4Uybr2Rr+e0Dd3NaJwImRIdUIRAd+aXB Gh5teTfbtfzMpJPj3tDBKZgFzmS5mlmBrnkoF7sVFwEJbCMR0mLiynojVgLjkRua5l/z Jt5ztc2pxVCyBjesZWtRfbkmlDfesh66I81XBwKeNiNnWtUj9LxhbhF8rFnCjIoD6Qkz 5qkA7+xMyP+WVT3O/i4bS82wLrECs65ph0tmx4TvRqJ2xIvEzEMUJc1/84Ohzkj4+Il0 jW4g== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g2-20020a170902e38200b001badbe8e441si71352ple.106.2023.08.09.15.09.22; Wed, 09 Aug 2023 15:09:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=b3MSMF8k; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232882AbjHITrM (ORCPT + 99 others); Wed, 9 Aug 2023 15:47:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229488AbjHITrJ (ORCPT ); Wed, 9 Aug 2023 15:47:09 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42C5310E0; Wed, 9 Aug 2023 12:47:08 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379JkwDl011908; Wed, 9 Aug 2023 14:46:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610418; bh=QC3zGGEWVNPoOuYVH11z0Jd/+0lyJRPhg2I9vTAORm8=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=b3MSMF8kleyxZiPo9x4GlsafrHwkfd3+Ufnq2KlJVTo0e3/ptrHmsJZJCmLAy5xr+ AFEwThDyiTGWusgCkePrn/OLZGoSwtGvxODolpo3qvDF2sT7A5cajvst60KOlRP78r euwSBhALriXuVNZ0ytgT8JVPSsYiJynj4Eu8Be8M= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379JkwAN069548 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:46:58 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:46:58 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:46:58 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Jkv07065120; Wed, 9 Aug 2023 14:46:58 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:20 +0530 Subject: [PATCH v6 2/7] arm64: dts: ti: k3-j721s2-som-p0: Add TP6594 family PMICs MIME-Version: 1.0 Message-ID: <20230810-tps6594-v6-2-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6089; i=j-luthra@ti.com; h=from:subject:message-id; bh=ZnNtOITeK/mZkX9caV/brC8y6tgnxXhJkwV81yr7UOo=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0uouykMJFVfP7JnxFf6LHA3DNgJF1YHL26d /GNoBnC6eCJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtLgAKCRBD3pH5JJpx RYSRD/0QujTd4dY/I/4Z+ijtm8V9WtGHHYsZvFsdsVzY7OFBHWhvFHWuD9OLwQet2htwtSyrDSm +R32resE1MY7gPWh/76YISVxS0clCQY6SrzvQX7cgR56LjOLgO2XfWewjiLbHlKNnc9ZfT2EUuo NmAPKFFLx/XcUniTmV7zuagFNXcMGl6gDeH5bbxpqWtOss+DBkWq3+W+BR3IW62A45selJeTTtH z21xwRghPhikLt7V9aSRH7f2Gn/vd5uCtjXA6Sj5WJU60s6i/sl8jE09nAdrOMMql9V8aIxCpfo 92LD8GeUokWtayWllkTzzwL4vgSi7h8jHHlQUW9zqN2lav++juugEC/GNvfsB3RU2T2iiIufZVb bx8ms4Y8fEyneLUObq2jkujoBQeZtv6kZP0VWpqYpOzueMsIpr9d7Wy6F21kCI0kMghuos0ioli hWxIx1ETgAXBl2eHoca5JoSfSO2ltVTGpquWtaWLcDLPhpdYSDF4Q2/bZEwMpAuozeAZyo2eYbx QZTrx4kY466whuN12u4LabjY3R7u5GvCycqQgv2b7shOozwmK6lF0952ZllxF20bfWWUwMbkM2K owEZwBzfWTJ7g8U+x0ZoJRpZP9r1+0J+mSgnw73PxKV/KFfD1uxYJLahkVJ8VnT+/GjAg4xMXrf 3FxmnU0iSuTyTng== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773791060135272508 X-GMAIL-MSGID: 1773791060135272508 From: Esteban Blanc This patch adds support for TPS6594 PMIC family on wakup I2C0 bus. Theses devices provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 199 +++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index a4006f328027..94b6162aba21 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -70,6 +70,15 @@ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ }; }; +&wkup_pmx1 { + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7) + >; + }; +}; + &wkup_pmx2 { wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < @@ -106,6 +115,196 @@ eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; }; + + tps659411: pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + ti,primary-pmic; + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1234-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + bucka1234: buck1234 { + regulator-name = "vdd_cpu_avs"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name = "vdd_mcu_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name = "vdd_mcuwk_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name = "vdd_mcu_gpioret_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name = "vdd_mcuio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name = "vda_mcu_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659414: pmic@4c { + compatible = "ti,tps6594-q1"; + reg = <0x4c>; + system-power-controller; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1-supply = <&vsys_3v3>; + buck2-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + buckb1: buck1 { + regulator-name = "vdd_io_1v8_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buckb2: buck2 { + regulator-name = "vdd_fpd_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb3: buck3 { + regulator-name = "vdd_phy_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb4: buck4 { + regulator-name = "vdd_ddr_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb5: buck5 { + regulator-name = "vdd_ram_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob1: ldo1 { + regulator-name = "vdd_wk_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob2: ldo2 { + regulator-name = "vdd_gpioret_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob3: ldo3 { + regulator-name = "vda_dll_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob4: ldo4 { + regulator-name = "vda_pll_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + lp876411: pmic@58 { + compatible = "ti,lp8764-q1"; + reg = <0x58>; + system-power-controller; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1234-supply = <&vsys_3v3>; + + regulators { + buckc1234: buck1234 { + regulator-name = "vdd_core_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &main_i2c0 { From patchwork Wed Aug 9 19:46:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 133478 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp3050053vqr; Wed, 9 Aug 2023 13:17:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGNLFLcIqdtx2kz0uxC6jxtEq9GgEMLr/S15ILjY9ZMs3S+R9kcxZmL1EX8zi3db0cxgPZE X-Received: by 2002:a05:6a20:428f:b0:13a:8082:5324 with SMTP id o15-20020a056a20428f00b0013a80825324mr311014pzj.44.1691612251523; Wed, 09 Aug 2023 13:17:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691612251; cv=none; d=google.com; s=arc-20160816; b=Ufq1sFcX5xkHtfNMyuny1Wah4PT73OYRH2VIPyl/YMMzK3ZmMATowHaUUSQfYMenGR POdwHcWS7NmFJA9wAiYCYy3LpSRUzqoso+8SNmbJ5Nt0k3ObT9vO0xoZqE+8ykRNnP3W 40FUz5PJ+bm38CCotHeb7VIdzW01H+gEoNPFPHKng8b5ZNgzLEPAYDx8zIy0rsMYNi2e aYODxqQ1r50BePvMKxPPZeA1XmfMAwI1SpB15AM8xQxXDim0EWkJQRWhX/lC+pem3AFd R7ETayyIh/WQJqvQvMDdnjasRqdoRXJBeyxyqxwTycCOSi43Bnn0ohMvk5r4WQzlnoE/ ddVA== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l73-20020a63914c000000b00564c67e66f3si8568618pge.467.2023.08.09.13.17.16; Wed, 09 Aug 2023 13:17:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TEjpWaFQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234080AbjHITrW (ORCPT + 99 others); Wed, 9 Aug 2023 15:47:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232461AbjHITrL (ORCPT ); Wed, 9 Aug 2023 15:47:11 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E472A2100; Wed, 9 Aug 2023 12:47:09 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl1JI011922; Wed, 9 Aug 2023 14:47:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610421; bh=7088h8X7s0covVaq45Tpol1RjrF9Tnavd64QUD8UpnQ=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=TEjpWaFQrQDHtJ/a+N6Q3htNwX4ZUVxNHWftq0MPG4AcAAGbuuczRBJt0P09TeN30 IPQxhvK+OZCJbbqwXzVz06h3pBbJJsZPp7g4LuoMefyvKyjzxLlcL5blJ9nZ1IMNYf Q4m/nBqPL7kBknpDEVERMZv2iXF7QjDKKe82MZJM= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379Jl1ia032227 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:47:01 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:46:59 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:46:59 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Jkx9J050920; Wed, 9 Aug 2023 14:46:59 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:21 +0530 Subject: [PATCH v6 3/7] arm64: dts: ti: k3-j721e-som-p0: Add TP6594 family PMICs MIME-Version: 1.0 Message-ID: <20230810-tps6594-v6-3-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5390; i=j-luthra@ti.com; h=from:subject:message-id; bh=6ytm+I/61w+Cti00xxMFIg2KdbZYmvKL4QcyqU6u35s=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0vpEUVKqyXFl2Ea8bz6sTNT1Kz5fbmxUbCM C3z7jHenmCJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtLwAKCRBD3pH5JJpx RaSpD/9ZW1fJczTYS5slQX7xSU/hkE138uYPvBkYfK9pODSx1NJDhXSx9dwrIyLJyuH+A3Lq1yl J1yt+Qb/7MvZ0imJ8p+owZydQBHvfDSHYzyvO+AKNwFrr8sqKJT51MW+lXWuaXBDNTMROeNCo0z cQRN+Zgc7wZIr+IQakqdZKk8Osa6hVY9c+eGw2EyFVV/MT5f3uw5Wm5Dx0vt79RN+sLYKsXenix Fj1ASxuECIFgGp0Q04RPuaN/tEaxb4MXUF7e6aB1ETg/Uomi8MYZvJGA3LDao0rTOjh1So6dfnm m6aZvZrZ3hj3JMO7N8O6t2J7e+5nHuvYvoIhXefvNW7IG0fmKtcf48XdS/AHmh4x3kBKzNMPNDd zs6qnlxhMx2rRf5zKK1NEzxH7faVEU5iPeMirKhlrnEUeWoCu1Tl5FXKV4+yifGpTM0l7XP60pp PuIQssf8rf3FShSPRBC9FKgMHwm0qdln+y85Z36fjmavPZacF2ipWEiwBYPS9//mJ1u0vSAYUWD BTzvULDt/ENg8Zr38BBbV93VbCH1bsMEjqZJJZ/+fggqtluzDX0OUpkcrbtjnkqJramigmY/25o wyhcpUh+AI/GraeGo/hC+jEqasKilo3jY9yOI5zFzJqndbLDqctm61+KXXE8iooNBJ7vXjUxr/R s6uFz2kUA0Yycpw== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773784008223512639 X-GMAIL-MSGID: 1773784008223512639 From: Jerome Neanne This patch adds support for TPS6594 PMIC family on wakup I2C0 bus. Theses devices provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Jerome Neanne Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 163 ++++++++++++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index e90e43202546..21f350cd9a45 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -152,6 +152,12 @@ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; }; + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0d4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */ + >; + }; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ @@ -199,6 +205,163 @@ eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; }; + + tps659413: pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + system-power-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells = <2>; + + buck12-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + bucka12: buck12 { + regulator-name = "vdd_cpu_avs"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name = "vdd_mcu_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name = "vdd_ddr_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name = "vdd_phyio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name = "vdd1_lpddr4_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name = "vdd_mcuio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name = "vdda_dll_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name = "vda_mcu_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659411: pmic@4c { + compatible = "ti,tps6594-q1"; + reg = <0x4c>; + system-power-controller; + interrupt-parent = <&wkup_gpio0>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1234-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + buckb1234: buck1234 { + regulator-name = "vdd_core_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb5: buck5 { + regulator-name = "vdd_ram_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob1: ldo1 { + regulator-name = "vdd_sd_dv"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob2: ldo2 { + regulator-name = "vdd_usb_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob3: ldo3 { + regulator-name = "vdd_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob4: ldo4 { + regulator-name = "vda_pll_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &ospi0 { From patchwork Wed Aug 9 19:46:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 133477 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp3049963vqr; Wed, 9 Aug 2023 13:17:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFFNL+DYUPWvFSgXi2/IPGNgUa0HlNAJpG55cXio3wFJMhQvGuxISlDgS5wG8a8yLLGvBnC X-Received: by 2002:a17:906:1099:b0:992:7295:61c9 with SMTP id u25-20020a170906109900b00992729561c9mr125503eju.69.1691612240500; Wed, 09 Aug 2023 13:17:20 -0700 (PDT) ARC-Seal: i=1; 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They were wrongly subtracted by 32 instead of following what is defined in the interrupt map in the TRM (Table 9-35). Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Link: https://www.ti.com/lit/ug/spruj52c/spruj52c.pdf Signed-off-by: Apelete Seketeli Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index a04c44708a09..013cf4ed98d8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -60,7 +60,7 @@ main_gpio_intr: interrupt-controller@a00000 { #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <10>; - ti,interrupt-ranges = <8 360 56>; + ti,interrupt-ranges = <8 392 56>; }; main_pmx0: pinctrl@11c000 { diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 740ee794d7b9..77a45f97e28b 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -107,7 +107,7 @@ wkup_gpio_intr: interrupt-controller@42200000 { #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <177>; - ti,interrupt-ranges = <16 928 16>; + ti,interrupt-ranges = <16 960 16>; }; /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ From patchwork Wed Aug 9 19:46:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 133501 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c765:0:b0:3f4:cb6f:45e2 with SMTP id a5csp112505vqu; Wed, 9 Aug 2023 13:44:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGE4XA7c45c//iTku617aBvugZmKkJT3JbDEIdheaFSSxcu51DuGJy1hQbwMVy+HLl5NFFD X-Received: by 2002:a05:6512:3d10:b0:4fb:9f24:bba9 with SMTP id d16-20020a0565123d1000b004fb9f24bba9mr236329lfv.5.1691613892468; Wed, 09 Aug 2023 13:44:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691613892; cv=none; d=google.com; s=arc-20160816; b=Ys6KFou2jiwrl/rjPgKANWvtgIgBjfqbQLfAoiDrnceQHEM114fcLAjpaQ5v5x+W// jIkO0YPuRCojCHDgV6zyBrcT/AOHimcVh1ObZGsmEbswe72Ty2Ro73l+sXFEM1EW46/h PN20w/1n5eAATWzg+QXxzrtspeBUloloA+BZvKZ9UCHfmCfDaDA6hC6tD8aD59H4rXNX 3sPV8CgeV9nUtlw7ySIX7dE+Ndn3hdSZGf2DxOikIQ2IjHOwFBU07XaI75gszOVQtwhU Igqp6jL5SW1iHRCPhfctakyloGNI5zrFETnPZardv0YfTLKvDf8MqLXIm3vQo/OAQe0L jA1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=6fIXIj7qWgkDWfpcBuKTTLH04m4gxyfxt/eZ75zcXrg=; fh=azp+WGX+92SugFe9HzGt4ECXpRy91zQVaDA8YXQu8MY=; b=VBH9ucPzb0RLZyQhc7eKVhBhn+fdZZ5tJM+szqYH9b+iF5kEL5Upw96VQ79SkJ4mGP InsSIhuktw0RmONaLJGI4D7DLEorvGRsjMIwZInxZE2u2ETd+2YsGWT3EyJR5xfwbhBe wWjWCGFT4EuTWWWrTW7DYqTtMa7cqeCmY7sGM3TAjMZstD0DIjCTEH1flqW0APg5P6gw fkP1CVi9pKw+BYJBg0faaxCNZ0jlwbz2Nsi+pZJpvmL+idY3SHQEFh+mFYOhjSUc+llu KqqApsG0+r6Nmb0sY9cI1oGjsBVutJESTUERt0ujmdDMtGoBhOjdmJ0ZtbqzlWO8clpD sHIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=x6slZVut; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w24-20020aa7dcd8000000b005234af90321si2749841edu.665.2023.08.09.13.44.29; Wed, 09 Aug 2023 13:44:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=x6slZVut; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233273AbjHITrR (ORCPT + 99 others); Wed, 9 Aug 2023 15:47:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232296AbjHITrL (ORCPT ); Wed, 9 Aug 2023 15:47:11 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF9442103; Wed, 9 Aug 2023 12:47:09 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl3Vi086091; Wed, 9 Aug 2023 14:47:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610423; bh=6fIXIj7qWgkDWfpcBuKTTLH04m4gxyfxt/eZ75zcXrg=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=x6slZVut+O71P8sAAzHLLSRiOlpyzUCUCsDhStBOs6IZCUFIo2xphTs9OFJaZgRPl OrKSk+5tPEaZj/h9nRUHu620hsDSSZSAhh7r7yjeikl2aoC1iWVEDRE1PeBN/EhmgW xOTGoa5ALVBQDTXZlgquvmO9S3xPEMTxlG3XP9ck= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379Jl2UJ039608 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:47:02 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:47:02 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:47:02 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl1GB051008; Wed, 9 Aug 2023 14:47:02 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:23 +0530 Subject: [PATCH v6 5/7] arm64: dts: ti: k3-j784s4-evm: Add support for TPS6594 PMIC MIME-Version: 1.0 Message-ID: <20230810-tps6594-v6-5-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3881; i=j-luthra@ti.com; h=from:subject:message-id; bh=RMpsPB4XdwxaSFr7ajZF4M8Jg1mgkdClDXv9BHS97K0=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0yI0b0V64Pkg7YYv/gAU0gb8IRHMFa0mWxX KjoqPLaiwmJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtMgAKCRBD3pH5JJpx RSpoEACJTY929b3uE2+v6J/JZe+VgZ2SHWYi/QYDjqXUFiXmQn3hJ/c+WDtk+F3x6hQXpfUFnOH 4x+9JYMZSCii+pQIhuk9VJykEaZXrS3Hshxl/1hSOU/gEdUuUR50W6rwbWJqJh2LV24VbW3ALw9 bsOwmGvmHjUS2HgyCye+O+54V2weUAK6t7HdZrpYq8BOA+e9HBWxnxUBBhtrCAnXZCyVcpYYm8q mcO/qo01AAhEb82kYu3kfoNej524uL+h71TNFF36cHOJX2ncK3wMkl09zuf8APgFUJer5OZEDEH 1yBlvInzYDLN8S736EIEKsEyyq+TxddKsOgXmMcFp8vzMYKdRJpyuUz1gq8hCbxCpWrsfhSURgo Lvlaed8/odknKnlZ8RaHRqitFdckXoQV65n74yNEWFmuomaylvMdYQRqflD4D2qZKIvvpavkbBw w3lNZGSuO+8UwLmFucSka6BMUZWZEUSywt9mye1E8AXrsaLqhzrvJr5FxAms7/WZV5twlM/nIWi AkJrbTQf/r0EYCU3TcYHhAENLG+8Uq6ON2XMZLvpFYpHVRITx34kiLUDtv0sIUXV+kRlEPB6n3M MRtdPAm29Sr8QqOyhiO3AEr1CzRej4iVYFDFe5o0rhDb7pYp6YyvIw/KdQsAP8woS/gmQc0Emwg PapBPTnmjNlvTIw== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773785728718888080 X-GMAIL-MSGID: 1773785728718888080 From: Jerome Neanne This patch adds support for TPS6593 PMIC on wkup I2C0 bus. This device provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Jerome Neanne Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 104 +++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index edc1009b2d1e..29202ef40f78 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -251,6 +251,10 @@ vdd_sd_dv: regulator-TLV71033 { }; }; +&wkup_gpio0 { + status = "okay"; +}; + &main_pmx0 { main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < @@ -365,6 +369,17 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ }; }; +&wkup_pmx1 { + status = "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) + >; + }; +}; + &wkup_pmx0 { mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < @@ -423,6 +438,95 @@ eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; }; + + tps659413: pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + system-power-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells = <2>; + + buck12-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + bucka12: buck12 { + regulator-name = "vdd_ddr_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name = "vdd_ram_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name = "vdd_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name = "vdd_mcu_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name = "vdd_mcuio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name = "vdd_mcuio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name = "vds_dll_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name = "vda_mcu_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &mcu_uart0 { From patchwork Wed Aug 9 19:46:24 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f13-20020a170902684d00b001b3f9cedbb7si10287626pln.398.2023.08.09.13.17.42; Wed, 09 Aug 2023 13:17:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BmvMDoMb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233523AbjHITr0 (ORCPT + 99 others); Wed, 9 Aug 2023 15:47:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232704AbjHITrL (ORCPT ); Wed, 9 Aug 2023 15:47:11 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E937F2108; Wed, 9 Aug 2023 12:47:10 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl4MH086096; Wed, 9 Aug 2023 14:47:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610424; bh=VB+r5z/W4Lii6r8oAhIOL+FU2R1kBLQG0ya0jHBEvqo=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=BmvMDoMbrm7T9OErrushRI3WeMZeOgH0a3zUU5lA4FPVpR+e3rNoRmW2LZgVCEKFC OegnVm7XhU4tkAImP0n49/6Ug3bVdMZ6X8+w/aCdT29TPDi0s96ZMTJgKmwTpQQy48 JCMg55Mhvsj9jlkbasZu4U4KqtgJJjS6KdSlMSnI= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379Jl4uH032322 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:47:04 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:47:04 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:47:04 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl3wV065302; Wed, 9 Aug 2023 14:47:03 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:24 +0530 Subject: [PATCH v6 6/7] arm64: dts: ti: k3-am62a7-sk: Add support for TPS6593 PMIC MIME-Version: 1.0 Message-ID: <20230810-tps6594-v6-6-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3367; i=j-luthra@ti.com; h=from:subject:message-id; bh=9kPfYgmoW8UezAiz/SVq0i+GIR4xFjfYwAcDxuvSWTU=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0zYKTlEL1CDDWVt0zWsjeYIJkHGG61cjbVk WOGlAIYYaqJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtMwAKCRBD3pH5JJpx RVDdD/4u78YxoHpO5m6eZLEcHcxXzM7zNsPVhuQ6Gq9s15G+AdEGIsGlnLmuydruGPoXKIMAf00 iwX17TVzzymQVw8ij/3cyObRdpSa1c6hDkGp573PYpN0LP0jJu4EIRG8gTg4G5qH/IPuR9fmvv7 6zfr5N3fj2u5IzwTjh1TcWYxmuW5c+lP7jUasNbPgnf1Bmshp7wAq/Y7U7QapvA+rdzIvn4NdU1 yxT4QzGX+anYKczLIDaDMU70vw5ZJU43Zfi0+p7nwQmQWqrMCM77q4EAEoXqONXpQVm5OYFfzth 471LauanBulhmp0TNVYNkHV4npBZWhIScsm/TyAWcvjNU6IeHFs7vvSeu5s4zGwc1WQy8fw5GqT wy13ypP1kTL07mlU/6aKaeq9P3YD3sJPqjXiPbaZEPVMXIkj34ghXHH5m4vjIqX4gzUfBX2mcZC KXJBbzXovfDDZ3FYR6xyVWKwBtAnRVbIc9ZVnJ+D4mfpl77nHs8fbdy+lDBjAojztQGSDOgtXsl 5dOM5s7LKqWbbPZ3yKIptEZPKRD3Sx7/Cy/TwS53IwjTRGLhxOEfUM21dfxurqP5Y5VOMahB+ut 7LEzpbnA+JgPDvnJX/qLZMYd0QdLZyiSWaLnZ+nZCiQLL+KsXwkEYXcs9zNBlQTajaxCVdmTsp6 F9+VaX22ys/R3Pw== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773784033618925504 X-GMAIL-MSGID: 1773784033618925504 From: Julien Panis This patch adds support for TPS6593 PMIC on main I2C0 bus. This device provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Julien Panis Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 95 +++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index cff283c75f8e..2616acab8c0e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -221,6 +221,20 @@ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */ }; }; +&mcu_pmx0 { + status = "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */ + >; + }; +}; + +&mcu_gpio0 { + status = "okay"; +}; + &main_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -244,6 +258,87 @@ usb_con_hs: endpoint { }; }; }; + + tps659312: pmic@48 { + compatible = "ti,tps6593-q1"; + reg = <0x48>; + ti,primary-pmic; + system-power-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&mcu_gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + buck123-supply = <&vcc_3v3_sys>; + buck4-supply = <&vcc_3v3_sys>; + buck5-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&vcc_3v3_sys>; + ldo3-supply = <&buck5>; + ldo4-supply = <&vcc_3v3_sys>; + + regulators { + buck123: buck123 { + regulator-name = "vcc_core"; + regulator-min-microvolt = <715000>; + regulator-max-microvolt = <895000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: buck4 { + regulator-name = "vcc_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: buck5 { + regulator-name = "vcc_1v8_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: ldo1 { + regulator-name = "vddshv5_sdio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: ldo2 { + regulator-name = "vpp_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: ldo3 { + regulator-name = "vcc_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: ldo4 { + regulator-name = "vdda_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &main_i2c1 { From patchwork Wed Aug 9 19:46:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 133555 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp30089vqi; Wed, 9 Aug 2023 14:58:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHMO3IXogAfG2cpV6qIsol2amrXfI2Rx4RIXpjfwrjyDZJcRkcktqLMKjK/i1jtf/5Gpdfr X-Received: by 2002:a05:6512:3da5:b0:4f8:46e9:9f19 with SMTP id k37-20020a0565123da500b004f846e99f19mr334760lfv.1.1691618293357; Wed, 09 Aug 2023 14:58:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691618293; cv=none; d=google.com; s=arc-20160816; b=aa3dEwh2t53o1iFc8N1sj9aRpo1k9tGjo0hnlIt/4/VtCd5e1mEP9IEBQVelkTqqUy TYC+cCLUvKU6H3iFyjoO1La0zOtBPUqu2A47IYLCEaIJaVHV1Kv1oFFXZyTFDMOmxNMa XDZNqYCXr4hKXhvrrXCr9J2/i7QWKUKXOY2LqEL/At0kl0E3RjB8lmnmDIBsl0MYwNx7 Nwvl92B6rMpG9wBl4+BKdfV8PYjCR5OUfGTr8n9hMRFLpAmWJS5s4tSFho1Lqd/3soAb AwT6YEcn6cHuwsPnWjIi9vupuR25gZErie1Et4TZhHXNs8AGLqpsVFQGALNJULINCJ8Z K/yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=FbAbSqwRAV98u35zcv0xFNhxf2gVaiT10GEUTg0GYws=; fh=2m71AqWQBGbyQgTlwktGM4LK6OYAmMqLznrImjn3cEc=; b=MhB4V0O7YgxO+iNoETW+uPPGw8MS0SOx399vX7ULE8PL3XH+dkNoNcAQIevo45ih0m tgBEAKiU7RCbUKm9YDuOxntOBSW6Wqo1NfLucP2W1kAPm1wjWPeX2jf+vaHcU5ardG83 fg6VfW/OZK2t803Jo76XRqS2XwEwiqM9WX3XvZxgnkRf3+1C0Ba0r4q3N6w2Oh3IdMoW +Ec2pZpEY+70WFqZuKWEkEeeku+Ota0rlhckyWVQbHxTtoqYywrwTEvRQlsak1rgNEJS pAG8Ok7Jg//JVjawZL9ym/mmwujbZTGF9uKkVYvGVIvItPgNDzLl9+OETHhcWlrfGj+W wFng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZovuTH6T; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Specifically, the audio codec (TLV320AIC3106) on the board relies on the PMIC for the DVDD (1.8V) supply. [1]: https://www.ti.com/lit/zip/sprr459 Reviewed-by: Devarsh Thakkar Signed-off-by: Jai Luthra --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index bf13d5c46578..9f7697caa5ca 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -719,6 +719,7 @@ CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SL28CPLD=y CONFIG_RZ_MTU3=y CONFIG_MFD_TPS65219=y +CONFIG_MFD_TPS6594_I2C=m CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_ROHM_BD718XX=y CONFIG_MFD_WCD934X=m