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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id p18-20020a170906499200b00991dfb5dfb7si7867976eju.573.2023.08.08.18.48.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 18:48:45 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Vued2M38; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0EA9E3858D20 for ; Wed, 9 Aug 2023 01:48:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0EA9E3858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691545724; bh=RD1RkFhmjZJCALHqZHknqoL7xk9qAFVYb3OzGZRKbJw=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=Vued2M38CnZkt9k/d7GuSqpt3dgbNFnHAKu4iLaM/AEwmPfTvIUf31Uus42xjk3hl jflj0WVCSs71HRAAcCYq60rhEdJP5bSLU6SXrfq3iqNPk6DSCXDJqlcIKLXx+e+SAk O2AzVYA6DhxBdwu5O6J14b3MAmtQ23BkcgjXXpfk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 8CBF23858D20 for ; Wed, 9 Aug 2023 01:48:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8CBF23858D20 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374706154" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374706154" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:47:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845738606" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845738606" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:47:57 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5379B1007BC7; Wed, 9 Aug 2023 09:47:56 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com Subject: [PATCH V2] [X86] Workaround possible CPUID bug in Sandy Bridge. Date: Wed, 9 Aug 2023 09:47:56 +0800 Message-Id: <20230809014756.19615-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773646935467721510 X-GMAIL-MSGID: 1773714250488222498 > Please rather do it in a more self-descriptive way, as proposed in the > attached patch. You won't need a comment then. > Adjusted in V2 patch. Don't access leaf 7 subleaf 1 unless subleaf 0 says it is supported via EAX. Intel documentation says invalid subleaves return 0. We had been relying on that behavior instead of checking the max sublef number. It appears that some Sandy Bridge CPUs return at least the subleaf 0 EDX value for subleaf 1. Best guess is that this is a bug in a microcode patch since all of the bits we're seeing set in EDX were introduced after Sandy Bridge was originally released. This is causing avxvnniint16 to be incorrectly enabled with -march=native on these CPUs. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Check EAX for valid subleaf before use CPUID. --- gcc/common/config/i386/cpuinfo.h | 82 +++++++++++++++++--------------- 1 file changed, 43 insertions(+), 39 deletions(-) diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 30ef0d334ca..9fa4dec2a7e 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -663,6 +663,7 @@ get_available_features (struct __processor_model *cpu_model, unsigned int max_cpuid_level = cpu_model2->__cpu_max_level; unsigned int eax, ebx; unsigned int ext_level; + unsigned int subleaf_level; /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */ #define XCR_XFEATURE_ENABLED_MASK 0x0 @@ -762,7 +763,7 @@ get_available_features (struct __processor_model *cpu_model, /* Get Advanced Features at level 7 (eax = 7, ecx = 0/1). */ if (max_cpuid_level >= 7) { - __cpuid_count (7, 0, eax, ebx, ecx, edx); + __cpuid_count (7, 0, subleaf_level, ebx, ecx, edx); if (ebx & bit_BMI) set_feature (FEATURE_BMI); if (ebx & bit_SGX) @@ -874,45 +875,48 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_AVX512FP16); } - __cpuid_count (7, 1, eax, ebx, ecx, edx); - if (eax & bit_HRESET) - set_feature (FEATURE_HRESET); - if (eax & bit_CMPCCXADD) - set_feature(FEATURE_CMPCCXADD); - if (edx & bit_PREFETCHI) - set_feature (FEATURE_PREFETCHI); - if (eax & bit_RAOINT) - set_feature (FEATURE_RAOINT); - if (avx_usable) - { - if (eax & bit_AVXVNNI) - set_feature (FEATURE_AVXVNNI); - if (eax & bit_AVXIFMA) - set_feature (FEATURE_AVXIFMA); - if (edx & bit_AVXVNNIINT8) - set_feature (FEATURE_AVXVNNIINT8); - if (edx & bit_AVXNECONVERT) - set_feature (FEATURE_AVXNECONVERT); - if (edx & bit_AVXVNNIINT16) - set_feature (FEATURE_AVXVNNIINT16); - if (eax & bit_SM3) - set_feature (FEATURE_SM3); - if (eax & bit_SHA512) - set_feature (FEATURE_SHA512); - if (eax & bit_SM4) - set_feature (FEATURE_SM4); - } - if (avx512_usable) - { - if (eax & bit_AVX512BF16) - set_feature (FEATURE_AVX512BF16); - } - if (amx_usable) + if (subleaf_level >= 1) { - if (eax & bit_AMX_FP16) - set_feature (FEATURE_AMX_FP16); - if (edx & bit_AMX_COMPLEX) - set_feature (FEATURE_AMX_COMPLEX); + __cpuid_count (7, 1, eax, ebx, ecx, edx); + if (eax & bit_HRESET) + set_feature (FEATURE_HRESET); + if (eax & bit_CMPCCXADD) + set_feature(FEATURE_CMPCCXADD); + if (edx & bit_PREFETCHI) + set_feature (FEATURE_PREFETCHI); + if (eax & bit_RAOINT) + set_feature (FEATURE_RAOINT); + if (avx_usable) + { + if (eax & bit_AVXVNNI) + set_feature (FEATURE_AVXVNNI); + if (eax & bit_AVXIFMA) + set_feature (FEATURE_AVXIFMA); + if (edx & bit_AVXVNNIINT8) + set_feature (FEATURE_AVXVNNIINT8); + if (edx & bit_AVXNECONVERT) + set_feature (FEATURE_AVXNECONVERT); + if (edx & bit_AVXVNNIINT16) + set_feature (FEATURE_AVXVNNIINT16); + if (eax & bit_SM3) + set_feature (FEATURE_SM3); + if (eax & bit_SHA512) + set_feature (FEATURE_SHA512); + if (eax & bit_SM4) + set_feature (FEATURE_SM4); + } + if (avx512_usable) + { + if (eax & bit_AVX512BF16) + set_feature (FEATURE_AVX512BF16); + } + if (amx_usable) + { + if (eax & bit_AMX_FP16) + set_feature (FEATURE_AMX_FP16); + if (edx & bit_AMX_COMPLEX) + set_feature (FEATURE_AMX_COMPLEX); + } } }