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[8.43.85.97]) by mx.google.com with ESMTPS id ke20-20020a17090798f400b0099cb159a120si5132581ejc.21.2023.08.07.21.16.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 21:16:56 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=m59qXGr6; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C22933858002 for ; Tue, 8 Aug 2023 04:16:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C22933858002 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1691468215; bh=0fNmJG8/e6G1w/Vowxdyg/Q6esgn4ZhLXCqdWgCoZ0E=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=m59qXGr6dzCsc/d8E4EIVYjvJlmwCgtE7hEJp8LCnn+TGDT4QsSIvjWNqPGxAl5iS jO9fzz3LQPEQ3nUVgQqVpX1Gr+XsnKjAqpq/HR1vy3LPE4ukZUey6f90//2zMj+kNl AfRBpUo+bJPayKOu/ZPi0zzBSlWYpifsNPlY0cz8= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 835AE3858D33 for ; Tue, 8 Aug 2023 04:16:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 835AE3858D33 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 9D0CF300089; Tue, 8 Aug 2023 04:16:44 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [PATCH] RISC-V: Prohibit combination of 'E' and 'H' Date: Tue, 8 Aug 2023 04:16:42 +0000 Message-ID: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773632976725133575 X-GMAIL-MSGID: 1773632976725133575 From: Tsukasa OI According to the ratified privileged specification (version 20211203), it says: > The hypervisor extension depends on an "I" base integer ISA with 32 x > registers (RV32I or RV64I), not RV32E, which has only 16 x registers. Also in the latest draft, it also prohibits RV64E with the 'H' extension. This commit prohibits the combination of 'E' and 'H' extensions. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Prohibit 'E' and 'H' combinations. gas/ChangeLog: * testsuite/gas/riscv/march-fail-rv32eh.d: New failure test to make sure that RV32E + 'H' is prohibited. * testsuite/gas/riscv/march-fail-rv32eh.l: Likewise. --- bfd/elfxx-riscv.c | 7 +++++++ gas/testsuite/gas/riscv/march-fail-rv32eh.d | 3 +++ gas/testsuite/gas/riscv/march-fail-rv32eh.l | 2 ++ 3 files changed, 12 insertions(+) create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32eh.d create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32eh.l base-commit: d734d43a048b33ee12df2c06c2e782887e9715f6 diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index ee4598729480..1655bb2df364 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1949,6 +1949,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) (_("rv%d does not support the `e' extension"), xlen); no_conflict = false; } + if (riscv_subset_supports (rps, "e") + && riscv_subset_supports (rps, "h")) + { + rps->error_handler + (_("rv%de does not support the `h' extension"), xlen); + no_conflict = false; + } if (riscv_lookup_subset (rps->subset_list, "q", &subset) && (subset->major_version < 2 || (subset->major_version == 2 && subset->minor_version < 2)) diff --git a/gas/testsuite/gas/riscv/march-fail-rv32eh.d b/gas/testsuite/gas/riscv/march-fail-rv32eh.d new file mode 100644 index 000000000000..b57199efa0f6 --- /dev/null +++ b/gas/testsuite/gas/riscv/march-fail-rv32eh.d @@ -0,0 +1,3 @@ +#as: -march=rv32eh +#source: empty.s +#error_output: march-fail-rv32eh.l diff --git a/gas/testsuite/gas/riscv/march-fail-rv32eh.l b/gas/testsuite/gas/riscv/march-fail-rv32eh.l new file mode 100644 index 000000000000..c7cd1ccc2a89 --- /dev/null +++ b/gas/testsuite/gas/riscv/march-fail-rv32eh.l @@ -0,0 +1,2 @@ +.*Assembler messages: +.*Error: .*rv32e does not support the `h' extension