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[8.43.85.97]) by mx.google.com with ESMTPS id dx25-20020a170906a85900b00977e10fafd3si6977907ejb.1045.2023.08.07.21.13.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 21:13:34 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 81AB53858431 for ; Tue, 8 Aug 2023 04:13:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTPS id A073D3858D33 for ; Tue, 8 Aug 2023 04:12:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A073D3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [43.139.163.53]) by APP-05 (Coremail) with SMTP id zQCowACHj_e9wNFkcAMZAg--.3109S2; Tue, 08 Aug 2023 12:12:46 +0800 (CST) From: shiyulong@iscas.ac.cn To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, wuwei2016@iscas.ac.cn, jiawei@iscas.ac.cn, shihua@iscas.ac.cn, chenyixuan@iscas.as.cn, juzhe.zhong@rivai.ai, pan2.li@intel.com, yulong Subject: [PATCH V1] RISC-V: Fix a bug that causes an error insn. Date: Tue, 8 Aug 2023 12:12:32 +0800 Message-Id: <20230808041232.15387-1-shiyulong@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CM-TRANSID: zQCowACHj_e9wNFkcAMZAg--.3109S2 X-Coremail-Antispam: 1UD129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73 VFW2AGmfu7bjvjm3AaLaJ3UjIYCTnIWjp_UUUY_7AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E 6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28Cjx kF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8I cVCY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87 Iv6xkF7I0E14v26F4UJVW0owAS0I0E0xvYzxvE52x082IY62kv0487M2AExVAIFx02aVAF z4v204v7Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7V C2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0 x7Aq67IIx4CEVc8vx2IErcIFxwAKzVCY07xG64k0F24lw4CEx2IqxVAFz4v204v26I0v72 4lc2xSY4AK6cvj6r45MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I 3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_Jr0_Jr4lx4CE17CEb7AF67AKxV WUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8I cVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aV AFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuY vjfUYR6zUUUUU X-Originating-IP: [43.139.163.53] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773632764361733071 X-GMAIL-MSGID: 1773632764361733071 From: yulong I test the following rvv intrinsics. vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);} And I got an error info,that is error: unrecognizable insn:(insn 17 16 18 2 (set (reg:RVVMIDI 134 [ _1 ])(if_then_else:RVVMIDI (unspec:RVVMF64BI [(reg/v:SI 142 [ vl ])(const_int 2 [x2])(const_int 日 [o])(reg:SI 66 vl)(reg:SI 67 vtype)] UNSPEC_VPREDICATE(vec_merge:RVVMIDI (reg:RVVMIDI 134 [ _1 ])(unspec:RVVMIDI [(reg:sI 日 zero)] UNSPEC_VUNDEF) (reg/v:RVVMF64BI 137 [ mask ])) (unspec:RVVM1DI[(reg:sI 日 zero)] UNSPEC_VUNDEF))) This patch fix it. gcc/ChangeLog: * config/riscv/riscv-v.cc (slide1_sew64_helper): Modify. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vslide1down-1.c: New test. * gcc.target/riscv/rvv/base/vslide1down-2.c: New test. * gcc.target/riscv/rvv/base/vslide1down-3.c: New test. * gcc.target/riscv/rvv/base/vslide1up-1.c: New test. * gcc.target/riscv/rvv/base/vslide1up-2.c: New test. * gcc.target/riscv/rvv/base/vslide1up-3.c: New test. --- gcc/config/riscv/riscv-v.cc | 5 ++--- .../gcc.target/riscv/rvv/base/vslide1down-1.c | 22 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vslide1down-2.c | 22 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vslide1down-3.c | 22 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vslide1up-1.c | 22 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vslide1up-2.c | 22 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vslide1up-3.c | 22 +++++++++++++++++++ 7 files changed, 134 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 278452b9e05..f73ec8c6474 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2103,9 +2103,8 @@ slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode, CONSTM1_RTX (demote_mask_mode), merge, temp, demote_scalar_op2, vl_x2, ta, ma, ops[8])); - if (rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1])))) - return true; - else + if (!rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1]))) + && !rtx_equal_p (ops[2], RVV_VUNDEF (GET_MODE (ops[2])))) emit_insn (gen_pred_merge (mode, ops[0], ops[2], ops[2], ops[0], ops[1], force_vector_length_operand (ops[5]), ops[6], ops[8])); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c new file mode 100644 index 00000000000..541745be2a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl); +} + +vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl); +} + +vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl); +} + +vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl); +} + +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c new file mode 100644 index 00000000000..9b5a240a9e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl); +} + +vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl); +} + +vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl); +} + +vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl); +} + +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c new file mode 100644 index 00000000000..7b05c85a243 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl); +} + +vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl); +} + +vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl); +} + +vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { + return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl); +} + +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c new file mode 100644 index 00000000000..74e8e5e63f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl); +} + +vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl); +} + +vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl); +} + +vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl); +} + +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c new file mode 100644 index 00000000000..e7e2ee950c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl); +} + +vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl); +} + +vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl); +} + +vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl); +} + +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c new file mode 100644 index 00000000000..b0b3af24e64 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl); +} + +vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl); +} + +vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl); +} + +vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl); +} + +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */