From patchwork Tue Aug 8 03:17:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 132498 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp1850545vqr; Mon, 7 Aug 2023 20:18:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHxIfE20MYjiFYvgulIxQYAzoSgSWwvldGG+82Bby0SfeJRuXjDuwXQXeCRp6Nyam32nOqN X-Received: by 2002:a17:906:7696:b0:99c:56d1:7c71 with SMTP id o22-20020a170906769600b0099c56d17c71mr10444027ejm.26.1691464698137; Mon, 07 Aug 2023 20:18:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464698; cv=none; d=google.com; s=arc-20160816; b=HS5gLBQ+sy32/nQ9BT9AhzFXRe3QkqHbGYZQY7ZjmqnwjYaMba6154lzefEmKI8VCo MdfpmkqbnxKoALtf6V0fdzsfGAIQMKYUEXVxdZoEM/yIxhr61rLejJ8212rXa/yesiIu 5RjIDR0ie/54oBJ6snyzkH4J3sdbFLyh2hod14072CAhIX1asDx0oh/NRsjBMOIUq6H8 FrjPrwQ+zj35MYlLqyyeMjcPUQfb63m5iAoRzZ9ok2lAlJrW/OaNPWuFssKJdAZXOQqB Qw39pmc0WpLEV3arL1RKZsIUPObSqz5XbPmBldEMQoaqiO3rfctd08fr0sDOIha8qlQn 7B8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=uHkqWZaM3PNIs+6L9l+YX23LTAHNgQ4u4VtWM8osAXQ=; fh=oLBbkpKGrMjsAiDUocfN7mW0LEnMJsqDdFE8uCs7/vo=; b=fZo2I/9fuEp2m2Pcc5HttrkFO+3DLHQ1alCQrybQyywNRAZdCVCIo3n8psTi42aKLW 7D5yHLMf6nNp7rPlA8c61hy7/up/HiiBaAoLfYzDHKgR1tAIxFIyqui3Mp9mgXjGHNd0 GMJvQgjDbizSUDA+dRxCnBfP0pcf+TSmJTGSKDWwc2wM0Te6nr1Y/f0hEMlZPeSdmS9O HSjvERRJI3AcoZJ2kLDgKo7dypS8WT8cRY6Ccf/ENuR7NY7GZzZ0WwzIbOl8aSZxf7vo TlepRZ1Z9Xx76t2fOgIHw8CLlvByueKGd73DcAVA0K+aFTKJVOThM3iXpUhs53yemHZr +0uQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=IzTyV0do; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id xo15-20020a170907bb8f00b0099bd5a646c2si6549247ejc.271.2023.08.07.20.18.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:18:18 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=IzTyV0do; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 84EA2385800A for ; Tue, 8 Aug 2023 03:18:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 84EA2385800A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1691464695; bh=uHkqWZaM3PNIs+6L9l+YX23LTAHNgQ4u4VtWM8osAXQ=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=IzTyV0doEwa1q7HoKL2PGNoiy6SV3IwEF47yKmLPXz46U0oXISrTazoLwhyvn/QWj 583ph6mSKxqmp171wJJAvHmPoFcEZXOiEC38Ji0lHJA43QjuKaUOuIstA+ciwiEqR1 NU+4vdu8tj0ToVEc4PjdPTzxjaHKBuPmBdPJSL88= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id EDA353858428 for ; Tue, 8 Aug 2023 03:18:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EDA353858428 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 3DD8E300089; Tue, 8 Aug 2023 03:18:06 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [RFC PATCH 1/2] RISC-V: Base for complex extension implications Date: Tue, 8 Aug 2023 03:17:45 +0000 Message-ID: <3a5169493b87c0769accb58056cb0c0770d84667.1691464661.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773629287206448613 X-GMAIL-MSGID: 1773629287206448613 From: Tsukasa OI Thanks to the commit 48558a5e5471 ("RISC-V: Allow nested implications for extensions"), we can write complex extension implications in theory. However, to actually do that, we need to pass more information to check_func. For example, we want to imply 'Zcf' from 'F' if and only if the 'Zce' extension is also enabled and XLEN is 32. Passing rps is a way to enable this. This commit prepares for such complex extension implications. bfd/ChangeLog: * elfxx-riscv.c (struct riscv_implicit_subset) Move around and change check_func function prototype. (check_implicit_always): New arguments. (check_implicit_for_i): Likewise. (riscv_implicit_subsets): Add comment for this variable. (riscv_parse_add_implicit_subsets): Call check_func with new arguments. --- bfd/elfxx-riscv.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index ee4598729480..b166e8d9c3c2 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1064,11 +1064,25 @@ riscv_elf_ignore_reloc (bfd *abfd ATTRIBUTE_UNUSED, return bfd_reloc_ok; } +/* Record all implicit information for the subsets. */ + +typedef struct riscv_implicit_subset +{ + const char *subset_name; + const char *implicit_name; + /* A function to determine if we need to add the implicit subset. */ + bool (*check_func) (riscv_parse_subset_t *, + const struct riscv_implicit_subset *, + const riscv_subset_t *); +} riscv_implicit_subset_t; + /* Always add the IMPLICIT for the SUBSET. */ static bool -check_implicit_always (const char *implicit ATTRIBUTE_UNUSED, - riscv_subset_t *subset ATTRIBUTE_UNUSED) +check_implicit_always (riscv_parse_subset_t *rps ATTRIBUTE_UNUSED, + const riscv_implicit_subset_t *implicit + ATTRIBUTE_UNUSED, + const riscv_subset_t *subset ATTRIBUTE_UNUSED) { return true; } @@ -1076,23 +1090,18 @@ check_implicit_always (const char *implicit ATTRIBUTE_UNUSED, /* Add the IMPLICIT only when the version of SUBSET less than 2.1. */ static bool -check_implicit_for_i (const char *implicit ATTRIBUTE_UNUSED, - riscv_subset_t *subset) +check_implicit_for_i (riscv_parse_subset_t *rps ATTRIBUTE_UNUSED, + const riscv_implicit_subset_t *implicit ATTRIBUTE_UNUSED, + const riscv_subset_t *subset) { return (subset->major_version < 2 || (subset->major_version == 2 && subset->minor_version < 1)); } -/* Record all implicit information for the subsets. */ -struct riscv_implicit_subset -{ - const char *subset_name; - const char *implicit_name; - /* A function to determine if we need to add the implicit subset. */ - bool (*check_func) (const char *, riscv_subset_t *); -}; -static struct riscv_implicit_subset riscv_implicit_subsets[] = +/* All extension implications. */ + +static riscv_implicit_subset_t riscv_implicit_subsets[] = { {"e", "i", check_implicit_always}, {"i", "zicsr", check_implicit_for_i}, @@ -1906,7 +1915,7 @@ riscv_parse_extensions (riscv_parse_subset_t *rps, static void riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps) { - struct riscv_implicit_subset *t = riscv_implicit_subsets; + riscv_implicit_subset_t *t = riscv_implicit_subsets; bool finished = false; while (!finished) { @@ -1918,7 +1927,7 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps) if (riscv_lookup_subset (rps->subset_list, t->subset_name, &subset) && !riscv_lookup_subset (rps->subset_list, t->implicit_name, &implicit_subset) - && t->check_func (t->implicit_name, subset)) + && t->check_func (rps, t, subset)) { riscv_parse_add_subset (rps, t->implicit_name, RISCV_UNKNOWN_VERSION, From patchwork Tue Aug 8 03:17:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 132499 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp1850884vqr; Mon, 7 Aug 2023 20:19:26 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHG/mQrhSjkBLl7G1sgTV2vvf19536iYE4ihIOdfDY8vz7UEpDNW472eZWoggq5thQZpOD8 X-Received: by 2002:a19:6702:0:b0:4fb:7cea:882a with SMTP id b2-20020a196702000000b004fb7cea882amr6495493lfc.3.1691464765809; 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[8.43.85.97]) by mx.google.com with ESMTPS id j4-20020a50ed04000000b005223c340277si6565488eds.426.2023.08.07.20.19.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:19:25 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=BOO6Ltsh; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 372BA385800C for ; Tue, 8 Aug 2023 03:19:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 372BA385800C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1691464745; bh=So60S345nM6itR0olRN6Iu4rREs6kDtcGf469Sd9GxQ=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=BOO6LtshsQsqy14JIXJT/5hjyHPi50dAT79nmZDIMdGC/VAhhr1VPRmSguNEMBKgD slOeMGlSDWLWbh65stM/eWv1o9jKZkncj1mUedQYwAM0NdbbLu67QSbJbPvxcBybLr wkdJUxIzSntN2z3RbcVAvRrmmNvjeZ5myE7PmkCE= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 298F33857806 for ; Tue, 8 Aug 2023 03:18:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 298F33857806 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id F2DE7300089; Tue, 8 Aug 2023 03:18:16 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [RFC PATCH 2/2] RISC-V: Add 'Zicntr' and 'Zihpm' support with compatibility measures Date: Tue, 8 Aug 2023 03:17:46 +0000 Message-ID: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773629276894695925 X-GMAIL-MSGID: 1773629357976364557 From: Tsukasa OI This commit adds support for 'Zicntr' and 'Zihpm' extensions (version 2.0). However, because GNU Binutils handled those as a part of 'I' and there was a time when a ratified specification did split counters from the 'I' extension without separate extension names. To preserve maximum compatibility, this commit implements as follows: * For RISC-V ISA version 20191213 or less (all current non-draft ones), imply counter extensions from 'I' and DO NOT imply the 'Zicsr' extension from counter extensions. We also suppress outputting the existence of counter extensions unless the version number is explicitly specified. * For future ratified ISAs, leave two options (each require minor edits): * Continue previous behaviors or * DO NOT imply counter extensions from 'I'. DO imply the 'Zicsr' extension from counter extensions. DO NOT suppress outputting the existence of such counter extensions by having a known version number (version 2.0 or [though unlikely] later). Make small changes to the disassembler to keep compatibility when disassembling old files. bfd/ChangeLog: * elfxx-riscv.c (check_implicit_compat_counter_from_i): New function for counter compatibility from 'I' to counter extensions. (check_implicit_compat_counter_to_zicsr): New function for counter compatibility from counter extensions to the 'Zicsr' extension. (riscv_implicit_subsets): Add implications related to counter extensions with compatibility measures. (riscv_supported_std_z_ext): Add 'Zicntr' and 'Zihpm' extensions. But make version "unknown" to suppress outputting implicit dependencies on older ISAs. (riscv_parse_add_subset): Add "zicntr" and "zihpm" to exceptions to recognize on older ISAs if there's no version number. (riscv_multi_subset_supports): Add support for 'Zicntr'. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Zicntr' and 'Zihpm' extensions. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/march-imply-i.s: Add 'Zicntr' instructions. include/ChangeLog: * opcode/riscv-opc.h: Change CSR classes for counter CSRs. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZICNTR for 'Zicntr' pseudoinstructions. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Recategorize counter pseudoinstructions to the 'Zicntr' extension. --- bfd/elfxx-riscv.c | 49 +++- gas/config/tc-riscv.c | 16 ++ gas/testsuite/gas/riscv/march-imply-i.s | 8 + include/opcode/riscv-opc.h | 310 ++++++++++++------------ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 12 +- 6 files changed, 233 insertions(+), 163 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index b166e8d9c3c2..ed38fcb37b97 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1099,6 +1099,32 @@ check_implicit_for_i (riscv_parse_subset_t *rps ATTRIBUTE_UNUSED, && subset->minor_version < 1)); } +/* Compatibility measure for counters (Zicntr and Zihpm): + Do or do not add the IMPLICIT only when the ISA version is + less than the border. */ + +static bool +check_implicit_compat_counter_from_i (riscv_parse_subset_t *rps, + const riscv_implicit_subset_t *implicit + ATTRIBUTE_UNUSED, + const riscv_subset_t *subset + ATTRIBUTE_UNUSED) +{ + /* When rps->isa_spec is NULL, we don't need to care about implicit + extensions because the caller is the linker. */ + return rps->isa_spec && *rps->isa_spec <= ISA_SPEC_CLASS_20191213; +} + +static bool +check_implicit_compat_counter_to_zicsr (riscv_parse_subset_t *rps, + const riscv_implicit_subset_t + *implicit, + const riscv_subset_t *subset) +{ + return (rps->isa_spec + && !check_implicit_compat_counter_from_i (rps, implicit, subset)); +} + /* All extension implications. */ static riscv_implicit_subset_t riscv_implicit_subsets[] = @@ -1106,6 +1132,8 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] = {"e", "i", check_implicit_always}, {"i", "zicsr", check_implicit_for_i}, {"i", "zifencei", check_implicit_for_i}, + {"i", "zicntr", check_implicit_compat_counter_from_i}, + {"i", "zihpm", check_implicit_compat_counter_from_i}, {"g", "i", check_implicit_always}, {"g", "m", check_implicit_always}, {"g", "a", check_implicit_always}, @@ -1191,6 +1219,8 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] = {"zcf", "zca", check_implicit_always}, {"zcd", "zca", check_implicit_always}, {"zcb", "zca", check_implicit_always}, + {"zicntr", "zicsr", check_implicit_compat_counter_to_zicsr}, + {"zihpm", "zicsr", check_implicit_compat_counter_to_zicsr}, {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, @@ -1258,12 +1288,20 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicntr", ISA_SPEC_CLASS_2P2, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 }, /* Compat. */ + {"zicntr", ISA_SPEC_CLASS_20190608, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 }, /* Compat. */ + {"zicntr", ISA_SPEC_CLASS_20191213, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 }, /* Compat. */ + {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zihpm", ISA_SPEC_CLASS_2P2, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 }, /* Compat. */ + {"zihpm", ISA_SPEC_CLASS_20190608, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 }, /* Compat. */ + {"zihpm", ISA_SPEC_CLASS_20191213, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 }, /* Compat. */ + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, @@ -1683,9 +1721,12 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps, rps->error_handler (_("x ISA extension `%s' must be set with the versions"), subset); - /* Allow old ISA spec can recognize zicsr and zifencei. */ + /* Allow old ISA spec (version 2.2) can recognize extensions + effectively split from the base 'I' extension version 2.0. */ else if (strcmp (subset, "zicsr") != 0 - && strcmp (subset, "zifencei") != 0) + && strcmp (subset, "zifencei") != 0 + && strcmp (subset, "zicntr") != 0 + && strcmp (subset, "zihpm") != 0) rps->error_handler (_("cannot find default versions of the ISA extension `%s'"), subset); @@ -2395,6 +2436,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zicbop"); case INSN_CLASS_ZICBOZ: return riscv_subset_supports (rps, "zicboz"); + case INSN_CLASS_ZICNTR: + return riscv_subset_supports (rps, "zicntr"); case INSN_CLASS_ZICOND: return riscv_subset_supports (rps, "zicond"); case INSN_CLASS_ZICSR: @@ -2588,6 +2631,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zicbop"; case INSN_CLASS_ZICBOZ: return "zicboz"; + case INSN_CLASS_ZICNTR: + return "zicntr"; case INSN_CLASS_ZICOND: return "zicond"; case INSN_CLASS_ZICSR: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index aaf8b9be64fd..b0bc3febb0fc 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -66,6 +66,10 @@ enum riscv_csr_class CSR_CLASS_I, CSR_CLASS_I_32, /* rv32 only */ + CSR_CLASS_ZICNTR, /* basic hardware perf counter */ + CSR_CLASS_ZICNTR_32, /* basic hardware perf counter, rv32 only */ + CSR_CLASS_ZIHPM, /* additional hardware perf counter */ + CSR_CLASS_ZIHPM_32, /* additional hardware perf counter, rv32 only */ CSR_CLASS_F, /* f-ext only */ CSR_CLASS_ZKR, /* zkr only */ CSR_CLASS_V, /* rvv only */ @@ -1031,6 +1035,18 @@ riscv_csr_address (const char *csr_name, need_check_version = true; extension = "i"; break; + case CSR_CLASS_ZICNTR_32: + is_rv32_only = true; + /* Fall through. */ + case CSR_CLASS_ZICNTR: + extension = "zicntr"; + break; + case CSR_CLASS_ZIHPM_32: + is_rv32_only = true; + /* Fall through. */ + case CSR_CLASS_ZIHPM: + extension = "zihpm"; + break; case CSR_CLASS_H_32: is_rv32_only = true; /* Fall through. */ diff --git a/gas/testsuite/gas/riscv/march-imply-i.s b/gas/testsuite/gas/riscv/march-imply-i.s index b65c3c32aa63..a225aaf72ae3 100644 --- a/gas/testsuite/gas/riscv/march-imply-i.s +++ b/gas/testsuite/gas/riscv/march-imply-i.s @@ -22,3 +22,11 @@ target: # zifencei fence.i + + # zicntr + rdcycle t0 + rdtime t0 + rdinstret t0 + rdcycleh t0 + rdtimeh t0 + rdinstreth t0 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 53f5f2005085..d486da4b862c 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3529,70 +3529,70 @@ DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ -DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_ZICNTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(time, CSR_TIME, CSR_CLASS_ZICNTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_ZICNTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_ZICNTR_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_ZICNTR_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_ZICNTR_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Privileged Supervisor CSRs. */ DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) @@ -3710,98 +3710,98 @@ DECLARE_CSR(pmpaddr60, CSR_PMPADDR60, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SP DECLARE_CSR(pmpaddr61, CSR_PMPADDR61, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(pmpaddr62, CSR_PMPADDR62, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(pmpaddr63, CSR_PMPADDR63, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_ZICNTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_ZICNTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_ZICNTR_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_ZICNTR_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_ZIHPM_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_ZIHPM, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Privileged Hypervisor CSRs. */ DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 808f36573030..62635f5a3962 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -389,6 +389,7 @@ enum riscv_insn_class INSN_CLASS_Q, INSN_CLASS_F_AND_C, INSN_CLASS_D_AND_C, + INSN_CLASS_ZICNTR, INSN_CLASS_ZICOND, INSN_CLASS_ZICSR, INSN_CLASS_ZIFENCEI, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 3efab9a407d2..67aca686b95c 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -498,12 +498,12 @@ const struct riscv_opcode riscv_opcodes[] = {"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, {"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 }, {"fence.tso", 0, INSN_CLASS_I, "", MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, 0 }, -{"rdcycle", 0, INSN_CLASS_I, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS }, -{"rdinstret", 0, INSN_CLASS_I, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS }, -{"rdtime", 0, INSN_CLASS_I, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS }, -{"rdcycleh", 32, INSN_CLASS_I, "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS }, -{"rdinstreth", 32, INSN_CLASS_I, "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS }, -{"rdtimeh", 32, INSN_CLASS_I, "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS }, +{"rdcycle", 0, INSN_CLASS_ZICNTR, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS }, +{"rdinstret", 0, INSN_CLASS_ZICNTR, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS }, +{"rdtime", 0, INSN_CLASS_ZICNTR, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS }, +{"rdcycleh", 32, INSN_CLASS_ZICNTR, "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS }, +{"rdinstreth", 32, INSN_CLASS_ZICNTR, "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS }, +{"rdtimeh", 32, INSN_CLASS_ZICNTR, "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS }, {"ecall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, {"scall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, {"xor", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },