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[8.43.85.97]) by mx.google.com with ESMTPS id h17-20020a1709063b5100b00991cb7517bbsi6823546ejf.947.2023.08.07.20.11.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:03 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A43D33858028 for ; Tue, 8 Aug 2023 03:10:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id 059743858418 for ; Tue, 8 Aug 2023 03:10:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 059743858418 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp88t1691464218tk6l8o0j Received: from server1.localdomain ( [58.60.1.10]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 08 Aug 2023 11:10:17 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 3M0okmaRx3gUbkcEEILlc9Cq6TcOMfosRipZ1cRHlTc0S7q1f7pIVGOMfKRYf 3POqItnE91MQXiI5X59d8QQdzpSQUb0IUSIeju7EPv0IObAEBIw43Vnq4swLVbmAlRJ/d9J HUkn5ivGZ7Tzsdw+UtwpZiug/iNgfP3oblMVmvKR7io/eiCrAPRe2AHwu0Ifbp2HyKMbs4p Iq1FML1e3GkyuHEGbU1CGa6dVw668zWZr+204W2AuQY8odyh7Wu1odjrXoD5sHgAqtNwRMw HAzdEEtTLG4qxwrnDiq4cz1oyIe4kVgn+7o4/249iuCLdW1CW2sVTAuUSQnhg5ZXO2PhCSq BnHvFfVwq8wH9DLt5rxdT/uu2vGlxvvUQHKtm3cb+EV9RPpqprtX9M/2pud5oCl8d3ghubI oe2dVSWSel8= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 9685197107541010080 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Support neg VLS auto-vectorization Date: Tue, 8 Aug 2023 11:10:16 +0800 Message-Id: <20230808031016.262528-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773628831493561180 X-GMAIL-MSGID: 1773628831493561180 #include "riscv_vector.h" #define DEF_OP_V(PREFIX, NUM, TYPE, OP) \ void __attribute__ ((noinline, noclone)) \ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) \ { \ for (int i = 0; i < NUM; ++i) \ a[i] = OP b[i]; \ } DEF_OP_V (neg, 16, int32_t, -) After this patch: neg_int32_t16: vsetivli zero,16,e32,mf2,ta,ma vle32.v v1,0(a1) vneg.v v1,v1 vse32.v v1,0(a0) ret gcc/ChangeLog: * config/riscv/autovec-vls.md (2): Add VLS neg. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Ditto. * gcc.target/riscv/rvv/autovec/vls/neg-1.c: New test. --- gcc/config/riscv/autovec-vls.md | 21 +++++++ gcc/config/riscv/vector.md | 10 ++-- .../gcc.target/riscv/rvv/autovec/vls/def.h | 8 +++ .../gcc.target/riscv/rvv/autovec/vls/neg-1.c | 57 +++++++++++++++++++ 4 files changed, 91 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index 4a9f8c8d0bc..1b1d940d779 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -181,3 +181,24 @@ riscv_vector::RVV_BINOP, operands); DONE; }) + +;; ------------------------------------------------------------------------------- +;; ---- [INT] Unary operations +;; ------------------------------------------------------------------------------- +;; Includes: +;; - vneg.v/vnot.v +;; ------------------------------------------------------------------------------- + +(define_insn_and_split "2" + [(set (match_operand:VLSI 0 "register_operand") + (any_int_unop:VLSI + (match_operand:VLSI 1 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands); + DONE; +}) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 9b51e0089d7..65b5fe456ed 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -3386,8 +3386,8 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_" - [(set (match_operand:VI 0 "register_operand" "=vd,vd, vr, vr") - (if_then_else:VI + [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr") + (if_then_else:V_VLSI (unspec: [(match_operand: 1 "vector_mask_operand" "vm,vm,Wc1,Wc1") (match_operand 4 "vector_length_operand" "rK,rK, rK, rK") @@ -3396,9 +3396,9 @@ (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_int_unop:VI - (match_operand:VI 3 "register_operand" "vr,vr, vr, vr")) - (match_operand:VI 2 "vector_merge_operand" "vu, 0, vu, 0")))] + (any_int_unop:V_VLSI + (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr")) + (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0")))] "TARGET_VECTOR" "v.v\t%0,%3%p1" [(set_attr "type" "vialu") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 33916ff0698..2a5baef747b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -142,3 +142,11 @@ typedef double v512df __attribute__ ((vector_size (4096))); for (int i = 0; i < NUM; ++i) \ a[i] = b[i] OP 7; \ } + +#define DEF_OP_V(PREFIX, NUM, TYPE, OP) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = OP b[i]; \ + } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c new file mode 100644 index 00000000000..0d723d70e8c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_V (neg, 1, int8_t, -) +DEF_OP_V (neg, 2, int8_t, -) +DEF_OP_V (neg, 4, int8_t, -) +DEF_OP_V (neg, 8, int8_t, -) +DEF_OP_V (neg, 16, int8_t, -) +DEF_OP_V (neg, 32, int8_t, -) +DEF_OP_V (neg, 64, int8_t, -) +DEF_OP_V (neg, 128, int8_t, -) +DEF_OP_V (neg, 256, int8_t, -) +DEF_OP_V (neg, 512, int8_t, -) +DEF_OP_V (neg, 1024, int8_t, -) +DEF_OP_V (neg, 2048, int8_t, -) +DEF_OP_V (neg, 4096, int8_t, -) + +DEF_OP_V (neg, 1, int16_t, -) +DEF_OP_V (neg, 2, int16_t, -) +DEF_OP_V (neg, 4, int16_t, -) +DEF_OP_V (neg, 8, int16_t, -) +DEF_OP_V (neg, 16, int16_t, -) +DEF_OP_V (neg, 32, int16_t, -) +DEF_OP_V (neg, 64, int16_t, -) +DEF_OP_V (neg, 128, int16_t, -) +DEF_OP_V (neg, 256, int16_t, -) +DEF_OP_V (neg, 512, int16_t, -) +DEF_OP_V (neg, 1024, int16_t, -) +DEF_OP_V (neg, 2048, int16_t, -) + +DEF_OP_V (neg, 1, int32_t, -) +DEF_OP_V (neg, 2, int32_t, -) +DEF_OP_V (neg, 4, int32_t, -) +DEF_OP_V (neg, 8, int32_t, -) +DEF_OP_V (neg, 16, int32_t, -) +DEF_OP_V (neg, 32, int32_t, -) +DEF_OP_V (neg, 64, int32_t, -) +DEF_OP_V (neg, 128, int32_t, -) +DEF_OP_V (neg, 256, int32_t, -) +DEF_OP_V (neg, 512, int32_t, -) +DEF_OP_V (neg, 1024, int32_t, -) + +DEF_OP_V (neg, 1, int64_t, -) +DEF_OP_V (neg, 2, int64_t, -) +DEF_OP_V (neg, 4, int64_t, -) +DEF_OP_V (neg, 8, int64_t, -) +DEF_OP_V (neg, 16, int64_t, -) +DEF_OP_V (neg, 32, int64_t, -) +DEF_OP_V (neg, 64, int64_t, -) +DEF_OP_V (neg, 128, int64_t, -) +DEF_OP_V (neg, 256, int64_t, -) +DEF_OP_V (neg, 512, int64_t, -) + +/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+} 42 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */