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Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 2ea0adae6832..aaec569fe91a 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -6,6 +6,7 @@ */ &cbass_main { + bootph-pre-ram; msmc_ram: sram@70000000 { compatible = "mmio-sram"; reg = <0x00 0x70000000 0x00 0x800000>; @@ -670,6 +671,7 @@ main_sdhci1: mmc@4fb0000 { }; main_navss: bus@30000000 { + bootph-pre-ram; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -705,6 +707,7 @@ main_udmass_inta: msi-controller@33d00000 { }; secure_proxy_main: mailbox@32c00000 { + bootph-pre-ram; compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; From patchwork Mon Aug 7 18:56:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 132379 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp1699100vqr; Mon, 7 Aug 2023 13:41:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGVEBsgfDF972Nhhoir88YRu9A7RC3RMVP1JFrJQLBOlC6GsWFzs+RWRdi3LpmXAKJXlD8y X-Received: by 2002:a17:907:b12:b0:98e:370c:be69 with SMTP id h18-20020a1709070b1200b0098e370cbe69mr8352902ejl.6.1691440859980; Mon, 07 Aug 2023 13:40:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691440859; cv=none; d=google.com; s=arc-20160816; b=ctCHN/JNff20LlV1A28BdAT/lzkKWE4wQLbLjEGkaq97Rik41QWhgkNRH2/qXm2pKi k/yLghSXDIpAOEVuizOTnCj+opGH5yPY0kCMiif+qpkGdaKqDz83RhLAl0iBafNYtSfC FoO2I4aQCPQq4f8M/jafPQQg8fFllD5w9WNFplfLtYtgd7rLtxBmPhPR1PXVuF+Y8Knq CJ0HWWugS3ayF/yhm92Lii8cTN1E6zhCSLp9WANx/CjCxyruJB8fE0MSEpHkGIuaThJE XhAQD+N1E30PkKs5i6iuxw8h1jp+5Cd9uH16fdB+BsmerY4GSlYihH+XT44EnrifMpCw 6Cqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xTf7ByXT/SyhX5YSoojCsqsftDwf0m9H3lr7P14WUsk=; fh=32MwQFC/OWOTTesZhIH/HSMNDNHEVSwT08x7vfzofjI=; b=W4Xc4HtFjtQqanQleC7lkuOZvj+ZPyp2JoVq2t0ejY5a7A8HfWANLQV/0VnB5kIZX3 poSnZWj62TS013+BFpalYPy3CCes/WydwmmTdiWxuAcCiMhfIeGeOl+xBQCm9S6ef07d pOu/69SQY5y2WrLiO1P7XaLFE3l3Dp+5/hHHR9b8bqiwveUmteFSmHb7R/sW42ty8cF8 fdF0O/+FLoCh2oXpepkVdW+XCVWfqVC+dfcz5u2qFLGk6Ad/4xXk5vqNND4b5HrEZgSq ncv8x+BlErJBXGjuO4ER3PIJsjCulYV8TuHDw2+LFRd+Q07ZwheWdpouORAQf/tbJVzM gN+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EBPycwYn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 657fb1d72512..521d3cfd10c4 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -6,7 +6,9 @@ */ &cbass_mcu_wakeup { + bootph-pre-ram; sms: system-controller@44083000 { + bootph-pre-ram; compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -19,22 +21,26 @@ sms: system-controller@44083000 { reg = <0x00 0x44083000 0x00 0x1000>; k3_pds: power-controller { + bootph-pre-ram; compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; k3_clks: clock-controller { + bootph-pre-ram; compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; k3_reset: reset-controller { + bootph-pre-ram; compatible = "ti,sci-reset"; #reset-cells = <2>; }; }; chipid@43000014 { + bootph-pre-ram; compatible = "ti,am654-chipid"; reg = <0x00 0x43000014 0x00 0x4>; }; @@ -161,6 +167,7 @@ mcu_timer0: timer@40400000 { }; mcu_timer1: timer@40410000 { + bootph-pre-ram; compatible = "ti,am654-timer"; reg = <0x00 0x40410000 0x00 0x400>; interrupts = ; @@ -442,6 +449,7 @@ mcu_spi2: spi@40320000 { }; mcu_navss: bus@28380000{ + bootph-pre-ram; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -451,6 +459,7 @@ mcu_navss: bus@28380000{ dma-ranges; mcu_ringacc: ringacc@2b800000 { + bootph-pre-ram; compatible = "ti,am654-navss-ringacc"; reg = <0x00 0x2b800000 0x00 0x400000>, <0x00 0x2b000000 0x00 0x400000>, @@ -465,6 +474,7 @@ mcu_ringacc: ringacc@2b800000 { }; mcu_udmap: dma-controller@285c0000 { + bootph-pre-ram; compatible = "ti,j721e-navss-mcu-udmap"; reg = <0x00 0x285c0000 0x00 0x100>, <0x00 0x2a800000 0x00 0x40000>, From patchwork Mon Aug 7 18:56:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 132361 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp1685737vqr; Mon, 7 Aug 2023 13:12:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE7BzeV1e9nfMQOIAIC8S3wiUXOk//igRYnkIa1bVPUns2N/9WTLKePVCqTSSqEMY3GT5mI X-Received: by 2002:aa7:d9d6:0:b0:523:22f6:e8a5 with SMTP id v22-20020aa7d9d6000000b0052322f6e8a5mr7432737eds.39.1691439129844; Mon, 07 Aug 2023 13:12:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691439129; cv=none; d=google.com; s=arc-20160816; b=odnk6TxMegtXn0FYJKXR43JzHWHdoHsQv3Lg/Y/F+xM2vX3ix5IHkNzvb0WWoItVKT EsPJfWHCmSZwOy3sE5SJ697AZr4SmWqgfoRg9dOPuKG7NESqfYVNGX3mzY+NlzKflc81 5y0bG80Z7apKeW2SIRuMYTb0OP3LAuXhZ+imLf/8g/MGjn/fXHbOvruqOox1/4qSs/2/ fXWjK5RMgTjIV6HvjLQ/dTA3rCQMeXmKHQCGSbdFMgTrb3j6zydsL/tyCvag/QyrXpdU njU6tjTknDcI9ss6pw+856vznmMg1YxUed3ECfiGbpndkNjuFdkIavFB6d2fD46QhoHn jRUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=w5YF8t5/AGI7RJ4NmAAvsHTFwqUck4gOdSoZjFlW+GM=; fh=32MwQFC/OWOTTesZhIH/HSMNDNHEVSwT08x7vfzofjI=; b=Hpki28w5BfazBQ4jpF2sjziU3FOgj9o7QYZX9zMFBKuI0t5vTWlqANUxNVZRairwuI meByzEhBR7YByhf9renTA20AoizziUx+xngYDdhumWPlwVuejmKSBxS275caCzKbS7Go xiA16q9m/BgEd9ZaFBYKQwu6nIBBYek9YYdi830asKiqx3uuPywgAvQEgImGfYY1lMcu +IGidlTvre8D2tihhKL2KChZzllZF6ZXPsjNtuvYLed0r3VOE8rcowilRDnlqnqEHNq6 PvbxSPL7Z8EalC0UtG8wz9I+FuhiJgE8MjhF75mNGJQ4YO1/5BGpJAOQYUcp/SuoJL73 BzrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QefX9mSM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index cb852031c802..35933551e6be 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -252,7 +252,9 @@ vdd_sd_dv: regulator-TLV71033 { }; &main_pmx0 { + bootph-pre-ram; main_uart8_pins_default: main-uart8-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -269,6 +271,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ }; main_mmc1_pins_default: main-mmc1-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -289,7 +292,9 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ }; &wkup_pmx2 { + bootph-pre-ram; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -299,6 +304,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -306,6 +312,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ }; mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -366,7 +373,9 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ }; &wkup_pmx0 { + bootph-pre-ram; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ @@ -384,7 +393,9 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ }; &wkup_pmx1 { + bootph-pre-ram; mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ @@ -392,6 +403,7 @@ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ }; mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ @@ -406,6 +418,7 @@ J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ }; &wkup_uart0 { + bootph-pre-ram; /* Firmware usage */ status = "reserved"; pinctrl-names = "default"; @@ -413,6 +426,7 @@ &wkup_uart0 { }; &wkup_i2c0 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; @@ -426,27 +440,32 @@ eeprom@50 { }; &mcu_uart0 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; }; &fss { + bootph-pre-ram; status = "okay"; }; &ospi0 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; flash@0 { + bootph-pre-ram; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -494,6 +513,7 @@ partition@800000 { }; partition@3fc0000 { + bootph-pre-ram; label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -502,11 +522,13 @@ partition@3fc0000 { }; &ospi1 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; flash@0{ + bootph-pre-ram; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; @@ -554,6 +576,7 @@ partition@800000 { }; partition@3fc0000 { + bootph-pre-ram; label = "qspi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -598,6 +621,7 @@ exp2: gpio@22 { }; &main_sdhci0 { + bootph-pre-ram; /* eMMC */ status = "okay"; non-removable; @@ -606,6 +630,7 @@ &main_sdhci0 { }; &main_sdhci1 { + bootph-pre-ram; /* SD card */ status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; From patchwork Mon Aug 7 18:56:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 132421 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp1748954vqr; Mon, 7 Aug 2023 15:34:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEJ1b0P4K1b0auGU6OfVPkVn/ikRTwbTSHLz0F8onhYNIWMvhPdX3U0VMSAMM2t9PcJYG/h X-Received: by 2002:a17:903:41cd:b0:1b6:72af:623d with SMTP id u13-20020a17090341cd00b001b672af623dmr9848292ple.55.1691447682077; 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Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index d282c2c633c1..cbe88a26b283 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -110,7 +110,9 @@ vdd_sd_dv: regulator-tlv71033 { }; &main_pmx0 { + bootph-pre-ram; main_uart8_pins_default: main-uart8-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ @@ -125,6 +127,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ }; main_mmc1_pins_default: main-mmc1-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -164,7 +167,9 @@ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ }; &wkup_pmx2 { + bootph-pre-ram; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -174,6 +179,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -181,6 +187,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ }; mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ @@ -242,6 +249,7 @@ J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ }; &wkup_uart0 { + bootph-pre-ram; /* Firmware usage */ status = "reserved"; pinctrl-names = "default"; @@ -249,6 +257,7 @@ &wkup_uart0 { }; &wkup_i2c0 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; @@ -268,6 +277,7 @@ &wkup_gpio0 { }; &mcu_uart0 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; @@ -281,6 +291,7 @@ &mcu_i2c0 { }; &main_uart8 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; @@ -307,6 +318,7 @@ exp1: gpio@21 { }; &main_sdhci0 { + bootph-pre-ram; /* eMMC */ status = "okay"; non-removable; @@ -315,6 +327,7 @@ &main_sdhci0 { }; &main_sdhci1 { + bootph-pre-ram; /* SD card */ status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>;