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[8.43.85.97]) by mx.google.com with ESMTPS id g17-20020a170906395100b00992b521a3f6si5333636eje.24.2023.08.07.00.37.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 00:37:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=fail header.i=@nextmovesoftware.com header.s=default header.b=jmI2h5Kz; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5CD1C3858004 for ; Mon, 7 Aug 2023 07:37:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 972783858D28 for ; Mon, 7 Aug 2023 07:37:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 972783858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=LktujGYAZdwuCBD6YnglxSAcHjgLz1SOAaNj3pLFlho=; b=jmI2h5KzAlPSVwMpc13xDLyh0l xgQH4n4fsLBNeYOZhMAORmUsmyoaCvTvdm9c6AGjTZwMO0ClrWE46IiAGIytG17oGcL9EZHUQ2PBW Zf0T0QHXWbUeVjzXJFbTFzew2SQKzaNNEA7LKusISoZxpTS21f5Kt61IJa+spJF5CmLD4g1jKRZXD 6oLaRCyOTfTrP/oVxyl/FnoBnxwnvx2Y6o+Yq/0OtjqF2vdHrCoavca2Gf4WktoTU/eAHARfptQjg XkqcI6hIZXVHAWH9myh2wVgZ+rvUvXlqC/7oTN0pft0yIxdlLpZnuZFBqE5R4N/56hfg3WMsVLh4u B/CtVBPQ==; Received: from host86-161-68-50.range86-161.btcentralplus.com ([86.161.68.50]:53495 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1qSunW-0003kc-39; Mon, 07 Aug 2023 03:37:03 -0400 From: "Roger Sayle" To: Cc: "'Uros Bizjak'" Subject: PR target/107671: Make more use of btl/btq on x86_64. Date: Mon, 7 Aug 2023 08:37:01 +0100 Message-ID: <004b01d9c901$f5bb66b0$e1323410$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdnJAO/voP9oDfhpShK11mQS+8DeJw== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773555012364323977 X-GMAIL-MSGID: 1773555012364323977 This patch is a partial solution to PR target/107671, updating Uros' patch from comment #4, to catch both bit set (setc) and bit not set (setnc) cases from the code in comment #2, when compiled on x86_64. Unfortunately, this is a partial solution, as the pointer variants in comment #1, aren't yet all optimized, and my attempts to check whether the 32-bit versions are optimized with -m32 revealed they also need further improvement. (Some of) These remaining issues might best be fixed in the middle-end, in either match.pd or the RTL optimizers, so I thought it reasonable to submit this independent backend piece, and gain/bank the improvements on x86_64. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32} with no new failures. Ok for mainline? 2023-08-07 Roger Sayle Uros Bizjak gcc/ChangeLog PR target/107671 * config/i386/i386.md (*bt_setc_mask): Allow the shift count to have a different mode (using SWI248) from either the bit-test or the result. (*bt_setnc_mask): New define_insn_and_split for the setnc (bit not set) case of the above pattern. (*btdi_setncsi_mask): New define_insn_and_split to handle the SImode result from a DImode bit-test variant of the above patterns. (*bt_setncqi_mask_2): New define_insn_and_split for the setnc (bit not set) version of *bt_setcqi_mask_2. gcc/testsuite/ChangeLog PR target/107671 * gcc.target/i386/pr107671-1.c: New test case. * gcc.target/i386/pr107671-2.c: Likewise. Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index ba376f8..aa8946a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -16405,19 +16405,19 @@ (ne:QI (reg:CCC FLAGS_REG) (const_int 0)))]) ;; Help combine recognize bt followed by setc -(define_insn_and_split "*bt_setc_mask" +(define_insn_and_split "*bt_setc_mask" [(set (match_operand:SWI48 0 "register_operand") (zero_extract:SWI48 (match_operand:SWI48 1 "register_operand") (const_int 1) (subreg:QI - (and:SWI48 - (match_operand:SWI48 2 "register_operand") + (and:SWI248 + (match_operand:SWI248 2 "register_operand") (match_operand 3 "const_int_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT - && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) - == GET_MODE_BITSIZE (mode)-1 + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) + == GET_MODE_BITSIZE (mode)-1 && ix86_pre_reload_split ()" "#" "&& 1" @@ -16432,6 +16432,90 @@ operands[2] = gen_lowpart (QImode, operands[2]); operands[3] = gen_reg_rtx (QImode); }) + +;; Help combine recognize bt followed by setnc +(define_insn_and_split "*bt_setnc_mask" + [(set (match_operand:SWI48 0 "register_operand") + (and:SWI48 + (not:SWI48 + (lshiftrt:SWI48 + (match_operand:SWI48 1 "register_operand") + (subreg:QI + (and:SWI248 (match_operand:SWI248 2 "register_operand") + (match_operand 3 "const_int_operand")) 0))) + (const_int 1))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_USE_BT + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) + == GET_MODE_BITSIZE (mode)-1 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2)) + (const_int 0))) + (set (match_dup 3) + (ne:QI (reg:CCC FLAGS_REG) (const_int 0))) + (set (match_dup 0) (zero_extend:SWI48 (match_dup 3)))] +{ + operands[2] = gen_lowpart (QImode, operands[2]); + operands[3] = gen_reg_rtx (QImode); +}) + +;; Help combine recognize bt followed by setnc +(define_insn_and_split "*btdi_setncsi_mask" + [(set (match_operand:SI 0 "register_operand") + (and:SI + (not:SI + (subreg:SI + (lshiftrt:DI (match_operand:DI 1 "register_operand") + (subreg:QI + (and:SWI248 + (match_operand:SWI248 2 "register_operand") + (const_int 63)) 0)) 0)) + (const_int 1))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT && TARGET_USE_BT && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (zero_extract:DI (match_dup 1) (const_int 1) (match_dup 2)) + (const_int 0))) + (set (match_dup 3) + (ne:QI (reg:CCC FLAGS_REG) (const_int 0))) + (set (match_dup 0) (zero_extend:SI (match_dup 3)))] +{ + operands[2] = gen_lowpart (QImode, operands[2]); + operands[3] = gen_reg_rtx (QImode); +}) + +;; Help combine recognize bt followed by setnc +(define_insn_and_split "*bt_setncqi_mask_2" + [(set (match_operand:QI 0 "register_operand") + (eq:QI + (zero_extract:SWI48 + (match_operand:SWI48 1 "register_operand") + (const_int 1) + (subreg:QI + (and:SWI248 (match_operand:SWI248 2 "register_operand") + (match_operand 3 "const_int_operand")) 0)) + (const_int 0))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_USE_BT + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) + == GET_MODE_BITSIZE (mode)-1 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2)) + (const_int 0))) + (set (match_dup 0) + (ne:QI (reg:CCC FLAGS_REG) (const_int 0)))] + "operands[2] = gen_lowpart (QImode, operands[2]);") ;; Store-flag instructions. diff --git a/gcc/testsuite/gcc.target/i386/pr107671-1.c b/gcc/testsuite/gcc.target/i386/pr107671-1.c new file mode 100644 index 0000000..d05b178 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr107671-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +int bt32v_setb(const __UINT32_TYPE__ v, __UINT32_TYPE__ bitnum) +{ + return ((v & (1 << (bitnum & 31)))) != 0; +} + +int bt32v_setb2(const __UINT32_TYPE__ v, __UINT32_TYPE__ bitnum) +{ + return (v >> (bitnum & 31)) & 1; +} + +int bt32v_setae(const __UINT32_TYPE__ v, __UINT32_TYPE__ bitnum) +{ + return ((v & (1 << (bitnum & 31)))) == 0; +} + +int bt32v_setae2(const __UINT32_TYPE__ v, __UINT32_TYPE__ bitnum) +{ + return !((v >> (bitnum & 31)) & 1); +} + +/* { dg-final { scan-assembler-times "btl" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr107671-2.c b/gcc/testsuite/gcc.target/i386/pr107671-2.c new file mode 100644 index 0000000..c90faea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr107671-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +int bt64v_setb(const __UINT64_TYPE__ v, __UINT64_TYPE__ bitnum) +{ + return ((v & (1LL << (bitnum & 63)))) != 0; +} + +int bt64v_setb2(const __UINT64_TYPE__ v, __UINT64_TYPE__ bitnum) +{ + return (v >> (bitnum & 63)) & 1; +} + +int bt64v_setae(const __UINT64_TYPE__ v, __UINT64_TYPE__ bitnum) +{ + return ((v & (1LL << (bitnum & 63)))) == 0; +} + +int bt64v_setae2(const __UINT64_TYPE__ v, __UINT64_TYPE__ bitnum) +{ + return !((v >> (bitnum & 63)) & 1); +} + +/* { dg-final { scan-assembler-times "btq" 4 } } */