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Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index a04c44708a09..6bba73c8f359 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -6,6 +6,7 @@ */ &cbass_main { + bootph-pre-ram; msmc_ram: sram@70000000 { compatible = "mmio-sram"; reg = <0x00 0x70000000 0x00 0x800000>; @@ -670,6 +671,7 @@ main_sdhci1: mmc@4fb0000 { }; main_navss: bus@30000000 { + bootph-pre-ram; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -705,6 +707,7 @@ main_udmass_inta: msi-controller@33d00000 { }; secure_proxy_main: mailbox@32c00000 { + bootph-pre-ram; compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; From patchwork Sun Aug 6 16:48:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 131617 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp1016751vqr; Sun, 6 Aug 2023 10:11:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF6e7uIH4k+v1r6w5KJFXVABx8CBDcgY1AuuXUz+kv++aeHgqfYQx5TwAJqxNXYB5fMzk0I X-Received: by 2002:a05:6a00:1ac7:b0:687:22ce:365f with SMTP id f7-20020a056a001ac700b0068722ce365fmr9195515pfv.29.1691341879823; Sun, 06 Aug 2023 10:11:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691341879; cv=none; d=google.com; s=arc-20160816; b=nbUQE3Igv5rSdDG8H1kgcYfghghpfPXmIWMy3R/nAmzN8ecX30u/qq8N6nZMPn2+b2 v2De2aykLfYouvtxDC24klyiUTXHm0TknUwnyK3DWZULkcP6/TImynDp/Q6iSQBUE64/ W4e5BZtjcj5hpQysQBxo/EcHymemIAP9mVDVjmIewn8PeyyKH+jIs9blRbmXmX65g0wY erKT4+yBO5mbAY8uC18FRigb1uTqR8CuVMLu17blYc5W0qGNNR1tR2ZpX6Ngr4swoRNP u6/04wuiXMR+xHL44JiYyEfh2F+ZlcIoobz/LDH8jYT6DFyKLs3HUPT4RjgQG0GAUgGk H23Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gOgHxaFNknEPQkRXnHJvFNHYD58prAaSGp1BrvLOPEk=; fh=AOFcl182NPcBrF8V1t7LgZHFt53dFJmF6BGNBNOJCmM=; b=lwiQX8IObfQx22qjYAbDXY7zRf5Ol7PDU0ZIawKM/dgjlBSgdRdF5vPxm/4KfNIvdE ThfizLnpEZ2yHHwyrwXesy1MxGZOMZLUYlXuj2gKWubUKE5ncv8VZ7WH9IlAyInqwCBb oItLe0L0VlAiom0CPwSr1mYXkKsvace1ciqctTI+78H6XLNiB9s+1BocUbl/AblYp5fl gq4UQP7woerZe9/bw8ylG8OoC9E/MPZazS81TYS3yIMIt3GmAdFjv9s92Xf+blODBXtw lGNAGynGxz+x21kQ3szhwK5D9RRYgLksk1VZrituSZPCwr5B5VTPTinxGGOWTIWwt22Q Jndw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=uWYxqcmI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 740ee794d7b9..57bf0261c343 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -6,7 +6,9 @@ */ &cbass_mcu_wakeup { + bootph-pre-ram; sms: system-controller@44083000 { + bootph-pre-ram; compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -19,22 +21,26 @@ sms: system-controller@44083000 { reg = <0x00 0x44083000 0x00 0x1000>; k3_pds: power-controller { + bootph-pre-ram; compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; k3_clks: clock-controller { + bootph-pre-ram; compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; k3_reset: reset-controller { + bootph-pre-ram; compatible = "ti,sci-reset"; #reset-cells = <2>; }; }; chipid@43000014 { + bootph-pre-ram; compatible = "ti,am654-chipid"; reg = <0x00 0x43000014 0x00 0x4>; }; @@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 { }; mcu_navss: bus@28380000 { + bootph-pre-ram; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -451,6 +458,7 @@ mcu_navss: bus@28380000 { dma-ranges; mcu_ringacc: ringacc@2b800000 { + bootph-pre-ram; compatible = "ti,am654-navss-ringacc"; reg = <0x00 0x2b800000 0x00 0x400000>, <0x00 0x2b000000 0x00 0x400000>, @@ -465,6 +473,7 @@ mcu_ringacc: ringacc@2b800000 { }; mcu_udmap: dma-controller@285c0000 { + bootph-pre-ram; compatible = "ti,j721e-navss-mcu-udmap"; reg = <0x00 0x285c0000 0x00 0x100>, <0x00 0x2a800000 0x00 0x40000>, From patchwork Sun Aug 6 16:48:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 131616 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp1016358vqr; Sun, 6 Aug 2023 10:10:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGvzu65iU+9CAA8opLY8lPpNbk8AcIxUHnfCq3mMBV829M7EsmwkeIfWm9+FVdAulKRCcuX X-Received: by 2002:a17:902:c407:b0:1b8:1c1b:125a with SMTP id k7-20020a170902c40700b001b81c1b125amr7564378plk.2.1691341822724; Sun, 06 Aug 2023 10:10:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691341822; cv=none; d=google.com; s=arc-20160816; b=VLGlsWIGLn2xiKmKdmQ0WzkEVO1SAKXPmjqhCRx9PwAqudXAm35N7KMxkBQGX50B1C DNbgzRHKsgnhH2J3C0irVwJ42DQIIvCKobLpWLirV5mZOQtrJkf09J5u8Mz2KNC4W1GB vacTLDOGa6Fg68gt4a/0AEuwh+J7pr+VMs/vCPWKZsPp440DORwF5ctMSzJchjHRuyr+ 1nDZYJzpyWsXH8Vne3fgcbgk3fRXnBoYen8zzFz60fvQHA8LId1mkP/cA/MQhywA9Rn5 YPq2nvLTGtGLsFI3xnkdaZGdlExA/L89tE2g3xT4zqHst/74CDsnwvmNzetIrVGIT8iB h/rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JPRORifvGrUrwDZIN/iGzlfeEl6AVt2arl7a65Q6VzE=; fh=AOFcl182NPcBrF8V1t7LgZHFt53dFJmF6BGNBNOJCmM=; b=l+8DjQwuSieu2oRP1mi3ZqZZ1DBKSt9kv/bB3x7AwbOBvvt8kB0gmPZMUBQiHHQdsj V8gMtd6nIOCIjQLFNcxvpJmstohBum751auhCLVyeoIEn4CWveOZZ7l6jqCajFdoqDrC huVpPt/WEG55XTmzist+Si7pJwY03ot1jG0iXCvD1Rndld7IZfKx/wCZIujxP88rPj6h 7XD9eWDEOspNRyexotxUVIOQk9IRklaLS4MK+Y/goGCfGireoPMDgwnO5LDJc93zhw/5 IoGMBAjtVkE977IbU93lzZBH5NT1EAk5FWM8/RNdRmBCcelbMH9NYI0yH2WpcEKc8Y3S /l6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=WLA6OcoX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 1e38a8f1bec5..12455baf68b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -252,7 +252,9 @@ vdd_sd_dv: regulator-TLV71033 { }; &main_pmx0 { + bootph-pre-ram; main_uart8_pins_default: main-uart8-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -269,6 +271,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ }; main_mmc1_pins_default: main-mmc1-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -289,7 +292,9 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ }; &wkup_pmx2 { + bootph-pre-ram; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -299,6 +304,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -306,6 +312,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ }; mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -366,7 +373,9 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ }; &wkup_pmx0 { + bootph-pre-ram; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ @@ -385,6 +394,7 @@ J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_ }; mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-pre-ram; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ @@ -399,6 +409,7 @@ J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ }; &wkup_uart0 { + bootph-pre-ram; /* Firmware usage */ status = "reserved"; pinctrl-names = "default"; @@ -406,6 +417,7 @@ &wkup_uart0 { }; &wkup_i2c0 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; @@ -419,12 +431,14 @@ eeprom@50 { }; &mcu_uart0 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; @@ -435,15 +449,18 @@ &ufs_wrapper { }; &fss { + bootph-pre-ram; status = "okay"; }; &ospi0 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; flash@0 { + bootph-pre-ram; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -491,6 +508,7 @@ partition@800000 { }; partition@3fc0000 { + bootph-pre-ram; label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -499,11 +517,13 @@ partition@3fc0000 { }; &ospi1 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; flash@0 { + bootph-pre-ram; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; @@ -551,6 +571,7 @@ partition@800000 { }; partition@3fc0000 { + bootph-pre-ram; label = "qspi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -595,6 +616,7 @@ exp2: gpio@22 { }; &main_sdhci0 { + bootph-pre-ram; /* eMMC */ status = "okay"; non-removable; @@ -603,6 +625,7 @@ &main_sdhci0 { }; &main_sdhci1 { + bootph-pre-ram; /* SD card */ status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>;