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Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index a43eb837f8da..57602c345cab 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -19,6 +19,7 @@ properties: - rockchip,rk3568-dwcmshc - rockchip,rk3588-dwcmshc - snps,dwcmshc-sdhci + - thead,th1520-dwcmshc reg: maxItems: 1 @@ -60,6 +61,14 @@ properties: description: Specify the number of delay for tx sampling. $ref: /schemas/types.yaml#/definitions/uint8 + thead,io-fixed-1v8: + description: SoC PHY pad is fixed 1.8V + type: boolean + + thead,pull-up: + description: True if pull-up, false if pull-down + type: boolean + required: - compatible From patchwork Sat Aug 5 03:14:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Fustini X-Patchwork-Id: 131439 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp276467vqr; Fri, 4 Aug 2023 22:21:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF8GrQ0gEK8PcP84nogYVfSxx02EjGqF5SRnPZy67deqDX/+mAyCliKq3prSlAxeky/fBaT X-Received: by 2002:a17:906:257:b0:991:fef4:bb7 with SMTP id 23-20020a170906025700b00991fef40bb7mr2797279ejl.73.1691212890190; Fri, 04 Aug 2023 22:21:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691212890; cv=none; d=google.com; s=arc-20160816; b=pDncvEAJxdp43saPrZUgj/uC2bl098I0MS1XKuoe/D5vbWpmVX0IS8A6SkV2odHTpc PJj+9cb/u1WrwVViOEeJuc6p/XrUPnRWQpojPdRA1MsZZAeUslFQiIBLUETdZMXorwM9 r9M5P9ORGkStBe+Ynh7bn/cHU1l9XyDtPt5K7UUGOnQaUjj9S19UFvDJ2QS+6IHoOp0S Lqsn6C70LLAR+aqyt9E1LfKOXRxGEvpo1cgFTr8Zwj/MH7j42hSlhmIaqVeWz81Hp5Kv 1+NQhubmQR6WAdNBfhgiwegrH8uXAX4AXZxEh8rVz3fRNJmu77KA+jDIJGDGXosAYksR vxuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=vubcOJoroAr2qpLW2iybw1ATfvK07sgIvUXsKV/dGPo=; fh=rHoFbZyzzIVIajVDRHhxvyJszxnYNymsdNARghy77aU=; b=hHGMbt2NF1YXch5hZdvzVVrP17aiFQXDmlBwgkkt91nbPb8p2Z9InphRiypFiYBib4 jubNXy5fxR9hXniU35sPOWWQ9WoOsgGwB0FUyWBIYLSt6mEEgUbr0dcwzrJrHEaVLF1a mzR8GAMxKTz0C/bcDCLOysXGx40FZOy8hNkt10K16vQhtOxim/YAI9bH9ttZ2p5Y0QhV cEUmnxw9UB1LUXn+zrjR9AaIgXMvuPibTa1vP1VdWMr4xPEYv3ADA2mg5LJwD0XSwTra 4qrmsa1p4qhrzlwTWheK0kDQsRYttxwbqY4FFfqYOwXopBlvgxgVGPPmb7ssHiPmJX8+ lYpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20221208.gappssmtp.com header.s=20221208 header.b=LGi433l6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 56a73134b49e..b33bfb04c955 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -134,6 +134,13 @@ uart_sclk: uart-sclk-clock { #clock-cells = <0>; }; + sdhci_clk: sdhci-clock { + compatible = "fixed-clock"; + clock-frequency = <198000000>; + clock-output-names = "sdhci_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -291,6 +298,16 @@ dmac0: dma-controller@ffefc00000 { status = "disabled"; }; + mmc0: mmc@ffe7080000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7080000 0x0 0x10000 + 0xff 0xef014060 0x0 0x4>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sdhciirq"; + clocks = <&sdhci_clk>; + clock-names = "core"; + }; + timer0: timer@ffefc32000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32000 0x0 0x14>; From patchwork Sat Aug 5 03:14:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Fustini X-Patchwork-Id: 131437 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp266636vqr; Fri, 4 Aug 2023 21:49:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGv+TTxPw6yefqlxkkO9lCs68PT8lN7mJGPG8ljLVyoGYiaer2KyNixmOtwKceapJ+yDhqF X-Received: by 2002:a05:6358:2610:b0:134:d559:259a with SMTP id l16-20020a056358261000b00134d559259amr5211645rwc.17.1691210951391; Fri, 04 Aug 2023 21:49:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691210951; cv=none; d=google.com; s=arc-20160816; b=qL7i/tMrTHYEFn34/gHXf0BtLCh4GCvYRfYUe4xd9Pffq0M1ppgFeNnvlm92ptzsLl BpXSH3HDXbpsZPo79JNBSe8qoQioma4z8ovrCb40+0RBABewxIsCazi9mAKGKBLOXFGn GikQFch1SSBzVH+7BlaOXxp8UYZS6Ms38KHnFYSF3NWgln6VeMDJXaKMFt+nIO62oVBU On01wEt/nAAveMkjacJbsTFkCw/hF47DScE/cKDGa8H4K6i3u1j+Y1neAOkuZptQK2D2 GobGuYm778UZh0ASoBXcFvyqfFA6GcGOL/1TJCtNAO1XEcRLbS4l3Ff1pU7KYkd/KePT aspw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=HdRLfV4DSjo6NuAp3G0Z9YBsmLluT1U9pYT+QCm2Ogw=; fh=rHoFbZyzzIVIajVDRHhxvyJszxnYNymsdNARghy77aU=; b=LHphc46uV9oTbBvlPvaEkAQXsYtgiBdGOJska8Rdu8uSKEYW068UlX/SBObgqCRawO f8x13NF7wm0yDLzyP4gh8fxtffsSamyvWMaI5PWV21H5vMMBxyoKye8KBIDtBXfAOYD/ I3RA4CDpgctUb0Q0RAoDBgZRg7SW8joaG0qlLE8Ua9spDlbQ4OgXO9vWTC4NW7bWRu06 vbN6aDf121x1wp6+BG0Vh/2I8HWt48UcwHzIMGTrVBW3grCijFEuknc2wz1pMyNU4kx9 5zJXf3hXqAgaEJw88wZYsylJ9IzPDGbZ2AhiOjVCk9kI3aanQEaMFEzrIYgDrGYoyBJj eUhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20221208.gappssmtp.com header.s=20221208 header.b=Sirb95ge; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index c315e5bd3d2d..f93c11754639 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -52,6 +52,10 @@ &uart_sclk { clock-frequency = <100000000>; }; +&sdhci_clk { + clock-frequency = <198000000>; +}; + &dmac0 { status = "okay"; }; @@ -59,3 +63,16 @@ &dmac0 { &uart0 { status = "okay"; }; + +&mmc0 { + max-frequency = <198000000>; + non-removable; + mmc-hs400-1_8v; + thead,io-fixed-1v8; + no-sdio; + no-sd; + thead,pull-up; + bus-width = <8>; + status = "okay"; + +}; From patchwork Sat Aug 5 03:14:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Fustini X-Patchwork-Id: 131432 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp255965vqr; Fri, 4 Aug 2023 21:11:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGq8acVPBLCL8pw1X00fE4ivedbKd+8Qs7H2WeE1RYZKqiuSQfhHJVYgkd75gtSjJ6Vg/xi X-Received: by 2002:aa7:c409:0:b0:522:2aee:6832 with SMTP id j9-20020aa7c409000000b005222aee6832mr2764679edq.9.1691208697302; Fri, 04 Aug 2023 21:11:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691208697; cv=none; d=google.com; s=arc-20160816; b=nnGj8MPB8g9SO8JiZHtAyUjxpFda2FGwcKv5tX8zggTnaXlbVK42xZRW9RJcb7lrKK SzsmrFDMfoG/1z63u+2Kqy4s7Q/Ar2DpXgbEmg6T16CQlaW/pRdMTJF9f68fDc2WTrjn LLsNneNJ7dt0TBB/Pf/ybzzUdygK9NxGqplUH2NU5DIuVmheuohoyKmu9r1oLRhUBSoS 7hpA6Pfbt8jvw28sjV4seVTKpo5eW0LThnM9FOOYJkp04jLR11tnwt0uQ6lMVbeOMntW 8uN15vVjNi57uS2YdVG4RHe9adEmvtB95/eGb35UmLrhWs4jza64ZF0s/gqP7Y8qDfHN zL0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=ZEssXYylfcRLmvvX1PZG2lu6ghbesKpJSC9p5adyHlA=; fh=rHoFbZyzzIVIajVDRHhxvyJszxnYNymsdNARghy77aU=; b=j+8ZGWP5gIWj1wK+HgmLQYNRcWVw8TgpmWNbbdK/R+OxfwGk9z3sxHX+8m4X00ca0t 72ovHOGUF+AJdQfkVAcSAjMluRMpltQKnjC71reXeIOTjCtmIHHKhe17fkPRxrML1z9y IX/BDVsdVvQG4xIEKA4go4huNjVL+xBfFMcLUf8Ut382xFksQmoJX2aXMbvclikbT0bF 0Cragr5BiHoTJ+g89i3dmhK2q/HSH8EH7M7cdQ4df7RExNdnlqiBiIi39+ns/xWDSkRG 4j/faA6iBfiHGul1ulrnwVA6/xvEJE8G3BaiKjB3An0TEkNxpMfXKdvsv1wL8rMXH1Hl m9gQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20221208.gappssmtp.com header.s=20221208 header.b=m9TtZJ1Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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However, quirks are currently set to disable DMA and use PIO. The proper settings for DMA support still need to be determined. Another issue is th1520-specific code for MMC_TIMING_MMC_HS400 in dwcmshc_set_uhs_signaling() will run on all platforms which is not correct. One solution could be to add a th1520 flag to dwcmshc_priv but that is hacky. Another solution could be to set the set_uhs_signaling op in sdhci_dwcmshc_th1520_ops to a th1520-specific function. However, that new function would have to duplicate all the code in the current dwcmshc_set_uhs_signaling(). Signed-off-by: Drew Fustini --- drivers/mmc/host/sdhci-of-dwcmshc.c | 336 ++++++++++++++++++++++++++++++++++++ 1 file changed, 336 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index e68cd87998c8..d35e204cdb16 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -71,6 +71,63 @@ (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) #define RK35xx_MAX_CLKS 3 +/* T-Head specific registers */ +#define DWC_MSHC_PTR_PHY_R 0x300 +#define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) +#define PHY_RSTN 0x0 +#define PAD_SP 0x10 +#define PAD_SN 0x14 + +#define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) +#define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06) +#define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08) +#define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a) +#define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c) +#define RXSEL 0x0 +#define WEAKPULL_EN 0x3 +#define TXSLEW_CTRL_P 0x5 +#define TXSLEW_CTRL_N 0x9 + +#define PHY_PADTEST_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0e) +#define PHY_PADTEST_OUT_R (DWC_MSHC_PTR_PHY_R + 0x10) +#define PHY_PADTEST_IN_R (DWC_MSHC_PTR_PHY_R + 0x12) +#define PHY_PRBS_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x18) +#define PHY_PHYLBK_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1a) +#define PHY_COMMDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1c) + +#define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) +#define UPDATE_DC 0x4 + +#define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) +#define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20) +#define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) +#define INPSEL_CNFG 2 + +#define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) +#define DLL_EN 0x0 + +#define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25) +#define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26) +#define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28) +#define SLV_INPSEL 0x5 + +#define P_VENDOR_SPECIFIC_AREA 0x500 +#define EMMC_CTRL_R (P_VENDOR_SPECIFIC_AREA + 0x2c) +#define AT_CTRL_R (P_VENDOR_SPECIFIC_AREA + 0x40) +#define AT_EN 0x0 +#define CI_SEL 0x1 +#define SWIN_TH_EN 0x2 +#define RPT_TUNE_ERR 0x3 +#define SW_TUNE_EN 0x4 +#define WIN_EDGE_SEL 0x8 +#define TUNE_CLK_STOP_EN 0x10 +#define PRE_CHANGE_DLY 0x11 +#define POST_CHANGE_DLY 0x13 +#define SWIN_TH_VAL 0x18 + +#define DELAY_LINE_HS400 24 +#define DELAY_LINE_DEFAULT 50 + #define BOUNDARY_OK(addr, len) \ ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) @@ -91,6 +148,10 @@ struct dwcmshc_priv { struct clk *bus_clk; int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */ void *priv; /* pointer to SoC private stuff */ + uint32_t delay_line; + bool non_removable; + bool pull_up_en; + bool io_fixed_1v8; }; /* @@ -156,11 +217,171 @@ static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq) sdhci_request(mmc, mrq); } +static void sdhci_phy_1_8v_init_no_pull(struct sdhci_host *host) +{ + uint32_t val; + sdhci_writel(host, 1, DWC_MSHC_PTR_PHY_R); + sdhci_writeb(host, 1 << 4, PHY_SDCLKDL_CNFG_R); + sdhci_writeb(host, 0x40, PHY_SDCLKDL_DC_R); + + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &= ~(1 << 4); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + + val = sdhci_readw(host, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val | 1, PHY_CMDPAD_CNFG_R); + + val = sdhci_readw(host, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val | 1, PHY_DATAPAD_CNFG_R); + + val = sdhci_readw(host, PHY_RSTNPAD_CNFG_R); + sdhci_writew(host, val | 1, PHY_RSTNPAD_CNFG_R); + + val = sdhci_readw(host, PHY_STBPAD_CNFG_R); + sdhci_writew(host, val | 1, PHY_STBPAD_CNFG_R); + + val = sdhci_readb(host, PHY_DLL_CTRL_R); + sdhci_writeb(host, val | 1, PHY_DLL_CTRL_R); +} + +static void sdhci_phy_3_3v_init_no_pull(struct sdhci_host *host) +{ + uint32_t val; + + sdhci_writel(host, 1, DWC_MSHC_PTR_PHY_R); + sdhci_writeb(host, 1 << 4, PHY_SDCLKDL_CNFG_R); + sdhci_writeb(host, 0x40, PHY_SDCLKDL_DC_R); + + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &= ~(1 << 4); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + val = sdhci_readw(host, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val | 2, PHY_CMDPAD_CNFG_R); + + val = sdhci_readw(host, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val | 2, PHY_DATAPAD_CNFG_R); + + val = sdhci_readw(host, PHY_RSTNPAD_CNFG_R); + sdhci_writew(host, val | 2, PHY_RSTNPAD_CNFG_R); + + val = sdhci_readw(host, PHY_STBPAD_CNFG_R); + sdhci_writew(host, val | 2, PHY_STBPAD_CNFG_R); + + val = sdhci_readb(host, PHY_DLL_CTRL_R); + sdhci_writeb(host, val | 1, PHY_DLL_CTRL_R); +} + +static void th1520_phy_1_8v_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u32 val; + + if (!priv) + return; + + if (priv->pull_up_en == 0) { + sdhci_phy_1_8v_init_no_pull(host); + return; + } + + /* set driving force */ + sdhci_writel(host, (1 << PHY_RSTN) | (0xc << PAD_SP) | (0xc << PAD_SN), PHY_CNFG_R); + + /* disable delay lane */ + sdhci_writeb(host, 1 << UPDATE_DC, PHY_SDCLKDL_CNFG_R); + + /* set delay lane */ + sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); + sdhci_writeb(host, 0xa, PHY_DLL_CNFG2_R); + + /* enable delay lane */ + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &= ~(1 << UPDATE_DC); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + val = (1 << RXSEL) | (1 << WEAKPULL_EN) | (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val = (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val = (1 << RXSEL) | (2 << WEAKPULL_EN) | (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); + + /* enable data strobe mode */ + sdhci_writeb(host, 3 << SLV_INPSEL, PHY_DLLDL_CNFG_R); + sdhci_writeb(host, (1 << DLL_EN), PHY_DLL_CTRL_R); +} + +static void th1520_phy_3_3v_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u32 val; + + if (priv->pull_up_en == 0) { + sdhci_phy_3_3v_init_no_pull(host); + return; + } + + /* set driving force */ + sdhci_writel(host, (1 << PHY_RSTN) | (0xc << PAD_SP) | (0xc << PAD_SN), PHY_CNFG_R); + + /* disable delay lane */ + sdhci_writeb(host, 1 << UPDATE_DC, PHY_SDCLKDL_CNFG_R); + + /* set delay lane */ + sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); + sdhci_writeb(host, 0xa, PHY_DLL_CNFG2_R); + + /* enable delay lane */ + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &= ~(1 << UPDATE_DC); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + val = (2 << RXSEL) | (1 << WEAKPULL_EN) | (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val = (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val = (2 << RXSEL) | (2 << WEAKPULL_EN) | (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); +} + + +static void th1520_sdhci_set_phy(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u8 emmc_ctl; + + /* Before power on, set PHY configs */ + emmc_ctl = sdhci_readw(host, EMMC_CTRL_R); + if (priv->non_removable) { + th1520_phy_1_8v_init(host); + emmc_ctl |= (1 << DWCMSHC_CARD_IS_EMMC); + } else { + th1520_phy_3_3v_init(host); + emmc_ctl &=~(1 << DWCMSHC_CARD_IS_EMMC); + } + sdhci_writeb(host, emmc_ctl, EMMC_CTRL_R); + sdhci_writeb(host, 0x25, PHY_DLL_CNFG1_R); +} + static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u16 ctrl, ctrl_2; ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); @@ -188,7 +409,22 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, ctrl_2 |= DWCMSHC_CTRL_HS400; } + if (priv->io_fixed_1v8) + ctrl_2 |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + + /* TODO: add check so that this only runs on th1520 */ + if (timing == MMC_TIMING_MMC_HS400) { + /* disable auto tuning */ + u32 reg = sdhci_readl(host, AT_CTRL_R); + reg &= ~1; + sdhci_writel(host, reg, AT_CTRL_R); + priv->delay_line = DELAY_LINE_HS400; + th1520_sdhci_set_phy(host); + } else { + sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); + } } static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, @@ -337,6 +573,49 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_reset(host, mask); } +static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + u32 val = 0; + + sdhci_writeb(host, 3 << INPSEL_CNFG, PHY_ATDL_CNFG_R); + + val = sdhci_readl(host, AT_CTRL_R); + val &= ~((1 << CI_SEL) | (1 << RPT_TUNE_ERR) \ + | (1 << SW_TUNE_EN) |(0xf << WIN_EDGE_SEL)); + val |= (1 << AT_EN) | (1 << SWIN_TH_EN) | (1 << TUNE_CLK_STOP_EN)\ + | (1 << PRE_CHANGE_DLY) | (3 << POST_CHANGE_DLY) | (9 << SWIN_TH_VAL); + + sdhci_writel(host, val, AT_CTRL_R); + + val = sdhci_readl(host, AT_CTRL_R); + if(!(val & (1 << AT_EN))) { + pr_warn("%s(): auto tuning is not enabled", __func__); + return -1; + } + + val &= ~(1 << AT_EN); + sdhci_writel(host, val, AT_CTRL_R); + + return 0; +} + +static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u16 ctrl_2; + + sdhci_reset(host, mask); + + if(priv->io_fixed_1v8){ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if(! (ctrl_2 & SDHCI_CTRL_VDD_180)){ + ctrl_2 |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + } + } +} + static const struct sdhci_ops sdhci_dwcmshc_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -355,6 +634,17 @@ static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { .adma_write_desc = dwcmshc_adma_write_desc, }; +static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = { + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = dwcmshc_set_uhs_signaling, + .get_max_clock = dwcmshc_get_max_clock, + .reset = th1520_sdhci_reset, + .adma_write_desc = dwcmshc_adma_write_desc, + .voltage_switch = th1520_phy_1_8v_init, + .platform_execute_tuning = &th1520_execute_tuning, +}; + static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { .ops = &sdhci_dwcmshc_ops, .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, @@ -378,6 +668,15 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, }; +static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = { + .ops = &sdhci_dwcmshc_th1520_ops, + + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_BROKEN_DMA | + SDHCI_QUIRK_BROKEN_ADMA, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +}; + static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) { int err; @@ -434,6 +733,10 @@ static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv } static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + { + .compatible = "thead,th1520-dwcmshc", + .data = &sdhci_dwcmshc_th1520_pdata, + }, { .compatible = "rockchip,rk3588-dwcmshc", .data = &sdhci_dwcmshc_rk35xx_pdata, @@ -541,6 +844,39 @@ static int dwcmshc_probe(struct platform_device *pdev) goto err_clk; } + if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) { + + priv->delay_line = DELAY_LINE_DEFAULT; + + if (device_property_present(&pdev->dev, "non-removable")) + priv->non_removable = 1; + else + priv->non_removable = 0; + + if (device_property_present(&pdev->dev, "thead,pull-up")) + priv->pull_up_en = 1; + else + priv->pull_up_en = 0; + + if (device_property_present(&pdev->dev, "thead,io-fixed-1v8")) + priv->io_fixed_1v8 = true; + else + priv->io_fixed_1v8 = false; + + /* + * start_signal_voltage_switch() will try 3.3V first + * then 1.8V. Use SDHCI_SIGNALING_180 ranther than + * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V + * in sdhci_start_signal_voltage_switch(). + */ + if(priv->io_fixed_1v8){ + host->flags &=~SDHCI_SIGNALING_330; + host->flags |= SDHCI_SIGNALING_180; + } + + sdhci_enable_v4_mode(host); + } + #ifdef CONFIG_ACPI if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) sdhci_enable_v4_mode(host);