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Signed-off-by: Shengyu Qu --- arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi index b958607c71dc..7b784a87efc6 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi @@ -215,6 +215,7 @@ tps: tps@24 { baseboard_eeprom: baseboard_eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; + vcc-supply = <&ldo4_reg>; #address-cells = <1>; #size-cells = <1>; From patchwork Fri Aug 4 19:00:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengyu Qu X-Patchwork-Id: 131334 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp76952vqr; Fri, 4 Aug 2023 13:13:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG2sRE2AomacBuLFKerRfjLl2Q84ql7nk9m2FzbrxaPef/CiSVHSmEjRIxGhZl2fJCr7NhY X-Received: by 2002:ac2:5bd0:0:b0:4f8:7333:d1fd with SMTP id u16-20020ac25bd0000000b004f87333d1fdmr2050080lfn.34.1691179984097; Fri, 04 Aug 2023 13:13:04 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1691179984; cv=pass; d=google.com; s=arc-20160816; b=rLHGAFOGeCo0uInQcoTrc7CHltaVjjr28VCOQzSREIULXjEgzhS3bddUTb3PX/q2jM G0aURrmagZJ2V0s7cBN53jBjFQ1ig1U5sEm/zUuaAjPYAuxq6KAykEZyG0RjuhDdUtkv Y93VobyqqLHoE6vvRgklULvSLbkn4YmWfPnP0BauP6AD+jCWUCRQoBZ8d40JZubwBcQq sTheAW5KSBSpq8JYwikfY6ZqqYVR5nhexH2evv3GynF/QSz4Ml0HczeGMnDqZkQ52OEM VZIlAmgneG7PUljdrencZG72DRPTmZewLaDElvauMvz0RE9I8H6CAmutC0IjExA5VtLu b7KQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=s8TI+tvlhNrVHsn+FD1ijhrN3b/IZnhW7occY6VAdho=; fh=LWhVFwyMTIo+AznxEvDCCBSjnZDmdwAR8ebmf4Piqfo=; b=ntaGoKTaN52Gag4RPM9ZhEkzShdslnniTx9RAx66wlDGGXEk6l+RMjzILUYiMXkk9t wsX7XMl//G43nQX8mIVwy/VY45nvtNcoqu3x80DX2+XPFtlp4vyLRiBlwiZ485l6k6QR cJMxjPigKr6F7II6RUz4ywkPHPFooT5cO4mxcwUhdMQ8DaSzlziBZVp7zHNMuoyp+GS6 PvlDSo/k2o2GRtk71Ha4XMNljDT9e32XGwhwgaEAOc8skBOWsM/RLX33aPqO+1LIeNY+ PPFrI+qXavVsmYtwB7534QsYqWqov85SM5rpYaCws0nrro5IyTkfkyX6yD5ezYOfSx4l v9Ig== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@outlook.com header.s=selector1 header.b=RLqvnn5M; arc=pass (i=1); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=outlook.com Received: from out1.vger.email (out1.vger.email. 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Fri, 4 Aug 2023 19:01:26 +0000 Received: from TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM ([fe80::e67d:f61a:b248:f597]) by TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM ([fe80::e67d:f61a:b248:f597%3]) with mapi id 15.20.6652.022; Fri, 4 Aug 2023 19:01:26 +0000 From: Shengyu Qu To: bcousson@baylibre.com, tony@atomide.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Shengyu Qu , Robert Nelson Subject: [PATCH v1 2/2] ARM: dts: am335x-bone-common: Add GPIO PHY reset on revision C3 board Date: Sat, 5 Aug 2023 03:00:43 +0800 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804190042.2529-2-wiagn233@outlook.com> References: <20230804190042.2529-2-wiagn233@outlook.com> X-TMN: [r5pGem7VIyW+eYsyHYRfShvE+tAeVVCy] X-ClientProxiedBy: TYCP286CA0110.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:29c::17) To TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:23e::10) X-Microsoft-Original-Message-ID: <20230804190042.2529-4-wiagn233@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY3P286MB2611:EE_|TY3P286MB3567:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e5da0d8-48c7-46ce-c764-08db951d3409 X-MS-Exchange-SLBlob-MailProps: m1FWN9UA3JLuNowzViqllKXmXhrH/oplBgeKe00ICNr7HlZtIRPckprOc1kF8R8MUKAW9q3lPNuQcOCjDpqbU1Mlnj/lxDni/74g+W7OYlzBM+a3bBO5hz0rRKSpVKSw75RMa3Ck1YXTDN6h0V+NFRx4Wo9NexgN7eP0djaUB7iSnPfWNeA2he2ZND9xm8dhi5aCQkJQI5USS8i3w2Op9bT145Dgx0lm8yzaf/wxKTFhEN35yZtBMgY+rqXZ0C+zrieRUhoBCzlogu7AR5iZtWpv7WtAwHD2LcGDgacGMrmW+a3Hztp2wHQOksgV0qIZeaX8gese6Og507ek/0nAmWtfFU1ysaEqIsgLWMBqodiNUv7bTua6NgJWl3egYOKQfjUt2qn+ACf/GWvjbz/oOVJyOWYC3E6N2yzA+g7t1EDuKzAEvtyZrUuVDj0hG6RIy2s4KcabiEHjUfLTXFhvvTJlvdVo9GgZzf/iX5NKCdshNPdVlQWyuejGK05p58YNjywqYPZWwDxUDoVbvN+1nq0g+oEwSkOucD2cJojThthTOI5+uMEcbnv+av+fRA5d86dLHrQ9VJaoyarLcvHvRUDEY6YuzIyvKW4xkvVcKERjnHBlJ73JiTJ6r0hLM46fZ2LMyQlJEBcYoffy1rG9g+7oPeH6phmBFVIJO0KgPCJn4tx6XJZgW4CQ8g4myMW9rMRYw/pEvtA9lYgAZtfO37FAhhEkAqGyfdk+9WpWfH0S8eLgoMafpANZOE0q5ZA/kOIYfSjFmSm0DC2NyuNMHDJmoVvTOSfnwE5Dki+cpXqYWS7PZDhS1pTqriHS+lrdOPFgHZy1UMef1BB09Jrb34WXFN9v2FSaQVQNiFV6TcKSW1PK6ApokDx8e9AlemHQ X-Microsoft-Antispam: BCL:0; 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This fixes a random phy startup failure bug discussed at [1]. The GPIO pin used for reset is not used on older revisions, so it is ok to apply to all board revisions. The reset timing was discussed and tested at [2]. [1] https://forum.digikey.com/t/ethernet-device-is-not-detecting-on-ubuntu-20-04-lts-on-bbg/19948 [2] https://forum.beagleboard.org/t/recognizing-a-beaglebone-black-rev-c3-board/31249/ Signed-off-by: Robert Nelson Signed-off-by: Shengyu Qu --- arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi index 7b784a87efc6..943d40fe2272 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi @@ -145,6 +145,8 @@ davinci_mdio_default: davinci-mdio-default-pins { /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + /* added to support GPIO controlled PHY reset */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE7) >; }; @@ -153,6 +155,8 @@ davinci_mdio_sleep: davinci-mdio-sleep-pins { /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + /* added to support GPIO controlled PHY reset */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; @@ -378,6 +382,10 @@ &davinci_mdio_sw { ethphy0: ethernet-phy@0 { reg = <0>; + // Support GPIO Reset on Rev C3 boards + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <300>; + reset-deassert-us = <6500>; }; };