From patchwork Fri Aug 4 17:08:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 131293 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp14311vqr; Fri, 4 Aug 2023 11:08:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHV4K9tX0TCAeAtD7o+ysPeZOsU4YZ7cYPOYvMxNdLppuoA31gDL42cYA6mWdVHuzKPJ7BT X-Received: by 2002:a17:902:b70e:b0:1bc:16bc:9f66 with SMTP id d14-20020a170902b70e00b001bc16bc9f66mr2699591pls.12.1691172538788; Fri, 04 Aug 2023 11:08:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691172538; cv=none; d=google.com; s=arc-20160816; b=VevZlKI4cJu7P6HMf7m87+qKSGp/flmAR837ux84rz8iaWfAby/gA0gSn2mrAjZHjy f/ay8W9aVWECmu8bWDntpB5WeuyqKi4GDDIbTaSIH1xl5v4+DvRgdDiCjECG11dznEI+ jxWiaE5tooWJPowGlOQdYCyDjpIeviwwBvAPD+Fvh+dW5FHPetHpdwGfYs2OI59N47Md lIkspZ53k61emGa3D4c/JW/dUJgVbPPSz1ZnmIk73Qbn1bHDdVqzEs9pmfQoTMu5RKT0 /jMRVnc//ods+wbsxXs79qDUVhpYlm56CPNl1oubmEF8dTX+FtEDaH/UIX986gteNOKb oYHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=oMaSpks2Xsjfcb4on0YgE81gmEIZ5HhkH7PhMDTtmN4=; fh=nThKA2TXpGJpfakb/DZinRN0V3NZQat6wKjbKP0xDlY=; b=NRtmP49DFw6giKxHFkzkZpPKzKUSz4NHyR3wul3eHxMxJ/mpLiiBhL5ZORcRFA//Dd oZttNPiaGo20rJZkzw17vwT5PEk+Sa9V1FnB9PLGJHPSvPDWW+qaTSox+glfCmiIXl+p 6dfZ/4TmXbHypi8j/2/g/t/CU7KGzTHxyDH2gUkkLranCJGSfik0J+FnaT0YTT7E0sqR vGk2mhFXrGC6BfhD8QjvfcTb5RPvvAJwBY8mWJWuyFepJiLXLpP/dFxwZxtdvBnJ8HXV dz1yBYV6yzQmht1z9jB3NJgK0njOUmv++UyzKa6XmmYhCpLSmjeIf45SL8l/D3NqD0Ul ITPQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f2-20020a170902ce8200b001b85ab48092si2167595plg.499.2023.08.04.11.08.45; Fri, 04 Aug 2023 11:08:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232137AbjHDRJ1 (ORCPT + 99 others); Fri, 4 Aug 2023 13:09:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231925AbjHDRJS (ORCPT ); Fri, 4 Aug 2023 13:09:18 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 11E3E4C2F; Fri, 4 Aug 2023 10:09:09 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 784A4113E; Fri, 4 Aug 2023 10:09:51 -0700 (PDT) Received: from donnerap.arm.com (donnerap.manchester.arm.com [10.32.100.58]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1B20F3F5A1; Fri, 4 Aug 2023 10:09:07 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Icenowy Zheng , Piotr Oniszczuk , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT Date: Fri, 4 Aug 2023 18:08:54 +0100 Message-Id: <20230804170856.1237202-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230804170856.1237202-1-andre.przywara@arm.com> References: <20230804170856.1237202-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773322935717638589 X-GMAIL-MSGID: 1773322935717638589 The Orange Pi Zero 2 got a successor (Zero 3), which shares quite some DT nodes with the Zero 2, but comes with a different PMIC. Move the common parts (except the PMIC) into a new shared file, and include that from the existing board .dts file. No functional change, the generated DTB is the same, except for some phandle numbering differences. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- .../allwinner/sun50i-h616-orangepi-zero.dtsi | 134 ++++++++++++++++++ .../allwinner/sun50i-h616-orangepi-zero2.dts | 119 +--------------- 2 files changed, 135 insertions(+), 118 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi new file mode 100644 index 0000000000000..8788c129b2887 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + * + * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3. + * Excludes PMIC nodes and properties, since they are different between the two. + */ + +#include "sun50i-h616.dtsi" + +#include +#include +#include + +/ { + aliases { + ethernet0 = &emac0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + }; +}; + +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts index cb8600d0ea1ef..d6e732b12c52d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -5,95 +5,19 @@ /dts-v1/; -#include "sun50i-h616.dtsi" - -#include -#include -#include +#include "sun50i-h616-orangepi-zero.dtsi" / { model = "OrangePi Zero2"; compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; - - aliases { - ethernet0 = &emac0; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = ; - gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ - default-state = "on"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_vcc5v>; - enable-active-high; - gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ - }; }; -&ehci1 { - status = "okay"; -}; - -/* USB 2 & 3 are on headers only. */ - &emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; phy-supply = <®_dcdce>; - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; - status = "okay"; -}; - -&mdio0 { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; }; &mmc0 { vmmc-supply = <®_dcdce>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; }; &r_rsb { @@ -211,44 +135,3 @@ &pio { vcc-ph-supply = <®_aldo1>; vcc-pi-supply = <®_aldo1>; }; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; From patchwork Fri Aug 4 17:08:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 131277 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:1a9a:b0:139:fa0d:b2d with SMTP id gm26csp96551rwb; Fri, 4 Aug 2023 10:38:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG/RukiNEIbjoDfW05ndOKTm4Aygm8/LishFgf6nQfEClxLkohEp+xy9kCWciwlenIGyUuj X-Received: by 2002:a05:6a00:1a54:b0:687:907f:487c with SMTP id h20-20020a056a001a5400b00687907f487cmr2743219pfv.19.1691170725713; Fri, 04 Aug 2023 10:38:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691170725; cv=none; d=google.com; s=arc-20160816; b=h3CQmQhsqXCijmZ/3cJ22NsnaMFfkCkBE1wCOl/zlV0afxSfw4ZcEMUQ2JQdl3F0o5 WQ0oXHhYIQ9+S6N3ePA4oKShdpEEbVnzKKAJESAik/ECrU+Rw+WK0cgwVebxS5hzKu5G NWHepilumtnNHP2gXwZpEUbdnBs8xux/5iSqRjSHoQhKzc+Uo7pIZXWE6ZDUV21nW1Cp XFBNr2dLkfYvJsY/MKClMbdZh3HsNWg/o96IOFLkTsqcg6X3D2x0U1ELl1txmvZSdl79 7nIylhzl707O3uWy7UQNL5EunRvbSNulg6kcpbGODRz9g3lnE/NNEgkrDWNr2z2d7ilE f2+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=4A9M/0Th40B7aD9GQa0+t3teNWcx9Zh83LfoIJr9q/0=; fh=nThKA2TXpGJpfakb/DZinRN0V3NZQat6wKjbKP0xDlY=; b=cWoyru+S2dAQcMranZrRf72wAvib9O7IAAlGKWVsh2oIrj/HeGBDN+n5ILazZOJB0F pkjiZaJ+85XacGEwIO/lIJWWfrxRRFVnDFaNz/I51vnQjyyYfOzwgcbdeVG1EjHWcKPS n1tXSyGz7Zyqy/J6XG6rClAz0yg2MtE96wbvjzTCwc9ILdIEyqB/YlghNQY/VL0tO3ju JwX8f4qkDudXtWaa1Be8WgNkbuCtXW60iW2sCONxpLUKIKPWLW7oaNdh3up0d100Vc6N 63g7QV34/Quas0V4FgkSttlSRzrT95Nh9EbTPxUoslsSFta4Ppc5Vrk+EF76+lS41qCR a/nQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id fa19-20020a056a002d1300b00687072296edsi2047356pfb.149.2023.08.04.10.38.32; Fri, 04 Aug 2023 10:38:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232169AbjHDRJa (ORCPT + 99 others); Fri, 4 Aug 2023 13:09:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231872AbjHDRJW (ORCPT ); Fri, 4 Aug 2023 13:09:22 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EDD0E4EC4; Fri, 4 Aug 2023 10:09:10 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4131E12FC; Fri, 4 Aug 2023 10:09:53 -0700 (PDT) Received: from donnerap.arm.com (donnerap.manchester.arm.com [10.32.100.58]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F31F83F5A1; Fri, 4 Aug 2023 10:09:08 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Icenowy Zheng , Piotr Oniszczuk , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] dt-bindings: arm: sunxi: document Orange Pi Zero 3 board name Date: Fri, 4 Aug 2023 18:08:55 +0100 Message-Id: <20230804170856.1237202-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230804170856.1237202-1-andre.przywara@arm.com> References: <20230804170856.1237202-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773321035023663227 X-GMAIL-MSGID: 1773321035023663227 The Orange Pi Zero 3 board is an updated version of the Zero 2 board. It uses a SoC called H618, which just seems to be an H616 with more L2 cache. Add the board/SoC compatible string pair to the list of known boards. Signed-off-by: Andre Przywara Reviewed-by: Krzysztof Kozlowski Acked-by: Jernej Skrabec --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ee8fdd2da869a..58f322b9585f2 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -997,4 +997,9 @@ properties: - const: xunlong,orangepi-zero2 - const: allwinner,sun50i-h616 + - description: Xunlong OrangePi Zero 3 + items: + - const: xunlong,orangepi-zero3 + - const: allwinner,sun50i-h618 + additionalProperties: true From patchwork Fri Aug 4 17:08:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 131302 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp38922vqr; Fri, 4 Aug 2023 11:59:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGEXxs9ntuE7a50KtIUxtOIOch56K0hRzIOWtsUDUGHzIb5KkhdR5u8y9WIYYkJ1Jj1s8Jg X-Received: by 2002:a17:907:a073:b0:988:8be0:3077 with SMTP id ia19-20020a170907a07300b009888be03077mr2183216ejc.31.1691175548271; Fri, 04 Aug 2023 11:59:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691175548; cv=none; d=google.com; s=arc-20160816; b=dOcc4t2TWPTKDJJCNhUWWCJ0yLCbg3kQeKV6XaiOK5IPS4RvenR7aMqnwsMjEZwWNn 5IUrveOcPq2GBcLDFkdTXlEGB6Mw5PqaVt0HlPA4gllFP/0DzU2ZVLYdEWLlPVUyJdbP uRkRb7m1SSQ1s9EKpUtQ1GbBCc82ITlEugZBG2edsiM4R5VuE6yK6rwBxvworlcbDFL9 mTs+xtf+z5PNgQ4JGawfEvjpMgCvMGNRNXRegkEF4JNpunYcGxjFDD78hpLNQrkCTq0Z OOme76QxSWmNuoZA5DZEyPRcUEP49w3tOuluZnYPU4kH4S4V66OCI9xFf20RxtQxRyQ4 Xuvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Qv9xYCKglKwlbXzPz5PgR0Y3hcGtT3P8FsbyLNZZAOU=; fh=nThKA2TXpGJpfakb/DZinRN0V3NZQat6wKjbKP0xDlY=; b=L8hx+5MADGbBP8h4N7ky/X2rI6iax4K0wMe38He6o07MA9IFfx8sfBWOkMYXajnX8Y 7+8OJIZfLM8XI5v0SXfCDT9TjtqEP/dOBO5lwOKdjn/BDrTYGNDsQP8m+nYuECZOmHKS updDhTBqGS4093DOi6XfqNBmFLjR7CmeIn5rLtw3Z8BVa7MNIWTJIN8zgVZRZJQiGNyC dsK3hAO1rZmAxGxah4eNkHoPoNLeAVMb8CXGDHnLzs8cF/iHmkcaCEa7FwaZ0bBuL2fe no5HMr1qL5HCfQjPppjWmzFHLPdlOcuz0Hi1TcjLPcNKeBEE4FW/69ISwhYxQ/K1gNUs gbSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e10-20020a170906248a00b0099caf50c27fsi519997ejb.1046.2023.08.04.11.58.44; Fri, 04 Aug 2023 11:59:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232080AbjHDRJi (ORCPT + 99 others); Fri, 4 Aug 2023 13:09:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231954AbjHDRJY (ORCPT ); Fri, 4 Aug 2023 13:09:24 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CEB924ECD; Fri, 4 Aug 2023 10:09:12 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0A37814BF; Fri, 4 Aug 2023 10:09:55 -0700 (PDT) Received: from donnerap.arm.com (donnerap.manchester.arm.com [10.32.100.58]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BC27E3F5A1; Fri, 4 Aug 2023 10:09:10 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Icenowy Zheng , Piotr Oniszczuk , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] arm64: dts: allwinner: h616: Add OrangePi Zero 3 board support Date: Fri, 4 Aug 2023 18:08:56 +0100 Message-Id: <20230804170856.1237202-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230804170856.1237202-1-andre.przywara@arm.com> References: <20230804170856.1237202-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773326091482986209 X-GMAIL-MSGID: 1773326091482986209 The OrangePi Zero 3 is a development board based on the Allwinner H618 SoC, which seems to be just an H616 with more L2 cache. The board itself is a slightly updated version of the Orange Pi Zero 2. It features: - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU - 1/1.5/2/4 GiB LPDDR4 DRAM SKUs (only up to 1GB on the Zero2) - AXP313a PMIC (more capable AXP305 on the Zero2) - Raspberry-Pi-1 compatible GPIO header - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports - 1 USB 2.0 host port - 1 USB 2.0 type C port (power supply + OTG) - MicroSD slot - on-board 16MiB bootable SPI NOR flash (only 2MB on the Zero2) - 1Gbps Ethernet port (via Motorcomm YT8531 PHY) (RTL8211 on the Zero2) - micro-HDMI port - (yet) unsupported Allwinner WiFi/BT chip Add the devicetree file describing the currently supported features, namely LEDs, SD card, PMIC, SPI flash, USB. Ethernet seems unstable at the moment, though the basic functionality works. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun50i-h618-orangepi-zero3.dts | 94 +++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 6a96494a2e0a3..3b0ad54062381 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts new file mode 100644 index 0000000000000..96a6851728111 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2023 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616-orangepi-zero.dtsi" + +/ { + model = "OrangePi Zero3"; + compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; +}; + +&emac0 { + phy-supply = <®_dldo1>; +}; + +&ext_rgmii_phy { + motorcomm,clk-out-frequency-hz = <125000000>; +}; + +&mmc0 { + /* + * The schematic shows the card detect pin wired up to PF6, via an + * inverter, but it just doesn't work. + */ + broken-cd; + vmmc-supply = <®_dldo1>; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL, so needs to be always on. */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +};