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Fri, 4 Aug 2023 00:28:59 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 66C7A66071BA; Fri, 4 Aug 2023 08:28:57 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691134138; bh=yEFNmriytfzFlnNR03nQnEhTvtOxc2/EEUJg2NG5628=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f9ioAsocMMQMJlAWukV5oFwbeEBSz6Hq/4lBQkiaAfOHyeqcnhOCgU1OgvshwsQuL P6YpwrqDRtaqvkXAZehl4vLg6Td6GwF0YKQF6ZzwmcULNYyvRYgX5pwJjUnZKIPihe vDXeDq0B6ITXqfYmNe0x7ZpS1XFsXvyUIlTMAY3YEjo6SAJFBAU+egiv9mS0Ma/BKR x+aq+TLIluOES8ZTQhhlX0h9HhcBTDLh9hdAzCuR58DOg+FqdLOdUVvsbxMRaAYvvo DZPCLU8svq6we7RM7+JMnJoX5jHY8JjqybKi/onI/60mvhqoAwRPHkOOa2wHm2YnDW wyj36ecMD9JEw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH.Lin" , Alexandre Mergnat Subject: [PATCH v10 01/16] drm/mediatek: gamma: Adjust mtk_drm_gamma_set_common parameters Date: Fri, 4 Aug 2023 09:28:35 +0200 Message-ID: <20230804072850.89365-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773285770304516191 X-GMAIL-MSGID: 1773285770304516191 From: "Jason-JH.Lin" Adjust the parameters in mtk_drm_gamma_set_common() - add (struct device *dev) to get lut_diff from gamma's driver data - remove (bool lut_diff) and use false as default value in the function Signed-off-by: Jason-JH.Lin Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 18 ++++++++++++------ 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index cdbec79474d1..2f602f1f1c49 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -66,7 +66,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) struct mtk_disp_aal *aal = dev_get_drvdata(dev); if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(aal->regs, state, false); + mtk_gamma_set_common(NULL, aal->regs, state); } void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 2254038519e1..75045932353e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -54,7 +54,7 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool lut_diff); +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 7746dceadb20..d42cc0698d83 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -54,14 +54,24 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool lut_diff) +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { + struct mtk_disp_gamma *gamma; unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; + bool lut_diff; u32 word; u32 diff[3] = {0}; + /* If we're called from AAL, dev is NULL */ + gamma = dev ? dev_get_drvdata(dev) : NULL; + + if (gamma && gamma->data) + lut_diff = gamma->data->lut_diff; + else + lut_diff = false; + if (state->gamma_lut) { reg = readl(regs + DISP_GAMMA_CFG); reg = reg | GAMMA_LUT_EN; @@ -91,12 +101,8 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); - bool lut_diff = false; - - if (gamma->data) - lut_diff = gamma->data->lut_diff; - mtk_gamma_set_common(gamma->regs, state, lut_diff); + mtk_gamma_set_common(dev, gamma->regs, state); } void mtk_gamma_config(struct device *dev, unsigned int w, From patchwork Fri Aug 4 07:28:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131013 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp115401vqb; Fri, 4 Aug 2023 01:39:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGyY6dvjm3e1gEXsnhj5PN5fJUyMt9Id5PR6CI/47haXWiCsb7BmvevrpPLIYVcV5b8UZEW X-Received: by 2002:a05:6512:3c9f:b0:4f9:5196:5ed0 with SMTP id h31-20020a0565123c9f00b004f951965ed0mr1062512lfv.7.1691138394395; Fri, 04 Aug 2023 01:39:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691138394; cv=none; d=google.com; s=arc-20160816; b=Rpf7HhSmJH6zumPScSsX9A2i7eWSQh4R99bhBBA6aIWgLkCc2DSMQImjdlXyjyWev5 3ToARPpofsoWHPtCNvipB9Aig9BGHYGt5yr49bcGqJ1/+7FIZKbqyjuY/P1v70dr9NJC E9x4roLalFNTsImOs6r0PzZZq21N0M9yaAvu1Llz3v4gmznsK4UJjhZLwI5y3+jfv409 Ug4tGtjcQFUDalfr30vj2nRnomd5TcTRVfnYfVXhONoiVmrVFbLk460bQxrUaQg+CtVI nrziNhDzOvb8F6nwAgDjSMl0s2L6dUtXbZjQ3pgdDpGM54UUlcZx8ucA4im+GKTgzfz3 5R/g== ARC-Message-Signature: i=1; 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Lin" , Alexandre Mergnat Subject: [PATCH v10 02/16] drm/mediatek: gamma: Reduce indentation in mtk_gamma_set_common() Date: Fri, 4 Aug 2023 09:28:36 +0200 Message-ID: <20230804072850.89365-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773287133081637432 X-GMAIL-MSGID: 1773287133081637432 Invert the check for state->gamma_lut and move it at the beginning of the function to reduce indentation: this prepares the code for keeping readability on later additions. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 45 ++++++++++++----------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index d42cc0698d83..47751864bd5c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -64,6 +64,10 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt u32 word; u32 diff[3] = {0}; + /* If there's no gamma lut there's nothing to do here. */ + if (!state->gamma_lut) + return; + /* If we're called from AAL, dev is NULL */ gamma = dev ? dev_get_drvdata(dev) : NULL; @@ -72,29 +76,26 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt else lut_diff = false; - if (state->gamma_lut) { - reg = readl(regs + DISP_GAMMA_CFG); - reg = reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); - lut_base = regs + DISP_GAMMA_LUT; - lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < MTK_LUT_SIZE; i++) { - - if (!lut_diff || (i % 2 == 0)) { - word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); - } else { - diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); - - word = ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); - } - writel(word, (lut_base + i * 4)); + reg = readl(regs + DISP_GAMMA_CFG); + reg = reg | GAMMA_LUT_EN; + writel(reg, regs + DISP_GAMMA_CFG); + lut_base = regs + DISP_GAMMA_LUT; + lut = (struct drm_color_lut *)state->gamma_lut->data; + for (i = 0; i < MTK_LUT_SIZE; i++) { + if (!lut_diff || (i % 2 == 0)) { + word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + + ((lut[i].blue >> 6) & LUT_10BIT_MASK); + } else { + diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); + diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); + diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + + word = ((diff[0] & LUT_10BIT_MASK) << 20) + + ((diff[1] & LUT_10BIT_MASK) << 10) + + (diff[2] & LUT_10BIT_MASK); } + writel(word, (lut_base + i * 4)); } } From patchwork Fri Aug 4 07:28:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131014 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp115631vqb; Fri, 4 Aug 2023 01:40:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEWe6xpdBSH/1iOEY+Gphki8PlV+ax1BO4rTeleR3wWC7WO80IqRMDFh7Ed0eXKTpEmJOV9 X-Received: by 2002:a05:6402:3d0:b0:523:e25:c33c with SMTP id t16-20020a05640203d000b005230e25c33cmr943636edw.41.1691138430080; Fri, 04 Aug 2023 01:40:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691138430; cv=none; d=google.com; s=arc-20160816; b=SzADqhGrHk9twmX8EBnuFpkt5Mw/9We3/ody5G2U/V3KZMzHcuOAQlH6jxUTH4ShOR GArP7N2ATQ2tf/0vQ171SCCSaK0kdg4P69RgZDe+M/wjiTUUqZK2oZHFa9LuJS/yU71s 8koAZjlSqc1DwrsvtxXg13LzMO20Sz7bvtveskRJheiPY8ilfYMRb4o60r5oib0QSL8X 0SAgpUevyYuHT57/Ylh2Ke4JVU1+SERtqNgLXmpI1EHHDuHYNrFkqd4tGzsjMh7HwWs3 1QLPS9gccDQI07GWpD/LxrM/4fOxvLQQBRCYf6lyJLWytkNlGLE/4t7dhZaaeJxVhPpH bkww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MY9lb1xK+lPvmtApb4D05N5/rllUxBXNetH8DwmCWro=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=JJo6sJEruREfIFm5fGd9TQAeRQt75tua70blbd6eVvc3Y/JNZdExiwJs+AmBVpZh1w AOVcoWm1MDsbWfA2h5RLD8d8QTi7jjEakwaI0dhcYb5m5EzdIxE1qCpzeL9eWSyMi6mL ITKgeLZGt3psmb8duPfdHMwCZHlC4tDztDBmMdhmetf42s6BcIhkfbG8Bfb0spi/TI61 Clf4me6QWmsP+jomMon1BMeSBBP73cXp9wNrcT7U7v3TCglf48lp26AYKmQlAIylZ/Zi E3J0rYfW8jfpIzNm5XY6hz3fF0EwlRq+0rkldvzggNJzJRSAfd+56NQxfnbD3PxUWx60 8m3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=ODT9G6xS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v10 03/16] drm/mediatek: gamma: Support SoC specific LUT size Date: Fri, 4 Aug 2023 09:28:37 +0200 Message-ID: <20230804072850.89365-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773287170551972195 X-GMAIL-MSGID: 1773287170551972195 Newer SoCs support a bigger Gamma LUT table: wire up a callback to retrieve the correct LUT size for each different Gamma IP. Co-developed-by: Jason-JH.Lin Signed-off-by: Jason-JH.Lin [Angelo: Rewritten commit message/description + porting] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 17 ++++++++++++++- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 ++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 23 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 8 +++++-- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 - drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 ++++++++ 7 files changed, 55 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index 2f602f1f1c49..e2e4155faf01 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -19,7 +19,7 @@ #define AAL_EN BIT(0) #define DISP_AAL_SIZE 0x0030 #define DISP_AAL_OUTPUT_SIZE 0x04d8 - +#define DISP_AAL_LUT_SIZE 512 struct mtk_disp_aal_data { bool has_gamma; @@ -61,6 +61,21 @@ void mtk_aal_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); } +/** + * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL + * @dev: Pointer to struct device + * + * Return: 0 if gamma control not supported in AAL or gamma LUT size + */ +unsigned int mtk_aal_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_aal *aal = dev_get_drvdata(dev); + + if (aal->data && aal->data->has_gamma) + return DISP_AAL_LUT_SIZE; + return 0; +} + void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_aal *aal = dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 75045932353e..ca377265e5eb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -17,6 +17,7 @@ void mtk_aal_clk_disable(struct device *dev); void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_aal_gamma_get_lut_size(struct device *dev); void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_aal_start(struct device *dev); void mtk_aal_stop(struct device *dev); @@ -53,6 +54,7 @@ void mtk_gamma_clk_disable(struct device *dev); void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 47751864bd5c..7575237625d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -24,10 +24,12 @@ #define DISP_GAMMA_LUT 0x0700 #define LUT_10BIT_MASK 0x03ff +#define LUT_SIZE_DEFAULT 512 struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_size; }; /* @@ -54,6 +56,15 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } +unsigned int mtk_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + if (gamma && gamma->data) + return gamma->data->lut_size; + return LUT_SIZE_DEFAULT; +} + void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma; @@ -61,6 +72,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; + u16 lut_size; u32 word; u32 diff[3] = {0}; @@ -71,17 +83,20 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt /* If we're called from AAL, dev is NULL */ gamma = dev ? dev_get_drvdata(dev) : NULL; - if (gamma && gamma->data) + if (gamma && gamma->data) { lut_diff = gamma->data->lut_diff; - else + lut_size = gamma->data->lut_size; + } else { lut_diff = false; + lut_size = LUT_SIZE_DEFAULT; + } reg = readl(regs + DISP_GAMMA_CFG); reg = reg | GAMMA_LUT_EN; writel(reg, regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < MTK_LUT_SIZE; i++) { + for (i = 0; i < lut_size; i++) { if (!lut_diff || (i % 2 == 0)) { word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + @@ -198,10 +213,12 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { .lut_diff = true, + .lut_size = 512, }; static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 8a43656ecc30..ebe0cc3a1a4c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -959,8 +959,12 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, mtk_crtc->ddp_comp[i] = comp; if (comp->funcs) { - if (comp->funcs->gamma_set) - gamma_lut_size = MTK_LUT_SIZE; + if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) { + unsigned int lut_sz = mtk_ddp_gamma_get_lut_size(comp); + + if (lut_sz) + gamma_lut_size = lut_sz; + } if (comp->funcs->ctm_set) has_ctm = true; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h index 3e9046993d09..b2e50292e57d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -10,7 +10,6 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_plane.h" -#define MTK_LUT_SIZE 512 #define MTK_MAX_BPC 10 #define MTK_MIN_BPC 3 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index f114da4d36a9..f3212e08f2cd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -271,6 +271,7 @@ static void mtk_ufoe_start(struct device *dev) static const struct mtk_ddp_comp_funcs ddp_aal = { .clk_enable = mtk_aal_clk_enable, .clk_disable = mtk_aal_clk_disable, + .gamma_get_lut_size = mtk_aal_gamma_get_lut_size, .gamma_set = mtk_aal_gamma_set, .config = mtk_aal_config, .start = mtk_aal_start, @@ -322,6 +323,7 @@ static const struct mtk_ddp_comp_funcs ddp_dsi = { static const struct mtk_ddp_comp_funcs ddp_gamma = { .clk_enable = mtk_gamma_clk_enable, .clk_disable = mtk_gamma_clk_disable, + .gamma_get_lut_size = mtk_gamma_get_lut_size, .gamma_set = mtk_gamma_set, .config = mtk_gamma_config, .start = mtk_gamma_start, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index febcaeef16a1..c1355960e195 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -67,6 +67,7 @@ struct mtk_ddp_comp_funcs { void (*layer_config)(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); + unsigned int (*gamma_get_lut_size)(struct device *dev); void (*gamma_set)(struct device *dev, struct drm_crtc_state *state); void (*bgclr_in_on)(struct device *dev); @@ -186,6 +187,14 @@ static inline void mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp, comp->funcs->layer_config(comp->dev, idx, state, cmdq_pkt); } +static inline unsigned int mtk_ddp_gamma_get_lut_size(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->gamma_get_lut_size) + return comp->funcs->gamma_get_lut_size(comp->dev); + + return 0; +} + static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { From patchwork Fri Aug 4 07:28:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 130995 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp90068vqb; Fri, 4 Aug 2023 00:35:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHZzxitLWmtdv99QGVinyxfCx9Yi+7izbLMPbzXcZoeGnf5JEEB3ZJ852ry16Sn7YYiuo9C X-Received: by 2002:a05:6a20:1588:b0:13f:87ce:80f1 with SMTP id h8-20020a056a20158800b0013f87ce80f1mr1281418pzj.52.1691134511736; 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Lin" , Alexandre Mergnat Subject: [PATCH v10 04/16] drm/mediatek: gamma: Improve and simplify HW LUT calculation Date: Fri, 4 Aug 2023 09:28:38 +0200 Message-ID: <20230804072850.89365-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773283062096680047 X-GMAIL-MSGID: 1773283062096680047 Use drm_color_lut_extract() to avoid open-coding the bits reduction calculations for each color channel and use a struct drm_color_lut to temporarily store the information instead of an array of u32. Also, slightly improve the precision of the HW LUT calculation in the LUT DIFF case by performing the subtractions on the 16-bits values and doing the 10 bits conversion later. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 30 +++++++++++++++-------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 7575237625d2..fd6a75a64a9f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -74,7 +74,6 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt bool lut_diff; u16 lut_size; u32 word; - u32 diff[3] = {0}; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -97,18 +96,29 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; for (i = 0; i < lut_size; i++) { + struct drm_color_lut diff, hwlut; + + hwlut.red = drm_color_lut_extract(lut[i].red, 10); + hwlut.green = drm_color_lut_extract(lut[i].green, 10); + hwlut.blue = drm_color_lut_extract(lut[i].blue, 10); + if (!lut_diff || (i % 2 == 0)) { - word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); + word = hwlut.red << 20 + + hwlut.green << 10 + + hwlut.red; } else { - diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + diff.red = lut[i].red - lut[i - 1].red; + diff.red = drm_color_lut_extract(diff.red, 10); + + diff.green = lut[i].green - lut[i - 1].green; + diff.green = drm_color_lut_extract(diff.green, 10); + + diff.blue = lut[i].blue - lut[i - 1].blue; + diff.blue = drm_color_lut_extract(diff.blue, 10); - word = ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); + word = diff.blue << 20 + + diff.green << 10 + + diff.red; } writel(word, (lut_base + i * 4)); } From patchwork Fri Aug 4 07:28:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131016 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp117686vqb; Fri, 4 Aug 2023 01:45:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFuWQWZ0VDyn0KhY2XTC7+aNKtbd/JhJcVzHQJ1HgNfAMpgY10MUkAU6Q49V8xbUhSHqX/L X-Received: by 2002:a05:6a20:a124:b0:12e:caac:f263 with SMTP id q36-20020a056a20a12400b0012ecaacf263mr1563210pzk.20.1691138750439; Fri, 04 Aug 2023 01:45:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691138750; cv=none; d=google.com; s=arc-20160816; b=RIPOumCyrG4Wa0XYBmJMqQZRrWX0u+D/MmOkLkA6Br/WP2I16/S8WXPPWOPatpMy1k GFLIIp6+Sc/hMPgbDyaA2t0kCkLZNL1Yyx/M7lYcnucIlX/NLu+J9fwQId3nb4EyUeUJ RGv8T5ONX5CoiaxjdrabYeB9BgFW5LLb7Hhi+pxBf6wMFw/T1X0YXqiEUY1F1fvRBJDL egXHs36m80AYWoWhcwmtuZcSBnzIB0Zske/gnm8lytwH7THkjrPeWOsGepcR5J3nKfOS gkovmqtZfTSWJI0xI6ae2P/n1gk0rxSFv3DXPYq/Oo985ftTtT3g9/90+COPL7OAm/Yk nsIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dm6Nc3M0XahRr5SgCwL2z7cNin/dAvbdfmHjVdvJV98=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=HK20Sccgh/OycgTRfGF2dtHlFYWXtg/5dmn+pJwHG76emtCWnANRXO7AB8EyBP6Cy2 fZPdQyUQdAsW4Z1ktfe5lCT00Cti2vD7qEp+prjgX4LTH3Bg0slJxYHd88k91qjT5/qL zx6UfNHzmXPNXCb3iC/18X+4Dfc+Sdj+ju/wZ2MpOiM68XNFkB0P67ibR3AwbQ7FbOBR G8rahn/zCUwfETx8bWbB0cZnZS4BdyMsfWcCUXLQwHsap6/kmv3PSqOAQbAf+wTzYyJY 2JqjmdyEgbeH1rjifOproAIask1uFI5+efgVhZmOFuSBqbGfQ2mWOxtOkgUqLPupCMyD lFsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=VhvKyaSd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v10 05/16] drm/mediatek: gamma: Enable the Gamma LUT table only after programming Date: Fri, 4 Aug 2023 09:28:39 +0200 Message-ID: <20230804072850.89365-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773287506009106186 X-GMAIL-MSGID: 1773287506009106186 Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after programming the actual table to avoid potential visual glitches during table modification. Note: GAMMA should get enabled in between vblanks, but this requires many efforts in order to make this happen, as that requires migrating all of the writes to make use of CMDQ instead of cpu writes and that's not trivial. For this reason, this patch only moves the LUT enable. The CMDQ rework will come at a later time. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index fd6a75a64a9f..18b102bef370 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -68,12 +68,12 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma; - unsigned int i, reg; + unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; u16 lut_size; - u32 word; + u32 cfg_val, word; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -90,9 +90,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt lut_size = LUT_SIZE_DEFAULT; } - reg = readl(regs + DISP_GAMMA_CFG); - reg = reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); + cfg_val = readl(regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; for (i = 0; i < lut_size; i++) { @@ -122,6 +120,11 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt } writel(word, (lut_base + i * 4)); } + + /* Enable the gamma table */ + cfg_val = cfg_val | GAMMA_LUT_EN; + + writel(cfg_val, regs + DISP_GAMMA_CFG); } void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) From patchwork Fri Aug 4 07:28:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131020 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp118293vqb; Fri, 4 Aug 2023 01:47:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFQnGcZMexC3IjxyTdk+AyRH0slT8JoJKq9BWcJFRTTe1UAW8xGokS2wbRvg1UZIR/vI16j X-Received: by 2002:a05:6830:4d1:b0:6b9:f1d3:160 with SMTP id s17-20020a05683004d100b006b9f1d30160mr1247348otd.11.1691138838975; Fri, 04 Aug 2023 01:47:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691138838; cv=none; d=google.com; s=arc-20160816; b=0fBEp3wD5FlTSr4y02M7yC9ngEI0zIRDN5QrIWHBa29iuIY781MudpsTJtrQgoFfBH D1u/2o4Dcj79gSWVca5dWAEEr3qMA4swdkBPzSFs0iG05my7OJaIgfGIcnnoKkKXGuQB vA9J3sAKdE//F3islacAKMk8/slAMIHCI/sAOiTfD0QXGF2z/uwm3FGVYHas3C9/j/tJ dMJg97ReT6gdbvELbkRlSw7Z8RaGnbwZE+lp5Xp5tL814zpjyzHyV4xnTtjrSvoKaFM5 9lK6NUXFQjEb0T0ZiewyMxN370N1cx5E5EyPxJcwyHpW6x20scb5JrSvlD6ZwyM4UuNd qARw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=x5jSNP/HLg0W4x1NzZ4fCZF9Dw9LqbXuRV+zXDZs1Ss=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=ghIf4UUMbwCuFwsjJr04Pf8bwEf3imD94pwPZ7eajbgaU/2ZmVY2FNgUagCGv4rHcz OBJUNrmxtFnK5FcTT+sqxGKRbJo49ALR9XRlFjgv4m4YEuVrhJ2fNyukqxUMv24OeJvJ lwPp1MO+1RpNIEVBc2+51Jn4jSoSVbJRACE4I5J8ll9Dz2IPJnEqwt6qS/zkvfMQrNPr 3C00C/Ab2Z1U6A9Mtu3td0HqgHMGoYXPWWpg/8GWUIRPryitlYzyD9NGIVjis5HfSxIg tfBxVc49/Bhe9DJlzMe7eXJsGbnvJ534e1bE7p+0vawFBN4vrnMMisKmYIJGL4DlUwge OXUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=CYZUskIy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v10 06/16] drm/mediatek: gamma: Use bitfield macros Date: Fri, 4 Aug 2023 09:28:40 +0200 Message-ID: <20230804072850.89365-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773287599088783257 X-GMAIL-MSGID: 1773287599088783257 Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. While at it, also add a definition for LUT_BITS_DEFAULT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 41 ++++++++++++++--------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 18b102bef370..ea91d3619716 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ +#include #include #include #include @@ -21,9 +22,16 @@ #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 +#define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) +#define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) +#define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) +#define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) + #define LUT_10BIT_MASK 0x03ff +#define LUT_BITS_DEFAULT 10 #define LUT_SIZE_DEFAULT 512 struct mtk_disp_gamma_data { @@ -96,33 +104,33 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt for (i = 0; i < lut_size; i++) { struct drm_color_lut diff, hwlut; - hwlut.red = drm_color_lut_extract(lut[i].red, 10); - hwlut.green = drm_color_lut_extract(lut[i].green, 10); - hwlut.blue = drm_color_lut_extract(lut[i].blue, 10); + hwlut.red = drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); + hwlut.green = drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); + hwlut.blue = drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); if (!lut_diff || (i % 2 == 0)) { - word = hwlut.red << 20 + - hwlut.green << 10 + - hwlut.red; + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red = lut[i].red - lut[i - 1].red; - diff.red = drm_color_lut_extract(diff.red, 10); + diff.red = drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); diff.green = lut[i].green - lut[i - 1].green; - diff.green = drm_color_lut_extract(diff.green, 10); + diff.green = drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); diff.blue = lut[i].blue - lut[i - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, 10); + diff.blue = drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); - word = diff.blue << 20 + - diff.green << 10 + - diff.red; + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); } writel(word, (lut_base + i * 4)); } /* Enable the gamma table */ - cfg_val = cfg_val | GAMMA_LUT_EN; + cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); writel(cfg_val, regs + DISP_GAMMA_CFG); } @@ -139,9 +147,12 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + u32 sz; + + sz = FIELD_PREP(DISP_GAMMA_SIZE_HSIZE, w); + sz |= FIELD_PREP(DISP_GAMMA_SIZE_VSIZE, h); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, - DISP_GAMMA_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZE); 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id k5-20020a1709067ac500b0098dd7b3684csi1186416ejo.994.2023.08.04.02.12.00; Fri, 04 Aug 2023 02:12:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=iqZfSylJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233694AbjHDH3c (ORCPT + 99 others); Fri, 4 Aug 2023 03:29:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234146AbjHDH3F (ORCPT ); Fri, 4 Aug 2023 03:29:05 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6945B3ABE for ; Fri, 4 Aug 2023 00:29:04 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id AAA4066071BB; Fri, 4 Aug 2023 08:29:02 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691134143; bh=sMSXWGMzRY15n7GP2+/uJ71airFfgmnnXjt646sPTj8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iqZfSylJV4GtvmL7oED7wG4r4kBsy/pRa+iYrHa6/pEsBw0l0YB8eZiZDtn4gIj3x S03ZZNNdyyEXbrnMoV0pNmF7YjJagOpp0lFu43fU9rZSk+caIX1aBnH/gjypHaRV/8 ygjQG7CW1W9laxBW3hEXCe7EhI3Gbe5a3lIypjcj330VSB1+uecL8s1jd4Z1LwWO5i VDeTVW+uwwQQuJGdOgIXbQQiKASWf4SGSBF26Qz5o/LvyUgvB3GJx7VvsaV95SH+c4 Mrs1qVWrw5rwNKSRKXFqRnVoPOd+GRkQdaaByKgV+n1Rh1iFYX01sGr0nY5xy4LiIq 487nvC+X3Db8Q== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v10 07/16] drm/mediatek: aal: Use bitfield macros Date: Fri, 4 Aug 2023 09:28:41 +0200 Message-ID: <20230804072850.89365-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773289178065276503 X-GMAIL-MSGID: 1773289178065276503 Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index e2e4155faf01..bec035780db0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -18,6 +18,8 @@ #define DISP_AAL_EN 0x0000 #define AAL_EN BIT(0) #define DISP_AAL_SIZE 0x0030 +#define DISP_AAL_SIZE_HSIZE GENMASK(28, 16) +#define DISP_AAL_SIZE_VSIZE GENMASK(12, 0) #define DISP_AAL_OUTPUT_SIZE 0x04d8 #define DISP_AAL_LUT_SIZE 512 @@ -56,9 +58,13 @@ void mtk_aal_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_aal *aal = dev_get_drvdata(dev); + u32 sz; - mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); - mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); + sz = FIELD_PREP(DISP_AAL_SIZE_HSIZE, w); + sz |= FIELD_PREP(DISP_AAL_SIZE_VSIZE, h); + + mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); } /** From patchwork Fri Aug 4 07:28:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131025 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp125366vqb; Fri, 4 Aug 2023 02:03:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH64c7fBds2yLo80+vD3H0rCGCKyX9QurDPPQtk6JnOPGSCn7ngV4uRyzf9XYJq/dB+1mQH X-Received: by 2002:a17:903:1205:b0:1bc:2abb:4e98 with SMTP id l5-20020a170903120500b001bc2abb4e98mr1318540plh.21.1691139809407; Fri, 04 Aug 2023 02:03:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691139809; cv=none; d=google.com; s=arc-20160816; b=eDvXl5+BAZmUNSfMHLZ/TY6S/dAJPQqneSOQEXWUVu+dr1VGoT5lAsdyEH+zXG7g4K WKqv7eKpTQy1a8RlMZv1Wz0JtRAQPYMbr6jAt0lBbcr0uVcu9hbob5lYVG5agw3CvKYQ H/Qc22+LMFhbskgIiTBYmQouCqJ5SqtEQLz+/c58iyJ4ZWYz7iyKX6YjxFM1EPuHATmO Q8DoV7qDtfzV3EMU+upoUGAoukLsepTFWVAXwZiFF54bOfYSk+/dehUwRidMA3tfvll9 ZOKGEGLbfCB7uWVILS5yWOMCLUSlp68imV6agn3UIyR0KIv0zG1wU1rHTsIrHdb9Y500 1WjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SZ/RJ4O+jzLeBoespGWHqrsEafIETtooyO1shbTBc78=; fh=9Aon3jQEVE1p+dS8p5fghxMOlPjmNOu/O0E5mCMmCJg=; b=audK2Q0z90+O7cDJUGwS5u8CLIAkGVtHRMF91XlwBw8ctjKIHRPGNXt6e8toaD/He6 v2pNjNFYDND6aiBZhBIbquJczjlcifGnQRevQ7nR2YyCCZaZUbPwlLC56eECM0JNniLq Oqz39/S8k+y9Rpbbp+8p3Pv7dPGkBPhCPEQ0mDYA1S1TadHjt2bY85B+56HqJdXVHJrU 4AZB6MxTXtrYZe74V3Rpdqha+BiFuZbWTa6sWcQZy31AzE5EJVriOYzjKNpjG0xe/mHp ICy04D69Vn5M1RtkFJzPi//XT0P1/P7vH8JseGMmyxVD5foeqbJ3NMluuxvnpq3HjD2h 2uiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=bdVg24vJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i4-20020a17090332c400b001bbb0fe3641si1503466plr.489.2023.08.04.02.03.14; Fri, 04 Aug 2023 02:03:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=bdVg24vJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234287AbjHDH3g (ORCPT + 99 others); Fri, 4 Aug 2023 03:29:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234161AbjHDH3G (ORCPT ); Fri, 4 Aug 2023 03:29:06 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BE7D3AA6 for ; Fri, 4 Aug 2023 00:29:05 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 78E8066071B9; Fri, 4 Aug 2023 08:29:03 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691134144; bh=JEghBTvHNSu8yfdUBd7VO3HyemOteRFeB2SfmGR0Hfs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bdVg24vJakDUuqCNbVft7PDFqonlDz85iOyEAaD02foARH5vQJ2GUAIM76VXt/8dR mcdv8isTfbpG9UDjqJ0vxWcj4GVIvcBYU5fN+eG5RKV/p9/uDYK0MWJ3lVdhnShunA 5A/2ORdPqozTDg4TKK7Elrp1UD7QKFuNrsENylQx5Ta6cqxAIecjNHHv7LETElQP9g GYWEfhBmeCDbhWpeLYEHq46OCrQ450s9oXLERe5uN8BFv9Kr4BBY9Cn/itglgn1Bt9 yLGnQnkL4Bt3qUyeacH8TeshWkoWEWnfUh+Xv+QeAArp33nGseYCifG+m+Thr8srSi x9U5PrvRuUmtw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v10 08/16] drm/mediatek: De-commonize disp_aal/disp_gamma gamma_set functions Date: Fri, 4 Aug 2023 09:28:42 +0200 Message-ID: <20230804072850.89365-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773288617048389171 X-GMAIL-MSGID: 1773288617048389171 In preparation for adding a 12-bits gamma support for the DISP_GAMMA IP, remove the mtk_gamma_set_common() function and move the relevant bits in mtk_gamma_set() for DISP_GAMMA and mtk_aal_gamma_set() for DISP_AAL: since the latter has no more support for gamma manipulation (being moved to a different IP) in newer revisions, those functions are about to diverge and it makes no sense to keep a common one (with all the complications of passing common data and making exclusions for device driver data) for just a few bits. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 39 +++++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 - drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 34 ++++---------------- 3 files changed, 44 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index bec035780db0..21b25470e9b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -17,10 +17,18 @@ #define DISP_AAL_EN 0x0000 #define AAL_EN BIT(0) +#define DISP_AAL_CFG 0x0020 +#define AAL_RELAY_MODE BIT(0) +#define AAL_GAMMA_LUT_EN BIT(1) #define DISP_AAL_SIZE 0x0030 #define DISP_AAL_SIZE_HSIZE GENMASK(28, 16) #define DISP_AAL_SIZE_VSIZE GENMASK(12, 0) #define DISP_AAL_OUTPUT_SIZE 0x04d8 +#define DISP_AAL_GAMMA_LUT 0x0700 +#define DISP_AAL_GAMMA_LUT_R GENMASK(29, 20) +#define DISP_AAL_GAMMA_LUT_G GENMASK(19, 10) +#define DISP_AAL_GAMMA_LUT_B GENMASK(9, 0) +#define DISP_AAL_LUT_BITS 10 #define DISP_AAL_LUT_SIZE 512 struct mtk_disp_aal_data { @@ -85,9 +93,36 @@ unsigned int mtk_aal_gamma_get_lut_size(struct device *dev) void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_aal *aal = dev_get_drvdata(dev); + struct drm_color_lut *lut; + unsigned int i; + u32 cfg_val; + + /* If gamma is not supported in AAL, go out immediately */ + if (!(aal->data && aal->data->has_gamma)) + return; + + /* Also, if there's no gamma lut there's nothing to do here. */ + if (!state->gamma_lut) + return; + + cfg_val = readl(aal->regs + DISP_AAL_CFG); + lut = (struct drm_color_lut *)state->gamma_lut->data; + + for (i = 0; i < DISP_AAL_LUT_SIZE; i++) { + struct drm_color_lut hwlut = { + .red = drm_color_lut_extract(lut[i].red, DISP_AAL_LUT_BITS), + .green = drm_color_lut_extract(lut[i].green, DISP_AAL_LUT_BITS), + .blue = drm_color_lut_extract(lut[i].blue, DISP_AAL_LUT_BITS) + }; + u32 word; + + word = FIELD_PREP(DISP_AAL_GAMMA_LUT_R, hwlut.red); + word |= FIELD_PREP(DISP_AAL_GAMMA_LUT_G, hwlut.green); + word |= FIELD_PREP(DISP_AAL_GAMMA_LUT_B, hwlut.blue); + writel(word, (aal->regs + DISP_AAL_GAMMA_LUT) + (i * 4)); + } - if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(NULL, aal->regs, state); + writel(cfg_val, aal->regs + DISP_AAL_CFG); } void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index ca377265e5eb..54d3712e2afd 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -56,7 +56,6 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index ea91d3619716..001b98694761 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -73,42 +73,29 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } -void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { - struct mtk_disp_gamma *gamma; + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; - bool lut_diff; - u16 lut_size; u32 cfg_val, word; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) return; - /* If we're called from AAL, dev is NULL */ - gamma = dev ? dev_get_drvdata(dev) : NULL; - - if (gamma && gamma->data) { - lut_diff = gamma->data->lut_diff; - lut_size = gamma->data->lut_size; - } else { - lut_diff = false; - lut_size = LUT_SIZE_DEFAULT; - } - - cfg_val = readl(regs + DISP_GAMMA_CFG); - lut_base = regs + DISP_GAMMA_LUT; + cfg_val = readl(gamma->regs + DISP_GAMMA_CFG); + lut_base = gamma->regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < lut_size; i++) { + for (i = 0; i < gamma->data->lut_size; i++) { struct drm_color_lut diff, hwlut; hwlut.red = drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); hwlut.green = drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); hwlut.blue = drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); - if (!lut_diff || (i % 2 == 0)) { + if (!gamma->data->lut_diff || (i % 2 == 0)) { word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); @@ -132,14 +119,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); - writel(cfg_val, regs + DISP_GAMMA_CFG); -} - -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) -{ - struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); - - mtk_gamma_set_common(dev, gamma->regs, state); + writel(cfg_val, gamma->regs + DISP_GAMMA_CFG); } void mtk_gamma_config(struct device *dev, unsigned int w, From patchwork Fri Aug 4 07:28:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131043 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp135226vqb; Fri, 4 Aug 2023 02:26:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHMFCMe6PQ54ZbvM6ZBtixO6kzbh6Jk7B69n8/3UCsV0RsNVyZVDkxOuYTuxykRb4OUgWbW X-Received: by 2002:a05:6a00:194b:b0:668:9bf9:fa70 with SMTP id s11-20020a056a00194b00b006689bf9fa70mr1173404pfk.34.1691141178678; Fri, 04 Aug 2023 02:26:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691141178; cv=none; d=google.com; s=arc-20160816; b=k/COj9Ta9Gi5x7EloW01zgElFjQlpSKugEJEZj7D3/fuw7CbmIG6TyAlEBG5NTSDuB 8NYo5VGpzaCUmFpHBIZLBiIJhHvEKCMqcHvjUAymzPkryRHwcRDDmGIP6Fi/xGRMoHce Vy8ZKOib8L2ADrhcVL5zwLFeBYmzmz3AyO6ICj0E0ZmZrO1nolRvt43+bZs1P41cste+ DxK1e1+s9ixJp6SU7+UAOHLBZr9zynzH6NPi6upLMtlAW6ErmfauS5z6e5ARirdBDuiK oUIUKcAloM+ErsO1T4PUd8XONECjWle7cdIAy9RRTrO+9Ab81FsJd/YMvlmXF41xY7qb ENOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kMdA727ML9GfYlwdB+N4dG3v8MdPr2da4KnC11PmGzE=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=rJA7Z18BPReQ43ujCV/hCND+U6d5zc/f755gJui8UjEgy9i6I+lOd3QX0LnzJ5b+0K CkXiV7ApZU+JDzm9oV4zSF5smohrDWqaWDlMIbAa9rFhuAInuVS053hSvznudg14Yqo1 3+yjVfmWulswKyldO5f2qbj99I2da94aA/0/N7yMXgrdt84X6m5WQGRhDeqGa68kmNvv xc4y5KFbluGy6ipYDe4f4yEz8tv4hQHSbR6sxi5ON0pUaiqWLxqTpHxs+2eRVG61dekZ 96IyeIpxwpkuD2yk5EEz19zopkgN7QXwcZHcj3RRNVd9n6Md8JjRYb5RtLjPpHyR7sZu Nq+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=loIubv0n; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v10 09/16] drm/mediatek: gamma: Support specifying number of bits per LUT component Date: Fri, 4 Aug 2023 09:28:43 +0200 Message-ID: <20230804072850.89365-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773290052459495579 X-GMAIL-MSGID: 1773290052459495579 New SoCs, like MT8195, not only may support bigger lookup tables, but have got a different register layout to support bigger precision: support specifying the number of `lut_bits` for each SoC and use it in mtk_gamma_set_common() to perform the right calculation. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 001b98694761..1845bd326a6d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -38,6 +38,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; u16 lut_size; + u8 lut_bits; }; /* @@ -91,9 +92,9 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) for (i = 0; i < gamma->data->lut_size; i++) { struct drm_color_lut diff, hwlut; - hwlut.red = drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); - hwlut.green = drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); - hwlut.blue = drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); + hwlut.red = drm_color_lut_extract(lut[i].red, gamma->data->lut_bits); + hwlut.green = drm_color_lut_extract(lut[i].green, gamma->data->lut_bits); + hwlut.blue = drm_color_lut_extract(lut[i].blue, gamma->data->lut_bits); if (!gamma->data->lut_diff || (i % 2 == 0)) { word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); @@ -101,13 +102,13 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red = lut[i].red - lut[i - 1].red; - diff.red = drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); + diff.red = drm_color_lut_extract(diff.red, gamma->data->lut_bits); diff.green = lut[i].green - lut[i - 1].green; - diff.green = drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); + diff.green = drm_color_lut_extract(diff.green, gamma->data->lut_bits); diff.blue = lut[i].blue - lut[i - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); + diff.blue = drm_color_lut_extract(diff.blue, gamma->data->lut_bits); word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); @@ -217,10 +218,12 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_bits = 10, .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { + .lut_bits = 10, .lut_diff = true, .lut_size = 512, }; From patchwork Fri Aug 4 07:28:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131006 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp110644vqb; Fri, 4 Aug 2023 01:27:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHSQa4w1QZN/u5wrldrySnUGSZlIPj50Te2wDXcgHwb01DCFUKehD/Vz1/rcgUF8vPybAe6 X-Received: by 2002:a05:6402:1492:b0:522:29b7:741d with SMTP id e18-20020a056402149200b0052229b7741dmr962004edv.29.1691137656222; Fri, 04 Aug 2023 01:27:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691137656; cv=none; d=google.com; s=arc-20160816; b=wtYuKvbdoQM0MktYjDHI21UhHl5TWxTrEOfOwglBCuXxB3fgvhHBP/eZhwX4oKSXQP h82fobAsSsm9xXOESCmL0/8cInXsLSbhd+lYAbneT58htOGvZXPl3Wk1VFiVx3pLtQi0 ZZKRSdTX6LlyVdYHW43VniSpC8hEYiOJiAJhRTJCK9oGQd4trvhUq+Ok+77OpsFwzPX4 s5zJYsswWSEGFpihQgc+bRN3KAjtZuYSVhDsHhCh0XgWqyOqnFbHoXKgsVv2yAmhSREv reMZ/3Ceq3iEOFfWaOLjfymq3bMnn7JWGQmMP+A/YvnfJ+MDAJzlwgQR/bhci3QzwCTp ViLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DuT5+JoXH2HL2TlvQsZt8Ht8tQqDvp9g/pL3+hiYlvk=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=J+Pfb9DWqcWcnzUenBwqTQWNV8JYFHlqSH/cd9QHOQg3Qopsp21FWKWbFZxR0p6rC2 wBQ+P0Q6zKdVMSewSeOLpH/aLJmm3DGpg01N8k2U0BBNsvz4pt5zIUEYHjkVcB9aNmwZ HnyMsOuX5SipLNOUit4y7jc3iVbGjZ6G7oyOeyT7f3VH65Z9ho+Ck/FWbEnor3Kp2YKT dRPci2mCPh8/vtYSE7OLpzCZcviS3gr2JmiJP5GXFQGd3nYmI1IcSUdH5SGcOud/vynN OqPZAAS0LvV/YYzeGaWgoNjb7KXH+QKTIY21pcBmFwROXyh35sOf+FZahp1IByRSusvu 77gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=YvLyS0S5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v10 10/16] drm/mediatek: gamma: Support multi-bank gamma LUT Date: Fri, 4 Aug 2023 09:28:44 +0200 Message-ID: <20230804072850.89365-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773286358679865812 X-GMAIL-MSGID: 1773286358679865812 Newer Gamma IP have got multiple LUT banks: support specifying the size of the LUT banks and handle bank-switching before programming the LUT in mtk_gamma_set_common() in preparation for adding support for MT8195 and newer SoCs. Suggested-by: Jason-JH.Lin [Angelo: Refactored original commit] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 70 ++++++++++++++--------- 1 file changed, 44 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 1845bd326a6d..3f1c6815ea5a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -24,6 +24,8 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) +#define DISP_GAMMA_BANK 0x0100 +#define DISP_GAMMA_BANK_BANK GENMASK(1, 0) #define DISP_GAMMA_LUT 0x0700 #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) @@ -37,6 +39,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_bank_size; u16 lut_size; u8 lut_bits; }; @@ -80,41 +83,54 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; - u32 cfg_val, word; + u32 cfg_val, lbank_val, word; + int cur_bank, num_lut_banks; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) return; + num_lut_banks = gamma->data->lut_size / gamma->data->lut_bank_size; cfg_val = readl(gamma->regs + DISP_GAMMA_CFG); lut_base = gamma->regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < gamma->data->lut_size; i++) { - struct drm_color_lut diff, hwlut; - - hwlut.red = drm_color_lut_extract(lut[i].red, gamma->data->lut_bits); - hwlut.green = drm_color_lut_extract(lut[i].green, gamma->data->lut_bits); - hwlut.blue = drm_color_lut_extract(lut[i].blue, gamma->data->lut_bits); - - if (!gamma->data->lut_diff || (i % 2 == 0)) { - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); - } else { - diff.red = lut[i].red - lut[i - 1].red; - diff.red = drm_color_lut_extract(diff.red, gamma->data->lut_bits); - - diff.green = lut[i].green - lut[i - 1].green; - diff.green = drm_color_lut_extract(diff.green, gamma->data->lut_bits); - - diff.blue = lut[i].blue - lut[i - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, gamma->data->lut_bits); - - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + + for (cur_bank = 0; cur_bank < num_lut_banks; cur_bank++) { + + /* Switch gamma bank and set data mode before writing LUT */ + if (num_lut_banks > 1) { + lbank_val = FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + writel(lbank_val, gamma->regs + DISP_GAMMA_BANK); + } + + for (i = 0; i < gamma->data->lut_bank_size; i++) { + int n = (cur_bank * gamma->data->lut_bank_size) + i; + struct drm_color_lut diff, hwlut; + + hwlut.red = drm_color_lut_extract(lut[n].red, gamma->data->lut_bits); + hwlut.green = drm_color_lut_extract(lut[n].green, gamma->data->lut_bits); + hwlut.blue = drm_color_lut_extract(lut[n].blue, gamma->data->lut_bits); + + if (!gamma->data->lut_diff || (i % 2 == 0)) { + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } else { + diff.red = lut[n].red - lut[n - 1].red; + diff.red = drm_color_lut_extract(diff.red, gamma->data->lut_bits); + + diff.green = lut[n].green - lut[n - 1].green; + diff.green = drm_color_lut_extract(diff.green, gamma->data->lut_bits); + + diff.blue = lut[n].blue - lut[n - 1].blue; + diff.blue = drm_color_lut_extract(diff.blue, gamma->data->lut_bits); + + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } + writel(word, (lut_base + i * 4)); } - writel(word, (lut_base + i * 4)); } /* Enable the gamma table */ @@ -218,11 +234,13 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_bank_size = 512, .lut_bits = 10, .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { + .lut_bank_size = 512, .lut_bits = 10, .lut_diff = true, .lut_size = 512, From patchwork Fri Aug 4 07:28:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131026 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp127391vqb; Fri, 4 Aug 2023 02:07:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEavncCTaE15qNKTzuumsIFWplZrCffmCOAJanC3P46qNQc743X6zbMLaBP5hysFiD5Iy0b X-Received: by 2002:a17:90a:6c06:b0:268:3ca4:6152 with SMTP id x6-20020a17090a6c0600b002683ca46152mr1756530pjj.15.1691140061145; Fri, 04 Aug 2023 02:07:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691140061; cv=none; d=google.com; s=arc-20160816; b=NwenHNbB6l6R4rbFsc+CWNluk2gG68aZVT94bVVBMcUWGP4nIeQ9HuKwEBJjAagNj4 MLkHh/nMkdyl0WU4dpIwPXOk/0ptVEiXTBndq71Byv2RkAWWN5v/4g/Vx3expqiUENHq 9NTR4XPdDyKnlmyFV3SadWX+yO65HViwQTd69rymhCXG7NsaN8T8UUA7wTArPXTklMgy 6HZomyxbx0N1CKQIUz7yGCZQKWLYyPPJ/LfhTZsZrYKGXLNFsfwT7AW5Fkjd0VRrYBPH 9TidsJR7uj6PJqPSIkgSzP5jX9F+vYeHh2M4kXlPBQ1XFT2LndYVMlBouZgQ7ioSCg3L y60Q== ARC-Message-Signature: i=1; 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Lin" , Alexandre Mergnat Subject: [PATCH v10 11/16] drm/mediatek: gamma: Add support for 12-bit LUT and MT8195 Date: Fri, 4 Aug 2023 09:28:45 +0200 Message-ID: <20230804072850.89365-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773288880720433500 X-GMAIL-MSGID: 1773288880720433500 Add support for 12-bit gamma lookup tables and introduce the first user for it: MT8195. While at it, also reorder the variables in mtk_gamma_set_common() and rename `lut_base` to `lut0_base` to improve readability. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 74 +++++++++++++++++++---- 1 file changed, 62 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 3f1c6815ea5a..7d2f8042ace0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -26,12 +26,20 @@ #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_BANK 0x0100 #define DISP_GAMMA_BANK_BANK GENMASK(1, 0) +#define DISP_GAMMA_BANK_DATA_MODE BIT(2) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT1 0x0b00 +/* For 10 bit LUT layout, R/G/B are in the same register */ #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) #define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) #define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) +/* For 12 bit LUT layout, R/G are in LUT, B is in LUT1 */ +#define DISP_GAMMA_LUT_12BIT_R GENMASK(11, 0) +#define DISP_GAMMA_LUT_12BIT_G GENMASK(23, 12) +#define DISP_GAMMA_LUT_12BIT_B GENMASK(11, 0) + #define LUT_10BIT_MASK 0x03ff #define LUT_BITS_DEFAULT 10 #define LUT_SIZE_DEFAULT 512 @@ -77,14 +85,30 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } +/* + * SoCs supporting 12-bits LUTs are using a new register layout that does + * always support (by HW) both 12-bits and 10-bits LUT but, on those, we + * ignore the support for 10-bits in this driver and always use 12-bits. + * + * Summarizing: + * - SoC HW support 9/10-bits LUT only + * - Old register layout + * - 10-bits LUT supported + * - 9-bits LUT not supported + * - SoC HW support both 10/12bits LUT + * - New register layout + * - 12-bits LUT supported + * - 10-its LUT not supported + */ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); - unsigned int i; - struct drm_color_lut *lut; - void __iomem *lut_base; - u32 cfg_val, lbank_val, word; + void __iomem *lut0_base = gamma->regs + DISP_GAMMA_LUT; + void __iomem *lut1_base = gamma->regs + DISP_GAMMA_LUT1; + u32 cfg_val, data_mode, lbank_val, word[2]; int cur_bank, num_lut_banks; + struct drm_color_lut *lut; + unsigned int i; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -92,14 +116,17 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) num_lut_banks = gamma->data->lut_size / gamma->data->lut_bank_size; cfg_val = readl(gamma->regs + DISP_GAMMA_CFG); - lut_base = gamma->regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; + /* Switch to 12 bits data mode if supported */ + data_mode = FIELD_PREP(DISP_GAMMA_BANK_DATA_MODE, !!(gamma->data->lut_bits == 12)); + for (cur_bank = 0; cur_bank < num_lut_banks; cur_bank++) { /* Switch gamma bank and set data mode before writing LUT */ if (num_lut_banks > 1) { lbank_val = FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + lbank_val |= data_mode; writel(lbank_val, gamma->regs + DISP_GAMMA_BANK); } @@ -112,9 +139,15 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) hwlut.blue = drm_color_lut_extract(lut[n].blue, gamma->data->lut_bits); if (!gamma->data->lut_diff || (i % 2 == 0)) { - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + if (gamma->data->lut_bits == 12) { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, hwlut.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, hwlut.green); + word[1] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, hwlut.blue); + } else { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } } else { diff.red = lut[n].red - lut[n - 1].red; diff.red = drm_color_lut_extract(diff.red, gamma->data->lut_bits); @@ -125,11 +158,19 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) diff.blue = lut[n].blue - lut[n - 1].blue; diff.blue = drm_color_lut_extract(diff.blue, gamma->data->lut_bits); - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + if (gamma->data->lut_bits == 12) { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, diff.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, diff.green); + word[1] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, diff.blue); + } else { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } } - writel(word, (lut_base + i * 4)); + writel(word[0], (lut0_base + i * 4)); + if (gamma->data->lut_bits == 12) + writel(word[1], (lut1_base + i * 4)); } } @@ -246,11 +287,20 @@ static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { .lut_size = 512, }; +static const struct mtk_disp_gamma_data mt8195_gamma_driver_data = { + .lut_bank_size = 256, + .lut_bits = 12, + .lut_diff = true, + .lut_size = 1024, +}; + static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { { .compatible = "mediatek,mt8173-disp-gamma", .data = &mt8173_gamma_driver_data}, { .compatible = "mediatek,mt8183-disp-gamma", .data = &mt8183_gamma_driver_data}, + { .compatible = "mediatek,mt8195-disp-gamma", + .data = &mt8195_gamma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); 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Lin" , Alexandre Mergnat Subject: [PATCH v10 12/16] drm/mediatek: gamma: Make sure relay mode is disabled Date: Fri, 4 Aug 2023 09:28:46 +0200 Message-ID: <20230804072850.89365-13-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773284258693236179 X-GMAIL-MSGID: 1773284258693236179 Disable relay mode at the end of LUT programming to make sure that the processed image goes through in both DISP_GAMMA and DISP_AAL for gamma setting. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 3 +++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index 21b25470e9b7..992dc1424c91 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -122,6 +122,9 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) writel(word, (aal->regs + DISP_AAL_GAMMA_LUT) + (i * 4)); } + /* Disable RELAY mode to pass the processed image */ + cfg_val &= ~AAL_RELAY_MODE; + writel(cfg_val, aal->regs + DISP_AAL_CFG); } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 7d2f8042ace0..fbff9f97b737 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -19,6 +19,7 @@ #define DISP_GAMMA_EN 0x0000 #define GAMMA_EN BIT(0) #define DISP_GAMMA_CFG 0x0020 +#define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 @@ -177,6 +178,9 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); + /* Disable RELAY mode to pass the processed image */ + cfg_val &= ~GAMMA_RELAY_MODE; + writel(cfg_val, gamma->regs + DISP_GAMMA_CFG); } From patchwork Fri Aug 4 07:28:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131015 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp115829vqb; Fri, 4 Aug 2023 01:41:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGezho8C4wxajbb4oI7CYASUrMXC9LM/mpFAXWObYJAAzfGfPx9AGh52ktuvEvqNLCGTBzw X-Received: by 2002:a17:906:3086:b0:99b:d2a9:9a01 with SMTP id 6-20020a170906308600b0099bd2a99a01mr1111453ejv.0.1691138460186; Fri, 04 Aug 2023 01:41:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691138460; cv=none; d=google.com; s=arc-20160816; b=ZN8z+D3hlu/Pm1zk/+YDCREr9P0sfWknwZWiuRPwhHprSE4Da5mE9YGP+pmjJMl//Z Fe52+DeASFPgFxmS5pSqYkafNqt2eucU09yDBrxP058prNQhMaZyWrGLf0Ju/gPOXgD9 PFrNb7qYtp7a/GCafKqueFGvok7bNC00n82aYBPhcHPMBdtCdl14o4f3IuR7+9h2RQMS kP08CM/SjOlimOwZGSCekv0y/4SPTraRNMB0Zc/SzFON+w92AjM0SwtRbOXmfGMkcDX8 WeB7A5386YZJl2raqzRtie84VyMAHB2Vw47LzSz0l8/6YggfvmR25pLWAeXRpftvcAk/ EtWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KrhrYJjj0iCkUTzbVZgmlZw0Jyqjtlkt8XtUKAvHtdo=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=tObqDfMyK+zbzZs2koEYT34gzMrIrh67dV7xbZgtUmjkHK4hIFQCA2PEp5xBSenIOS kwv6FFHz8cdTHSam8IpdJnkBDBjYmQ51vHSgDA48PbsE4uGI+5mMryoVEaUoXtu0kdIP BraiBXU9B4WtRFk2PfMVMDhyPXoAiqOHmte5efFABOQoN8WHbNcSjOVtr7qRULuJvM3/ vL8NXV0MvvO30MZhFx7fve2O2wzcEvRJX26Z4LdfpLPjW9BGU8fZ022URrlhjjBz96Hc Hxo5IB4R5mfswF6lajYEyNcNgsvm08Uu6XIynaTi9JRJR/ncwywmgV6q7kGb9rtykN0V iqCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=OsX9MPNA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v10 13/16] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Fri, 4 Aug 2023 09:28:47 +0200 Message-ID: <20230804072850.89365-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773287202478370002 X-GMAIL-MSGID: 1773287202478370002 All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index fbff9f97b737..d9a70238d524 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -22,6 +22,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -86,6 +87,17 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut_size) +{ + u64 first, last; + int last_entry = lut_size - 1; + + first = lut[0].red + lut[0].green + lut[0].blue; + last = lut[last_entry].red + lut[last_entry].green + lut[last_entry].blue; + + return !!(first > last); +} + /* * SoCs supporting 12-bits LUTs are using a new register layout that does * always support (by HW) both 12-bits and 10-bits LUT but, on those, we @@ -175,6 +187,14 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) } } + if (!gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, gamma->data->lut_size - 1)) + cfg_val |= FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &= ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); From patchwork Fri Aug 4 07:28:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 130996 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp95971vqb; Fri, 4 Aug 2023 00:50:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEVPcoHqaRuYXfBBu4d+Qp0z/zZgU0XlXvyWw5vMrlxZHTLNWBwZBLtJnfiXdRhRFEHpe3r X-Received: by 2002:a05:620a:b8d:b0:765:aac1:100c with SMTP id k13-20020a05620a0b8d00b00765aac1100cmr966852qkh.78.1691135457310; Fri, 04 Aug 2023 00:50:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691135457; cv=none; d=google.com; s=arc-20160816; b=qEOUpDe1OsNvIjekY+DUlgRI4Smeod9xG+8k6AliKDQhCnuQE75A0ir4veDBVDDOPk CpYKoo6h9ntsfX1phBTYDFmCCpZGqfetsjEDjS9p4Y3d67+alwYzV9i7l//QfGBxmPwy 3MTiYlRCkKw2C0k77IX2MLCEvESp4GxsYqxclfSd/8BmZlqGmyX5BKp5E4xvN8FZMbUZ VlHMWqgL4TACMDnbb4LYqGRNQ5TSNn6blRfOifqZv/yHyTMr3LjAIyVi6HZIOeAHZgx1 T7O65Bc6+T9CblTstCxNpUfg7jIXzgDDiU0KOAUNl0um08pFdG2bBshbIh4iBCl3pnc1 94Nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KOh0egWiIzOhiKedrMVp6vfsrLVNuJ8Xkfw0kLaMAfY=; fh=9Aon3jQEVE1p+dS8p5fghxMOlPjmNOu/O0E5mCMmCJg=; b=iEaSRGNplMvzwclFUEDt8ogzhcGd/MYUQg+JFGWzJPRaH9izYRV8yfcWvRpzfNmYwT Cjq2SPrKC0jbreQMXuWt29VcD8siho0jt8PiMABrytfVqaavwyP1jjDTqZOWbbSW+0W3 kCb/chUjWZQ0A7C8j7uHZazlcguNWaBQojG2gQ4opuszTBm/DkMHvRy4qwgPUIqG3/kp dtXrE2kM/XY3OUMaVMieiVy+djbJUsHAiwD9OQBp3kp8rB6R5FlclKTCAJEnzZQzGf/x nlaVQrgj6f7Z39nSKwayXQl56D2SiSL8SoZcSadTUxQ1HmmI6MrLPlkwG4lSrIC+kbuf HQ0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=UOwWAxNQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l137-20020a633e8f000000b0056416221db2si828575pga.816.2023.08.04.00.50.42; Fri, 04 Aug 2023 00:50:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=UOwWAxNQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234369AbjHDH36 (ORCPT + 99 others); Fri, 4 Aug 2023 03:29:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234184AbjHDH3L (ORCPT ); Fri, 4 Aug 2023 03:29:11 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B9AD3ABC for ; Fri, 4 Aug 2023 00:29:10 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id AD0FF66071BF; Fri, 4 Aug 2023 08:29:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691134149; bh=0mQCLyW1Ws1lLoPWJcO0iech2ujtO9xHY8S2bs46Dv8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UOwWAxNQxMg5ozA9RguaWrWLqegvxwOAfHp5ZX6QqCIRs8CeVOzqZ/HGJlt3aRsjv vdCDBWxpKO+QMU2Zzbs/pXZR+v3H9Tljfq/UpHm7FDVSD5Q/FWVu+OGokXv3o08NmD HHDjk/aluxo1bWSIKpQXA7EPB0TDw6I7zYDAsCiW463GxZiOzmBgV8/6en/2GiNKgt 21lViRXHP4Nol307aLBsgbzFidLMTZVST5l6qSzuRdgbhJUPwNO1Xlt9gEIYUDczmT 015CAQO//jiJESk/kJF26uX3dQTYAxel/v4a6YKkzIFaF+T1LQZ8yGLvvHs7BOjVIy ng+9l+AhMcNZw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v10 14/16] drm/mediatek: aal: Rewrite kerneldoc for struct mtk_disp_aal Date: Fri, 4 Aug 2023 09:28:48 +0200 Message-ID: <20230804072850.89365-15-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773284053106873881 X-GMAIL-MSGID: 1773284053106873881 The kerneldoc for struct mtk_disp_aal was entirely wrong: rewrite it to actually document the structure. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index 992dc1424c91..e6ab3eaa1126 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -36,9 +36,11 @@ struct mtk_disp_aal_data { }; /** - * struct mtk_disp_aal - DISP_AAL driver structure - * @ddp_comp - structure containing type enum and hardware resources - * @crtc - associated crtc to report irq events to + * struct mtk_disp_aal - Display Adaptive Ambient Light driver structure + * @clk: clock for DISP_AAL controller + * @regs: MMIO registers base + * @cmdq_reg: CMDQ Client register + * @data: platform specific data for DISP_AAL */ struct mtk_disp_aal { struct clk *clk; From patchwork Fri Aug 4 07:28:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131010 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp112145vqb; Fri, 4 Aug 2023 01:31:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFpMrKyrXKsGDInCIJM/tc62Ij9NluyBvEGx1cX9Kjpdm0/JylThzS50znSfp7nq0nsmufh X-Received: by 2002:aa7:d055:0:b0:51d:91ef:c836 with SMTP id n21-20020aa7d055000000b0051d91efc836mr964056edo.32.1691137896807; Fri, 04 Aug 2023 01:31:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691137896; cv=none; d=google.com; s=arc-20160816; b=smK3NXIuFb6isX5+AV+nbNxoroA+oqr+MMPWdeX2j4LieqfTaZEwMPQPQ4CM8Uiydh fo/+70RZo1xRsCdbmbUbXhRv27Q5TvVgviEugX7o4AjWNpGGtoe/jA7B3MbYu8gD1w64 uIT/3AZBteI+fmrU5CcXa9bx5vNc81za/l4RwdO18wRKKekEqApd4HbtxkUJl6SnZA/V BCqeBpADCkwEfKshZ61jm2vij3EBzGVmNe7GZXAq4wAyCGMUudaTWUggMjJNfYd2uf/4 pQwHrGWShTBsn6KIdnPjUUp7ZEiDi78RxbeNixXs8NTRRnFsauL+ddoRwvie5erKXmgu 4Q4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Rsq7plQ/F0ndcc9bEjUHw97Zaa92iAqhmMCCUBU7WwA=; fh=9Aon3jQEVE1p+dS8p5fghxMOlPjmNOu/O0E5mCMmCJg=; b=bzxUO6hY5MCWA5Nb2csauikQr9oNmq5m09EGTYhl89Op+/xI/K3jRAhu9FpUyM5BgH /8fs6ix5QjKXa+wfqPKr2DoiIMp1FZTj4dzJpSuVGGc/6bJSAkwJ/EA++WL2lYZx/Oop 4w26HGH7ooGIcbvF22ollfGKQt0Omww8AmxVMbROtMZtefolRRzsaNJpk4qYeODzrdt3 U+Asgls0wX8EB+M1OWKxmjwjj9b4PQhLeuXI9mDiQPL+Aubmwz9q95LpP7Q88TlkNCzv vEBlImj1Hb7zsofYt+jujNe7zkKlMvoBzMEGZfdDLy+rWhUul9+KnFEIVaK0twZDJ8+N N1Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=DZ4suX32; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q14-20020aa7da8e000000b0052245c04c89si1259733eds.164.2023.08.04.01.31.14; Fri, 04 Aug 2023 01:31:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=DZ4suX32; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234394AbjHDHaG (ORCPT + 99 others); Fri, 4 Aug 2023 03:30:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234208AbjHDH3U (ORCPT ); Fri, 4 Aug 2023 03:29:20 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C4EF3ABE for ; Fri, 4 Aug 2023 00:29:11 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7DA1866071D1; Fri, 4 Aug 2023 08:29:09 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691134150; bh=EES2yF/cg8QCjFjl2OGiEbmr3nkWYxd9TW0sjHleq8s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DZ4suX32XpOL+CYUuFHlSVO0rS7HgQFHbA8J1dyuPAHng3BijJ2irAInj7XnFnMd4 2yXbBVcYAMnt62oTnufnGwLm0BxZQA4TySctu9gTK4JJJpTTrdGIBPVFBSbXGf2vd0 NyvOOzA63Ta2n0pz1bRi7KVvVkTkuzG0dppVu5jjYFFLkrQiXJRdb9YdIkKLYGOKqW 0sM4zqbZc/kEQBarHw9hfAVW6QvgeNpE8w4CXlJONAnihctdOMmYCTWm1vf+m7YGEl 8lK92k6tZlYxKVDDWWN60vohzYuhPcmD/rfJ6NyUo9R+4bahWEVMZT4dp3kbZodPsZ ZW2v2KPU3Vv/A== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v10 15/16] drm/mediatek: gamma: Add kerneldoc for struct mtk_disp_gamma Date: Fri, 4 Aug 2023 09:28:49 +0200 Message-ID: <20230804072850.89365-16-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773286611038170412 X-GMAIL-MSGID: 1773286611038170412 The mtk_disp_gamma structure was completely undocumented: add some kerneldoc documentation to it. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index d9a70238d524..867445a2af9e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -54,8 +54,12 @@ struct mtk_disp_gamma_data { u8 lut_bits; }; -/* - * struct mtk_disp_gamma - DISP_GAMMA driver structure +/** + * struct mtk_disp_gamma - Display Gamma driver structure + * @clk: clock for DISP_GAMMA block + * @regs: MMIO registers base + * @cmdq_reg: CMDQ Client register + * @data: platform data for DISP_GAMMA */ struct mtk_disp_gamma { struct clk *clk; From patchwork Fri Aug 4 07:28:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131018 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp117933vqb; Fri, 4 Aug 2023 01:46:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFSGItrr+563o6z/7NBvQuP8IZliIpY5MGiueeuxQ1aFJqA0d9YevNvUN0iGACKzJIkQbZJ X-Received: by 2002:a05:620a:47b0:b0:768:3bef:da86 with SMTP id dt48-20020a05620a47b000b007683befda86mr1568356qkb.37.1691138788289; Fri, 04 Aug 2023 01:46:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691138788; cv=none; d=google.com; s=arc-20160816; b=N6NX2Pto05G7EmZJV15yv7YuiyGRC8qtDhIOJz5Z4oBZ4ABKVFUUEzRCfd1ivjp1sh yu9vKpZrBTNH0i8b4hlNXf0/2BzqHGzL9hhq2kp7Afjd8DTaGRYS3yuOQ4var9VbAIyP xyofXUTVk2CJkw/BvBblna8t7v04qlzqrlww4mkYktFjSqZUHkjz80E0Q9zO/IUmCdtv CrDeC/nhdbjVl6DKqQdOnwfPcJL9jcHJathL38LeoKbG/NQ+myvzp1qehZWBATuxfX89 Or25hO/MYu6g4Ph+VSu+FxNiE6+assriGLaDKVrgVF5QKUWWUbq4/lNXvsIIXCFW4+O8 7Z1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ala1ks6V0rarnm7IA1fl3swYvyi677tS76330+JRWP4=; fh=9Aon3jQEVE1p+dS8p5fghxMOlPjmNOu/O0E5mCMmCJg=; b=rFzgu/fTwIFtIzj3hIRVlHYam2QH0zHd8vllpc3wpbLiV2qGfGZ3UpcffmVef0gaow g7/M3nNR6q/qzXUtm4ZPQ7cAr+swTK6yNgzFzQPDEKer+ketMawHrTAeerMfB3L8JW7h uM5BhnxmS8VdhJxGwWNwZl0j7lk0tK0h+rhLhLL3l7TU2ksA29YPICUnm2l6MSCNbZDc Q8CwNpVeTZdExdYVuSbDVGZFnbh3BTIwoQKg6fDxyiwkhXVAwM8i3IcOM2wTDyOlQ5oC dlDR/+GQfvdhowjbLBpkZXG1/ylS6SG4mdhUQYBBCTzM0I4/uOD/U1XvU60AwPfhyAk8 f6nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=cB9BjZ+U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 134-20020a63028c000000b0055e48c43ab7si1417776pgc.470.2023.08.04.01.46.14; Fri, 04 Aug 2023 01:46:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=cB9BjZ+U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234208AbjHDHaN (ORCPT + 99 others); Fri, 4 Aug 2023 03:30:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234218AbjHDH3U (ORCPT ); Fri, 4 Aug 2023 03:29:20 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 129423AB2 for ; Fri, 4 Aug 2023 00:29:12 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4D8D766071C2; Fri, 4 Aug 2023 08:29:10 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691134150; bh=eOGxKFVDezkCZBwW2hUee7R5nYDwDHZk82jsXyRXIgQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cB9BjZ+Uh0lMovSOzN0a/Ugu0u79UdFA39R9jOkGWpsGAIuE/yvVPkSaK9yGjcD1A atqx7Bn/kZGL3XX2lgxbpyhURUD4/G2snCvNmr3pdr0EXiKC3UFNVQo9+jtvZvi3pd BNZDHv3q9fSSm/Q7r97fR/tmZN0xbjxL59PpWye9XAcVASV28skJwuhd/xv2hftjpA zj90iUOorcQrN+C3ygC7ChzInMNnuznvohNKXV7RqxZivGFYmKuuahD6ZX+irw0VL7 BN1kawNtm1oeJC1xd1EkeUde0ybauzjNS6iq5jhYwkorvdjp8/UvWmzxFQ6c1TB5TB rE/jinzzjd+Ag== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v10 16/16] drm/mediatek: aal: Compress of_device_id entries and add sentinel Date: Fri, 4 Aug 2023 09:28:50 +0200 Message-ID: <20230804072850.89365-17-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773287545855461185 X-GMAIL-MSGID: 1773287545855461185 Compress the entry for mediatek,mt8173-disp-aal, as it fits in one line, and fix the style; while at it, also add the usual sentinel comment to the last entry. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index e6ab3eaa1126..70de5f3007e4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -212,10 +212,9 @@ static const struct mtk_disp_aal_data mt8173_aal_driver_data = { }; static const struct of_device_id mtk_disp_aal_driver_dt_match[] = { - { .compatible = "mediatek,mt8173-disp-aal", - .data = &mt8173_aal_driver_data}, - { .compatible = "mediatek,mt8183-disp-aal"}, - {}, + { .compatible = "mediatek,mt8173-disp-aal", .data = &mt8173_aal_driver_data }, + { .compatible = "mediatek,mt8183-disp-aal" }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_disp_aal_driver_dt_match);