From patchwork Fri Aug 4 02:02:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 130923 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1533281vqx; Thu, 3 Aug 2023 19:30:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFSluD4+FyFeta/B8XQXY9MQqaHsP1RYxWn0Ekv43tGK7VMBFMNVbEWsW+99m+jcr5KfbjD X-Received: by 2002:a17:906:1099:b0:99c:9e69:6a1c with SMTP id u25-20020a170906109900b0099c9e696a1cmr315897eju.67.1691116216104; Thu, 03 Aug 2023 19:30:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691116216; cv=none; d=google.com; s=arc-20160816; b=hNxAM9JAhTAzFdRWbKsN4lt0rjn43Clp0Qc/M5xSlNhqtEdZZkstSjXRKD63b48+I7 AtQdnx8HvfJs/nHetpp7XxnF88h1Wii+Xb17gWAhckiVx3wteGejIEHI1Q+9W17oN0ZQ LO/gO+8CMAm2fBzwIbkj0ymt+hQBWvgysA+R/E+s0La6f5vmvJdXTywBRY4E9yqmyHp6 wEBe28KvxjvpeFS5TlPB0V7dF0zKK9yrLWq51d+KtmlUrGRqHBwdubfwVlVACKGfyZN0 YP6InxWK6t6f/Xa5Jyc0Wt25Mo0ySGKcmNUUw0P+qeNEkb1taBYD60/lCHMrL9LPmrbh eOTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=FDK3czEZ4MiEPXOG4Kz3LGP8DV54T6JWxX/ewnAGyII=; fh=WCphHDjGHb2n6ExUxc8S0xlUZruKuzZWzdl57wRIMGI=; b=zZFmxg0OJbRHkCchbJt20VHZaj24+whHzVE9ZuSnfkdaoPuxdypwKhwsn9Ct6U4y6t Fn84HfYm2WSi0vK4rVNkgfdznO8dPPxPDXTCFIP+4B0Hrc8YgRLhP9V38NGFjRrVE4bu pYlAB9LFFLTyuvS/wqzW56s9rQccYRjs3dO7lFnAu54gr3MK7Nn8stC3ZY+bvf3T63Cr QMG5jtkLn/TT0oHdoZ8qULTBrK6vpKLMZkW36sflpy/fAgiSW+ayh+jT67Ujq3vhqXIT luYUoeITgPkxqqn06sU8/Mm3WzC1CDhg29BwfJhr9fEaPuJy12PWsrmoukonyBY1Qj38 RxVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ka2-20020a170907990200b0099bd2067164si683454ejc.1041.2023.08.03.19.29.48; Thu, 03 Aug 2023 19:30:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232661AbjHDCDB convert rfc822-to-8bit (ORCPT + 99 others); Thu, 3 Aug 2023 22:03:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232875AbjHDCC7 (ORCPT ); Thu, 3 Aug 2023 22:02:59 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C3744482; Thu, 3 Aug 2023 19:02:58 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 3EB2980DF; Fri, 4 Aug 2023 10:02:57 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 4 Aug 2023 10:02:56 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 4 Aug 2023 10:02:55 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Ziv Xu , William Qiu Subject: [PATCH v6 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC Date: Fri, 4 Aug 2023 10:02:52 +0800 Message-ID: <20230804020254.291239-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804020254.291239-1-william.qiu@starfivetech.com> References: <20230804020254.291239-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773263877299122412 X-GMAIL-MSGID: 1773263877299122412 The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Signed-off-by: William Qiu Reviewed-by: Hal Feng Reviewed-by: Conor Dooley --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 4f15f9a0cc34..cca81f89e252 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -86,7 +86,17 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 + + clock-names: + oneOf: + - items: + - const: ref + - items: + - const: ref + - const: ahb + - const: apb cdns,fifo-depth: description: From patchwork Fri Aug 4 02:02:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 130915 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1530475vqx; Thu, 3 Aug 2023 19:22:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGLzFRTumJhhFT2S3vmJsbe2FsgzKRigIroUwy4VOatr2DmFbbe7vkBTomC8CaMtbN3FC+C X-Received: by 2002:a2e:9016:0:b0:2b6:e283:32cb with SMTP id h22-20020a2e9016000000b002b6e28332cbmr370834ljg.23.1691115721504; Thu, 03 Aug 2023 19:22:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691115721; cv=none; d=google.com; s=arc-20160816; b=RgATcQdRavGCa5gYqx+NIV8FsWJ2VtLgF2Vw70qEGlviasKtISpaxOQPCMIwkrHCJy ysTJ+j9CbWXa58aG0Uaem6uK3k4SB50V8+E7a++qhI1gBtJ2sScoJAbc4B3Vvin4HJqC VdM27fRWTSsByghSiBl/m7N/BujgQXJd6hfOSuhLS9gav1vD1ISkJqLiYuWZkb12Fy79 RP7MTNbzT7T60/VDFeZ+55rJvmWFLuvkFz84S9wlQngCiT2vuKJIyJmA8pC7ik8wyTZp XgqGM+gQqyMpkR/tNjBugPCZ20k18RA81SLj/miXKQKNad6HPF2+9h0ynOlA9Bjj9IAo QhMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=FIlhYjTOVFKAiFppnFneTyNvgG+/p6wVoTk4eZYuaEQ=; fh=WCphHDjGHb2n6ExUxc8S0xlUZruKuzZWzdl57wRIMGI=; b=DZoHX6zh8PcvWbxh+mxeolp63YwFZlVIXzUwVEyHjIUa+mTgeUbj8Xu26982FlAilJ hVgK66CuiEcFaZGzirvts8aZhZBIMKGmp+OY1F+eThVeyInyxfAKREwFsOMmsK5kbuJK qPFEFB5tw38V8ABw4KheCbV7dQbLfj7oJKDaobMlNJpmxCLv484Aj4lFhZ3Jxj0BAeLY nHmF0XgZyJGC5d7e1wob5JjVQz3TzElJ4s8La4YUe5KiSodC3L9AiND6KVd1ctqRqV7Z /vm/gNkJGuI+8mRHP67O2OmvA4gQNVBxgAIxje7cvW3u0oHb5at9IENohJV0OVymLT8+ mpog== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p13-20020a170906140d00b0099bcf4f5e79si819970ejc.674.2023.08.03.19.21.38; Thu, 03 Aug 2023 19:22:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232787AbjHDCDE convert rfc822-to-8bit (ORCPT + 99 others); Thu, 3 Aug 2023 22:03:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231528AbjHDCDB (ORCPT ); Thu, 3 Aug 2023 22:03:01 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA04B448B; Thu, 3 Aug 2023 19:02:59 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 5724124DCFA; Fri, 4 Aug 2023 10:02:57 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 4 Aug 2023 10:02:57 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 4 Aug 2023 10:02:56 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Ziv Xu , William Qiu Subject: [PATCH v6 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI Date: Fri, 4 Aug 2023 10:02:53 +0800 Message-ID: <20230804020254.291239-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804020254.291239-1-william.qiu@starfivetech.com> References: <20230804020254.291239-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773263358665421123 X-GMAIL-MSGID: 1773263358665421123 Add JH7110's clock initialization code to the driver. Signed-off-by: William Qiu Reviewed-by: Hal Feng --- drivers/spi/spi-cadence-quadspi.c | 67 +++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index abf10f92415d..16985e1fe610 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -47,6 +47,12 @@ #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) +enum { + CLK_QSPI_APB = 0, + CLK_QSPI_AHB, + CLK_QSPI_NUM, +}; + struct cqspi_st; struct cqspi_flash_pdata { @@ -64,6 +70,7 @@ struct cqspi_st { struct platform_device *pdev; struct spi_master *master; struct clk *clk; + struct clk *clks[CLK_QSPI_NUM]; unsigned int sclk; void __iomem *iobase; @@ -92,6 +99,8 @@ struct cqspi_st { bool wr_completion; bool slow_sram; bool apb_ahb_hazard; + + bool is_jh7110; /* Flag for StarFive JH7110 SoC */ }; struct cqspi_driver_platdata { @@ -100,6 +109,8 @@ struct cqspi_driver_platdata { int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx); u32 (*get_dma_status)(struct cqspi_st *cqspi); + int (*jh7110_clk_init)(struct platform_device *pdev, + struct cqspi_st *cqspi); }; /* Operation timeout value */ @@ -1630,6 +1641,51 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) return 0; } +static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi) +{ + static struct clk_bulk_data qspiclk[] = { + { .id = "apb" }, + { .id = "ahb" }, + }; + + int ret = 0; + + ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); + if (ret) { + dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); + return ret; + } + + cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk; + cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk; + + ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); + if (ret) { + dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); + return ret; + } + + ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); + if (ret) { + dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); + goto disable_apb_clk; + } + + cqspi->is_jh7110 = true; + + return 0; + +disable_apb_clk: + clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); + + return ret; +} + +static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi) +{ + clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); + clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); +} static int cqspi_probe(struct platform_device *pdev) { const struct cqspi_driver_platdata *ddata; @@ -1655,6 +1711,7 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->pdev = pdev; cqspi->master = master; + cqspi->is_jh7110 = false; platform_set_drvdata(pdev, cqspi); /* Obtain configuration from OF. */ @@ -1766,6 +1823,12 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) cqspi->apb_ahb_hazard = true; + if (ddata->jh7110_clk_init) { + ret = cqspi_jh7110_clk_init(pdev, cqspi); + if (ret) + goto probe_clk_failed; + } + if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) { ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); @@ -1830,6 +1893,9 @@ static void cqspi_remove(struct platform_device *pdev) clk_disable_unprepare(cqspi->clk); + if (cqspi->is_jh7110) + cqspi_jh7110_disable_clk(pdev, cqspi); + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } @@ -1897,6 +1963,7 @@ static const struct cqspi_driver_platdata versal_ospi = { static const struct cqspi_driver_platdata jh7110_qspi = { .quirks = CQSPI_DISABLE_DAC_MODE, + .jh7110_clk_init = cqspi_jh7110_clk_init, }; static const struct cqspi_driver_platdata pensando_cdns_qspi = { From patchwork Fri Aug 4 02:02:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 130917 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1530592vqx; Thu, 3 Aug 2023 19:22:26 -0700 (PDT) X-Google-Smtp-Source: APBJJlH7bHWb5AraluQZKyw4QN06EsYpK6BQwEV1CWyY5ro7qXOtKwn3VZ/2F6lIa/ilC9mF4Ral X-Received: by 2002:a17:906:519d:b0:99b:d682:f306 with SMTP id y29-20020a170906519d00b0099bd682f306mr12857022ejk.4.1691115746007; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s5-20020a170906354500b00992f7fe9c0bsi856027eja.328.2023.08.03.19.22.02; Thu, 03 Aug 2023 19:22:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232800AbjHDCDG convert rfc822-to-8bit (ORCPT + 99 others); Thu, 3 Aug 2023 22:03:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231594AbjHDCDB (ORCPT ); Thu, 3 Aug 2023 22:03:01 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C975FE69; Thu, 3 Aug 2023 19:02:59 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 041E724E188; Fri, 4 Aug 2023 10:02:58 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 4 Aug 2023 10:02:58 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 4 Aug 2023 10:02:57 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Ziv Xu , William Qiu Subject: [PATCH v6 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC Date: Fri, 4 Aug 2023 10:02:54 +0800 Message-ID: <20230804020254.291239-4-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804020254.291239-1-william.qiu@starfivetech.com> References: <20230804020254.291239-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773263384639200838 X-GMAIL-MSGID: 1773263384639200838 Add the quad spi controller node for the StarFive JH7110 SoC. Co-developed-by: Ziv Xu Signed-off-by: Ziv Xu Signed-off-by: William Qiu Reviewed-by: Hal Feng --- .../jh7110-starfive-visionfive-2.dtsi | 36 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 19 ++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index fa0061eb33a7..7f2d41ccc52d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -143,6 +143,42 @@ &i2c6 { status = "okay"; }; +&qspi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + cdns,read-delay = <5>; + spi-max-frequency = <12000000>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + spl@0 { + reg = <0x0 0x80000>; + }; + uboot-env@f0000 { + reg = <0xf0000 0x10000>; + }; + uboot@100000 { + reg = <0x100000 0x400000>; + }; + reserved-data@600000 { + reg = <0x600000 0x1000000>; + }; + }; + }; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins { diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index ec2e70011a73..9740adc9df4e 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -473,6 +473,25 @@ i2c6: i2c@12060000 { status = "disabled"; }; + qspi: spi@13010000 { + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000>, + <0x0 0x21000000 0x0 0x400000>; + interrupts = <25>; + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_QSPI_AHB>, + <&syscrg JH7110_SYSCLK_QSPI_APB>; + clock-names = "ref", "ahb", "apb"; + resets = <&syscrg JH7110_SYSRST_QSPI_APB>, + <&syscrg JH7110_SYSRST_QSPI_AHB>, + <&syscrg JH7110_SYSRST_QSPI_REF>; + reset-names = "qspi", "qspi-ocp", "rstc_ref"; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + status = "disabled"; + }; + syscrg: clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x0 0x13020000 0x0 0x10000>;