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Thu, 3 Aug 2023 18:01:42 -0500 From: Smita Koralahalli To: , , CC: Bjorn Helgaas , , Lukas Wunner , Kuppuswamy Sathyanarayanan , Mahesh J Salgaonkar , Alison Schofield , "Vishal Verma" , Ira Weiny , "Ben Widawsky" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Terry Bowman , Robert Richter , Smita Koralahalli Subject: [PATCH v3 1/3] cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers Date: Thu, 3 Aug 2023 23:01:27 +0000 Message-ID: <20230803230129.127590-2-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230803230129.127590-1-Smita.KoralahalliChannabasappa@amd.com> References: <20230803230129.127590-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|PH7PR12MB7455:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b71e10a-1d5f-4c1a-2e6a-08db94759b73 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2023 23:01:44.1439 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b71e10a-1d5f-4c1a-2e6a-08db94759b73 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7455 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773256053022223296 X-GMAIL-MSGID: 1773256053022223296 According to Section 9.17.2, Table 9-26 of CXL Specification [1], owner of AER should also own CXL Protocol Error Management as there is no explicit control of CXL Protocol error. And the CXL RAS Cap registers reported on Protocol errors should check for AER _OSC rather than CXL Memory Error Reporting Control _OSC. The CXL Memory Error Reporting Control _OSC specifically highlights handling Memory Error Logging and Signaling Enhancements. These kinds of errors are reported through a device's mailbox and can be managed independently from CXL Protocol Errors. This change fixes handling and reporting CXL Protocol Errors and RAS registers natively with native AER and FW-First CXL Memory Error Reporting Control. [1] Compute Express Link (CXL) Specification, Revision 3.1, Aug 1 2022. Fixes: 248529edc86f ("cxl: add RAS status unmasking for CXL") Signed-off-by: Smita Koralahalli Reviewed-by: Robert Richter --- v2: Added fixes tag. Included what the patch fixes in commit message. v3: Added "Reviewed-by" tag. --- drivers/cxl/pci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 1cb1494c28fe..2323169b6e5f 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -541,9 +541,9 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) return 0; } - /* BIOS has CXL error control */ - if (!host_bridge->native_cxl_error) - return -ENXIO; + /* BIOS has PCIe AER error control */ + if (!host_bridge->native_aer) + return 0; rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); if (rc) From patchwork Thu Aug 3 23:01:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 130888 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1485935vqx; Thu, 3 Aug 2023 17:16:33 -0700 (PDT) X-Google-Smtp-Source: APBJJlGGsJrwk2Zxe7aeH2oHMCkfgsafFtpJlX0pPA6WIv82SLhxeJdaKxJajXv0G6ATA7t6v27E X-Received: by 2002:a17:90a:53a3:b0:268:437:7bd9 with SMTP id y32-20020a17090a53a300b0026804377bd9mr15728125pjh.3.1691108193524; Thu, 03 Aug 2023 17:16:33 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1691108193; cv=pass; d=google.com; s=arc-20160816; b=PKt28v5mw3bQFq0OCQbj5L1y58yz8bz9DdNx+DbMq0Y3S8H1KVLVti+Y6nVqKh9zKn iIvyjfb8MiMxjbkaMhDHXsJMhmpQkWcsyssC2f8NHoBQ6W6U9mU0k3gO3KLwWZ2M8nqP MIA3MHCCwIqfqURhLi9XFBoywC0/ylSds/PSdkzVZI20GWatGTaYEYP6ISBlQs/L9yYK +NbVgEjFNAsfmTANDolza0kaSbMKaG0maSDEFa2ulIkN4VsADpC5yiKq8F6yVDzh8ddM sWQ5cBtZHaLgXTCaXVkAkXi/lrGveAtQjsRwKcYQXBlgXj+YmQkMjIasO0AaI4nM4key jyDQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=n8PcQoZqkJdOCwCS8Ahh13hNf57wf2tT1bkYRbMh4wA=; fh=XsftW3UEsKVDpg34R8O86oa1udFTwHG6Ldr3ac/pbNM=; b=iHacUMV/gBNFT/RycM/FNuERuqQqzRV4d6u0doLeorPYqPvZQ2Eo/a5QrqkFrG+JEf uK6lN4KcBcOhZEZLLMsIPsDpXKyJ7uHzKxvjEUaOJml9DRQETY9NVBRS3n1TDYi54b/j g46x3EEULD5YobUOp1m9bIILqlvPXlLmao5xT9pRXgxJinFLtnjt+iU+39KasoWInkS3 b5cSEaCaRipdscTFdxAuuZd4VVqzTna7Ap7dJipqtrGRv/V1pnA4rof/qqMNM9nbGRuc 7H4ObVJxYgrCirZO25XtQZBonayDkaJqkX7nmi7Ur+oRXyWfGjHn4kw0B0omDAdHAS2J 9Feg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=zFNuR+NH; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 3 Aug 2023 18:01:43 -0500 From: Smita Koralahalli To: , , CC: Bjorn Helgaas , , Lukas Wunner , Kuppuswamy Sathyanarayanan , Mahesh J Salgaonkar , Alison Schofield , "Vishal Verma" , Ira Weiny , "Ben Widawsky" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Terry Bowman , Robert Richter , Smita Koralahalli Subject: [PATCH v3 2/3] PCI/AER: Export pcie_aer_is_native() Date: Thu, 3 Aug 2023 23:01:28 +0000 Message-ID: <20230803230129.127590-3-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230803230129.127590-1-Smita.KoralahalliChannabasappa@amd.com> References: <20230803230129.127590-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|SJ2PR12MB8845:EE_ X-MS-Office365-Filtering-Correlation-Id: 2558bfcd-e1a0-467d-e811-08db94759c6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Smita Koralahalli Acked-by: Bjorn Helgaas Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Robert Richter --- v2: Fixed $SUBJECT v3: Added "Reviewd-by" tag. --- drivers/pci/pcie/aer.c | 1 + drivers/pci/pcie/portdrv.h | 2 -- include/linux/aer.h | 2 ++ 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index f6c24ded134c..87d90dbda023 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -229,6 +229,7 @@ int pcie_aer_is_native(struct pci_dev *dev) return pcie_ports_native || host->native_aer; } +EXPORT_SYMBOL_GPL(pcie_aer_is_native); int pci_enable_pcie_error_reporting(struct pci_dev *dev) { diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 58a2b1a1cae4..1f3803bde7ee 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -29,10 +29,8 @@ extern bool pcie_ports_dpc_native; #ifdef CONFIG_PCIEAER int pcie_aer_init(void); -int pcie_aer_is_native(struct pci_dev *dev); #else static inline int pcie_aer_init(void) { return 0; } -static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } #endif #ifdef CONFIG_HOTPLUG_PCI_PCIE diff --git a/include/linux/aer.h b/include/linux/aer.h index 3a3ab05e13fd..94ce49a5f8d5 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -45,6 +45,7 @@ struct aer_capability_regs { int pci_enable_pcie_error_reporting(struct pci_dev *dev); int pci_disable_pcie_error_reporting(struct pci_dev *dev); int pci_aer_clear_nonfatal_status(struct pci_dev *dev); +int pcie_aer_is_native(struct pci_dev *dev); #else static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) { @@ -58,6 +59,7 @@ static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) { return -EINVAL; } +static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } #endif void cper_print_aer(struct pci_dev *dev, int aer_severity, From patchwork Thu Aug 3 23:01:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 130895 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1499749vqx; Thu, 3 Aug 2023 17:56:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFkVCfYnOw98HCBr4A/npsC5W+2uwfD5cQ1oPYM5DPzumx4hN2bUeNeTAQpPj5El6R8Mrgp X-Received: by 2002:a17:906:209b:b0:99c:55ee:1798 with SMTP id 27-20020a170906209b00b0099c55ee1798mr3915605ejq.4.1691110578363; Thu, 03 Aug 2023 17:56:18 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1691110578; cv=pass; d=google.com; s=arc-20160816; b=w9FrZvVv8DfiMeq99auLUcKWu1Kcg8IFCF7zGAVx4sJLVkTzpbXfa0+oehjWDdFXuV vLpLII8ob22wks3JPI55NCBbeEZcbNLLl58m1VKy0vquW8gm6I1HvNY/rP0GySlxHh7P hdFUS8tO0nfv5bu86Tb5QWYgAO0d0IeDCdwqTZz+QZW8Sgg+fLemn2zuPCLE3HdhONv4 aA0+wFQfMSMQw9SsTjIw0MiH5Cg4xphtWVr2Vy18zCURggpX7Czcw/eWDXAnzMH4ZV/y BIZeS67gbhEvDqd1ToZqGgblnD6ph8gkb1mlWJTy8VVH5ebepF2d+MJWSKhAfMNHBA0O uwXA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=E139Cu/GtI+mpX6fMkqExTq66BfVTreBbBqZapwpS/M=; fh=XsftW3UEsKVDpg34R8O86oa1udFTwHG6Ldr3ac/pbNM=; b=pvqz9SyZLJViZybdIX0KxoiYXDovJTSEaAVqk41IoTqxQ5FkC0K6sX6PVMXbu3lbjg 5661CPObZ30mLV6UNW++cTJ4fGBeoDt6fwRtLEc4PZPjnCLJNRGEX222DCsXr7T0UhbP xaG2AkxHOJX9uOAsUNvKadf/QE2AGxbGHaQh7sRoov9P/MLc3XMZ6spmXiJunShPHaQo QCSXo0vTohUOTJTOkn8r1mDiqOJiBXCw8fNbA8lYa3Byi0eqIDPg5tI/vt9q72kNw2xi OJiK9jgsv6lBBEF4EGnr2vfNGEbeAHkWEaota+/oz3cLMXjMW+nRkdYNn7uQHEZVdZak mVxA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="qB/dkOjE"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 3 Aug 2023 18:01:44 -0500 From: Smita Koralahalli To: , , CC: Bjorn Helgaas , , Lukas Wunner , Kuppuswamy Sathyanarayanan , Mahesh J Salgaonkar , Alison Schofield , "Vishal Verma" , Ira Weiny , "Ben Widawsky" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Terry Bowman , Robert Richter , Smita Koralahalli Subject: [PATCH v3 3/3] cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native() Date: Thu, 3 Aug 2023 23:01:29 +0000 Message-ID: <20230803230129.127590-4-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230803230129.127590-1-Smita.KoralahalliChannabasappa@amd.com> References: <20230803230129.127590-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|BL0PR12MB4963:EE_ X-MS-Office365-Filtering-Correlation-Id: d4381ef0-5a58-4f72-81ce-08db94759cca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2023 23:01:46.4096 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4381ef0-5a58-4f72-81ce-08db94759cca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4963 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773257965687155554 X-GMAIL-MSGID: 1773257965687155554 Use pcie_aer_is_native() to determine the native AER ownership as the usage of host_bride->native_aer does not cover command line override of AER ownership. Signed-off-by: Smita Koralahalli Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Robert Richter --- v2: Replaced pcie_aer_is_native() at a later stage for automated backports. v3: Added more context to commit message. Added "Reviewed-by" tag. --- drivers/cxl/pci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 2323169b6e5f..44a21ab7add5 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, static int cxl_pci_ras_unmask(struct pci_dev *pdev) { - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); void __iomem *addr; u32 orig_val, val, mask; @@ -542,7 +541,7 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) } /* BIOS has PCIe AER error control */ - if (!host_bridge->native_aer) + if (!pcie_aer_is_native(pdev)) return 0; rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);