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Wysocki" Subject: [RFC PATCH v1 01/21] ACPICA: MADT: Add RISC-V external interrupt controllers Date: Thu, 3 Aug 2023 23:28:56 +0530 Message-Id: <20230803175916.3174453-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773237065271919883 X-GMAIL-MSGID: 1773237065271919883 ACPICA commit 8c048cee4ea7b9ded8db3e1b3b9c14e21e084a2c This adds 3 different external interrupt controller definitions in MADT for RISC-V. 1) RISC-V PLIC is a platform interrupt controller for handling wired interrupt in a RISC-V systems. 2) RISC-V IMSIC is MSI interrupt controller to support MSI interrupts. 3) RISC-V APLIC has dual functionality. First it can act like PLIC and direct all wired interrupts to the CPU which doesn't have MSI controller. Second, when the CPU has MSI controller (IMSIC), it will act as a converter from wired interrupts to MSI. Update the existing RINTC structure also to support these external interrupt controllers. This codefirst ECR is approved by UEFI forum and will be part of next ACPI spec version. Link: https://github.com/acpica/acpica/commit/8c048cee Co-developed-by: Haibo Xu Signed-off-by: Haibo Xu Signed-off-by: Sunil V L Signed-off-by: Bob Moore Signed-off-by: Rafael J. Wysocki --- include/acpi/actbl2.h | 50 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 0029336775a9..280ab4c7f77a 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -893,7 +893,10 @@ enum acpi_madt_type { ACPI_MADT_TYPE_BIO_PIC = 22, ACPI_MADT_TYPE_LPC_PIC = 23, ACPI_MADT_TYPE_RINTC = 24, - ACPI_MADT_TYPE_RESERVED = 25, /* 25 to 0x7F are reserved */ + ACPI_MADT_TYPE_IMSIC = 25, + ACPI_MADT_TYPE_APLIC = 26, + ACPI_MADT_TYPE_PLIC = 27, + ACPI_MADT_TYPE_RESERVED = 28, /* 28 to 0x7F are reserved */ ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */ }; @@ -1261,6 +1264,9 @@ struct acpi_madt_rintc { u32 flags; u64 hart_id; u32 uid; /* ACPI processor UID */ + u32 ext_intc_id; /* External INTC Id */ + u64 imsic_addr; /* IMSIC base address */ + u32 imsic_size; /* IMSIC size */ }; /* Values for RISC-V INTC Version field above */ @@ -1271,6 +1277,48 @@ enum acpi_madt_rintc_version { ACPI_MADT_RINTC_VERSION_RESERVED = 2 /* 2 and greater are reserved */ }; +/* 25: RISC-V IMSIC */ +struct acpi_madt_imsic { + struct acpi_subtable_header header; + u8 version; + u8 reserved; + u32 flags; + u16 num_ids; + u16 num_guest_ids; + u8 guest_index_bits; + u8 hart_index_bits; + u8 group_index_bits; + u8 group_index_shift; +}; + +/* 26: RISC-V APLIC */ +struct acpi_madt_aplic { + struct acpi_subtable_header header; + u8 version; + u8 id; + u32 flags; + u8 hw_id[8]; + u16 num_idcs; + u16 num_sources; + u32 gsi_base; + u64 base_addr; + u32 size; +}; + +/* 27: RISC-V PLIC */ +struct acpi_madt_plic { + struct acpi_subtable_header header; + u8 version; + u8 id; + u8 hw_id[8]; + u16 num_irqs; + u16 max_prio; + u32 flags; + u32 size; + u64 base_addr; + u32 gsi_base; +}; + /* 80: OEM data */ struct acpi_madt_oem_data { From patchwork Thu Aug 3 17:58:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130800 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1341168vqx; Thu, 3 Aug 2023 11:50:12 -0700 (PDT) X-Google-Smtp-Source: APBJJlFPjW0SBn/lvP19Xemi/20CrF0EFCzMjTn7R1o41w/DsGTCvmTZrc/7ec1eOWt4wJQFxJqc X-Received: by 2002:a17:906:cc55:b0:975:63f4:4b with SMTP id mm21-20020a170906cc5500b0097563f4004bmr8694986ejb.36.1691088612315; Thu, 03 Aug 2023 11:50:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691088612; cv=none; d=google.com; s=arc-20160816; b=n1kW15ak0wuPRCNfpP2fX0Eeg42v8CJDmwfWk0T7OhITe3F5RIYwMLEcv+kfh/i97y MIRXEz4aWje64wSJ2y1gU2o/oXmN+VhbwadWNZ05EF/zlOdQdcBtFtAJAJ4MR4phoOce dena+J5spMMR51EM62WCi7yk51AnrhHGgP5Du8xkdL57sAWHz+UwanoBZm8psjNddpqA Kx1jH1uIzU+V9+Be8zgyEex+aalu4tleoRQ/m+X8cgxXe61HhwTGrQEkknywPOmWDj53 +um7EJb9kcXnR2DBjjwGVR6jZjp8TdmWRG0xOGYcG1fDo5uqh5OegnKrA+iW4jgBXHC8 YlGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uZnV0ewqSpbZRhAC/LQ4a5BRuhAMm0ngpEEdA3S7vUc=; fh=EMQkoiWSc4qWd2/rN2S9A04kB0sxFY9qB+AxnVO+lBs=; b=HC4RpYwH3ce0brWC8RHQSAh46Yb4eIFU6UXLBWGduJUw3fSb6WOf+FRN/wpiJbcjbw 9ESSOqaaCJ7es9h5k3F4G6nhspYHnl1YOOvXA1T6pmVMjPhItlkaMiEXNYafczKQwFbE Tj72yOABaWMK8swzNpAWO7boZS1MBnvRHolMJsXEbYYBkyOrJO0GEqnGiyW7RCeesetD z49E1+YgisB6z46ggxIO2flKsA97vZWev+v7aszchnhHHdCMPY0/4/rXVcTJUdUwX4cH gmhXgJxZTzWqAIXiJyQIBFNyuw4n/YWrISmg9eUfBRuiEP3tQaXcvSb5ua1owLGddWDq U+og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=bnUHrvcB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L , "Rafael J . Wysocki" Subject: [RFC PATCH v1 02/21] ACPICA: RHCT: Add flags, CMO and MMU nodes Date: Thu, 3 Aug 2023 23:28:57 +0530 Message-Id: <20230803175916.3174453-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773234932645802151 X-GMAIL-MSGID: 1773234932645802151 ACPICA commit 2eded5a6a13d892b7dc3be6096e7b1e8d4407600 Update RHCT table with below details. 1) Add additional structure to describe the Cache Management Operation (CMO) related information. 2) Add structure to describe MMU type. 3) Convert the current reserved field to flags and define a flag to indicate timer capability. This codefirst ECR is approved by UEFI forum and will be part of next ACPI spec version. Link: https://github.com/acpica/acpica/commit/2eded5a6 Signed-off-by: Sunil V L Signed-off-by: Bob Moore Signed-off-by: Rafael J. Wysocki --- include/acpi/actbl2.h | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 280ab4c7f77a..3751ae69432f 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -2778,12 +2778,15 @@ enum acpi_rgrt_image_type { struct acpi_table_rhct { struct acpi_table_header header; /* Common ACPI table header */ - u32 reserved; + u32 flags; /* RHCT flags */ u64 time_base_freq; u32 node_count; u32 node_offset; }; +/* RHCT Flags */ + +#define ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU (1) /* * RHCT subtables */ @@ -2797,6 +2800,9 @@ struct acpi_rhct_node_header { enum acpi_rhct_node_type { ACPI_RHCT_NODE_TYPE_ISA_STRING = 0x0000, + ACPI_RHCT_NODE_TYPE_CMO = 0x0001, + ACPI_RHCT_NODE_TYPE_MMU = 0x0002, + ACPI_RHCT_NODE_TYPE_RESERVED = 0x0003, ACPI_RHCT_NODE_TYPE_HART_INFO = 0xFFFF, }; @@ -2810,6 +2816,24 @@ struct acpi_rhct_isa_string { char isa[]; }; +struct acpi_rhct_cmo_node { + u8 reserved; /* Must be zero */ + u8 cbom_size; /* CBOM size in powerof 2 */ + u8 cbop_size; /* CBOP size in powerof 2 */ + u8 cboz_size; /* CBOZ size in powerof 2 */ +}; + +struct acpi_rhct_mmu_node { + u8 reserved; /* Must be zero */ + u8 mmu_type; /* Virtual Address Scheme */ +}; + +enum acpi_rhct_mmu_type { + ACPI_RHCT_MMU_TYPE_SV39 = 0, + ACPI_RHCT_MMU_TYPE_SV48 = 1, + ACPI_RHCT_MMU_TYPE_SV57 = 2 +}; + /* Hart Info node structure */ struct acpi_rhct_hart_info { u16 num_offsets; From patchwork Thu Aug 3 17:58:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130820 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1361166vqx; Thu, 3 Aug 2023 12:28:18 -0700 (PDT) X-Google-Smtp-Source: APBJJlGCUqFEFnxrHqnIhKKioZDb82S8lqlPFL4FdFOUitYqHjiCy7soww9wurFarFQsU5sobo1T X-Received: by 2002:a05:6a00:13a5:b0:687:1bb1:91ab with SMTP id t37-20020a056a0013a500b006871bb191abmr24166564pfg.33.1691090898300; Thu, 03 Aug 2023 12:28:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691090898; cv=none; d=google.com; s=arc-20160816; b=fGvGjhl0ePnDten4ErmZlFevpaJXYgM18qUybJOeKj3Dis8Y95XKyl1n7J/EHWvmhy whos2VYAZvL+OV1VeI9e5yb00sIjFqL29slmixmD1tlBpXck7zp3VIMH+a3V9X1iYKgp Exc+v2c8tvK1UT6LUjy9w8I9wxI0g2M96cgWl2EV+tEefkk2VrpnBeOy+GLzgd650K4C I7CoCh43UpmlGz6V66QyfNpYi/Xim/ZX8b1KOGp1zdxOJyWsovDKQBWVJC4/IF/oRZtm qJuOnyCzrSxYXNHIV0oa6jwyhztaDCnaV/M3Fv+ffbAjzPvQ/TEPkk5UytuUglXAndqh zJaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dlgMxBU+gnbxavLK2CnXHLqjxrOHpsQhLJivrmp7gq8=; fh=Ii7qdeG42WQpLpi2F+Y9OG8JPs/iA1NkIDq1oHnDEC8=; b=b9ib6Ist5lNqyZOXWgjmjpBxrLhSXlzhpmeGnvuedyP2zV05rnuLPocWYfxJrO9110 NTEyaPTBd/cpENt4792HfViGaF3zpnP/lf4pnLqw31nQ3+fcptLbw5Ksa7Orvz/FsY3r PHk8s5FNKKNgUOsmfThtamo0WcsgWQiCZhXF5Sdb77906xUA/l7OszFcVTRt5gNyV2XL gQ+MtIsOHr2vkrSQhCTe/Fex4Rlhhfaz9nkxDXD9fG8r4/wrb2WYRtfS5/0mICK3IdlM 3x8k8v8zaFztJSjEe5s/OXvfHCdt4mItR9UP95go1tMjrIKJ+5/g0MozemGa+J5eVAa8 gLjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="Mn/vo0Mo"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L , kernel test robot Subject: [RFC PATCH v1 03/21] RISC-V: ACPI: Fix acpi_os_ioremap to return iomem address Date: Thu, 3 Aug 2023 23:28:58 +0530 Message-Id: <20230803175916.3174453-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773237329604173428 X-GMAIL-MSGID: 1773237329604173428 acpi_os_ioremap() currently is a wrapper to memremap() on RISC-V. But the callers of acpi_os_ioremap() expect it to return __iomem address and hence sparse tool reports a new warning. Fix this issue by type casting to __iomem type. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202307230357.egcTAefj-lkp@intel.com/ Fixes: a91a9ffbd3a5 ("RISC-V: Add support to build the ACPI core") Signed-off-by: Sunil V L Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 2 +- arch/riscv/kernel/acpi.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index f71ce21ff684..d5604d2073bc 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -19,7 +19,7 @@ typedef u64 phys_cpuid_t; #define PHYS_CPUID_INVALID INVALID_HARTID /* ACPI table mapping after acpi_permanent_mmap is set */ -void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); +void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); #define acpi_os_ioremap acpi_os_ioremap #define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */ diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 5ee03ebab80e..56cb2c986c48 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -215,9 +215,9 @@ void __init __acpi_unmap_table(void __iomem *map, unsigned long size) early_iounmap(map, size); } -void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) +void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) { - return memremap(phys, size, MEMREMAP_WB); + return (void __iomem *)memremap(phys, size, MEMREMAP_WB); } #ifdef CONFIG_PCI From patchwork Thu Aug 3 17:58:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130816 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1357822vqx; Thu, 3 Aug 2023 12:21:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEXpSRYlYOiodT32NgZt2K2pgGOLML6BO7SKWPiyQ+5NZ16pGpu9URylhmA1kkUbDqwRvFO X-Received: by 2002:aa7:d056:0:b0:523:1561:9033 with SMTP id n22-20020aa7d056000000b0052315619033mr900617edo.9.1691090463959; Thu, 03 Aug 2023 12:21:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691090463; cv=none; d=google.com; s=arc-20160816; b=ObsAXo/LOKmeF1F6L2ibyvkWvKxQ/+f2dbSIHAk0UJ0cx+nMxkP2Pu4NxI4KW8Fid0 4cbebuguEPHePWctgSm+WXr5yqHVLE5kzhvyV1Amu1gT2rBDwviJVR/dcIJKy0fuXds9 XwQAcRDeAGrstaIE0F9kySoLlwUKeCvEqBsfzW5tdKqtqnvmlpRF+HgVtF4YBNE1ICjW K+TpwKy0O/d8cZaJm3ZvGzokecEzWolQYCvZASWjb5cLI9fSn4MweVU6PpEek5zRihNb wEhHeGV7dIAo9YPmBQcErjUHhx+ELMFR/CcKGsqrTdPBn3yUaLseWWMVnSnowCUrPqtN cNtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Zrij3XCVzAcOqQorsC5sehKTr0CEJKtsrFsGaW9zZqM=; fh=UWUr25pr4rB0jy3IJcSr4OthRy6UhgP+er7dvxoyJpo=; b=kwXXrd+P3VoNIkTWU9KM1mS9UJUmp1hlaCFnqxW81n56tcFiIXp6YpIf8aTOEbQYle oAwMYdiTpWUjfa+nYAje4a7IDtDIiA1miQCUMmABZsdbTVNDqNJ95N164gWL7UlFXNd3 qFVc7QyanI1g5/u+YS6gxz0pnf/wVsXL59KsY7OfH5lRG2nv2JBiRXGGbzi//4I1V3cr bCkbfd8TJEyBeY4ix0qJ2ZwYNdIHMCTPouzGKv1gWU/WLApGU6tWiPvz7ISkdtP+4tW4 ZuCtmA0teTWcH4U63W2C8OqtF54zDuIbIPAnShRHE4qXMuCRK8Y9bSNpdXNIQ79kTMc0 bJ9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=g6+YMcM4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L , Ard Biesheuvel , Alexandre Ghiti Subject: [RFC PATCH v1 04/21] RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remapping Date: Thu, 3 Aug 2023 23:28:59 +0530 Message-Id: <20230803175916.3174453-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773236874133659644 X-GMAIL-MSGID: 1773236874133659644 Enhance the acpi_os_ioremap() to support opregions in MMIO space. Also, have strict checks using EFI memory map to allow remapping the RAM similar to arm64. Cc: Ard Biesheuvel Cc: Alexandre Ghiti Signed-off-by: Sunil V L Reviewed-by: Andrew Jones --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/acpi.c | 86 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 86 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 318f62a0a187..e19f32c12a68 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -38,6 +38,7 @@ config RISCV select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UBSAN_SANITIZE_ALL select ARCH_HAS_VDSO_DATA + select ARCH_KEEP_MEMBLOCK select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT select ARCH_STACKWALK diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 56cb2c986c48..aa4433bca6d9 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -17,6 +17,7 @@ #include #include #include +#include int acpi_noirq = 1; /* skip ACPI IRQ initialization */ int acpi_disabled = 1; @@ -217,7 +218,90 @@ void __init __acpi_unmap_table(void __iomem *map, unsigned long size) void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) { - return (void __iomem *)memremap(phys, size, MEMREMAP_WB); + efi_memory_desc_t *md, *region = NULL; + pgprot_t prot; + + if (WARN_ON_ONCE(!efi_enabled(EFI_MEMMAP))) + return NULL; + + for_each_efi_memory_desc(md) { + u64 end = md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT); + + if (phys < md->phys_addr || phys >= end) + continue; + + if (phys + size > end) { + pr_warn(FW_BUG "requested region covers multiple EFI memory regions\n"); + return NULL; + } + region = md; + break; + } + + /* + * It is fine for AML to remap regions that are not represented in the + * EFI memory map at all, as it only describes normal memory, and MMIO + * regions that require a virtual mapping to make them accessible to + * the EFI runtime services. + */ + prot = PAGE_KERNEL_IO; + if (region) { + switch (region->type) { + case EFI_LOADER_CODE: + case EFI_LOADER_DATA: + case EFI_BOOT_SERVICES_CODE: + case EFI_BOOT_SERVICES_DATA: + case EFI_CONVENTIONAL_MEMORY: + case EFI_PERSISTENT_MEMORY: + if (memblock_is_map_memory(phys) || + !memblock_is_region_memory(phys, size)) { + pr_warn(FW_BUG "requested region covers kernel memory @ %p\n", + &phys); + return NULL; + } + + /* + * Mapping kernel memory is permitted if the region in + * question is covered by a single memblock with the + * NOMAP attribute set: this enables the use of ACPI + * table overrides passed via initramfs. + * This particular use case only requires read access. + */ + fallthrough; + + case EFI_RUNTIME_SERVICES_CODE: + /* + * This would be unusual, but not problematic per se, + * as long as we take care not to create a writable + * mapping for executable code. + */ + prot = PAGE_KERNEL_RO; + break; + + case EFI_ACPI_RECLAIM_MEMORY: + /* + * ACPI reclaim memory is used to pass firmware tables + * and other data that is intended for consumption by + * the OS only, which may decide it wants to reclaim + * that memory and use it for something else. We never + * do that, but we usually add it to the linear map + * anyway, in which case we should use the existing + * mapping. + */ + if (memblock_is_map_memory(phys)) + return (void __iomem *)__va(phys); + fallthrough; + + default: + if (region->attribute & EFI_MEMORY_WB) + prot = PAGE_KERNEL; + else if ((region->attribute & EFI_MEMORY_WC) || + (region->attribute & EFI_MEMORY_WT)) + prot = pgprot_writecombine(PAGE_KERNEL); + } + } + + return ioremap_prot(phys, size, pgprot_val(prot)); } #ifdef CONFIG_PCI From patchwork Thu Aug 3 17:59:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130826 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1367403vqx; Thu, 3 Aug 2023 12:41:33 -0700 (PDT) X-Google-Smtp-Source: APBJJlEU8gcqUbuRc+LZo/Cl4B9Vk/rrDrTXjavkpOwJoEHKyMR/QSY47uL4nmInibbuFMbluu8D X-Received: by 2002:a05:6512:20cd:b0:4f8:70d8:28f8 with SMTP id u13-20020a05651220cd00b004f870d828f8mr6929271lfr.55.1691091693190; Thu, 03 Aug 2023 12:41:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691091693; cv=none; d=google.com; s=arc-20160816; b=DxttIhBxTIsWmgAZnyevoKDrv5NJindol5sUdt6fUzlWZ92Y791BpMyl4G2d1jkZKk VwPOEALaJVPM6hsgv6lNd9swOvGE3NorAWaMLuPsTKJeZcYEJwTuCpWKGaIqPAbQb9/k SvmR1HnQp1KUnJCDMBlYPqG/+eReuDRyL4RL9ocKTrgvYEvYs3ersb6gPdYASbFBPMXw YySqTmx5q6CR3DqdxaYUxube04QdkKHofFRtk1PuOyDdrMLWxFbNeB1f+jpFGjulzMTC KnhDAxsQUX03GGCAXBdEqfwFOGOEY5RmZDgXPgLbBj9wtEC93UuxwxIVY+mNz5LZ21WA sOhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HZyznREMZ8qiEWo3qjSd8Z0EQsRbIhIXLSiUggIdL7w=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=zXHhjdYt8VAmPc60CpdkCqBGP0TGGVATFkIfttYTAQNq5x2hR+rAKwKc49KNN6+uNc wL6RURF7Q8G7b9gG0ORlwZVNlYipI7AvverSd3uWo8ie6afajLpeYE6QafNRmvYWyvyO gy9a/FUtJmIyCDhgrRx8ziDEXmJfSjPuwilsTBcZSdEVbVLy83PUAcCbtpDwPj5btcUf yapCUVSA0LGh9hF2nQBmGASvqVnTByesW4Z37ejivf/y5j6uORUVy8D14PclHGBSkFMe 4nIQfcfe749OrgJT2lV7HGtEsvQggOX9Lw3BsTFV+mAWsrr2DTVT8fPYXPAEkh/WKOtB L4HA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=bhy59+dh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 05/21] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Date: Thu, 3 Aug 2023 23:29:00 +0530 Message-Id: <20230803175916.3174453-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773238163372420220 X-GMAIL-MSGID: 1773238163372420220 The functions defined in arm64 for ACPI support are required for RISC-V also. To avoid duplication, copy these functions to common location. Signed-off-by: Sunil V L --- arch/arm64/kernel/pci.c | 193 ---------------------------------------- drivers/pci/pci-acpi.c | 182 +++++++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+), 193 deletions(-) diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index 2276689b5411..fd9a7bed83ce 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -6,30 +6,7 @@ * Copyright (C) 2014 ARM Ltd. */ -#include -#include -#include -#include -#include -#include -#include #include -#include -#include -#include - -#ifdef CONFIG_ACPI -/* - * Try to assign the IRQ number when probing a new device - */ -int pcibios_alloc_irq(struct pci_dev *dev) -{ - if (!acpi_disabled) - acpi_pci_irq_enable(dev); - - return 0; -} -#endif /* * raw_pci_read/write - Platform-specific PCI config space access. @@ -63,173 +40,3 @@ int pcibus_to_node(struct pci_bus *bus) EXPORT_SYMBOL(pcibus_to_node); #endif - -#ifdef CONFIG_ACPI - -struct acpi_pci_generic_root_info { - struct acpi_pci_root_info common; - struct pci_config_window *cfg; /* config space mapping */ -}; - -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) -{ - struct pci_config_window *cfg = bus->sysdata; - struct acpi_device *adev = to_acpi_device(cfg->parent); - struct acpi_pci_root *root = acpi_driver_data(adev); - - return root->segment; -} - -int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) -{ - struct pci_config_window *cfg; - struct acpi_device *adev; - struct device *bus_dev; - - if (acpi_disabled) - return 0; - - cfg = bridge->bus->sysdata; - - /* - * On Hyper-V there is no corresponding ACPI device for a root bridge, - * therefore ->parent is set as NULL by the driver. And set 'adev' as - * NULL in this case because there is no proper ACPI device. - */ - if (!cfg->parent) - adev = NULL; - else - adev = to_acpi_device(cfg->parent); - - bus_dev = &bridge->bus->dev; - - ACPI_COMPANION_SET(&bridge->dev, adev); - set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); - - return 0; -} - -static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) -{ - struct resource_entry *entry, *tmp; - int status; - - status = acpi_pci_probe_root_resources(ci); - resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { - if (!(entry->res->flags & IORESOURCE_WINDOW)) - resource_list_destroy_entry(entry); - } - return status; -} - -/* - * Lookup the bus range for the domain in MCFG, and set up config space - * mapping. - */ -static struct pci_config_window * -pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) -{ - struct device *dev = &root->device->dev; - struct resource *bus_res = &root->secondary; - u16 seg = root->segment; - const struct pci_ecam_ops *ecam_ops; - struct resource cfgres; - struct acpi_device *adev; - struct pci_config_window *cfg; - int ret; - - ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops); - if (ret) { - dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); - return NULL; - } - - adev = acpi_resource_consumer(&cfgres); - if (adev) - dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, - dev_name(&adev->dev)); - else - dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", - &cfgres); - - cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); - if (IS_ERR(cfg)) { - dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, - PTR_ERR(cfg)); - return NULL; - } - - return cfg; -} - -/* release_info: free resources allocated by init_info */ -static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) -{ - struct acpi_pci_generic_root_info *ri; - - ri = container_of(ci, struct acpi_pci_generic_root_info, common); - pci_ecam_free(ri->cfg); - kfree(ci->ops); - kfree(ri); -} - -/* Interface called from ACPI code to setup PCI host controller */ -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - struct acpi_pci_generic_root_info *ri; - struct pci_bus *bus, *child; - struct acpi_pci_root_ops *root_ops; - struct pci_host_bridge *host; - - ri = kzalloc(sizeof(*ri), GFP_KERNEL); - if (!ri) - return NULL; - - root_ops = kzalloc(sizeof(*root_ops), GFP_KERNEL); - if (!root_ops) { - kfree(ri); - return NULL; - } - - ri->cfg = pci_acpi_setup_ecam_mapping(root); - if (!ri->cfg) { - kfree(ri); - kfree(root_ops); - return NULL; - } - - root_ops->release_info = pci_acpi_generic_release_info; - root_ops->prepare_resources = pci_acpi_root_prepare_resources; - root_ops->pci_ops = (struct pci_ops *)&ri->cfg->ops->pci_ops; - bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); - if (!bus) - return NULL; - - /* If we must preserve the resource configuration, claim now */ - host = pci_find_host_bridge(bus); - if (host->preserve_config) - pci_bus_claim_resources(bus); - - /* - * Assign whatever was left unassigned. If we didn't claim above, - * this will reassign everything. - */ - pci_assign_unassigned_root_bus_resources(bus); - - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - - return bus; -} - -void pcibios_add_bus(struct pci_bus *bus) -{ - acpi_pci_add_bus(bus); -} - -void pcibios_remove_bus(struct pci_bus *bus) -{ - acpi_pci_remove_bus(bus); -} - -#endif diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index a05350a4e49c..d6b2d64b8237 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1517,4 +1518,185 @@ static int __init acpi_pci_init(void) return 0; } + arch_initcall(acpi_pci_init); + +#if defined(CONFIG_ARM64) +/* + * Try to assign the IRQ number when probing a new device + */ +int pcibios_alloc_irq(struct pci_dev *dev) +{ + if (!acpi_disabled) + acpi_pci_irq_enable(dev); + + return 0; +} + +struct acpi_pci_generic_root_info { + struct acpi_pci_root_info common; + struct pci_config_window *cfg; /* config space mapping */ +}; + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + struct pci_config_window *cfg = bus->sysdata; + struct acpi_device *adev = to_acpi_device(cfg->parent); + struct acpi_pci_root *root = acpi_driver_data(adev); + + return root->segment; +} + +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) +{ + struct pci_config_window *cfg; + struct acpi_device *adev; + struct device *bus_dev; + + if (acpi_disabled) + return 0; + + cfg = bridge->bus->sysdata; + + /* + * On Hyper-V there is no corresponding ACPI device for a root bridge, + * therefore ->parent is set as NULL by the driver. And set 'adev' as + * NULL in this case because there is no proper ACPI device. + */ + if (!cfg->parent) + adev = NULL; + else + adev = to_acpi_device(cfg->parent); + + bus_dev = &bridge->bus->dev; + + ACPI_COMPANION_SET(&bridge->dev, adev); + set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); + + return 0; +} + +static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) +{ + struct resource_entry *entry, *tmp; + int status; + + status = acpi_pci_probe_root_resources(ci); + resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { + if (!(entry->res->flags & IORESOURCE_WINDOW)) + resource_list_destroy_entry(entry); + } + return status; +} + +/* + * Lookup the bus range for the domain in MCFG, and set up config space + * mapping. + */ +static struct pci_config_window * +pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) +{ + struct device *dev = &root->device->dev; + struct resource *bus_res = &root->secondary; + u16 seg = root->segment; + const struct pci_ecam_ops *ecam_ops; + struct resource cfgres; + struct acpi_device *adev; + struct pci_config_window *cfg; + int ret; + + ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops); + if (ret) { + dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); + return NULL; + } + + adev = acpi_resource_consumer(&cfgres); + if (adev) + dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, + dev_name(&adev->dev)); + else + dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", + &cfgres); + + cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); + if (IS_ERR(cfg)) { + dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, + PTR_ERR(cfg)); + return NULL; + } + + return cfg; +} + +/* release_info: free resources allocated by init_info */ +static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) +{ + struct acpi_pci_generic_root_info *ri; + + ri = container_of(ci, struct acpi_pci_generic_root_info, common); + pci_ecam_free(ri->cfg); + kfree(ci->ops); + kfree(ri); +} + +/* Interface called from ACPI code to setup PCI host controller */ +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + struct acpi_pci_generic_root_info *ri; + struct pci_bus *bus, *child; + struct acpi_pci_root_ops *root_ops; + struct pci_host_bridge *host; + + ri = kzalloc(sizeof(*ri), GFP_KERNEL); + if (!ri) + return NULL; + + root_ops = kzalloc(sizeof(*root_ops), GFP_KERNEL); + if (!root_ops) { + kfree(ri); + return NULL; + } + + ri->cfg = pci_acpi_setup_ecam_mapping(root); + if (!ri->cfg) { + kfree(ri); + kfree(root_ops); + return NULL; + } + + root_ops->release_info = pci_acpi_generic_release_info; + root_ops->prepare_resources = pci_acpi_root_prepare_resources; + root_ops->pci_ops = (struct pci_ops *)&ri->cfg->ops->pci_ops; + bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); + if (!bus) + return NULL; + + /* If we must preserve the resource configuration, claim now */ + host = pci_find_host_bridge(bus); + if (host->preserve_config) + pci_bus_claim_resources(bus); + + /* + * Assign whatever was left unassigned. If we didn't claim above, + * this will reassign everything. + */ + pci_assign_unassigned_root_bus_resources(bus); + + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + + return bus; +} + +void pcibios_add_bus(struct pci_bus *bus) +{ + acpi_pci_add_bus(bus); +} + +void pcibios_remove_bus(struct pci_bus *bus) +{ + acpi_pci_remove_bus(bus); +} + +#endif From patchwork Thu Aug 3 17:59:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130804 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1341765vqx; Thu, 3 Aug 2023 11:51:25 -0700 (PDT) X-Google-Smtp-Source: APBJJlHXLMVp0r+FZwvSnaJ/RdVBHQ8LvZL0Evj+6WmiFz24Ltgm8Nb43dcgc11XmRBHQB5K9/Rg X-Received: by 2002:a05:6a00:2316:b0:687:535f:6712 with SMTP id h22-20020a056a00231600b00687535f6712mr10416464pfh.14.1691088685022; Thu, 03 Aug 2023 11:51:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691088685; cv=none; d=google.com; s=arc-20160816; b=hpK7wyYWnCEegpw2utKcX1PMp/TpAE0cRcA2wSHKilFA9FIsycTHgSvjR/AJHK8V+f wkp8RQTCdAes/sRIZbctw7i2o4nzcSGqLr3J3MVIfwonMU4/amohv1OjgknLGizVsR9M WlYCif3WxXK/Wm4pSL2nZ35mhLq4SQa1Kj8w5KzCdls8HTl65yOt9xpHoiIYtvTxga1U TevJBXaxXBSjm1WlYaK1ZFjheR9tStY7BtUl/gxjV10pymXiJt1dQ2t38hJ/8AZooekk HTHjCfi9mrV8KK3rNE8i7jk7EFcTIKTYVXr/q13khVh1EsbIXWVz/txDyX0h8dR0V4kx QPnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7mbYpJBEy7QtZn0rLm+Z46rszMOgig5KvbO250k7OII=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=ryDeuYneHm9j2l8oSTHp83uwzbOVML+np8pQ2P+eRlFgezrPb7/Com4mfgxd4iSzIH Tm00MwGyfBzqY77H0jnfmOepRZa8afATFxU4w8OSOEnJHFMES51lazCmp4YPu9q0zDTU i12FvNlO1n4QakfmClbBSyxa05My+ScB+rwjNQW3xh/SS9mh1sqQodDYHTpwHVcGvZ0m +xP9kykjfdnge8A41jPvQKASBwe+YNJdfFJ63VngtNTq5BvOI0tzgF2diVhBpRri3XRI RH++Oyc4noJsf7+v+5MRqkUe5M9PgOlZ3xpH5xhDBCwtWOwldHwIXUFMEXS8Fkz1B3/t 7VIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=YfGQrWrq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 06/21] RISC-V: ACPI: Implement PCI related functionality Date: Thu, 3 Aug 2023 23:29:01 +0530 Message-Id: <20230803175916.3174453-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773235008620211222 X-GMAIL-MSGID: 1773235008620211222 Replace the dummy implementation for PCI related functions with actual implementation. Signed-off-by: Sunil V L --- arch/riscv/kernel/acpi.c | 32 +++++++++++++++----------------- drivers/pci/pci-acpi.c | 2 +- 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index aa4433bca6d9..01022c5802ec 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -307,29 +307,27 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) #ifdef CONFIG_PCI /* - * These interfaces are defined just to enable building ACPI core. - * TODO: Update it with actual implementation when external interrupt - * controller support is added in RISC-V ACPI. + * raw_pci_read/write - Platform-specific PCI config space access. */ -int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, - int reg, int len, u32 *val) +int raw_pci_read(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *val) { - return PCIBIOS_DEVICE_NOT_FOUND; -} + struct pci_bus *b = pci_find_bus(domain, bus); -int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, - int reg, int len, u32 val) -{ - return PCIBIOS_DEVICE_NOT_FOUND; -} + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) -{ - return -1; + return b->ops->read(b, devfn, reg, len, val); } -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +int raw_pci_write(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 val) { - return NULL; + struct pci_bus *b = pci_find_bus(domain, bus); + + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + + return b->ops->write(b, devfn, reg, len, val); } #endif /* CONFIG_PCI */ diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index d6b2d64b8237..5af6188cdbe0 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1521,7 +1521,7 @@ static int __init acpi_pci_init(void) arch_initcall(acpi_pci_init); -#if defined(CONFIG_ARM64) +#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV) /* * Try to assign the IRQ number when probing a new device */ From patchwork Thu Aug 3 17:59:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130782 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1329496vqx; Thu, 3 Aug 2023 11:24:56 -0700 (PDT) X-Google-Smtp-Source: APBJJlEAQJR3SjO3l9bDjJs4ms7bK1ToZr1ypUB3PIneQr5RqZyfNhbtCPOtas9KuwNn3V6vzysa X-Received: by 2002:a19:6908:0:b0:4f8:4512:c846 with SMTP id e8-20020a196908000000b004f84512c846mr6834090lfc.49.1691087095856; Thu, 03 Aug 2023 11:24:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691087095; cv=none; d=google.com; s=arc-20160816; b=kjWNIky3ORDPcqyzdXbQFQ2BVippGXqQmSnls5OdMMQFFco6WC6G333MWJIS2QXEib OQBgiZvvW+vYjC3e8k7aPUhAHIET5bv9INpSmqFDOczyi/6C4lUo6c7yr5nYSKKeDXi/ OpJOEDgTD7uCvyvpxRnYEzCgiQcJnSUP+e8K64fQ71NbxS2ikGwRAPQAH83Bj5hcJ9CM jzfR9aNpNp6uH3zkALZuz94f7ocEXyLdYHKR7+hj7TQRzmfosSwsPnRC1pP4KzArkyVI o92QMnb+9V+dK0g91m/B86Ng2TahzwIXgUDAuHQucmNyv+fRyx7Dd2WO/NpuqM3EQ/Bs UMkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jB8h6dbqqCupn7mkThrMa44SDq8B8ddxZkj2FYKCJmg=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=PYq/tgnrmULc5d9WUeZtfb2fpwcMIgAIB9EybuUiKH+L5XTJd4AHf/XR9dK4eLTTij M90OMkgEGRi6vKGiFbKKgv4E6h/RW2fu9QyyRPwPcCTgVElBQgK7Xrz0lWBGgpMYTtEY /xW+E6LPm0S4yG/2HbOv6uoK4YxIquH7P7UiY4oIAadMZPtmvMdPHjPhSw9Gi1ndy5jA K7RARj733hvNONiAy8fwN2vLAZnmPRhb6X5FSbea9XWrZEJfec4akN/xBzgO67w87zP0 dK+0KcSeifb7aNmMdFP8MUbIbb6Ddq9LxgiTq2mdLpIz2+4dAti2XjCCSYRiySrmuvMQ EtJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=fgyTbFbS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 07/21] RISC-V: Kconfig: Select ECAM and MCFG Date: Thu, 3 Aug 2023 23:29:02 +0530 Message-Id: <20230803175916.3174453-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773233342775167687 X-GMAIL-MSGID: 1773233342775167687 Enable ECAM and MCFG to support PCIe on ACPI based platforms. Signed-off-by: Sunil V L --- arch/riscv/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index e19f32c12a68..79dc35e89d5f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -13,6 +13,7 @@ config 32BIT config RISCV def_bool y select ACPI_GENERIC_GSI if ACPI + select ACPI_MCFG if (ACPI && PCI) select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_DMA_DEFAULT_COHERENT select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION @@ -147,6 +148,7 @@ config RISCV select OF_EARLY_FLATTREE select OF_IRQ select PCI_DOMAINS_GENERIC if PCI + select PCI_ECAM if (ACPI && PCI) select PCI_MSI if PCI select RISCV_ALTERNATIVE if !XIP_KERNEL select RISCV_APLIC From patchwork Thu Aug 3 17:59:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130783 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1329570vqx; Thu, 3 Aug 2023 11:25:06 -0700 (PDT) X-Google-Smtp-Source: APBJJlH00cp3FKHHgq/9hoU06NTnt8KH32/elOKaiPV79gFvTOTS+mUZR5+QZpAy1EJ3w+v+larX X-Received: by 2002:a17:907:778e:b0:99b:f859:95e9 with SMTP id ky14-20020a170907778e00b0099bf85995e9mr7474854ejc.14.1691087106499; Thu, 03 Aug 2023 11:25:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691087106; cv=none; d=google.com; s=arc-20160816; b=vzsDqW26vK4BTN3j5Eel0PU8X/lqcoOnFIhIGCKN2uz8MdxNfTx0qcLTAHjebQVJuc AIgz90QOVfLrjt+450qvL2OBqyLW4GQvEnudskyKI6vN1HIbKQLuEUwr02Rizh1wkL/x pHxA7+LbBZ9eq0xCHbZ6lic7leASJ7JLHDSm25dhaB+au0pkkpJ5a4lsG1BxBo6UsQ2E 2hFT0Cqdc8ONZR4cNGkL+lkLU5Me931DAisMmeAxjP6X2x8TlJabwRfDWbFKlEeg/C7x caLIFAWst9RvOYyi1YJwZWM99Dy2Wuh+GfkudCq5FrxA37MqAhtNDfbn6zuAUPLohjE2 RfMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vQhuhHdTYaoWEXKHMdQb/AIiT1M0AyktuFOnKoEYTGc=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=k2ta5Ukg9o2Yl1jMXWyKMoutoCqGD9nZFWo+2wBsazDvleOqEXXaK9qopriVOxadxd wmyV5sXBguPvi7E7jMtKovOwIyWOC1IQIGzmc0q7y/OMbjPivKWmPfkiUkjx68QO8J1x BIjZKXow6k0Laj5L4t8PFdlOnOTltga1xBDH8wbKmDGczqB0wtHVfnbDsuO1SjsFM/FX oaPaV4Q/pK93L5MnV6495l5IDg8E15JDwsjPIxrFb9ehq0uA4S7VXDdaJiiuTByDzW2R 2qKguxYmFXPlV9HE2f4femz4Xr5Q+mj3eNUTmMybQ+nwGiM5mpWI1EMIbgjtijPs0DVL tTRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=InAgb86b; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 08/21] RISC-V: ACPI: RHCT: Add function to get CBO block sizes Date: Thu, 3 Aug 2023 23:29:03 +0530 Message-Id: <20230803175916.3174453-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773233353821581768 X-GMAIL-MSGID: 1773233353821581768 CBO related block size in ACPI is provided by RHCT. Add support to read the CMO node in RHCT to get this information. Signed-off-by: Sunil V L --- arch/riscv/include/asm/acpi.h | 9 ++++++ drivers/acpi/riscv/rhct.c | 61 +++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index d5604d2073bc..0c4e8b35103e 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -66,6 +66,8 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa); static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; } +int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, u32 *cbom_size, + u32 *cboz_size, u32 *cbop_size); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -79,6 +81,13 @@ static inline int acpi_get_riscv_isa(struct acpi_table_header *table, return -EINVAL; } +static inline int acpi_get_cbo_block_size(struct acpi_table_header *table, + unsigned int cpu, u32 *cbom_size, + u32 *cboz_size, u32 *cbop_size) +{ + return -EINVAL; +} + #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c index b280b3e9c7d9..07309525f277 100644 --- a/drivers/acpi/riscv/rhct.c +++ b/drivers/acpi/riscv/rhct.c @@ -81,3 +81,64 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const return -1; } + +/* + * During early boot, the caller should call acpi_get_table() and pass its pointer to + * these functions(and free up later). At run time, since this table can be used + * multiple times, pass NULL so that the table remains in memory + */ +int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, + u32 *cbom_size, u32 *cboz_size, u32 *cbop_size) +{ + struct acpi_rhct_node_header *node, *ref_node, *end; + u32 size_hdr = sizeof(struct acpi_rhct_node_header); + u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info); + struct acpi_rhct_hart_info *hart_info; + struct acpi_rhct_cmo_node *cmo_node; + struct acpi_table_rhct *rhct; + u32 *hart_info_node_offset; + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + + BUG_ON(acpi_disabled); + + if (!table) { + rhct = (struct acpi_table_rhct *)acpi_get_rhct(); + if (!rhct) + return -ENOENT; + } else { + rhct = (struct acpi_table_rhct *)table; + } + + end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length); + + for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset); + node < end; + node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) { + if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) { + hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr); + hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo); + if (acpi_cpu_id != hart_info->uid) + continue; + + for (int i = 0; i < hart_info->num_offsets; i++) { + ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header, + rhct, hart_info_node_offset[i]); + if (ref_node->type == ACPI_RHCT_NODE_TYPE_CMO) { + cmo_node = ACPI_ADD_PTR(struct acpi_rhct_cmo_node, + ref_node, size_hdr); + if (cbom_size) + *cbom_size = 1 << cmo_node->cbom_size; + + if (cboz_size) + *cboz_size = 1 << cmo_node->cboz_size; + + if (cbop_size) + *cbop_size = 1 << cmo_node->cbop_size; + return 0; + } + } + } + } + + return -ENOENT; +} From patchwork Thu Aug 3 17:59:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130817 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1359243vqx; Thu, 3 Aug 2023 12:24:01 -0700 (PDT) X-Google-Smtp-Source: APBJJlHLbwB8b5svEL5Lr81KkoX+n3wDn/zWqIDo9aMNJIgCAtHSVbUwSBGSVMyPTGyu/wXhjvK6 X-Received: by 2002:a17:902:c94e:b0:1bb:32de:95c5 with SMTP id i14-20020a170902c94e00b001bb32de95c5mr18862488pla.65.1691090640953; Thu, 03 Aug 2023 12:24:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691090640; cv=none; d=google.com; s=arc-20160816; b=vFdLdL2jp7c/j85jFPFotyQYENyVbXfGmlBT3gPl4ZI0YgzCACUXJeOWXdJqEnlM7L /tJNgtxdAFfY65xTxDzp9ggwXcW+oDN+0YXthBMXRwoxDypStCMRWe4o5O2Q1c7N/1A9 6ULrAArHrnkxNa4fHTmmjP/DV67FTLg7GiDN2RSVNFxmqKKPYSeotO6If6KErkjPJz55 Hhh7bd6gkxzKfmCuNvO95kGoUIS2x79uFlhkdx3DHkHhXrwcXEIF1nzcK+qbZ3tID64j K4siXXQ8Qkw4coFDlC440RsqMV3p7X+aKNQFnd/oykjQyIy8tLi+Q/rSGEbnCgB0D0l3 WWig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dVaxSLrcyWrDv537p1b6trWUWlm89roci1AhpEn7YYs=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=pRDFxp+13Sv7D8wzhoHgRagKm5To74ledVCJra8jo9Pw1AxOefejOsK8iaOI9Sy3aT B3sW9amuFGYHaRS6chUfWBCHDY3UU2tS/TU3HVqPJErSPT3ef7R3eyibCUYPWrd6zwgi BhMbi8mIPt2pXxQTg6jPyqUW97iLOFCYrimHj9u89NvoImO9ODxhocXRLuO3t3FWFnni V7vmWRcaoRzjHznRKfPVVkNPboR60F+55UoliQ0djHcBg6yysjYvdwuk4wAYLicxj17A ykbUXL1dePf6wSONaQoNEJ5aL5vaIwPzTdIDp+1HQuVjirvqTs1cYJA0WpY9bvphClHx UlmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="fYo/3hat"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 09/21] RISC-V: cacheflush: Initialize CBO variables on ACPI systems Date: Thu, 3 Aug 2023 23:29:04 +0530 Message-Id: <20230803175916.3174453-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773237060255263134 X-GMAIL-MSGID: 1773237060255263134 Using new interface to get the CBO block size information in RHCT, initialize the variables on ACPI platforms. Signed-off-by: Sunil V L --- arch/riscv/mm/cacheflush.c | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index fbc59b3f69f2..63bb56819b37 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #ifdef CONFIG_SMP @@ -131,15 +133,38 @@ void __init riscv_init_cbo_blocksizes(void) unsigned long cbom_hartid, cboz_hartid; u32 cbom_block_size = 0, cboz_block_size = 0; struct device_node *node; + struct acpi_table_header *rhct; + acpi_status status; + unsigned int cpu; + + if (!acpi_disabled) { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) + return; + } - for_each_of_cpu_node(node) { - /* set block-size for cbom and/or cboz extension if available */ - cbo_get_block_size(node, "riscv,cbom-block-size", - &cbom_block_size, &cbom_hartid); - cbo_get_block_size(node, "riscv,cboz-block-size", - &cboz_block_size, &cboz_hartid); + for_each_possible_cpu(cpu) { + if (acpi_disabled) { + node = of_cpu_device_node_get(cpu); + if (!node) { + pr_warn("Unable to find cpu node\n"); + continue; + } + + /* set block-size for cbom and/or cboz extension if available */ + cbo_get_block_size(node, "riscv,cbom-block-size", + &cbom_block_size, &cbom_hartid); + cbo_get_block_size(node, "riscv,cboz-block-size", + &cboz_block_size, &cboz_hartid); + } else { + acpi_get_cbo_block_size(rhct, cpu, &cbom_block_size, + &cboz_block_size, NULL); + } } + if (!acpi_disabled && rhct) + acpi_put_table((struct acpi_table_header *)rhct); + if (cbom_block_size) riscv_cbom_block_size = cbom_block_size; From patchwork Thu Aug 3 17:59:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130845 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1393987vqx; Thu, 3 Aug 2023 13:40:31 -0700 (PDT) X-Google-Smtp-Source: APBJJlFHCo+cSPdUXojs6TDhQuKtvXFEyH7rH08859dfPPKFbrQUVs7U4AWWwSvm5Zln/QwIusc4 X-Received: by 2002:a17:907:7893:b0:989:450:e585 with SMTP id ku19-20020a170907789300b009890450e585mr7714370ejc.45.1691095230959; Thu, 03 Aug 2023 13:40:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691095230; cv=none; d=google.com; s=arc-20160816; b=eskpxjAA4hqchlaXtf/uwgZyK424T+T1QNla3FQk6JX/4D4vfPuudrBqETUHg2vxm3 CzMCNfNrW/zA055zh3CejP66PAYlGySWM10VHdzyangDaqI6K4js7xYmOqo24DxZCuUx aeeHDoPh+GNV0s/Tt508ZuTo29xnt3kS+zMC/8cmOATvZaDFDTIJluiDe6gy97MSrm7b rh2q6V/gvWe+Lb/eExBi7iWKRJOpBMu/IDND2d50nDCjb1MbEEXdXB3kgz+T/Z5/5eWq RsqhdUvZ+PQJXsfPBjsZW4F3MFJ4RuEBz/SgBu7nu7TshMVUPsq2QLpgLX94Ecw2UxqN 1g8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LwCzqc1PMCRcx2h1vYzs9FDmhl8QjorV5J8xX30vpfA=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=zNVu3uhj2l84Ktfe5YCS+LUDKQRAyT9h/2f2vzfIRTCBKCKUZhvtHH9/PP8oP9rT5Q 5IsDu5VCIGhhltxY1qpOxD27erHFLG2FfC2m6v3M1iTuExG9H4/q8BfnEjJCoDAXfD59 k+AULmWcV7BNX+H6CWndfvYfIe53/qjaWQj6w3uKzVRnBIOftcrAZ7gITeFykRZY5AjB JQhDJfMpa/3wkspAnrAU7FHWbZ5KFvKYeVoWNAqVr3w6NBFV7BFccPa2UrRin/SWWQLO r+R3/t8IU3EKCHHOv7RGFPHYdm8SeMwcxqLVXndgWo8ZS3PfYxqLT3f0aPuDANvsYU29 EKkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=lGptm+1F; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 10/21] clocksource/timer-riscv: ACPI: Add timer_cannot_wakeup_cpu Date: Thu, 3 Aug 2023 23:29:05 +0530 Message-Id: <20230803175916.3174453-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773241872801213969 X-GMAIL-MSGID: 1773241872801213969 The timer capability to wakeup the cpu irrespective of its idle state is provided by the flag in RHCT. Update the timer code to set this flag. Signed-off-by: Sunil V L --- drivers/clocksource/timer-riscv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index da3071b387eb..50198657230e 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -212,6 +212,10 @@ TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); #ifdef CONFIG_ACPI static int __init riscv_timer_acpi_init(struct acpi_table_header *table) { + struct acpi_table_rhct *rhct = (struct acpi_table_rhct *)table; + + riscv_timer_cannot_wake_cpu = rhct->flags & ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU; + return riscv_timer_init_common(); } From patchwork Thu Aug 3 17:59:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130859 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1401928vqx; Thu, 3 Aug 2023 13:59:53 -0700 (PDT) X-Google-Smtp-Source: APBJJlFQfAi7bt8YMO+lEIf8qWsxtddI/peymKpISxq/r1ZIAXPRtzTY8VoOdOpXLqREKhlMNyM+ X-Received: by 2002:a05:6a20:3d03:b0:13f:3d25:d83 with SMTP id y3-20020a056a203d0300b0013f3d250d83mr5137468pzi.19.1691096393452; Thu, 03 Aug 2023 13:59:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691096393; cv=none; d=google.com; s=arc-20160816; b=YLrIVK+AFrp59qutpMOCezXrXWEuHaWnNz71wBIXzVO4uaNNG2LjXB/12h6KSldOs4 xS8DmQoogwrOeejgbTsoJOQSKgaaxGmDqWq3Vm/WuYFXBEtM0S5ygDbW9HvrRqV55ilh 3YT32jRiyZIv8cYB1Kz7ZZOTgrKMR8sz3cwspoBAEcdsFdujPll/FqAU1/K+YExQ+g9g cQJUSMIzcLupgUfBWnfDLqVoUSdoJQRIM1OVs8U0A06v9UrljH5czCX9CTkANjxNmdcp 4LBv8QszR/U9eHf8JDQc0lUcR62m8jGOyIXjQSwvz8v7KW7ephLyBLVpaCBCYQCbX6f/ qOOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DyY105ZWYDcmAte3LXmkGWmEUp/pfY0rBCzPBKLc5no=; fh=ILryJ7PnbPvE2SU7M6p+Egr9seyd+/ZOS1JnvbNkjks=; b=X8hUvN0rBesgh7rF7MoGWZx1UT1M/NYpPODcCDWJJidw3drQP2AZXopU0q8bDQYBaI 02Kd5bIj2+fL8cwluSHi8mnt3nE50u4RrHtLn5VMGjjNtBXYrnBwuVhCz64MEjN1w4nH d3v4dAKQanZgERY99EYmhgJSu3Y9tT1NnYrfLj7OVQUFbS9IdtqKQfXTDI4kBB/lVHmY kGWXr3dXiVh2Oin4m9LVzVi6HoA0y4YW5HzqylhUrxYyZNxS0Gd55uIgI6p1YjGG0Sw5 NodPv6ZLwVY5gRZZ+NFbfIWS3w424MHhD3umH1vbDxA0L/e7nPWVsCMPJaAO8s/h96P0 2CUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=F2No1P8d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Anup Patel , Sunil V L Subject: [RFC PATCH v1 11/21] swnode: Add support to create early during boot Date: Thu, 3 Aug 2023 23:29:06 +0530 Message-Id: <20230803175916.3174453-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773243091884976133 X-GMAIL-MSGID: 1773243091884976133 From: Anup Patel swnode framework can be used to create fwnode for interrupt controllers. This helps in keeping the drivers same for both DT and ACPI. To enable this, enhance the swnode framework so that it can be created early during boot without dependency on sysfs. Signed-off-by: Anup Patel Co-developed-by: Sunil V L Signed-off-by: Sunil V L --- drivers/base/swnode.c | 117 +++++++++++++++++++++++++++++++++------ include/linux/property.h | 3 + 2 files changed, 103 insertions(+), 17 deletions(-) diff --git a/drivers/base/swnode.c b/drivers/base/swnode.c index 1886995a0b3a..43f191a38980 100644 --- a/drivers/base/swnode.c +++ b/drivers/base/swnode.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "base.h" @@ -21,6 +22,7 @@ struct swnode { /* hierarchy */ struct ida child_ids; + struct list_head early; struct list_head entry; struct list_head children; struct swnode *parent; @@ -32,6 +34,9 @@ struct swnode { static DEFINE_IDA(swnode_root_ids); static struct kset *swnode_kset; +static DEFINE_SPINLOCK(swnode_early_lock); +static LIST_HEAD(swnode_early_list); + #define kobj_to_swnode(_kobj_) container_of(_kobj_, struct swnode, kobj) static const struct fwnode_operations software_node_ops; @@ -73,6 +78,17 @@ software_node_to_swnode(const struct software_node *node) if (!node) return NULL; + spin_lock(&swnode_early_lock); + + list_for_each_entry(swnode, &swnode_early_list, early) { + if (swnode->node == node) { + spin_unlock(&swnode_early_lock); + return swnode; + } + } + + spin_unlock(&swnode_early_lock); + spin_lock(&swnode_kset->list_lock); list_for_each_entry(k, &swnode_kset->list, entry) { @@ -698,6 +714,19 @@ software_node_find_by_name(const struct software_node *parent, const char *name) if (!name) return NULL; + spin_lock(&swnode_early_lock); + + list_for_each_entry(swnode, &swnode_early_list, early) { + if (parent == swnode->node->parent && swnode->node->name && + !strcmp(name, swnode->node->name)) { + kobject_get(&swnode->kobj); + spin_unlock(&swnode_early_lock); + return swnode->node; + } + } + + spin_unlock(&swnode_early_lock); + spin_lock(&swnode_kset->list_lock); list_for_each_entry(k, &swnode_kset->list, entry) { @@ -742,10 +771,16 @@ static void software_node_free(const struct software_node *node) kfree(node); } -static void software_node_release(struct kobject *kobj) +static void software_node_release_common(struct kobject *kobj, bool early) { struct swnode *swnode = kobj_to_swnode(kobj); + if (early) { + spin_lock(&swnode_early_lock); + list_del(&swnode->early); + spin_unlock(&swnode_early_lock); + } + if (swnode->parent) { ida_simple_remove(&swnode->parent->child_ids, swnode->id); list_del(&swnode->entry); @@ -760,6 +795,20 @@ static void software_node_release(struct kobject *kobj) kfree(swnode); } +static void software_node_release(struct kobject *kobj) +{ + software_node_release_common(kobj, false); +} + +static void software_node_release_early(struct kobject *kobj) +{ + software_node_release_common(kobj, true); +} + +static const struct kobj_type software_node_type_early = { + .release = software_node_release_early +}; + static const struct kobj_type software_node_type = { .release = software_node_release, .sysfs_ops = &kobj_sysfs_ops, @@ -767,7 +816,7 @@ static const struct kobj_type software_node_type = { static struct fwnode_handle * swnode_register(const struct software_node *node, struct swnode *parent, - unsigned int allocated) + unsigned int allocated, unsigned int early) { struct swnode *swnode; int ret; @@ -786,21 +835,39 @@ swnode_register(const struct software_node *node, struct swnode *parent, swnode->id = ret; swnode->node = node; swnode->parent = parent; - swnode->kobj.kset = swnode_kset; + swnode->kobj.kset = (!early) ? swnode_kset : NULL; fwnode_init(&swnode->fwnode, &software_node_ops); ida_init(&swnode->child_ids); + INIT_LIST_HEAD(&swnode->early); INIT_LIST_HEAD(&swnode->entry); INIT_LIST_HEAD(&swnode->children); - if (node->name) - ret = kobject_init_and_add(&swnode->kobj, &software_node_type, - parent ? &parent->kobj : NULL, - "%s", node->name); - else - ret = kobject_init_and_add(&swnode->kobj, &software_node_type, - parent ? &parent->kobj : NULL, - "node%d", swnode->id); + if (early) { + ret = 0; + kobject_init(&swnode->kobj, &software_node_type_early); + swnode->kobj.parent = parent ? &parent->kobj : NULL; + if (node->name) + ret = kobject_set_name(&swnode->kobj, + "%s", node->name); + else + ret = kobject_set_name(&swnode->kobj, + "node%d", swnode->id); + if (!ret) { + spin_lock(&swnode_early_lock); + list_add_tail(&swnode->early, &swnode_early_list); + spin_unlock(&swnode_early_lock); + } + } else { + if (node->name) + ret = kobject_init_and_add(&swnode->kobj, &software_node_type, + parent ? &parent->kobj : NULL, + "%s", node->name); + else + ret = kobject_init_and_add(&swnode->kobj, &software_node_type, + parent ? &parent->kobj : NULL, + "node%d", swnode->id); + } if (ret) { kobject_put(&swnode->kobj); return ERR_PTR(ret); @@ -815,7 +882,8 @@ swnode_register(const struct software_node *node, struct swnode *parent, if (parent) list_add_tail(&swnode->entry, &parent->children); - kobject_uevent(&swnode->kobj, KOBJ_ADD); + if (!early) + kobject_uevent(&swnode->kobj, KOBJ_ADD); return &swnode->fwnode; } @@ -892,7 +960,7 @@ int software_node_register(const struct software_node *node) if (node->parent && !parent) return -EINVAL; - return PTR_ERR_OR_ZERO(swnode_register(node, parent, 0)); + return PTR_ERR_OR_ZERO(swnode_register(node, parent, 0, 0)); } EXPORT_SYMBOL_GPL(software_node_register); @@ -910,9 +978,10 @@ void software_node_unregister(const struct software_node *node) } EXPORT_SYMBOL_GPL(software_node_unregister); -struct fwnode_handle * -fwnode_create_software_node(const struct property_entry *properties, - const struct fwnode_handle *parent) +static struct fwnode_handle * +fwnode_create_software_node_common(const struct property_entry *properties, + const struct fwnode_handle *parent, + bool early) { struct fwnode_handle *fwnode; struct software_node *node; @@ -931,12 +1000,26 @@ fwnode_create_software_node(const struct property_entry *properties, node->parent = p ? p->node : NULL; - fwnode = swnode_register(node, p, 1); + fwnode = swnode_register(node, p, 1, early); if (IS_ERR(fwnode)) software_node_free(node); return fwnode; } + +struct fwnode_handle * +fwnode_create_software_node_early(const struct property_entry *properties, + const struct fwnode_handle *parent) +{ + return fwnode_create_software_node_common(properties, parent, true); +} + +struct fwnode_handle * +fwnode_create_software_node(const struct property_entry *properties, + const struct fwnode_handle *parent) +{ + return fwnode_create_software_node_common(properties, parent, false); +} EXPORT_SYMBOL_GPL(fwnode_create_software_node); void fwnode_remove_software_node(struct fwnode_handle *fwnode) diff --git a/include/linux/property.h b/include/linux/property.h index 8c3c6685a2ae..7137338bfabb 100644 --- a/include/linux/property.h +++ b/include/linux/property.h @@ -503,6 +503,9 @@ void software_node_unregister_node_group(const struct software_node **node_group int software_node_register(const struct software_node *node); void software_node_unregister(const struct software_node *node); +struct fwnode_handle * +fwnode_create_software_node_early(const struct property_entry *properties, + const struct fwnode_handle *parent); struct fwnode_handle * fwnode_create_software_node(const struct property_entry *properties, const struct fwnode_handle *parent); From patchwork Thu Aug 3 17:59:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130795 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1338346vqx; Thu, 3 Aug 2023 11:44:00 -0700 (PDT) X-Google-Smtp-Source: APBJJlGBRY4hUvcnQ20EMc50bqMUAjKq9+8Ji/O6eofDNGQU5/ttpyPHr+G0n+ip0vR13td3Y4pF X-Received: by 2002:adf:e889:0:b0:317:660f:6f5e with SMTP id d9-20020adfe889000000b00317660f6f5emr7027475wrm.42.1691088240525; Thu, 03 Aug 2023 11:44:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691088240; cv=none; d=google.com; s=arc-20160816; b=wuUYHEa4GPxZfUJwHsYHjiIyL4rf+3ZV3KP8mqhdzs8pgSFrpNrosrqvvyUX1/AOkl vxFv+jNChJo7ChxpNkYu2V17Tuu4pxol0Ez9isWZgeSVMHc8kJjo9KOz6zd08Uru9pwE Kc+zTR2JATi5yutHemtK3owfBVnSZSP8VQSHPAdMiMYjIQWClqa2dTQIfmWU+dYzVjRs ErWoTEJ+aOOQcQPpJG84LR3hjS96dERKKUEu+0VAW38Lef0vkGLhy4F7qx23TAYHlSqt nNvUm12c5/3/AmaLA/W56PJTRoIDGexNOp5p5TgJ4cabHYpxAY9dlDsCNhnat58zgsKx PDWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Vqi3iZnSO0pCz4r86HvzjXAIoq/LUkNm+cOCoheLdcU=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=xwmWTufJnBJviwTPY22C0RFYTEhrMdvGvzvG8Jbmx8aevV8jbXBJjLdCBRQaeMJfdj UMoLIq8rauF6XnWFIRP4IBLu5h+YPZKnUACxj/tPidPiSnsHg1NKUA8Rvd9XbDkfsL1B iTdXAhunBmz9pWVElRSI5YH7wjwmjcALRUCkZk4/ZqVW67RIGahDAPnnQ58xF2fVKajx p6n+bkd7EqKWkInoMrhfSodfGbPy7kI4bud9lDtbsZdTJdgvg44oXD2DqogcocnpamCE DZHQ8NfFZ4obwGj95wR6+zXAezXCeTIUNFOdqGYb1AqDD9tjIbNPWWqwv+CStuFi7u1h qX9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=RGBk6rx5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 12/21] irqchip/riscv-intc: Use swnode framework to create fwnode Date: Thu, 3 Aug 2023 23:29:07 +0530 Message-Id: <20230803175916.3174453-13-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773234542974460685 X-GMAIL-MSGID: 1773234542974460685 By using swnode framework, all data from ACPI tables can be populated as properties of the swnode. This simplifies the driver code and removes the need for ACPI vs DT checks. Use this framework for RISC-V INTC driver. Signed-off-by: Sunil V L --- Documentation/riscv/acpi.rst | 21 +++++++++++++++ arch/riscv/include/asm/acpi.h | 1 + drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/irqchip.c | 46 ++++++++++++++++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 12 ++++----- 5 files changed, 75 insertions(+), 7 deletions(-) create mode 100644 drivers/acpi/riscv/irqchip.c diff --git a/Documentation/riscv/acpi.rst b/Documentation/riscv/acpi.rst index 9870a282815b..e2406546bc16 100644 --- a/Documentation/riscv/acpi.rst +++ b/Documentation/riscv/acpi.rst @@ -8,3 +8,24 @@ The ISA string parsing rules for ACPI are defined by `Version ASCIIDOC Conversion, 12/2022 of the RISC-V specifications, as defined by tag "riscv-isa-release-1239329-2023-05-23" (commit 1239329 ) `_ + +Interrupt Controller Drivers +======= + +ACPI drivers for RISC-V interrupt controllers use software node framework to +create the fwnode for the interrupt controllers. Below properties are +additionally required for some firmware nodes apart from the properties +defined by the device tree bindings for these interrupt controllers. The +properties are created using the data in MADT table. + +1) RISC-V Interrupt Controller (INTC) +----------- +``hartid`` - Hart ID of the hart this interrupt controller belongs to. + +``riscv,imsic-addr`` - Physical base address of the Incoming MSI Controller +(IMSIC) MMIO region of this hart. + +``riscv,imsic-size`` - Size in bytes of the IMSIC MMIO region of this hart. + +``riscv,ext-intc-id`` - The unique ID of the external interrupts connected +to this hart. diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 0c4e8b35103e..0ac2df2dd194 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -68,6 +68,7 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; } int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, u32 *cbom_size, u32 *cboz_size, u32 *cbop_size); +struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 8b3b126e0b94..8b664190d172 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += rhct.o +obj-y += rhct.o irqchip.o diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c new file mode 100644 index 000000000000..36f066a2cad5 --- /dev/null +++ b/drivers/acpi/riscv/irqchip.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include +#include +#include +#include +#include + +struct riscv_irqchip_list { + struct fwnode_handle *fwnode; + struct list_head list; +}; + +LIST_HEAD(rintc_list); + +struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc) +{ + struct property_entry props[6] = {}; + struct fwnode_handle *fwnode; + struct riscv_irqchip_list *rintc_element; + + props[0] = PROPERTY_ENTRY_U64("hartid", rintc->hart_id); + props[1] = PROPERTY_ENTRY_U32("riscv,ext-intc-id", rintc->ext_intc_id); + props[2] = PROPERTY_ENTRY_U64("riscv,imsic-addr", rintc->imsic_addr); + props[3] = PROPERTY_ENTRY_U32("riscv,imsic-size", rintc->imsic_size); + props[4] = PROPERTY_ENTRY_U32("#interrupt-cells", 1); + + fwnode = fwnode_create_software_node_early(props, NULL); + if (fwnode) { + rintc_element = kzalloc(sizeof(*rintc_element), GFP_KERNEL); + if (!rintc_element) { + fwnode_remove_software_node(fwnode); + return NULL; + } + + rintc_element->fwnode = fwnode; + list_add_tail(&rintc_element->list, &rintc_list); + } + + return fwnode; +} diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 1a0fc87152c5..1ef9cada1ed3 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -203,6 +203,12 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, rintc = (struct acpi_madt_rintc *)header; + fn = acpi_rintc_create_irqchip_fwnode(rintc); + if (!fn) { + pr_err("unable to create INTC FW node\n"); + return -ENOMEM; + } + /* * The ACPI MADT will have one INTC for each CPU (or HART) * so riscv_intc_acpi_init() function will be called once @@ -212,12 +218,6 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id()) return 0; - fn = irq_domain_alloc_named_fwnode("RISCV-INTC"); - if (!fn) { - pr_err("unable to allocate INTC FW node\n"); - return -ENOMEM; - } - return riscv_intc_init_common(fn); } From patchwork Thu Aug 3 17:59:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130798 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1338884vqx; Thu, 3 Aug 2023 11:45:08 -0700 (PDT) X-Google-Smtp-Source: APBJJlFWy0mV9xoBBV8blTkOFGcLORCxJfGZ8pnEE7lmDE0doS+4dEeEOLS+FMQ0VUlT1M15DMfE X-Received: by 2002:a19:7419:0:b0:4fd:cab4:7d13 with SMTP id v25-20020a197419000000b004fdcab47d13mr9363285lfe.0.1691088308182; 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 13/21] irqchip/riscv-imsic-early: Add ACPI support Date: Thu, 3 Aug 2023 23:29:08 +0530 Message-Id: <20230803175916.3174453-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773234613664381231 X-GMAIL-MSGID: 1773234613664381231 Add support to probe the IMSIC early driver on ACPI based RISC-V platforms. Signed-off-by: Sunil V L --- arch/riscv/include/asm/acpi.h | 6 +++ drivers/acpi/riscv/irqchip.c | 57 +++++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-early.c | 28 ++++++++++++ drivers/irqchip/irq-riscv-imsic-state.c | 33 +++++++++++--- 4 files changed, 119 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 0ac2df2dd194..6dde3d63dc0e 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -69,6 +69,8 @@ static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; } int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, u32 *cbom_size, u32 *cboz_size, u32 *cbop_size); struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc); +struct fwnode_handle *acpi_imsic_create_fwnode(struct acpi_madt_imsic *imsic); +struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -89,6 +91,10 @@ static inline int acpi_get_cbo_block_size(struct acpi_table_header *table, return -EINVAL; } +static inline struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev) +{ + return NULL; +} #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c index 36f066a2cad5..6e15d45cb229 100644 --- a/drivers/acpi/riscv/irqchip.c +++ b/drivers/acpi/riscv/irqchip.c @@ -18,6 +18,8 @@ struct riscv_irqchip_list { LIST_HEAD(rintc_list); +static struct fwnode_handle *imsic_acpi_fwnode; + struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc) { struct property_entry props[6] = {}; @@ -44,3 +46,58 @@ struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *r return fwnode; } + +static struct fwnode_handle *acpi_imsic_get_rintc_fwnode(u32 idx) +{ + struct riscv_irqchip_list *rintc_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + unsigned int j = 0; + + list_for_each_safe(i, tmp, &rintc_list) { + rintc_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = rintc_element->fwnode; + + if (j == idx) + return fwnode; + + j++; + } + + return NULL; +} + +struct fwnode_handle *acpi_imsic_create_fwnode(struct acpi_madt_imsic *imsic) +{ + struct property_entry props[8] = {}; + struct software_node_ref_args *refs; + struct fwnode_handle *parent_fwnode; + unsigned int nr_rintc, i; + + props[0] = PROPERTY_ENTRY_U32("riscv,guest-index-bits", imsic->guest_index_bits); + props[1] = PROPERTY_ENTRY_U32("riscv,hart-index-bits", imsic->hart_index_bits); + props[2] = PROPERTY_ENTRY_U32("riscv,group-index-bits", imsic->group_index_bits); + props[3] = PROPERTY_ENTRY_U32("riscv,group-index-shift", imsic->group_index_shift); + props[4] = PROPERTY_ENTRY_U32("riscv,num-ids", imsic->num_ids); + props[5] = PROPERTY_ENTRY_U32("riscv,num-guest-ids", imsic->num_guest_ids); + + nr_rintc = list_count_nodes(&rintc_list); + refs = kcalloc(nr_rintc, sizeof(*refs), GFP_KERNEL); + if (!refs) + return NULL; + + for (i = 0; i < nr_rintc; i++) { + parent_fwnode = acpi_imsic_get_rintc_fwnode(i); + refs[i] = SOFTWARE_NODE_REFERENCE(to_software_node(parent_fwnode), RV_IRQ_EXT); + } + props[6] = PROPERTY_ENTRY_REF_ARRAY_LEN("interrupts-extended", refs, nr_rintc); + + imsic_acpi_fwnode = fwnode_create_software_node_early(props, NULL); + + return imsic_acpi_fwnode; +} + +struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev) +{ + return imsic_acpi_fwnode; +} diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c index 1de89ce1ec2f..93f4d748ca6d 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -256,3 +257,30 @@ static int __init imsic_early_dt_init(struct device_node *node, return 0; } IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); + +#ifdef CONFIG_ACPI +static int __init imsic_early_acpi_init(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct fwnode_handle *fwnode; + int rc; + + /* + * There should be only one IMSIC node. + */ + fwnode = acpi_imsic_create_fwnode((struct acpi_madt_imsic *)header); + if (!fwnode) { + pr_err("unable to create IMSIC FW node\n"); + return -ENOMEM; + } + + rc = imsic_early_probe(fwnode); + if (!rc) + pci_msi_register_fwnode_provider(&acpi_riscv_get_msi_fwnode); + + return rc; +} + +IRQCHIP_ACPI_DECLARE(riscv_imsic, ACPI_MADT_TYPE_IMSIC, + NULL, 1, imsic_early_acpi_init); +#endif diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index 412b5b919dcc..d0e09e51e8ae 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -225,15 +225,38 @@ static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, return riscv_get_intc_hartid(parent.fwnode, hartid); } +static int __init imsic_acpi_get_mmio_resource(struct fwnode_handle *fwnode, + u32 index, struct resource *res) +{ + int rc; + struct fwnode_reference_args parent; + u64 base; + u32 size; + + rc = fwnode_property_get_reference_args(fwnode, + "interrupts-extended", NULL, + 0, index, &parent); + if (rc) + return rc; + + rc = fwnode_property_read_u64_array(parent.fwnode, "riscv,imsic-addr", + &base, 1); + rc = fwnode_property_read_u32_array(parent.fwnode, "riscv,imsic-size", + &size, 1); + if (!rc) { + res->start = base; + res->end = res->start + size - 1; + } + + return 0; +} + static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, u32 index, struct resource *res) { - /* - * Currently, only OF fwnode is support so extend this function - * for other types of fwnode for ACPI support. - */ if (!is_of_node(fwnode)) - return -EINVAL; + return imsic_acpi_get_mmio_resource(fwnode, index, res); + return of_address_to_resource(to_of_node(fwnode), index, res); } From patchwork Thu Aug 3 17:59:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130858 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1401541vqx; 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 14/21] ACPI: bus: Add acpi_riscv_init function Date: Thu, 3 Aug 2023 23:29:09 +0530 Message-Id: <20230803175916.3174453-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773243031985643767 X-GMAIL-MSGID: 1773243031985643767 Add a new function for RISC-V to do any architecture specific initialization. This function will be used to create platform devices like APLIC, IMSIC MSI controller, RISC-V IOMMU etc. Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 1 + drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/init.c | 12 ++++++++++++ include/linux/acpi.h | 6 ++++++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/init.c diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 2fc2b43a4ed3..9a8c16170a4b 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1388,6 +1388,7 @@ static int __init acpi_init(void) pci_mmcfg_late_init(); acpi_arm_init(); + acpi_riscv_init(); acpi_viot_early_init(); acpi_hest_init(); acpi_ghes_init(); diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 8b664190d172..3433a19c421d 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += rhct.o irqchip.o +obj-y += rhct.o irqchip.o init.o diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c new file mode 100644 index 000000000000..b5807bbdb171 --- /dev/null +++ b/drivers/acpi/riscv/init.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include + +void __init acpi_riscv_init(void) +{ +} diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 641dc4843987..d16739928888 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1511,6 +1511,12 @@ void acpi_arm_init(void); static inline void acpi_arm_init(void) { } #endif +#ifdef CONFIG_RISCV +void acpi_riscv_init(void); +#else +static inline void acpi_riscv_init(void) { } +#endif + #ifdef CONFIG_ACPI_PCC void acpi_init_pcc(void); #else From patchwork Thu Aug 3 17:59:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130851 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1397909vqx; Thu, 3 Aug 2023 13:49:36 -0700 (PDT) X-Google-Smtp-Source: APBJJlHWKfX4KIiQJp3VJRpqcplGK7uSmcnqURkFLK5SCERt2/qhNX+6bce7IAQGTBnYH3KJ4f6Z X-Received: by 2002:a05:6a20:72a5:b0:136:42c8:693c with SMTP id o37-20020a056a2072a500b0013642c8693cmr19930832pzk.6.1691095776028; Thu, 03 Aug 2023 13:49:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691095776; cv=none; d=google.com; s=arc-20160816; b=Hyv0MtxmTNWH2TwHvni88MYGq7q90elWDc9EfRCVFoMtWwhxZZ/5N228cvbln9L8g8 4DMMmryzOLJ8k5oNa/ruT9ccjle1xAoMiehiw1L65J9fxdMPmpiGUYqXqdHzsk1sQegv D9+ZQJDnI/gkadsTbNmVItKvzp95ntxXleG03Lrnz5cFFCDgL+TkSxaXd7tI/EMfsTl8 lv+feGcWQ6821IW9MuivhLlU6P04rFMhrkOo0+b5mLx7UqiwtE10Ae9BZQC4uEvYXdrB U3Ts1DHUudUR79bm9EArWqjfF1Su2v58vjHQ1iZgwphWh80w+xzH8eYfDY8mjnvIFoE8 Qvqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9aQz/o5NvlReZUl/stpeRs4o5FY0c8qnUYDCfHqNmJI=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=MRBUyIEKpsDBQ/iEwSLOWLnRQQ14e64LqAfIGif2fkxO5exToRE7cpo3xoDZQeQwp6 ZUWQOUN/hVKZ/OI81AdF0CY/G6G1cJ0Ue1YvIGwkTYVRgXvIe/6oKJzD1cX5Y1OQq11e YO0P0EhbVjLwd8pSg4w1gsXGkSWzL2Naf0cYcIjMVrZPA6ZP1dbxiGhXnZDSM2gMaJUK Zdu2Q7wosWM04fsQtKK119UkeYoGS/Y0/daQHgmgetU75Z2EPdO5VQnJ26sSWpn92pn9 Ye57xLdYk1nMC+prg4E/ITYOb2DrWK1eDiMr7j08omyZLx9KppLqxx80JWzZXw8cksvb Pwjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Yv3oRH7T; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 15/21] ACPI: RISC-V: Create IMSIC platform device Date: Thu, 3 Aug 2023 23:29:10 +0530 Message-Id: <20230803175916.3174453-16-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773242444532865162 X-GMAIL-MSGID: 1773242444532865162 The MSI controller functionality of the RISC-V IMSIC is probed as a platform device by the driver. So, create the IMSIC platform device if the IMSIC was discovered in MADT during early IMSIC driver probe. Signed-off-by: Sunil V L --- drivers/acpi/riscv/init.c | 2 ++ drivers/acpi/riscv/init.h | 4 ++++ drivers/acpi/riscv/irqchip.c | 23 +++++++++++++++++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/acpi/riscv/init.h diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index b5807bbdb171..be61c08ea385 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -6,7 +6,9 @@ */ #include +#include "init.h" void __init acpi_riscv_init(void) { + riscv_acpi_imsic_platform_init(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h new file mode 100644 index 000000000000..a2f72bb294d3 --- /dev/null +++ b/drivers/acpi/riscv/init.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +void __init riscv_acpi_imsic_platform_init(void); diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c index 6e15d45cb229..ca96bf109cf7 100644 --- a/drivers/acpi/riscv/irqchip.c +++ b/drivers/acpi/riscv/irqchip.c @@ -9,7 +9,10 @@ #include #include #include +#include +#include #include +#include "../../../drivers/pci/pci.h" struct riscv_irqchip_list { struct fwnode_handle *fwnode; @@ -101,3 +104,23 @@ struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev) { return imsic_acpi_fwnode; } + +void __init riscv_acpi_imsic_platform_init(void) +{ + struct platform_device *pdev; + int ret; + + if (!acpi_riscv_get_msi_fwnode(NULL)) { + pci_no_msi(); + return; + } + + pdev = platform_device_alloc("riscv-imsic", 0); + if (!pdev) + return; + + pdev->dev.fwnode = acpi_riscv_get_msi_fwnode(NULL); + ret = platform_device_add(pdev); + if (ret) + platform_device_put(pdev); +} From patchwork Thu Aug 3 17:59:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130811 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1348183vqx; Thu, 3 Aug 2023 12:03:53 -0700 (PDT) X-Google-Smtp-Source: APBJJlFhK/wCd9M6wpPynotF/RkotcbyaQDEYfUUyUqRNnQzxn2JsxnlwI8UW7I7HoDweQNbTHSD X-Received: by 2002:a05:6358:998b:b0:134:e3e6:c0bd with SMTP id j11-20020a056358998b00b00134e3e6c0bdmr11217607rwb.32.1691089433313; Thu, 03 Aug 2023 12:03:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691089433; cv=none; d=google.com; s=arc-20160816; b=T5I/rWyUksmFyU1VDLReeCjgKEFnRR7XYo/hRfiuMKVcqQkVCDQR4ceqal1VB8yrjf 6mgFoObLDYtkAcZn74OEy8CwRIkluyaIVgBn/eTUqei9FC4aZzv4HGACPQEivJsgu9J9 G0lmOodbfnOhEtXbiMVwR4kJ/qVkEx1ioBxhhZGPISACtcB6uUm8EFIm7V7TfDjDf/0R 1XhrgksoUBskafWFyirEVXK1dSpspjsrp0zIwcAayvyej23AqaQnuZrHdTRBSFDF5+bD 3DTgPdSZpy8h9HdjS4umAJ81lFQ499IKWQL+bHOftebqU5g8ftanTluXILGR5ZlQGTnE usFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=95yH1ZRY1l5+vMULtm7DKGPnoBqPk/7PEb2F1bhVxfo=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=FMyIx7U15ACdoUFZNGTvOqPMZyxVlzhvwRcW0LjnDjuun2vvjUuYDW840NTenFOTvL XCYl3d2SOvkUOj2JjHrkNqTYBZ0WjKrmQkpQRQsT0inuCSRrnN2WEMPMgDouqlDHUNCT mrlgE6RBe9DN8l42jBhv1G/fyhitZ5v5eQixcjTOAZo31cK9ZgWoKg7NBUaCgHk1hHDD IZz17CeF+cIF1uOiSQYKR0DYWsEtKJvny1ukfZdBz/xnB82VgE3A67ruDSRq8ZMdhw72 rSGgt+zAJNr5yPy6tmlDN7fxzng64BlhlNLBRW1NSseKqgPw2BvbX8+dC3yQPjk6jb+U eTOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=V2wPisBD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 16/21] ACPI: Add APLIC IRQ model for RISC-V Date: Thu, 3 Aug 2023 23:29:11 +0530 Message-Id: <20230803175916.3174453-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773235793636436735 X-GMAIL-MSGID: 1773235793636436735 Add the IRQ model for RISC-V APLIC so that acpi_set_irq_model can use this for RISC-V. Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 3 +++ include/linux/acpi.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 9a8c16170a4b..dd9d80630bf6 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1132,6 +1132,9 @@ static int __init acpi_bus_init_irq(void) case ACPI_IRQ_MODEL_LPIC: message = "LPIC"; break; + case ACPI_IRQ_MODEL_APLIC: + message = "APLIC"; + break; default: pr_info("Unknown interrupt routing model\n"); return -ENODEV; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index d16739928888..698d120a1bd2 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -95,6 +95,7 @@ enum acpi_irq_model_id { ACPI_IRQ_MODEL_PLATFORM, ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_LPIC, + ACPI_IRQ_MODEL_APLIC, ACPI_IRQ_MODEL_COUNT }; From patchwork Thu Aug 3 17:59:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130819 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1360184vqx; Thu, 3 Aug 2023 12:25:56 -0700 (PDT) X-Google-Smtp-Source: APBJJlGBrr6Y7peox6RdOshB+S6J/V048IZ9j4a4+QAbxoWoywyIWHrhuCsWHs496OTUnFDhOUU2 X-Received: by 2002:a05:6a00:2e08:b0:687:472f:5150 with SMTP id fc8-20020a056a002e0800b00687472f5150mr12347102pfb.8.1691090755680; Thu, 03 Aug 2023 12:25:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691090755; cv=none; d=google.com; s=arc-20160816; b=aLm/ambMvzR8damoZR1j9z/zsmMBeoeyhQ0OS1W3qx15WJ1GK4dl9oP7+twN96Vary CHKSiP02QRNPzr9eb7AwVIfXIZ/Ep69bQs8d5jCin1tBhSzIX8O/qgdfurI8hJ5P/9Q/ iyIvNvAM4ra2+IIIbJTpWh/qXWiVvnAPSdC+Pdlb9kSSN3FychcwulWlT/7hyPV0pV7N kAuAVbX7ARHTYZBEckF/G6mjNNm593oNZLHMugLaOY2cwRR6tDqN2f3DDg3AmbhR0maI 0/0CTopEBq783AESAalFwb+Uhbx7YdmJn96n19BZA0wBb3w1JsoEp3nk2VdXxT34reHo UY2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MqlDPHKEWaBxTYs/0M8htriIKOWDT6nuJRMhsrHXzuE=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=PwNQTbzyP67dk5ZoRZm0o5bv2s0x1KD8oA+LjaFP1EqlHPD1DoNUdIlMwyTJmVlDD1 V/EH3igkdpc/criaI7pKjempZ96ZzO/xMlC9T9uXgNLfAmkfAbQVsUWA4wTaDlgvFDC8 b/k9+nYLQWbV31bwk1wbRw3hGuiPBsmCe7IXNMMb/rBZDWXLqbY0mf37iU4zNhxoG5Jj YOzVSyRK+q4SjC1mcoVqHgrNhkYFLppB1C547qCrrEnyv+vBkZW7Qt/K/WxA9KkpI+k8 tx1GPYnxevBSMhxkTw/2r1g3C8Zb1+U2Dyw+3K6IwiCXgmfYC2XiktDmpQs1ttBFBxoK dpbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Mck7EqqR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 17/21] ACPI: RISC-V: Create APLIC platform device Date: Thu, 3 Aug 2023 23:29:12 +0530 Message-Id: <20230803175916.3174453-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773237180145435961 X-GMAIL-MSGID: 1773237180145435961 Since APLIC needs to be a platform device, probe the MADT and create platform devices for each APLIC in the system. Use software node framework for the fwnode which allows to create properties and hence the actual irqchip driver doesn't need to do anything different for ACPI vs DT. Signed-off-by: Sunil V L --- Documentation/riscv/acpi.rst | 6 ++ drivers/acpi/riscv/init.c | 1 + drivers/acpi/riscv/init.h | 1 + drivers/acpi/riscv/irqchip.c | 183 +++++++++++++++++++++++++++++++++++ 4 files changed, 191 insertions(+) diff --git a/Documentation/riscv/acpi.rst b/Documentation/riscv/acpi.rst index e2406546bc16..9ea9008288ea 100644 --- a/Documentation/riscv/acpi.rst +++ b/Documentation/riscv/acpi.rst @@ -29,3 +29,9 @@ properties are created using the data in MADT table. ``riscv,ext-intc-id`` - The unique ID of the external interrupts connected to this hart. + +2) RISC-V Advanced Platform Level Interrupt Controller (APLIC) +----------- + +``riscv,gsi-base`` - The global system interrupt number where this APLIC’s +interrupt inputs start. diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index be61c08ea385..ee747211174f 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -11,4 +11,5 @@ void __init acpi_riscv_init(void) { riscv_acpi_imsic_platform_init(); + riscv_acpi_aplic_platform_init(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h index a2f72bb294d3..17bcf0baaadb 100644 --- a/drivers/acpi/riscv/init.h +++ b/drivers/acpi/riscv/init.h @@ -2,3 +2,4 @@ #include void __init riscv_acpi_imsic_platform_init(void); +void __init riscv_acpi_aplic_platform_init(void); diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c index ca96bf109cf7..7fb7befdb303 100644 --- a/drivers/acpi/riscv/irqchip.c +++ b/drivers/acpi/riscv/irqchip.c @@ -23,6 +23,8 @@ LIST_HEAD(rintc_list); static struct fwnode_handle *imsic_acpi_fwnode; +LIST_HEAD(aplic_list); + struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc) { struct property_entry props[6] = {}; @@ -124,3 +126,184 @@ void __init riscv_acpi_imsic_platform_init(void) if (ret) platform_device_put(pdev); } + +/* + * The ext_intc_id format is as follows: + * Bits [31:24] APLIC/PLIC ID + * Bits [15:0] APLIC IDC ID / PLIC S-Mode Context ID for this hart + */ +#define APLIC_PLIC_ID(x) ((x) >> 24) +#define IDC_CONTEXT_ID(x) ((x) & 0x0000ffff) + +static struct fwnode_handle *acpi_ext_intc_get_rintc_fwnode(u8 aplic_plic_id, u16 index) +{ + struct riscv_irqchip_list *rintc_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + u32 id; + int rc; + + list_for_each_safe(i, tmp, &rintc_list) { + rintc_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = rintc_element->fwnode; + rc = fwnode_property_read_u32_array(fwnode, "riscv,ext-intc-id", &id, 1); + if (rc) + continue; + + if ((APLIC_PLIC_ID(id) == aplic_plic_id) && (IDC_CONTEXT_ID(id) == index)) + return fwnode; + } + + return NULL; +} + +static struct fwnode_handle *acpi_aplic_create_fwnode(struct acpi_madt_aplic *aplic) +{ + struct fwnode_handle *fwnode, *parent_fwnode; + struct riscv_irqchip_list *aplic_element; + struct software_node_ref_args *refs; + struct property_entry props[8] = {}; + unsigned int i; + + props[0] = PROPERTY_ENTRY_U32("riscv,gsi-base", aplic->gsi_base); + props[1] = PROPERTY_ENTRY_U32("riscv,num-sources", aplic->num_sources); + props[2] = PROPERTY_ENTRY_U32("riscv,num-idcs", aplic->num_idcs); + props[3] = PROPERTY_ENTRY_U32("riscv,aplic-id", aplic->id); + props[4] = PROPERTY_ENTRY_U64("riscv,aplic-base", aplic->base_addr); + props[5] = PROPERTY_ENTRY_U32("riscv,aplic-size", aplic->size); + if (aplic->num_idcs) { + refs = kcalloc(aplic->num_idcs, sizeof(*refs), GFP_KERNEL); + if (!refs) + return NULL; + + for (i = 0; i < aplic->num_idcs; i++) { + parent_fwnode = acpi_ext_intc_get_rintc_fwnode(aplic->id, i); + refs[i] = SOFTWARE_NODE_REFERENCE(to_software_node(parent_fwnode), + RV_IRQ_EXT); + } + props[6] = PROPERTY_ENTRY_REF_ARRAY_LEN("interrupts-extended", + refs, aplic->num_idcs); + } else { + props[6] = PROPERTY_ENTRY_BOOL("msi-parent"); + } + + fwnode = fwnode_create_software_node_early(props, NULL); + + if (fwnode) { + aplic_element = kzalloc(sizeof(*aplic_element), GFP_KERNEL); + if (!aplic_element) { + fwnode_remove_software_node(fwnode); + return NULL; + } + + aplic_element->fwnode = fwnode; + list_add_tail(&aplic_element->list, &aplic_list); + } + + return fwnode; +} + +static struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi) +{ + struct riscv_irqchip_list *aplic_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + u32 gsi_base; + u32 nr_irqs; + int rc; + + list_for_each_safe(i, tmp, &aplic_list) { + aplic_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = aplic_element->fwnode; + rc = fwnode_property_read_u32_array(fwnode, "riscv,gsi-base", &gsi_base, 1); + if (!rc) { + rc = fwnode_property_read_u32_array(fwnode, "riscv,num-sources", + &nr_irqs, 1); + if (!rc && (gsi >= gsi_base && gsi < gsi_base + nr_irqs)) + return fwnode; + } + } + + return NULL; +} + +static u32 __init aplic_gsi_to_irq(u32 gsi) +{ + return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH); +} + +static int __init aplic_create_platform_device(struct fwnode_handle *fwnode) +{ + struct platform_device *pdev; + u32 aplic_size, aplic_id; + struct resource *res; + u64 aplic_base; + int ret; + + if (!fwnode) + return -ENODEV; + + ret = fwnode_property_read_u64_array(fwnode, "riscv,aplic-base", &aplic_base, 1); + if (ret) + return -ENODEV; + + ret = fwnode_property_read_u32_array(fwnode, "riscv,aplic-size", &aplic_size, 1); + if (ret) + return -ENODEV; + + ret = fwnode_property_read_u32_array(fwnode, "riscv,aplic-id", &aplic_id, 1); + if (ret) + return -ENODEV; + + pdev = platform_device_alloc("riscv-aplic", aplic_id); + if (!pdev) + return -ENOMEM; + + res = kcalloc(1, sizeof(*res), GFP_KERNEL); + if (!res) { + ret = -ENOMEM; + goto dev_put; + } + + res->start = aplic_base; + res->end = res->start + aplic_size - 1; + res->flags = IORESOURCE_MEM; + ret = platform_device_add_resources(pdev, res, 1); + /* + * Resources are duplicated in platform_device_add_resources, + * free their allocated memory + */ + kfree(res); + + pdev->dev.fwnode = fwnode; + ret = platform_device_add(pdev); + if (ret) + goto dev_put; + + return 0; + +dev_put: + platform_device_put(pdev); + return ret; +} + +static int __init aplic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_aplic *aplic = (struct acpi_madt_aplic *)header; + struct fwnode_handle *fwnode; + + fwnode = acpi_aplic_create_fwnode(aplic); + if (fwnode) + aplic_create_platform_device(fwnode); + + return 0; +} + +void __init riscv_acpi_aplic_platform_init(void) +{ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, aplic_parse_madt, 0) > 0) { + acpi_set_irq_model(ACPI_IRQ_MODEL_APLIC, aplic_get_gsi_domain_id); + acpi_set_gsi_to_irq_fallback(aplic_gsi_to_irq); + } +} From patchwork Thu Aug 3 17:59:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130863 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1408279vqx; Thu, 3 Aug 2023 14:11:08 -0700 (PDT) X-Google-Smtp-Source: APBJJlFi3zWQPvBi372VEg71/lc/2JlbnYpP7Gk4eBVWD8J0l8X3ShanvL5rRZx/YyynRrYdepJQ X-Received: by 2002:a2e:9f50:0:b0:2b9:ad7d:a144 with SMTP id v16-20020a2e9f50000000b002b9ad7da144mr8456406ljk.11.1691097068298; Thu, 03 Aug 2023 14:11:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691097068; cv=none; d=google.com; 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 18/21] irqchip/irq-riscv-aplic-msi: Add ACPI support Date: Thu, 3 Aug 2023 23:29:13 +0530 Message-Id: <20230803175916.3174453-19-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773243799299174037 X-GMAIL-MSGID: 1773243799299174037 Search and configure the MSI domain for the APLIC on ACPI based systems. Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-aplic-msi.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/irq-riscv-aplic-msi.c index 086d00e0429e..1948444c9e0c 100644 --- a/drivers/irqchip/irq-riscv-aplic-msi.c +++ b/drivers/irqchip/irq-riscv-aplic-msi.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "irq-riscv-aplic-main.h" @@ -178,6 +179,8 @@ static void aplic_msi_write_msg(struct msi_desc *desc, struct msi_msg *msg) int aplic_msi_setup(struct device *dev, void __iomem *regs) { const struct imsic_global_config *imsic_global; + struct irq_domain *msi_domain = NULL; + struct fwnode_handle *msi_fwnode; struct irq_domain *irqdomain; struct aplic_priv *priv; struct aplic_msicfg *mc; @@ -261,8 +264,17 @@ int aplic_msi_setup(struct device *dev, void __iomem *regs) * IMSIC and the IMSIC MSI domains are created later through * the platform driver probing so we set it explicitly here. */ - if (is_of_node(dev->fwnode)) + if (is_of_node(dev->fwnode)) { of_msi_configure(dev, to_of_node(dev->fwnode)); + } else { + msi_fwnode = acpi_riscv_get_msi_fwnode(dev); + if (msi_fwnode) + msi_domain = irq_find_matching_fwnode(msi_fwnode, + DOMAIN_BUS_PLATFORM_MSI); + + if (msi_domain) + dev_set_msi_domain(dev, msi_domain); + } } /* Create irq domain instance for the APLIC MSI-mode */ From patchwork Thu Aug 3 17:59:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130843 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1385473vqx; Thu, 3 Aug 2023 13:20:27 -0700 (PDT) X-Google-Smtp-Source: APBJJlGPZusfamHUzis2OXfnum3B2wWl9uJ6mY+oGVv3RNa97XR3zM4Fp9Bajq97DNlwnWfRoD6x X-Received: by 2002:a05:6a20:8e27:b0:13e:aede:f37e with SMTP id y39-20020a056a208e2700b0013eaedef37emr9074145pzj.41.1691094026720; Thu, 03 Aug 2023 13:20:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691094026; cv=none; d=google.com; s=arc-20160816; b=mbwjucWBLIGtgejdDm6qmHKb3jYAZbG+dYWEKnQspUXv+FKaodKvXv/Yff4hLYXrrn dsVgOfB+HapoXztX1irsEwsuuOqixTS8mn0Uc2+BpcbM9MM7BdCAqtLM6f5d8neZ7uld YEprchCOvwOS2VpqULU9/H95CnIdIdqR1TjbBs86hAeDxUf22uSxUtaH33gBbCXbz3cR ZmH7YRcgeVdloEextC69pRF1OyVyw+qAxMb0R3SVEviAjtrYLR9R2cIRlAFQH/5/KB4H iwbXxdRva3k6y+FHxVVyrnGk4kvQNrKjJ/gPqsQGMm25N016ye14XnqrJxAkJbcwVbkB bdHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oa5JuUdn7+qjYPf/m5YirkX0l5WPw2pxjpAQ3vHoF5I=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=u0aA68fZbr2kARVMqI9IWx/eapEIco3Jvj7VoVAjQBda2fTnV2PmebkhO7JU8eGUQP I0g41rleZTuD4+TWjT0+wNSZTNZ9Esy9mIb8F9IPg5jaOeGZf1qlKVdlgc4AljWaeuCV u41GJTTUh3/7NRCpROjxdRudPOGPFZ2rsn352aCY3GLkATWT1K/bBiY6MXExjUlW8eCU /MyQzrBIcDnM12wmGouH/biS9kXGytWsUOyAk9Vewgkw7/GEQdDJygBrRLsndwVNiFAD kytLKdFJSO0NvIcA4RlzQP/q3atj07IMzp5zAQhu4ku9N4MfRQxCVms7aLZy6CYVIzGv U1hA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=KQbJbLeA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 19/21] ACPI: bus: Add PLIC IRQ model Date: Thu, 3 Aug 2023 23:29:14 +0530 Message-Id: <20230803175916.3174453-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773240610102189245 X-GMAIL-MSGID: 1773240610102189245 Add the IRQ model for RISC-V PLIC so that acpi_set_irq_model can use this for RISC-V. Signed-off-by: Haibo Xu Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 3 +++ include/linux/acpi.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index dd9d80630bf6..68b8d38ec48a 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1135,6 +1135,9 @@ static int __init acpi_bus_init_irq(void) case ACPI_IRQ_MODEL_APLIC: message = "APLIC"; break; + case ACPI_IRQ_MODEL_PLIC: + message = "PLIC"; + break; default: pr_info("Unknown interrupt routing model\n"); return -ENODEV; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 698d120a1bd2..31f080df179d 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -96,6 +96,7 @@ enum acpi_irq_model_id { ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_LPIC, ACPI_IRQ_MODEL_APLIC, + ACPI_IRQ_MODEL_PLIC, ACPI_IRQ_MODEL_COUNT }; From patchwork Thu Aug 3 17:59:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130809 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1347500vqx; Thu, 3 Aug 2023 12:02:57 -0700 (PDT) X-Google-Smtp-Source: APBJJlEQ7pt99eqg6BusN1bmTADO19XvLMkfdHwGlDHH2ypISLseUI56MQ20uBYdR7XkdEcZxtil X-Received: by 2002:a17:90b:4b42:b0:268:808:8e82 with SMTP id mi2-20020a17090b4b4200b0026808088e82mr24700831pjb.1.1691089377298; Thu, 03 Aug 2023 12:02:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691089377; cv=none; d=google.com; s=arc-20160816; b=L72/g2mGQ5sJYtDm8jIAtH/Vhi53ZLB0KHGHFMwT1F1OIL+pZFyL+J9CFudYteCed3 2SDJqbS4i6ipZ5Qwy/wLFjljpR6yTdzZXhnnSX2PlzW1rSg4p9tNFBdcsJcR1eSEWvhH lHfhWX+kGnVB6kwcMCWtdYaUCVw0hJOk9STksI6uHcM30Fy1rZDp144tV7r2H3TwlbKq FgFKqiXN3XLZDUVL6n0DXKmdNrQ6P40jRQnSVVOLlhYSnz6YLy1i2LXH1t60K4whm8Ql +bnwjCgkYoRHuG4McpE3DzePqek3i3YPhMwUrJAvo5yjNQh/yp5KhbDpPGfzeBTlOzob bs8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4+Q8KfNrcpLCQ+Zm4Z9cXmSMTUQ/Cx2NE3GzYzgbHwU=; fh=dzn7FZXuyjRD/SsADoLVmv8ajN6bypv0shpvYBNDmUc=; b=rRghs4fQBXWS9/ZscPCoiF5aKEd52Kh6LYKdQYzPaYfZtbplto+PHB3/ZuhEzsXvA7 dFKr51eh8nHUQCqSrfHzMViKGsNs7QeM1NLcAMNNCs53M6E4CSLnD5ALWsHNFT5ONRPu DFF1yOP9tzqQh1PadCDsMgm3lzDSvHtSyXcAD6B+FWxERRdXllCGvVipIXxCUXzbDSTZ vYb1BUokXz6+81zhCTYn1KZ2/hrqFDhvY11vOisXSI0AcaxIeuw2YRTXCh+4x+hVQWJO 8SDuQ3Fo59uVtqTbDDVCBTrz/P9aWUzEzB4LxIld1jMHjqBvELRRgd6ZHDTDa8ZNfntn A5cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=TWzDXrq5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 20/21] RISC-V: ACPI: Create PLIC platform device Date: Thu, 3 Aug 2023 23:29:15 +0530 Message-Id: <20230803175916.3174453-21-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773235735303899681 X-GMAIL-MSGID: 1773235735303899681 Since PLIC needs to be a platform device, probe the MADT and create platform devices for each PLIC in the system. Use software node framework for the fwnode which allows to create properties and hence the actual irqchip driver doesn't need to do anything different for ACPI vs DT. Signed-off-by: Sunil V L Co-developed-by: Haibo Xu Signed-off-by: Haibo Xu --- Documentation/riscv/acpi.rst | 6 ++ arch/riscv/include/asm/acpi.h | 3 + drivers/acpi/riscv/init.c | 1 + drivers/acpi/riscv/init.h | 1 + drivers/acpi/riscv/irqchip.c | 198 ++++++++++++++++++++++++++++++++++ 5 files changed, 209 insertions(+) diff --git a/Documentation/riscv/acpi.rst b/Documentation/riscv/acpi.rst index 9ea9008288ea..007483dfddc1 100644 --- a/Documentation/riscv/acpi.rst +++ b/Documentation/riscv/acpi.rst @@ -35,3 +35,9 @@ to this hart. ``riscv,gsi-base`` - The global system interrupt number where this APLIC’s interrupt inputs start. + +3) RISC-V Platform Level Interrupt Controller (PLIC) +----------- + +``riscv,gsi-base`` - The global system interrupt number where this PLIC’s +interrupt inputs start. diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6dde3d63dc0e..163b8eefa744 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -71,6 +71,7 @@ int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, u struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc); struct fwnode_handle *acpi_imsic_create_fwnode(struct acpi_madt_imsic *imsic); struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev); +int acpi_plic_get_context_id(u8 plic_id, u16 idx); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -95,6 +96,8 @@ static inline struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev { return NULL; } + +static inline int acpi_plic_get_context_id(u8 plic_id, u16 idx) { return idx; } #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index ee747211174f..cc733ea9ef1d 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -12,4 +12,5 @@ void __init acpi_riscv_init(void) { riscv_acpi_imsic_platform_init(); riscv_acpi_aplic_platform_init(); + riscv_acpi_plic_platform_init(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h index 17bcf0baaadb..b4b305d83b3a 100644 --- a/drivers/acpi/riscv/init.h +++ b/drivers/acpi/riscv/init.h @@ -3,3 +3,4 @@ void __init riscv_acpi_imsic_platform_init(void); void __init riscv_acpi_aplic_platform_init(void); +void __init riscv_acpi_plic_platform_init(void); diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c index 7fb7befdb303..cb70f0f2294b 100644 --- a/drivers/acpi/riscv/irqchip.c +++ b/drivers/acpi/riscv/irqchip.c @@ -25,6 +25,8 @@ static struct fwnode_handle *imsic_acpi_fwnode; LIST_HEAD(aplic_list); +LIST_HEAD(plic_list); + struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc) { struct property_entry props[6] = {}; @@ -307,3 +309,199 @@ void __init riscv_acpi_aplic_platform_init(void) acpi_set_gsi_to_irq_fallback(aplic_gsi_to_irq); } } + +static int acpi_plic_get_nr_contexts(u8 plic_id) +{ + struct riscv_irqchip_list *rintc_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + u32 id; + int rc, nr_contexts = 0; + + list_for_each_safe(i, tmp, &rintc_list) { + rintc_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = rintc_element->fwnode; + rc = fwnode_property_read_u32_array(fwnode, "riscv,ext-intc-id", &id, 1); + if (rc) + continue; + + if (APLIC_PLIC_ID(id) == plic_id) + nr_contexts++; + } + + return nr_contexts * 2; +} + +int acpi_plic_get_context_id(u8 plic_id, u16 idx) +{ + struct riscv_irqchip_list *rintc_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + u32 id; + int rc, nr_contexts = -1; + + list_for_each_safe(i, tmp, &rintc_list) { + rintc_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = rintc_element->fwnode; + rc = fwnode_property_read_u32_array(fwnode, "riscv,ext-intc-id", &id, 1); + if (rc) + continue; + + if (APLIC_PLIC_ID(id) == plic_id) + nr_contexts++; + if (nr_contexts == idx) + return IDC_CONTEXT_ID(id); + } + + return -1; +} + +static struct fwnode_handle *acpi_plic_create_fwnode(struct acpi_madt_plic *plic) +{ + struct fwnode_handle *fwnode, *parent_fwnode; + struct riscv_irqchip_list *plic_element; + struct software_node_ref_args *refs; + struct property_entry props[8] = {}; + int nr_contexts; + + props[0] = PROPERTY_ENTRY_U32("riscv,gsi-base", plic->gsi_base); + props[1] = PROPERTY_ENTRY_U32("riscv,ndev", plic->num_irqs); + props[2] = PROPERTY_ENTRY_U32("riscv,max_prio", plic->max_prio); + props[3] = PROPERTY_ENTRY_U8("riscv,plic-id", plic->id); + props[4] = PROPERTY_ENTRY_U64("riscv,plic-base", plic->base_addr); + props[5] = PROPERTY_ENTRY_U32("riscv,plic-size", plic->size); + + nr_contexts = acpi_plic_get_nr_contexts(plic->id); + if (nr_contexts) { + refs = kcalloc(nr_contexts, sizeof(*refs), GFP_KERNEL); + for (int i = 0; i < nr_contexts / 2; i++) { + int context_id = acpi_plic_get_context_id(plic->id, i); + + parent_fwnode = acpi_ext_intc_get_rintc_fwnode(plic->id, context_id); + refs[2 * i] = SOFTWARE_NODE_REFERENCE(to_software_node(parent_fwnode), 0); + refs[2 * i + 1] = SOFTWARE_NODE_REFERENCE(to_software_node(parent_fwnode), + RV_IRQ_EXT); + } + props[6] = PROPERTY_ENTRY_REF_ARRAY_LEN("interrupts-extended", refs, nr_contexts); + } + + fwnode = fwnode_create_software_node_early(props, NULL); + + if (fwnode) { + plic_element = kzalloc(sizeof(*plic_element), GFP_KERNEL); + if (!plic_element) { + fwnode_remove_software_node(fwnode); + return NULL; + } + + plic_element->fwnode = fwnode; + list_add_tail(&plic_element->list, &plic_list); + } + + return fwnode; +} + +static struct fwnode_handle *plic_get_gsi_domain_id(u32 gsi) +{ + struct riscv_irqchip_list *plic_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + u32 gsi_base; + u32 nr_irqs; + int rc; + + list_for_each_safe(i, tmp, &plic_list) { + plic_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = plic_element->fwnode; + rc = fwnode_property_read_u32_array(fwnode, "riscv,gsi-base", &gsi_base, 1); + if (!rc) { + rc = fwnode_property_read_u32_array(fwnode, "riscv,ndev", &nr_irqs, 1); + if (!rc && (gsi >= gsi_base && gsi < gsi_base + nr_irqs)) + return fwnode; + } + } + + return NULL; +} + +static u32 plic_gsi_to_irq(u32 gsi) +{ + return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH); +} + +static int __init plic_create_platform_device(struct fwnode_handle *fwnode) +{ + struct platform_device *pdev; + u32 plic_size; + u8 plic_id; + struct resource *res; + u64 plic_base; + int ret; + + if (!fwnode) + return -ENODEV; + + ret = fwnode_property_read_u64_array(fwnode, "riscv,plic-base", &plic_base, 1); + if (ret) + return -ENODEV; + + ret = fwnode_property_read_u32_array(fwnode, "riscv,plic-size", &plic_size, 1); + if (ret) + return -ENODEV; + + ret = fwnode_property_read_u8_array(fwnode, "riscv,plic-id", &plic_id, 1); + if (ret) + return -ENODEV; + + pdev = platform_device_alloc("riscv-plic", plic_id); + if (!pdev) + return -ENOMEM; + + res = kcalloc(1, sizeof(*res), GFP_KERNEL); + if (!res) { + ret = -ENOMEM; + goto dev_put; + } + + res->start = plic_base; + res->end = res->start + plic_size - 1; + res->flags = IORESOURCE_MEM; + ret = platform_device_add_resources(pdev, res, 1); + /* + * Resources are duplicated in platform_device_add_resources, + * free their allocated memory + */ + kfree(res); + + pdev->dev.fwnode = fwnode; + ret = platform_device_add(pdev); + if (ret) + goto dev_put; + + return 0; + +dev_put: + platform_device_put(pdev); + return ret; +} + +static int __init plic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_plic *plic = (struct acpi_madt_plic *)header; + struct fwnode_handle *fwnode; + + fwnode = acpi_plic_create_fwnode(plic); + if (fwnode) + plic_create_platform_device(fwnode); + + return 0; +} + +void __init riscv_acpi_plic_platform_init(void) +{ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, plic_parse_madt, 0) > 0) { + acpi_set_irq_model(ACPI_IRQ_MODEL_PLIC, plic_get_gsi_domain_id); + acpi_set_gsi_to_irq_fallback(plic_gsi_to_irq); + } +} From patchwork Thu Aug 3 17:59:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 130842 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1382801vqx; Thu, 3 Aug 2023 13:14:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHAq3eRHKXVN/rgA2/Ek5hWsb/lFMIj11MpYJPzn03k5LcSl/Y9BqkWzgFipLXx/pi4Ep5P X-Received: by 2002:a17:902:a703:b0:1bc:3f9b:2d57 with SMTP id w3-20020a170902a70300b001bc3f9b2d57mr3038964plq.37.1691093673752; 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 21/21] irqchip/sifive-plic: Add GSI conversion support Date: Thu, 3 Aug 2023 23:29:16 +0530 Message-Id: <20230803175916.3174453-22-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773240240117450157 X-GMAIL-MSGID: 1773240240117450157 ACPI uses flat Global System Interrupt Vector space and hence the GSI number needs to be converted to corresponding local IRQ number of the interrupt controller. Add a new gsi_base field in the priv structure to handle this which will be 0 on DT based systems. Signed-off-by: Sunil V L --- drivers/irqchip/irq-sifive-plic.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 72d6e06ef52b..1c22070e9cdd 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -68,6 +68,7 @@ struct plic_priv { unsigned long plic_quirks; unsigned int nr_irqs; unsigned long *prio_save; + u32 gsi_base; }; struct plic_handler { @@ -314,6 +315,10 @@ static int plic_irq_domain_translate(struct irq_domain *d, { struct plic_priv *priv = d->host_data; + /* For DT, gsi_base is always zero. */ + if (fwspec->param[0] >= priv->gsi_base) + fwspec->param[0] = fwspec->param[0] - priv->gsi_base; + if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) return irq_domain_translate_twocell(d, fwspec, hwirq, type); @@ -453,6 +458,17 @@ static int plic_probe(struct platform_device *pdev) return -EIO; } + /* + * Find out GSI base number + * + * Note: DT does not define "riscv,gsi-base" property so GSI + * base is always zero for DT. + */ + rc = fwnode_property_read_u32_array(dev->fwnode, "riscv,gsi-base", + &priv->gsi_base, 1); + if (rc) + priv->gsi_base = 0; + rc = fwnode_property_read_u32_array(dev->fwnode, "riscv,ndev", &nr_irqs, 1); if (rc) {