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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id h17-20020aa7de11000000b0051debd3e95asi11928035edv.146.2023.08.03.07.39.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:39:34 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=AAXh4DVg; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5756F3858023 for ; Thu, 3 Aug 2023 14:39:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5756F3858023 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691073566; bh=VYyeE3ObhZA0LqAVeEMXdN59kwmdreiPNDB6hiMaHCs=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=AAXh4DVgR5qHQdQRNMXW4f24mJjmr/edvau6sqQPKrtGpVkGWaeCxP5Ik2jccp+jX wzhymtoE/44NDgBk5uMn1K0mVQ7qYqg1Qc5ZtVX1SZJLKui6WbfWimR5hCs/d+Lbh8 IESW10nj2A2+u4vDZNw2hbjhIRE0TRnuvIO09pLQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (unknown [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id BB1A93858D1E for ; Thu, 3 Aug 2023 14:38:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BB1A93858D1E X-IronPort-AV: E=McAfee;i="6600,9927,10791"; a="349485116" X-IronPort-AV: E=Sophos;i="6.01,252,1684825200"; d="scan'208";a="349485116" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2023 07:38:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="872950763" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga001.fm.intel.com with ESMTP; 03 Aug 2023 07:38:41 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 244B01007BD3; Thu, 3 Aug 2023 22:38:38 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFMACC rounding mode intrinsic API Date: Thu, 3 Aug 2023 22:38:37 +0800 Message-Id: <20230803143837.2092129-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773219163990859059 X-GMAIL-MSGID: 1773219163990859059 From: Pan Li This patch would like to support the rounding mode API for the VFMACC for the below samples. * __riscv_vfmacc_vv_f32m1_rm * __riscv_vfmacc_vv_f32m1_rm_m * __riscv_vfmacc_vf_f32m1_rm * __riscv_vfmacc_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfmacc_frm): New class for vfmacc frm. (vfmacc_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfmacc_frm): New function definition. * config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Add frm operand support. * config/riscv/vector.md: Add vfmuladd to frm_mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-multiply-add.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li > --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + gcc/config/riscv/riscv-vector-builtins.cc | 22 +++++++-- gcc/config/riscv/vector.md | 2 +- .../base/float-point-single-multiply-add.c | 47 +++++++++++++++++++ 6 files changed, 93 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-multiply-add.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 8d689f0c935..204ea77c372 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -355,6 +355,29 @@ public: } }; +/* Implements below instructions for frm + - vfmacc +*/ +class vfmacc_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_ternop_insn (true, + code_for_pred_mul_scalar (PLUS, + e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_ternop_insn (true, + code_for_pred_mul (PLUS, e.vector_mode ())); + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2115,6 +2138,7 @@ static CONSTEXPR const reverse_binop_frm
vfrdiv_frm_obj; static CONSTEXPR const widen_binop vfwmul_obj; static CONSTEXPR const widen_binop_frm vfwmul_frm_obj; static CONSTEXPR const vfmacc vfmacc_obj; +static CONSTEXPR const vfmacc_frm vfmacc_frm_obj; static CONSTEXPR const vfnmsac vfnmsac_obj; static CONSTEXPR const vfmadd vfmadd_obj; static CONSTEXPR const vfnmsub vfnmsub_obj; @@ -2350,6 +2374,7 @@ BASE (vfrdiv_frm) BASE (vfwmul) BASE (vfwmul_frm) BASE (vfmacc) +BASE (vfmacc_frm) BASE (vfnmsac) BASE (vfmadd) BASE (vfnmsub) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 2d2b52a312c..67d18412b4c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -160,6 +160,7 @@ extern const function_base *const vfrdiv_frm; extern const function_base *const vfwmul; extern const function_base *const vfwmul_frm; extern const function_base *const vfmacc; +extern const function_base *const vfmacc_frm; extern const function_base *const vfnmsac; extern const function_base *const vfmadd; extern const function_base *const vfnmsub; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index d43b33ded17..3906f2e6248 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -348,6 +348,8 @@ DEF_RVV_FUNCTION (vfnmadd, alu, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfnmadd, alu, full_preds, f_vvfv_ops) DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops) +DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops) +DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops) // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 528dca7ae85..abab06c00ed 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode) } for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++) - add_input_operand (argno); + { + if (base->has_rounding_mode_operand_p () + && argno == call_expr_nargs (exp) - 2) + { + /* Since the rounding mode argument position is not consistent with + the instruction pattern, we need to skip rounding mode argument + here. */ + continue; + } + add_input_operand (argno); + } add_input_operand (Pmode, get_tail_policy_for_pred (pred)); add_input_operand (Pmode, get_mask_policy_for_pred (pred)); add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX)); - /* TODO: Currently, we don't support intrinsic that is modeling rounding mode. - We add default rounding mode for the intrinsics that didn't model rounding - mode yet. */ + if (base->has_rounding_mode_operand_p ()) + add_input_operand (call_expr_nargs (exp) - 2); + + /* The RVV floating-point only support dynamic rounding mode in the + FRM register. */ if (opno != insn_data[icode].n_generator_args) - add_input_operand (Pmode, const0_rtx); + add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode)); return generate_insn (icode); } diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 750b2de8df9..01dc7b0fd5f 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -866,7 +866,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" - (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul") + (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd") (cond [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") (const_string "rne") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-multiply-add.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-multiply-add.c new file mode 100644 index 00000000000..df29f4d240f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-multiply-add.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmacc_vv_f32m1_rm (vd, op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmacc_vf_f32m1_rm (vd, op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfmacc_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmacc_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfmacc_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmacc_vv_f32m1 (vd, op1, op2, vl); +} + +vfloat32m1_t +test_vfmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmacc_vv_f32m1_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfmacc\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */