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While at it, update the maintainers list. Signed-off-by: Imran Shaik Acked-by: Rob Herring --- Changes since v4: - Updated the commit text Changes since v3: - None Changes since v2: - None Changes since v1: - Removed the v2 variant compatible string changes - Updated the maintainers list Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 3 ++- include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml index 767a9d03aa32..d712b1a87e25 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 maintainers: - - Melody Olvera + - Taniya Das + - Imran Shaik description: | Qualcomm global clock control module which supports the clocks, resets and diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h index ddbc6b825e80..2fd36cbfddbb 100644 --- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ /* - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H @@ -138,6 +138,8 @@ #define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 #define GCC_PCIE_0_PIPE_CLK_SRC 129 #define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 +#define GCC_GPLL1_OUT_EVEN 131 +#define GCC_DDRSS_ECPRI_GSI_CLK 132 /* GCC resets */ #define GCC_ECPRI_CC_BCR 0 From patchwork Thu Aug 3 10:57:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 130495 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1084838vqx; Thu, 3 Aug 2023 04:39:10 -0700 (PDT) X-Google-Smtp-Source: APBJJlGKacRC5viDqmJuMs3ndjUIxGNTohbKi01Ql6Onu+GUt3yFnZ5QfjzWmscTI5FHSZEJe/3c X-Received: by 2002:a17:902:d88d:b0:1b6:af1a:7dd3 with SMTP id b13-20020a170902d88d00b001b6af1a7dd3mr15557655plz.23.1691062750054; Thu, 03 Aug 2023 04:39:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691062750; cv=none; d=google.com; s=arc-20160816; b=M6rXvBHzWJrJ/pLsZeKjoodjA15tgaPtSoeiLJxqti2Qdq46Um0qVkYCc1kXdsa/zZ KQ5Z3s1IaPuXS6pS1HGhu5siFP2FgWpHWCEiNAB0LdZSMgHAjAXnxcrFranEeIzMVr8S Xwf/+o4EIZ/nm1GUukDNwYHHiqACGaG45nbfkM9GpxPn81/j+wFiPwRq+saPrfR+hzbO lqpIkXEJZ/nsJ4kTvEeaxaQGQRC7rDLUU4OcZwOLzRaSSVwD/bPrLLkjCfpQXtxEwI1d ELmIq3LxLAN6Xf+4p6MoWGvLgFxCI9QycSgJKRe1s2wA8dC/mfQK/Uocg/jliMhs10Ym MQbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=H0hyPgFsN3rrtEP0ALoiF8TOZT704TBpnLiHmk0qdCs=; fh=JGIPdwR/ghosjNwmGX0PEjhcJN3y9idmuh+UBOLugoc=; b=dUF1C7QUjALQuz1eQpoGTkDYRU9txEnZkKH6OBQ3kCqH0kmzWPZO8BLra/DpAAUVhh 9599wGa6QSsLv0BkkF657B0259B/bJbhlYRAT8Z4/Zv0/je/ptD8mCu8fyd4yWAqdCFC UotyiDirbHiM4CZpQZ5/UKDGupkb8l3EGr3uzjNe88PPVAAJ1wVLJRR4RzprCN0UADKK 8REglez66/Gz+hWY1G1smFWUBv7MQE6HrxrfLLQUOpUf1scS7DXwWL5BrpDQmlvOrwId KQdj7hAsco1FTRfv02qN/qrT61cx9WO0t1ttXZ5G4FuvF4MI80EcavaSfVPq6fPndHBo JHFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=MrD63mbz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - None Changes since v3: - None Changes since v2: - Updated the commit text Changes since v1: - Newly added drivers/clk/qcom/gcc-qdu1000.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 328b306297ef..9fa0616952d9 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -371,16 +371,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = { { .index = DT_TCXO_IDX }, }; -static const struct parent_map gcc_parent_map_7[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_7[] = { - { .index = DT_PCIE_0_PIPE_CLK_IDX }, - { .index = DT_TCXO_IDX }, -}; - static const struct parent_map gcc_parent_map_8[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -440,16 +430,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x9d064, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_7, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_7, - .num_parents = ARRAY_SIZE(gcc_parent_data_7), + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_0_PIPE_CLK_IDX, + }, + .num_parents = 1, .ops = &clk_regmap_phy_mux_ops, }, }, From patchwork Thu Aug 3 10:57:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 130539 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1106883vqx; Thu, 3 Aug 2023 05:18:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHJRNqmK8ew1s1KCohZfKsLWGAH1X6gzYWsmy1xj4YzUg958Tya3CEn2KmbDOUzhzCUq0BL X-Received: by 2002:a05:6a20:158a:b0:13f:83a3:828a with SMTP id h10-20020a056a20158a00b0013f83a3828amr1039315pzj.33.1691065102718; Thu, 03 Aug 2023 05:18:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691065102; cv=none; d=google.com; s=arc-20160816; b=N1DYG8PdUKQ9xpyAsWIPMv5DfnB+TAgnbUjVJDHDM52v+kftUm6SIeMtv5QvnLY+DR r/SC9YmAz5P0hW3Lp3iMvZTJWvVXzZg57Gn/2dy9RaoYETbIKxpxKOmHHHTN0gCZdxXU hu9LQgAZHFbRMiZ8WdKgFUYw5nFpFPWBl5ZlckRSjDsIWWTuJLY3iKnW7FUZvnVkr7RW eNY+KzyIfvZqdUTs+AxzxU5rhvjHIzdvQiNfUapk15A6m/0066rGuqkNX4QSqwi1++56 7EUVOe4CD5R8NnsOdFrKFHzgMQ4TzSwauci64++kIk67m/ZRteXq6fE+EJw+O6mhmDeg /0ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4SyeQspML/A9eUNxJj/DuxhbRjNbVUrslGvkB6v5bWM=; fh=JGIPdwR/ghosjNwmGX0PEjhcJN3y9idmuh+UBOLugoc=; b=I6kQx/nLnwOG5/AD79BXfu6tm04HbrYhwrPexNuvicJXy6IdJ1SqRvXd/yuuJV2/83 YOUhWuVny3dmy8s7DYaz0Z5ngvFUtzLTYVWRHG9xC0sHftWw4fBrV/LpKdm+F8IWiZWR 1k8aE5X5Xp04O9ltpMK8/jBH7HTX3bw+ZUwGaKzpC4CUjSA5g1u4Q4S000lCZs8PE4jm l6hwb+GO926Dta8QMnjZPmtji26AIpynbjCa7ni0xTw5IPJHC0wMULzzNp7eiXFdxEMq i4QdBmH+hAdvxXX6JAtGquCDAOOmD8+VcYJs518r1jASUXAegCyPPYxmKrmiWISINseI taew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=RG3tjmCv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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While at it, fix the gcc clkref clock ops as well. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - Update the commit text Changes since v3: - None Changes since v2: - Split the patch as per the review comments - Newly added drivers/clk/qcom/gcc-qdu1000.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 9fa0616952d9..6a6e0f55516a 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1448,14 +1448,13 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { static struct clk_branch gcc_pcie_0_clkref_en = { .halt_reg = 0x9c004, - .halt_bit = 31, - .halt_check = BRANCH_HALT_ENABLE, + .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9c004, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_clkref_en", - .ops = &clk_branch_ops, + .ops = &clk_branch2_ops, }, }, }; @@ -2275,14 +2274,13 @@ static struct clk_branch gcc_tsc_etu_clk = { static struct clk_branch gcc_usb2_clkref_en = { .halt_reg = 0x9c008, - .halt_bit = 31, - .halt_check = BRANCH_HALT_ENABLE, + .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9c008, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_usb2_clkref_en", - .ops = &clk_branch_ops, + .ops = &clk_branch2_ops, }, }, }; From patchwork Thu Aug 3 10:57:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 130497 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1084929vqx; Thu, 3 Aug 2023 04:39:22 -0700 (PDT) X-Google-Smtp-Source: APBJJlHAHKbBLymI3DCd1onYgMr6TRIVrQQ1btRrMXT+LDEESX63/RGm3sQS2AGJv5zLBvwB1gZI X-Received: by 2002:a17:902:c411:b0:1b8:a67f:1c0f with SMTP id k17-20020a170902c41100b001b8a67f1c0fmr24736867plk.39.1691062762317; Thu, 03 Aug 2023 04:39:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691062762; cv=none; d=google.com; s=arc-20160816; b=fWYqV+MijOwkNsZzsaGLLJCrwbXpjOk6MkVgkq4lsOK4NTYy9gwhUjXUQuOGw0Y2e/ CSXc+xaTJxrwFmQslKf/vfvAYahXnn1GaG5atxoSZFEkbKuIoEXxpeT1+/3tPdxLs55p lXDvvwDT95jDW/meOaitf53PUtudUSt3LW2KV0LQ6TiytxKvnw5vTucu0rW/qTOhpsAS +JMFny14zyW2ifEw3Vh09C6F0U+ew6jEIk3nLbuR75CUNjbmxmaEKwn7gdBvpC9y5bvI SqmIHzzTNlrglnpm3JEL/xrTKNXoMBjKm7BJehIWiHJRH2jYl+wssyNRJd+4vgrrigGX kvjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Nt4C0mVR+ky0DpSB8k45/C39Em/flWndJ3l9xoOdKaA=; fh=JGIPdwR/ghosjNwmGX0PEjhcJN3y9idmuh+UBOLugoc=; b=HHzaFrpYSSxHHit90LbYDX6gH5E7lT8cxiWmIRYPI8zi0f0o6PtkWLKlSjCErNXlwM Tpg/mPAuRKFuG4/lSWIBhBIS73fGaGYduennYQV2SwtcMxU0cWXzc05uy13F5bmAC53A 3+CoaRM/FgJTQTgMCDK1CNcm4Fbv5Ap42J0NlH/Il3uUHVVbd3kx3WD2f/rBBzOmofy7 zQF6n4D/FNqAXZlh3gmL2BCQcD36fOsnoMyroMeuCfeh2yXisv9M42K3ahTgU9wrC/D3 KvG+/21JSQiyaADCipNlZ71cJlGvyyzbm/8Jt70bTIdHbb/goqd0SDYYzkwXUIfrgWGO Culw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZreTtSBs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Hence add support to register the same. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - Split the gcc_ddrss_ecpri_gsi_clk clock changes - Update the commit text Changes since v3: - None Changes since v2: - Split the patch as per the review comments - Newly added drivers/clk/qcom/gcc-qdu1000.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 6a6e0f55516a..97fd1947637a 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -2522,6 +2522,7 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, }; static const struct qcom_reset_map gcc_qdu1000_resets[] = { From patchwork Thu Aug 3 10:57:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 130554 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1118997vqx; Thu, 3 Aug 2023 05:40:30 -0700 (PDT) X-Google-Smtp-Source: APBJJlHNjiIbeBMARbqGT/G3wUtqBNwyQNFNus0KRMGYn4oVmLStMFV0MvQqaW5IbyOwg9VP+4iE X-Received: by 2002:a17:906:3119:b0:99b:d4a0:1329 with SMTP id 25-20020a170906311900b0099bd4a01329mr7101898ejx.38.1691066430083; Thu, 03 Aug 2023 05:40:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691066430; cv=none; d=google.com; s=arc-20160816; b=F8/t/mglMxC1AKrXONQPaQL/ItNi6qT4l/rGHaxmmfw9t/DdjoblXwtIuB/uY4EqWE KUFVTrXpUZpgqRx9ukzjI2jhuG6Evc8eif4rdXGUmCZUC+h1thOcl2oMH4KETX2vMkM5 hSr+j0nSIlUL4S50N5ZxXCs+k/XYKEXW1K7t6I5L2bpk0gLRXfGFjJXsLAZHc/gvuAPO PJMmbvTpWNHKYSRMM2UDm18CSwZVrEunyEUqeiJHUcXN+ndHxurtz+X6u65J3KQsOITs xu9A0NX9+1mLJiGkuj9vBsKH2PPbXV7RmFogDe+thNug1h9uZs3Wr670eCUo5tsoPcRY lmFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IvbjYkcQ4xO4GHSYw7uTvmpP+2Y7A3N1+mj5asrdtcg=; fh=JGIPdwR/ghosjNwmGX0PEjhcJN3y9idmuh+UBOLugoc=; b=gp3R5KYwTGtdg1y17IFavpBH0OvOZQ+2jcVnWWvM/dtKevZlZZeDLv9ZdgFwreESxn Qe9yBHxz7j9XzfYpyKwwPjI4FwnksoDEOhK/DRm0LmYjXo7DnOClylGEm6lPOr0aDKa6 b0OvUge7eqmlaqNF/iP/cbfi9nCoigpnSoAGaBQGSyzkObszeONUALdGkoxmbSekZIaa yA/FEkhVgPKtUjJOwzpW+CzGRV3DR0RPQyNY8lQ0qMRyEReUIb2RQ9R0445Pt/ni/h8t M0oOCKpfJ6dagBu2UErTOzzvC+xsY+0vt0SAPxeTvq1fr8AObw7oOcC7ceyLUFcZNZZV OdEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="CLA/IoNC"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - Split the patch - Newly added drivers/clk/qcom/gcc-qdu1000.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 97fd1947637a..5bf62f04cf12 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1132,6 +1132,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { }, }; +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { + .halt_reg = 0x54298, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x54298, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x54298, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ddrss_ecpri_gsi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_ecpri_ahb_clk = { .halt_reg = 0x3a008, .halt_check = BRANCH_HALT_VOTED, @@ -2523,6 +2543,7 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, }; static const struct qcom_reset_map gcc_qdu1000_resets[] = { From patchwork Thu Aug 3 10:57:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 130498 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1085294vqx; Thu, 3 Aug 2023 04:39:59 -0700 (PDT) X-Google-Smtp-Source: APBJJlEpC2rrHjDGYYu3yXmOn/wytPmLc8ra8vS4+gbxIY4Y0mTk8v2UubN86TpdHvtqQflXPJWt X-Received: by 2002:a05:6a00:2e8d:b0:667:d0ff:6a0f with SMTP id fd13-20020a056a002e8d00b00667d0ff6a0fmr23040046pfb.5.1691062799394; Thu, 03 Aug 2023 04:39:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691062799; cv=none; d=google.com; s=arc-20160816; b=b4djMS8fy0jRi/tGQ9e5HllaoTiFFSMGav1EEsT/1TmsEk6Bmfyu5/o2HDGwUJqX5+ m9bfbiqsCzBRxy8tFooITSoXtDPt0F54fmXF2eNSbwFV63l+EnEHXxR9V5jKDqn7OJyx uVKPpyNg/QR7LKKL6MIwY1i9HFUR02YOWKhaBL6h30bCxO4korxqN+6/uwFsYXhSh6Qy r5Gz30GzQFPqjRBG7/rcyI6agrBiM7Wlqpmux5MZEhS/THVAK/tbEaciS4kjNfp+1v6M FxecA6V1XfdXS2odntR+VBJSoxO115L9fJiVZXd/x7uN00S+VXH/ojr0qLjPGwwRcLne HTlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rvvOiRD45oZV5kvVyafqIbV/XjrZdeWz8n3OYhw6wU4=; fh=JGIPdwR/ghosjNwmGX0PEjhcJN3y9idmuh+UBOLugoc=; b=njxWa3NjNdc37oPdDk9ownfpz2frAjb1Rr+iibRXG428s65o9TpMhR1AEPN/MJf3um gTPrdl03sZIfNFuJRgjQ0GrM3ZkW3036X/WETaU77kKXtybpS5+0HYFxeob1EQ1VHRq/ AA2VYe1V3BPBU8PZWTb15q4GrnriDe76hdcKs4Myr526HynPmOzXgnqWh58AJ46RJbQx Ha5XDFr7YH0Lm++DxbVWHYZEiwjn0MNh9E1oeIWropSj968JMANY1JD6YmheWZHJsv8l DQIUSmXwzPRokJ3RbVstkQ+Bkmiy17YavYQB2YpavskSSHaLCUGAhGwKiGUzatCTrTnQ e1Fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=QxpmJSb4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - None Changes since v3: - None Changes since v2: - None Changes since v1: - Newly added drivers/clk/qcom/gcc-qdu1000.c | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 5bf62f04cf12..fe1d0e8946a7 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -18,6 +18,7 @@ #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" #include "clk-regmap-phy-mux.h" +#include "gdsc.h" #include "reset.h" enum { @@ -2410,6 +2411,39 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { }, }; +static struct gdsc pcie_0_gdsc = { + .gdscr = 0x9d004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_pcie_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_0_phy_gdsc = { + .gdscr = 0x7c004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gcc_pcie_0_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_prim_gdsc = { + .gdscr = 0x49004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_usb30_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, @@ -2546,6 +2580,12 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, }; +static struct gdsc *gcc_qdu1000_gdscs[] = { + [PCIE_0_GDSC] = &pcie_0_gdsc, + [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc, + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, +}; + static const struct qcom_reset_map gcc_qdu1000_resets[] = { [GCC_ECPRI_CC_BCR] = { 0x3e000 }, [GCC_ECPRI_SS_BCR] = { 0x3a000 }, @@ -2607,6 +2647,8 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = { .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), .resets = gcc_qdu1000_resets, .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), + .gdscs = gcc_qdu1000_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs), }; static const struct of_device_id gcc_qdu1000_match_table[] = { From patchwork Thu Aug 3 10:57:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 130552 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1117951vqx; Thu, 3 Aug 2023 05:38:08 -0700 (PDT) X-Google-Smtp-Source: APBJJlEvqKxNwHLezBoHKA3hFkeqoPbied8/Xd2JuaVmkWOSepsP92RbHYVwBGeqnmv6nbtcEecP X-Received: by 2002:a17:90a:6be6:b0:268:36a2:bd0 with SMTP id w93-20020a17090a6be600b0026836a20bd0mr16216881pjj.8.1691066287582; Thu, 03 Aug 2023 05:38:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691066287; cv=none; d=google.com; s=arc-20160816; b=BRngUSMCBzzp9gNxeyQuDXs3ULU29dgrs3LilW76Wi6FHYVVjdkPMwcJ2T6/Yhl59O hYCHQXjRvYaPtyDdvNYIgoIzBioEEDIJuZzv7ikJG/sNGm8Rjjc6hagbM2NmkQpnNO+M o9tDzLc9udfjdI+oBqDykn2ZpytWeBBokDNtoXPVHcbjDohH25P3ZiA6iekTAjRPC0k0 OL+RbLC0ENC99p8P6eZygJ/Jm2gYidjoxhL/alxXTb4lpXccRSUyAI8eb2X9rrPT2ntL 5SKOM95B5s8oaPfC/c6CfYQUXo15vMv0UxeNgCT5Eip/5lZ0vsSHzUJj3cB1K7HFq72R FtYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dKoLAN6T9eXidautHVrIhL8exaoziZw7nYxsqDqzca4=; fh=JGIPdwR/ghosjNwmGX0PEjhcJN3y9idmuh+UBOLugoc=; b=BVyJ336xvIJvkHHIdJW0TyWyJx1UvHXTEbLIp/LC1pHYzRomTdVXSGudQeg8Cyf//m KSvseJQv3x+cwp9SNLdIgBcAxzqGIMKsfSlASyZC7wsPP0kS9qTQcp7Cj6Ut4R9y9EFa z76IHHAcuhmqhgPF+1E/G6nx4vqb1aAX0PvBrKJkDzQ+fQevPg5WgbMC78Td6ZwjRGV5 QDviURjv6RJNeeH6KWSw2zp71qfmyz2felLcE3D9G3zq/GIc76k0P3ggG8eccC1ncNtL ya0ckZ2x4Me9nKYuIoQcdZw7d5ZzZ63fsm4N1UBgolkh45KpquAvqKcUEYIwyJDw3OX1 r7Og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=LCzbRr9a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - Updated the commit text Changes since v3: - Split the patch as per the review comments - Newly added drivers/clk/qcom/gcc-qdu1000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index fe1d0e8946a7..82391918c93e 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -904,7 +904,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { .name = "gcc_sdcc5_apps_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; @@ -923,7 +923,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { .name = "gcc_sdcc5_ice_core_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; From patchwork Thu Aug 3 10:57:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 130574 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp1131730vqx; Thu, 3 Aug 2023 06:03:47 -0700 (PDT) X-Google-Smtp-Source: APBJJlHHpYtSfJH9LJysyULh24mMmAQV11w0HG9X1ucIMfoLnJA1W6eraEHJU2RrSWOLAgPalmRe X-Received: by 2002:a05:6a00:1f0f:b0:67a:72d5:3365 with SMTP id be15-20020a056a001f0f00b0067a72d53365mr20102336pfb.6.1691067827326; Thu, 03 Aug 2023 06:03:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691067827; cv=none; d=google.com; s=arc-20160816; b=GKtwNiz2j+rKL0W+xi4QkPhrfVbPioi1OK8ZmPYefOH9gHRh+rxohH0aOVQbXcI94H /d9E0qrQu4bYKa8dfT+UYPH/Yl/9WY/gVYFC14kxzUoOucvSHD/909cIZwifzItlqSei RL3FcMgIQ908QzLgAOOpmol/SygNhEMHl7BgMCsjMDAaWs2XJZJR9ct3bdMhOvINRZSN iC1iZjWMS8yLg0ghuXeud0KB8Hh7/wL1XTxN+19NT/54hVFnLxSAdcVA39d9aeuKlZqC f0DVXu/3kzCQ7DAnUCK3G91V6jYF6zpIZIH1ga2TgPvCUG0NLtfno3hqwcSxUClnisb+ VoAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LgQ4C3GUdSQw7QoTxJ2cWTWy1NEDZ8kFpk5lJD7dTok=; fh=JGIPdwR/ghosjNwmGX0PEjhcJN3y9idmuh+UBOLugoc=; b=Bv/sCSRvYUWEECw/zjSSEAtfr4R3MONVPlzbZwVTHBl+ZDCzJDA6deR2XjlrYOH5U+ R1jkKf9q+GgmXJkkKQUHHKcQll94I/lm5AEWaTfG4BgY+hndZ7S1WqeLa+rAXwLaCMNO YjnxohUsKUAfPp8JeoSi53ey9quj6D2TBcV7mcDq1dEYWZtzV7/v4zFTBdlkIwJMpABf ML7qktqmTq0vgzPZerrxVzqLY7JBmoA/kEScKrNcZXNpMwSWX+dcxL96Qe2Nrie1xVSp Rdaq/2y23yNCZojxsEPm6nZMmAu1wc9v+T3IfgsHXTRE5TtlzFgAgqkEnMBCs925RrSp BTjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=OjrbiKeE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Hence update the clock RCG ops to clk_rcg2_shared_ops. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - Updated the commit text Changes since v3: - Split the patch as per the review comments - Newly added drivers/clk/qcom/gcc-qdu1000.c | 58 +++++++++++++++++----------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 82391918c93e..9f42d2601464 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -476,7 +476,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = { .name = "gcc_aggre_noc_ecpri_dma_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -496,7 +496,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = { .name = "gcc_aggre_noc_ecpri_gsi_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -515,7 +515,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -529,7 +529,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -543,7 +543,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -562,7 +562,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .name = "gcc_pcie_0_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -582,7 +582,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { .name = "gcc_pcie_0_phy_rchng_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -601,7 +601,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -623,7 +623,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { @@ -639,7 +639,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { @@ -655,7 +655,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { @@ -671,7 +671,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { @@ -687,7 +687,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { @@ -708,7 +708,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { @@ -724,7 +724,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { .name = "gcc_qupv3_wrap0_s6_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { @@ -740,7 +740,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { .name = "gcc_qupv3_wrap0_s7_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { @@ -756,7 +756,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { .name = "gcc_qupv3_wrap1_s0_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { @@ -772,7 +772,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { .name = "gcc_qupv3_wrap1_s1_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { @@ -788,7 +788,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { .name = "gcc_qupv3_wrap1_s2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { @@ -804,7 +804,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { .name = "gcc_qupv3_wrap1_s3_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { @@ -820,7 +820,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { .name = "gcc_qupv3_wrap1_s4_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { @@ -836,7 +836,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { .name = "gcc_qupv3_wrap1_s5_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { @@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { .name = "gcc_qupv3_wrap1_s6_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { @@ -868,7 +868,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { .name = "gcc_qupv3_wrap1_s7_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { @@ -937,7 +937,7 @@ static struct clk_rcg2 gcc_sm_bus_xo_clk_src = { .name = "gcc_sm_bus_xo_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -956,7 +956,7 @@ static struct clk_rcg2 gcc_tsc_clk_src = { .name = "gcc_tsc_clk_src", .parent_data = gcc_parent_data_9, .num_parents = ARRAY_SIZE(gcc_parent_data_9), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -976,7 +976,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -990,7 +990,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1004,7 +1004,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, };