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A value of 2 simply cannot occur anymore. Instead extend the comment to mention the use of the attribute in "length_vex", clarifying why "prefix_extra" can actually be meaningful on VEX-encoded insns despite those not having any real prefixes except possibly segment overrides. gcc/ * config/i386/i386.md (prefix_extra): Correct comment. Fold cases yielding 2 into ones yielding 1. --- I question the 3DNow! aspect here: There's no extra prefix there. It's an immediate instead which "sub-divides" major opcode 0f0f. --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -620,13 +620,11 @@ (const_int 0))) ;; There are also additional prefixes in 3DNOW, SSSE3. -;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte, -;; sseiadd1,ssecvt1 to 0f7a with no DREX byte. ;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a. +;; While generally inapplicable to VEX/XOP/EVEX encodings, "length_vex" uses +;; the attribute evaluating to zero to know that VEX2 encoding may be usable. (define_attr "prefix_extra" "" - (cond [(eq_attr "type" "ssemuladd,sse4arg") - (const_int 2) - (eq_attr "type" "sseiadd1,ssecvt1") + (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1") (const_int 1) ] (const_int 0))) From patchwork Thu Aug 3 08:10:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 130377 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp988019vqx; Thu, 3 Aug 2023 01:11:23 -0700 (PDT) X-Google-Smtp-Source: APBJJlElvxQnoEkFVlOfQ+soMwNx+j/Pn7o6a2L5kSISl1QbPV+c4bR2hMCHDNcLwDtlG/2yuIZk X-Received: by 2002:a17:906:3f54:b0:99b:d6f5:afee with SMTP id f20-20020a1709063f5400b0099bd6f5afeemr7153266ejj.23.1691050282918; Thu, 03 Aug 2023 01:11:22 -0700 (PDT) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. 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The drop now (or already previously) redundant explicit attributes, adding "mode" ones where they were missing. Furthermore use "sse4arg" consistently for all VPCOM* insns; so far signed comparisons did use it, while unsigned ones used "ssecmp". Note that while they have (not counting the explicit or implicit immediate operand) they really only have 3 operands, the operator is also counted in those patterns. That's relevant for establishing the "memory" attribute's value, and at the same time benign when there are only register operands. Note that despite also having 4 operands, multiply-add insns aren't affected by this change, as they use "ssemuladd" for "type". gcc/ * config/i386/i386.md (length_immediate): Handle "sse4arg". (prefix): Likewise. (*xop_pcmov_): Add "mode" attribute. * config/i386/mmx.md (*xop_maskcmp3): Drop "prefix_data16", "prefix_rep", "prefix_extra", and "length_immediate" attributes. (*xop_maskcmp_uns3): Likewise. Switch "type" to "sse4arg". (*xop_pcmov_): Add "mode" attribute. * config/i386/sse.md (xop_pcmov_): Add "mode" attribute. (xop_maskcmp3): Drop "prefix_data16", "prefix_rep", "prefix_extra", and "length_immediate" attributes. (xop_maskcmp_uns3): Likewise. Switch "type" to "sse4arg". (xop_maskcmp_uns23): Drop "prefix_data16", "prefix_extra", and "length_immediate" attributes. Switch "type" to "sse4arg". (xop_pcom_tf3): Likewise. (xop_vpermil23): Drop "length_immediate" attribute. --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -536,6 +536,8 @@ (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave, bitmanip,imulx,msklog,mskmov") (const_int 0) + (eq_attr "type" "sse4arg") + (const_int 1) (eq_attr "unit" "i387,sse,mmx") (const_int 0) (eq_attr "type" "alu,alu1,negnot,imovx,ishift,ishiftx,ishift1, @@ -635,6 +637,8 @@ (const_string "vex") (eq_attr "mode" "XI,V16SF,V8DF") (const_string "evex") + (eq_attr "type" "sse4arg") + (const_string "vex") ] (const_string "orig"))) @@ -23286,7 +23290,8 @@ (match_operand:MODEF 3 "register_operand" "x")))] "TARGET_XOP" "vpcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}" - [(set_attr "type" "sse4arg")]) + [(set_attr "type" "sse4arg") + (set_attr "mode" "TI")]) ;; These versions of the min/max patterns are intentionally ignorant of ;; their behavior wrt -0.0 and NaN (via the commutative operand mark). --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -2909,10 +2909,6 @@ "TARGET_XOP" "vpcom%Y1\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "sse4arg") - (set_attr "prefix_data16" "0") - (set_attr "prefix_rep" "0") - (set_attr "prefix_extra" "2") - (set_attr "length_immediate" "1") (set_attr "mode" "TI")]) (define_insn "*xop_maskcmp3" @@ -2923,10 +2919,6 @@ "TARGET_XOP" "vpcom%Y1\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "sse4arg") - (set_attr "prefix_data16" "0") - (set_attr "prefix_rep" "0") - (set_attr "prefix_extra" "2") - (set_attr "length_immediate" "1") (set_attr "mode" "TI")]) (define_insn "*xop_maskcmp_uns3" @@ -2936,11 +2928,7 @@ (match_operand:MMXMODEI 3 "register_operand" "x")]))] "TARGET_XOP" "vpcom%Y1u\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssecmp") - (set_attr "prefix_data16" "0") - (set_attr "prefix_rep" "0") - (set_attr "prefix_extra" "2") - (set_attr "length_immediate" "1") + [(set_attr "type" "sse4arg") (set_attr "mode" "TI")]) (define_insn "*xop_maskcmp_uns3" @@ -2950,11 +2938,7 @@ (match_operand:VI_16_32 3 "register_operand" "x")]))] "TARGET_XOP" "vpcom%Y1u\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssecmp") - (set_attr "prefix_data16" "0") - (set_attr "prefix_rep" "0") - (set_attr "prefix_extra" "2") - (set_attr "length_immediate" "1") + [(set_attr "type" "sse4arg") (set_attr "mode" "TI")]) (define_expand "vec_cmp" @@ -3144,7 +3128,8 @@ (match_operand:MMXMODE124 2 "register_operand" "x")))] "TARGET_XOP && TARGET_MMX_WITH_SSE" "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "sse4arg")]) + [(set_attr "type" "sse4arg") + (set_attr "mode" "TI")]) (define_insn "*xop_pcmov_" [(set (match_operand:VI_16_32 0 "register_operand" "=x") @@ -3154,7 +3139,8 @@ (match_operand:VI_16_32 2 "register_operand" "x")))] "TARGET_XOP" "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "sse4arg")]) + [(set_attr "type" "sse4arg") + (set_attr "mode" "TI")]) ;; XOP permute instructions (define_insn "mmx_ppermv64" --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -24821,7 +24821,8 @@ (match_operand:V_128_256 2 "nonimmediate_operand" "xm,x")))] "TARGET_XOP" "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "sse4arg")]) + [(set_attr "type" "sse4arg") + (set_attr "mode" "")]) ;; Recognize XOP's vpcmov from canonical (xor (and (xor t f) c) f) (define_split @@ -25739,10 +25740,6 @@ "TARGET_XOP" "vpcom%Y1\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "sse4arg") - (set_attr "prefix_data16" "0") - (set_attr "prefix_rep" "0") - (set_attr "prefix_extra" "2") - (set_attr "length_immediate" "1") (set_attr "mode" "TI")]) (define_insn "xop_maskcmp_uns3" @@ -25752,11 +25749,7 @@ (match_operand:VI_128 3 "nonimmediate_operand" "xm")]))] "TARGET_XOP" "vpcom%Y1u\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssecmp") - (set_attr "prefix_data16" "0") - (set_attr "prefix_rep" "0") - (set_attr "prefix_extra" "2") - (set_attr "length_immediate" "1") + [(set_attr "type" "sse4arg") (set_attr "mode" "TI")]) ;; Version of pcom*u* that is called from the intrinsics that allows pcomequ* @@ -25771,10 +25764,7 @@ UNSPEC_XOP_UNSIGNED_CMP))] "TARGET_XOP" "vpcom%Y1u\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssecmp") - (set_attr "prefix_data16" "0") - (set_attr "prefix_extra" "2") - (set_attr "length_immediate" "1") + [(set_attr "type" "sse4arg") (set_attr "mode" "TI")]) ;; Pcomtrue and pcomfalse support. These are useless instructions, but are @@ -25792,10 +25782,7 @@ ? "vpcomtrue\t{%2, %1, %0|%0, %1, %2}" : "vpcomfalse\t{%2, %1, %0|%0, %1, %2}"); } - [(set_attr "type" "ssecmp") - (set_attr "prefix_data16" "0") - (set_attr "prefix_extra" "2") - (set_attr "length_immediate" "1") + [(set_attr "type" "sse4arg") (set_attr "mode" "TI")]) (define_insn "xop_vpermil23" @@ -25809,7 +25796,6 @@ "TARGET_XOP" "vpermil2\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}" [(set_attr "type" "sse4arg") - (set_attr "length_immediate" "1") (set_attr "mode" "")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; From patchwork Thu Aug 3 08:10:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 130380 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp988590vqx; Thu, 3 Aug 2023 01:12:37 -0700 (PDT) X-Google-Smtp-Source: APBJJlH2rUw2cLVQ3YAcpQX5uywiohpUMa1sssaPzuMu/rREKA97A9UrkKuFbMQ2SEh/6wCKGfEJ X-Received: by 2002:a17:906:7397:b0:99b:ef8a:d64a with SMTP id f23-20020a170906739700b0099bef8ad64amr7796043ejl.0.1691050357363; Thu, 03 Aug 2023 01:12:37 -0700 (PDT) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. 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Express that in the default calculation of "prefix". FMA4 insns also all have a 1-byte immediate operand. Where the default calculation is not sufficient / applicable, add explicit "prefix" attributes. While there also add a "mode" attribute to fma___pair. gcc/ * config/i386/i386.md (isa): Move up. (length_immediate): Handle "fma4". (prefix): Handle "ssemuladd". * config/i386/sse.md (*fma_fmadd_): Add "prefix" attribute. (fma_fmadd_): Likewise. (_fmadd__mask): Likewise. (_fmadd__mask3): Likewise. (fma_fmsub_): Likewise. (_fmsub__mask): Likewise. (_fmsub__mask3): Likewise. (*fma_fnmadd_): Likewise. (fma_fnmadd_): Likewise. (_fnmadd__mask): Likewise. (_fnmadd__mask3): Likewise. (fma_fnmsub_): Likewise. (_fnmsub__mask): Likewise. (_fnmsub__mask3): Likewise. (fma_fmaddsub_): Likewise. (_fmaddsub__mask): Likewise. (_fmaddsub__mask3): Likewise. (fma_fmsubadd_): Likewise. (_fmsubadd__mask): Likewise. (_fmsubadd__mask3): Likewise. (*fmai_fmadd_): Likewise. (*fmai_fmsub_): Likewise. (*fmai_fnmadd_): Likewise. (*fmai_fnmsub_): Likewise. (avx512f_vmfmadd__mask): Likewise. (avx512f_vmfmadd__mask3): Likewise. (avx512f_vmfmadd__maskz_1): Likewise. (*avx512f_vmfmsub__mask): Likewise. (avx512f_vmfmsub__mask3): Likewise. (*avx512f_vmfmsub__maskz_1): Likewise. (avx512f_vmfnmadd__mask): Likewise. (avx512f_vmfnmadd__mask3): Likewise. (avx512f_vmfnmadd__maskz_1): Likewise. (*avx512f_vmfnmsub__mask): Likewise. (*avx512f_vmfnmsub__mask3): Likewise. (*avx512f_vmfnmsub__maskz_1): Likewise. (*fma4i_vmfmadd_): Likewise. (*fma4i_vmfmsub_): Likewise. (*fma4i_vmfnmadd_): Likewise. (*fma4i_vmfnmsub_): Likewise. (fma__): Likewise. (___mask): Likewise. (avx512fp16_fma_sh_v8hf): Likewise. (avx512fp16_sh_v8hf_mask): Likewise. (xop_p): Likewise. (xop_pdql): Likewise. (xop_pdqh): Likewise. (xop_pwd): Likewise. (xop_pwd): Likewise. (fma___pair): Likewise. Add "mode" attribute. --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -531,12 +531,23 @@ (const_string "unknown")] (const_string "integer"))) +;; Used to control the "enabled" attribute on a per-instruction basis. +(define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx, + x64_avx,x64_avx512bw,x64_avx512dq,aes, + sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx, + avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, + avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl, + avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16,avxifma, + avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl" + (const_string "base")) + ;; The (bounding maximum) length of an instruction immediate. (define_attr "length_immediate" "" (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave, bitmanip,imulx,msklog,mskmov") (const_int 0) - (eq_attr "type" "sse4arg") + (ior (eq_attr "type" "sse4arg") + (eq_attr "isa" "fma4")) (const_int 1) (eq_attr "unit" "i387,sse,mmx") (const_int 0) @@ -637,6 +648,10 @@ (const_string "vex") (eq_attr "mode" "XI,V16SF,V8DF") (const_string "evex") + (eq_attr "type" "ssemuladd") + (if_then_else (eq_attr "isa" "fma4") + (const_string "vex") + (const_string "maybe_evex")) (eq_attr "type" "sse4arg") (const_string "vex") ] @@ -842,16 +857,6 @@ ;; Define attribute to indicate unaligned ssemov insns (define_attr "movu" "0,1" (const_string "0")) -;; Used to control the "enabled" attribute on a per-instruction basis. -(define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx, - x64_avx,x64_avx512bw,x64_avx512dq,aes, - sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx, - avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, - avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl, - avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16,avxifma, - avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl" - (const_string "base")) - ;; Define instruction set of MMX instructions (define_attr "mmx_isa" "base,native,sse,sse_noavx,avx" (const_string "base")) --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -5422,6 +5422,7 @@ vfmadd213\t{%3, %2, %0|%0, %2, %3} vfmadd231\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_expand "cond_fma" @@ -5461,6 +5462,7 @@ vfmadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} vfmadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "_fmadd__mask3" @@ -5475,6 +5477,7 @@ "TARGET_AVX512F" "vfmadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "*fma_fmsub_" @@ -5522,6 +5525,7 @@ vfmsub213\t{%3, %2, %0|%0, %2, %3} vfmsub231\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_expand "cond_fms" @@ -5563,6 +5567,7 @@ vfmsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} vfmsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "_fmsub__mask3" @@ -5578,6 +5583,7 @@ "TARGET_AVX512F && " "vfmsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "*fma_fnmadd_" @@ -5625,6 +5631,7 @@ vfnmadd213\t{%3, %2, %0|%0, %2, %3} vfnmadd231\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_expand "cond_fnma" @@ -5666,6 +5673,7 @@ vfnmadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} vfnmadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "_fnmadd__mask3" @@ -5681,6 +5689,7 @@ "TARGET_AVX512F && " "vfnmadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "*fma_fnmsub_" @@ -5730,6 +5739,7 @@ vfnmsub213\t{%3, %2, %0|%0, %2, %3} vfnmsub231\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_expand "cond_fnms" @@ -5773,6 +5783,7 @@ vfnmsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} vfnmsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "_fnmsub__mask3" @@ -5789,6 +5800,7 @@ "TARGET_AVX512F" "vfnmsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) ;; FMA parallel floating point multiply addsub and subadd operations. @@ -5889,6 +5901,7 @@ vfmaddsub213\t{%3, %2, %0|%0, %2, %3} vfmaddsub231\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "_fmaddsub__mask" @@ -5906,6 +5919,7 @@ vfmaddsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} vfmaddsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "_fmaddsub__mask3" @@ -5921,6 +5935,7 @@ "TARGET_AVX512F" "vfmaddsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "*fma_fmsubadd_" @@ -5956,6 +5971,7 @@ vfmsubadd213\t{%3, %2, %0|%0, %2, %3} vfmsubadd231\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "_fmsubadd__mask" @@ -5974,6 +5990,7 @@ vfmsubadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} vfmsubadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "_fmsubadd__mask3" @@ -5990,6 +6007,7 @@ "TARGET_AVX512F" "vfmsubadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) ;; FMA3 floating point scalar intrinsics. These merge result with @@ -6057,6 +6075,7 @@ vfmadd132\t{%2, %3, %0|%0, %3, %2} vfmadd213\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "")]) (define_insn "*fmai_fmsub_" @@ -6074,6 +6093,7 @@ vfmsub132\t{%2, %3, %0|%0, %3, %2} vfmsub213\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "")]) (define_insn "*fmai_fnmadd_" @@ -6091,6 +6111,7 @@ vfnmadd132\t{%2, %3, %0|%0, %3, %2} vfnmadd213\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "")]) (define_insn "*fmai_fnmsub_" @@ -6109,6 +6130,7 @@ vfnmsub132\t{%2, %3, %0|%0, %3, %2} vfnmsub213\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "")]) (define_insn "avx512f_vmfmadd__mask" @@ -6128,6 +6150,7 @@ vfmadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} vfmadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "avx512f_vmfmadd__mask3" @@ -6145,6 +6168,7 @@ "TARGET_AVX512F" "vfmadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %3, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_expand "avx512f_vmfmadd__maskz" @@ -6178,6 +6202,7 @@ vfmadd132\t{%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %3, %2} vfmadd213\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "*avx512f_vmfmsub__mask" @@ -6198,6 +6223,7 @@ vfmsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} vfmsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "avx512f_vmfmsub__mask3" @@ -6216,6 +6242,7 @@ "TARGET_AVX512F" "vfmsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %3, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "*avx512f_vmfmsub__maskz_1" @@ -6236,6 +6263,7 @@ vfmsub132\t{%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %3, %2} vfmsub213\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "avx512f_vmfnmadd__mask" @@ -6256,6 +6284,7 @@ vfnmadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} vfnmadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "avx512f_vmfnmadd__mask3" @@ -6274,6 +6303,7 @@ "TARGET_AVX512F" "vfnmadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %3, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_expand "avx512f_vmfnmadd__maskz" @@ -6308,6 +6338,7 @@ vfnmadd132\t{%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %3, %2} vfnmadd213\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "*avx512f_vmfnmsub__mask" @@ -6329,6 +6360,7 @@ vfnmsub132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} vfnmsub213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "*avx512f_vmfnmsub__mask3" @@ -6348,6 +6380,7 @@ "TARGET_AVX512F" "vfnmsub231\t{%2, %1, %0%{%4%}|%0%{%4%}, %3, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "*avx512f_vmfnmsub__maskz_1" @@ -6369,6 +6402,7 @@ vfnmsub132\t{%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %3, %2} vfnmsub213\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) ;; FMA4 floating point scalar intrinsics. These write the @@ -6398,6 +6432,7 @@ "TARGET_FMA4" "vfmadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "vex") (set_attr "mode" "")]) (define_insn "*fma4i_vmfmsub_" @@ -6413,6 +6448,7 @@ "TARGET_FMA4" "vfmsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "vex") (set_attr "mode" "")]) (define_insn "*fma4i_vmfnmadd_" @@ -6428,6 +6464,7 @@ "TARGET_FMA4" "vfnmadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "vex") (set_attr "mode" "")]) (define_insn "*fma4i_vmfnmsub_" @@ -6444,6 +6481,7 @@ "TARGET_FMA4" "vfnmsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "vex") (set_attr "mode" "")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -6591,6 +6629,7 @@ "TARGET_AVX512FP16 && && " "v\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn_and_split "fma__fadd_fmul" @@ -6654,7 +6693,9 @@ UNSPEC_COMPLEX_F_C_MA_PAIR))] "TARGET_AVX512FP16" "vph\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "ssemuladd")]) + [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) (define_insn_and_split "fma__fmaddc_bcst" [(set (match_operand:VF_AVX512FP16VL 0 "register_operand") @@ -6726,6 +6767,7 @@ "TARGET_AVX512FP16 && " "v\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_expand "cmul3" @@ -6913,6 +6955,7 @@ "TARGET_AVX512FP16" "vsh\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "V8HF")]) (define_insn "avx512fp16_sh_v8hf_mask" @@ -6932,6 +6975,7 @@ "TARGET_AVX512FP16" "vsh\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") (set_attr "mode" "V8HF")]) (define_insn "avx512fp16_sh_v8hf" @@ -24721,6 +24765,7 @@ "TARGET_XOP" "vp\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "vex") (set_attr "mode" "TI")]) (define_insn "xop_pdql" @@ -24739,6 +24784,7 @@ "TARGET_XOP" "vpdql\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "vex") (set_attr "mode" "TI")]) (define_insn "xop_pdqh" @@ -24757,6 +24803,7 @@ "TARGET_XOP" "vpdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "vex") (set_attr "mode" "TI")]) ;; XOP parallel integer multiply/add instructions for the intrinisics @@ -24778,6 +24825,7 @@ "TARGET_XOP" "vpwd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "vex") (set_attr "mode" "TI")]) (define_insn "xop_pwd" @@ -24810,6 +24858,7 @@ "TARGET_XOP" "vpwd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") + (set_attr "prefix" "vex") (set_attr "mode" "TI")]) ;; XOP parallel XMM conditional moves From patchwork Thu Aug 3 08:11:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 130379 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp988570vqx; Thu, 3 Aug 2023 01:12:35 -0700 (PDT) X-Google-Smtp-Source: APBJJlHU/nNS4c65Ov2QscOTRf1jzO7ygaDf+mvFi5WtbmxGVLFs91RBZ1mNcy5gGCDkqN2tU8Ys X-Received: by 2002:a17:907:7618:b0:977:ecff:3367 with SMTP id jx24-20020a170907761800b00977ecff3367mr7500110ejc.40.1691050355541; Thu, 03 Aug 2023 01:12:35 -0700 (PDT) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. 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Drop "prefix_extra". (wrbase): Likewise. (ptwrite): Likewise. --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -25914,7 +25914,8 @@ "TARGET_64BIT && TARGET_FSGSBASE" "rdbase\t%0" [(set_attr "type" "other") - (set_attr "prefix_extra" "2")]) + (set_attr "prefix_0f" "1") + (set_attr "prefix_rep" "1")]) (define_insn "wrbase" [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")] @@ -25922,7 +25923,8 @@ "TARGET_64BIT && TARGET_FSGSBASE" "wrbase\t%0" [(set_attr "type" "other") - (set_attr "prefix_extra" "2")]) + (set_attr "prefix_0f" "1") + (set_attr "prefix_rep" "1")]) (define_insn "ptwrite" [(unspec_volatile [(match_operand:SWI48 0 "nonimmediate_operand" "rm")] @@ -25930,7 +25932,8 @@ "TARGET_PTWRITE" "ptwrite\t%0" [(set_attr "type" "other") - (set_attr "prefix_extra" "2")]) + (set_attr "prefix_0f" "1") + (set_attr "prefix_rep" "1")]) (define_insn "@rdrand" [(set (match_operand:SWI248 0 "register_operand" "=r") From patchwork Thu Aug 3 08:12:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 130386 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp989903vqx; Thu, 3 Aug 2023 01:15:38 -0700 (PDT) X-Google-Smtp-Source: APBJJlFT7WREC8P8N1mCEeiiUwcNQ5OmTnOmQCgl+zFD2J+eEod4v1bZzkKbOMX5L2ytAz+Y7rNP X-Received: by 2002:a17:906:8444:b0:993:e752:1a6f with SMTP id e4-20020a170906844400b00993e7521a6fmr6905949ejy.6.1691050537829; Thu, 03 Aug 2023 01:15:37 -0700 (PDT) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. 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For mmx_floatv2siv2sf2 1 is correct only for the first alternative. For the integer min/max cases 1 uniformly applies to legacy and VEX encodings (the UB and SW variants are dealt with separately anyway). Same for {,V}MOVNTDQA. Unlike {,V}PEXTRW, which has two encoding forms, {,V}PINSRW only has a single form in 0f space. (In *vec_extract note that the dropped part if the condition also referenced non-existing alternative 2.) Of the integer compare insns, only the 64-bit element forms are encoded in 0f38 space. gcc/ * config/i386/i386.md (@rdrand): Add "prefix_0f". Drop "prefix_extra". (@rdseed): Likewise. * config/i386/mmx.md (3 [smaxmin and umaxmin cases]): Adjust "prefix_extra". * config/i386/sse.md (@vec_set_0): Likewise. (*sse4_1_3): Likewise. (*avx2_eq3): Likewise. (avx2_gt3): Likewise. (_pinsr): Likewise. (*vec_extract): Likewise. (_movntdqa): Likewise. --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -25943,7 +25943,7 @@ "TARGET_RDRND" "rdrand\t%0" [(set_attr "type" "other") - (set_attr "prefix_extra" "1")]) + (set_attr "prefix_0f" "1")]) (define_insn "@rdseed" [(set (match_operand:SWI248 0 "register_operand" "=r") @@ -25953,7 +25953,7 @@ "TARGET_RDSEED" "rdseed\t%0" [(set_attr "type" "other") - (set_attr "prefix_extra" "1")]) + (set_attr "prefix_0f" "1")]) (define_expand "pause" [(set (match_dup 0) --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -2483,7 +2483,7 @@ vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1,1,*") + (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "TI")]) @@ -2532,7 +2532,7 @@ vpb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1,1,*") + (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "TI")]) @@ -2561,7 +2561,7 @@ vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1,1,*") + (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "TI")]) @@ -2623,7 +2623,7 @@ vpw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1,1,*") + (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "TI")]) --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -11064,7 +11064,7 @@ (const_string "1") (const_string "*"))) (set (attr "prefix_extra") - (if_then_else (eq_attr "alternative" "5,6,7,8,9") + (if_then_else (eq_attr "alternative" "5,6,9") (const_string "1") (const_string "*"))) (set (attr "length_immediate") @@ -16779,7 +16779,7 @@ vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1,1,*") + (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "TI")]) @@ -16813,7 +16813,10 @@ "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpcmpeq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecmp") - (set_attr "prefix_extra" "1") + (set (attr "prefix_extra") + (if_then_else (eq (const_string "mode") (const_string "V4DImode")) + (const_string "1") + (const_string "*"))) (set_attr "prefix" "vex") (set_attr "mode" "OI")]) @@ -17048,7 +17051,10 @@ "TARGET_AVX2" "vpcmpgt\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecmp") - (set_attr "prefix_extra" "1") + (set (attr "prefix_extra") + (if_then_else (eq (const_string "mode") (const_string "V4DImode")) + (const_string "1") + (const_string "*"))) (set_attr "prefix" "vex") (set_attr "mode" "OI")]) @@ -18843,7 +18849,7 @@ (const_string "*"))) (set (attr "prefix_extra") (if_then_else - (and (not (match_test "TARGET_AVX")) + (ior (eq_attr "prefix" "evex") (match_test "GET_MODE_NUNITS (mode) == 8")) (const_string "*") (const_string "1"))) @@ -20004,8 +20010,7 @@ (set_attr "prefix_data16" "1") (set (attr "prefix_extra") (if_then_else - (and (eq_attr "alternative" "0,2") - (eq (const_string "mode") (const_string "V8HImode"))) + (eq (const_string "mode") (const_string "V8HImode")) (const_string "*") (const_string "1"))) (set_attr "length_immediate" "1") @@ -22349,7 +22354,7 @@ "%vmovntdqa\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssemov") - (set_attr "prefix_extra" "1,1,*") + (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "")]) From patchwork Thu Aug 3 08:12:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 130389 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp990258vqx; Thu, 3 Aug 2023 01:16:21 -0700 (PDT) X-Google-Smtp-Source: APBJJlFF9HEJsW08oxsTWhiyPBNS2l54hK3e8dCFawM19ufQ5yR1TjXsEG1Mb5TUxnVMo3aLMS28 X-Received: by 2002:a17:907:a087:b0:993:d617:bdc2 with SMTP id hu7-20020a170907a08700b00993d617bdc2mr5973276ejc.75.1691050580893; Thu, 03 Aug 2023 01:16:20 -0700 (PDT) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. 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While there in avx512dq_broadcast_1 add the missing "length_immediate". gcc/ * config/i386/sse.md (*_eq3_1): Drop "prefix_extra". (avx512dq_vextract64x2_1_mask): Likewise. (*avx512dq_vextract64x2_1): Likewise. (avx512f_vextract32x4_1_mask): Likewise. (*avx512f_vextract32x4_1): Likewise. (vec_extract_lo__mask [AVX512 forms]): Likewise. (vec_extract_lo_ [AVX512 forms]): Likewise. (vec_extract_hi__mask [AVX512 forms]): Likewise. (vec_extract_hi_ [AVX512 forms]): Likewise. (@vec_extract_lo_ [AVX512 forms]): Likewise. (@vec_extract_hi_ [AVX512 forms]): Likewise. (vec_extract_lo_v64qi): Likewise. (vec_extract_hi_v64qi): Likewise. (*vec_widen_umult_even_v16si): Likewise. (*vec_widen_smult_even_v16si): Likewise. (*avx512f_3): Likewise. (*vec_extractv4ti): Likewise. (avx512bw_v32qiv32hi2): Likewise. (avx512dq_broadcast_1): Likewise. Add "length_immediate". --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4030,7 +4030,6 @@ vpcmpeq\t{%2, %1, %0|%0, %1, %2} vptestnm\t{%1, %1, %0|%0, %1, %1}" [(set_attr "type" "ssecmp") - (set_attr "prefix_extra" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -4128,7 +4127,6 @@ vpcmpeq\t{%2, %1, %0|%0, %1, %2} vptestnm\t{%1, %1, %0|%0, %1, %1}" [(set_attr "type" "ssecmp") - (set_attr "prefix_extra" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -11487,7 +11485,6 @@ return "vextract64x2\t{%2, %1, %0%{%5%}%N4|%0%{%5%}%N4, %1, %2}"; } [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -11506,7 +11503,6 @@ return "vextract64x2\t{%2, %1, %0|%0, %1, %2}"; } [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -11554,7 +11550,6 @@ return "vextract32x4\t{%2, %1, %0%{%7%}%N6|%0%{%7%}%N6, %1, %2}"; } [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -11577,7 +11572,6 @@ return "vextract32x4\t{%2, %1, %0|%0, %1, %2}"; } [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -11671,7 +11665,6 @@ && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))" "vextract64x4\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,store") (set_attr "prefix" "evex") @@ -11691,7 +11684,6 @@ return "#"; } [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,store,load") (set_attr "prefix" "evex") @@ -11710,7 +11702,6 @@ && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))" "vextract64x4\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -11724,7 +11715,6 @@ "TARGET_AVX512F" "vextract64x4\t{$0x1, %1, %0|%0, %1, 0x1}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -11744,7 +11734,6 @@ && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))" "vextract32x8\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -11762,7 +11751,6 @@ vextract32x8\t{$0x1, %1, %0|%0, %1, 0x1} vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "isa" "avx512dq,noavx512dq") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") @@ -11850,7 +11838,6 @@ && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))" "vextract32x8\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,store") (set_attr "prefix" "evex") @@ -11880,7 +11867,6 @@ return "#"; } [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,load,store") (set_attr "prefix" "evex") @@ -11923,7 +11909,6 @@ && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))" "vextract64x2\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,store") (set_attr "prefix" "evex") @@ -11961,7 +11946,6 @@ && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))" "vextract64x2\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -12013,7 +11997,6 @@ && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))" "vextract32x4\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -12102,7 +12085,6 @@ operands[1] = gen_lowpart (mode, operands[1]); } [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,load,store") (set_attr "prefix" "evex") @@ -12123,7 +12105,6 @@ "TARGET_AVX512F" "vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) @@ -12204,7 +12185,6 @@ operands[1] = gen_lowpart (V32QImode, operands[1]); } [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,load,store") (set_attr "prefix" "evex") @@ -12233,7 +12213,6 @@ "TARGET_AVX512F" "vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}" [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) @@ -15446,7 +15425,6 @@ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpmuludq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseimul") - (set_attr "prefix_extra" "1") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) @@ -15562,7 +15540,6 @@ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpmuldq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseimul") - (set_attr "prefix_extra" "1") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) @@ -16585,7 +16562,6 @@ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_evex") (set_attr "mode" "")]) @@ -20322,7 +20298,6 @@ "TARGET_AVX512F" "vextracti32x4\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) @@ -21893,7 +21868,6 @@ } [(set_attr "type" "sseishft") (set_attr "atom_unit" "sishuf") - (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -22666,7 +22640,6 @@ "TARGET_AVX512BW" "vpmovbw\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") - (set_attr "prefix_extra" "1") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) @@ -26796,7 +26769,7 @@ vshuf32x4\t{$0x44, %g1, %g1, %0|%0, %g1, %g1, 0x44} vbroadcast32x8\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") - (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1,*") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -26813,7 +26786,7 @@ vshuf64x2\t{$0x0, %1, %1, %0|%0, %1, %1, 0x0} vbroadcast64x2\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") - (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) From patchwork Thu Aug 3 08:12:49 2023 Content-Type: text/plain; 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Where missing, "mode" attributes are also added. (Note that "sse4arg" and "ssemuladd" ones don't need further adjustment in this regard.) gcc/ * config/i386/sse.md (xop_phaddbw): Add "prefix", "prefix_extra", and "mode" attributes. (xop_phaddbd): Likewise. (xop_phaddbq): Likewise. (xop_phaddwd): Likewise. (xop_phaddwq): Likewise. (xop_phadddq): Likewise. (xop_phsubbw): Likewise. (xop_phsubwd): Likewise. (xop_phsubdq): Likewise. (xop_rotl3): Add "prefix" and "prefix_extra" attributes. (xop_rotr3): Likewise. (xop_frcz2): Likewise. (*xop_vmfrcz2): Likewise. (xop_vrotl3): Add "prefix" attribute. Change "prefix_extra" to 1. (xop_sha3): Likewise. (xop_shl3): Likewise. --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -24897,7 +24897,10 @@ (const_int 13) (const_int 15)])))))] "TARGET_XOP" "vphaddbw\t{%1, %0|%0, %1}" - [(set_attr "type" "sseiadd1")]) + [(set_attr "type" "sseiadd1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") + (set_attr "mode" "TI")]) (define_insn "xop_phaddbd" [(set (match_operand:V4SI 0 "register_operand" "=x") @@ -24926,7 +24929,10 @@ (const_int 11) (const_int 15)]))))))] "TARGET_XOP" "vphaddbd\t{%1, %0|%0, %1}" - [(set_attr "type" "sseiadd1")]) + [(set_attr "type" "sseiadd1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") + (set_attr "mode" "TI")]) (define_insn "xop_phaddbq" [(set (match_operand:V2DI 0 "register_operand" "=x") @@ -24971,7 +24977,10 @@ (parallel [(const_int 7) (const_int 15)])))))))] "TARGET_XOP" "vphaddbq\t{%1, %0|%0, %1}" - [(set_attr "type" "sseiadd1")]) + [(set_attr "type" "sseiadd1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") + (set_attr "mode" "TI")]) (define_insn "xop_phaddwd" [(set (match_operand:V4SI 0 "register_operand" "=x") @@ -24988,7 +24997,10 @@ (const_int 5) (const_int 7)])))))] "TARGET_XOP" "vphaddwd\t{%1, %0|%0, %1}" - [(set_attr "type" "sseiadd1")]) + [(set_attr "type" "sseiadd1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") + (set_attr "mode" "TI")]) (define_insn "xop_phaddwq" [(set (match_operand:V2DI 0 "register_operand" "=x") @@ -25013,7 +25025,10 @@ (parallel [(const_int 3) (const_int 7)]))))))] "TARGET_XOP" "vphaddwq\t{%1, %0|%0, %1}" - [(set_attr "type" "sseiadd1")]) + [(set_attr "type" "sseiadd1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") + (set_attr "mode" "TI")]) (define_insn "xop_phadddq" [(set (match_operand:V2DI 0 "register_operand" "=x") @@ -25028,7 +25043,10 @@ (parallel [(const_int 1) (const_int 3)])))))] "TARGET_XOP" "vphadddq\t{%1, %0|%0, %1}" - [(set_attr "type" "sseiadd1")]) + [(set_attr "type" "sseiadd1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") + (set_attr "mode" "TI")]) (define_insn "xop_phsubbw" [(set (match_operand:V8HI 0 "register_operand" "=x") @@ -25049,7 +25067,10 @@ (const_int 13) (const_int 15)])))))] "TARGET_XOP" "vphsubbw\t{%1, %0|%0, %1}" - [(set_attr "type" "sseiadd1")]) + [(set_attr "type" "sseiadd1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") + (set_attr "mode" "TI")]) (define_insn "xop_phsubwd" [(set (match_operand:V4SI 0 "register_operand" "=x") @@ -25066,7 +25087,10 @@ (const_int 5) (const_int 7)])))))] "TARGET_XOP" "vphsubwd\t{%1, %0|%0, %1}" - [(set_attr "type" "sseiadd1")]) + [(set_attr "type" "sseiadd1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") + (set_attr "mode" "TI")]) (define_insn "xop_phsubdq" [(set (match_operand:V2DI 0 "register_operand" "=x") @@ -25081,7 +25105,10 @@ (parallel [(const_int 1) (const_int 3)])))))] "TARGET_XOP" "vphsubdq\t{%1, %0|%0, %1}" - [(set_attr "type" "sseiadd1")]) + [(set_attr "type" "sseiadd1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") + (set_attr "mode" "TI")]) ;; XOP permute instructions (define_insn "xop_pperm" @@ -25209,6 +25236,8 @@ "TARGET_XOP" "vprot\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseishft") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "mode" "TI")]) @@ -25224,6 +25253,8 @@ return \"vprot\t{%3, %1, %0|%0, %1, %3}\"; } [(set_attr "type" "sseishft") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "mode" "TI")]) @@ -25264,8 +25295,8 @@ "TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vprot\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseishft") - (set_attr "prefix_data16" "0") - (set_attr "prefix_extra" "2") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") (set_attr "mode" "TI")]) ;; XOP packed shift instructions. @@ -25501,8 +25532,8 @@ "TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpsha\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseishft") - (set_attr "prefix_data16" "0") - (set_attr "prefix_extra" "2") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") (set_attr "mode" "TI")]) (define_insn "xop_shl3" @@ -25520,8 +25551,8 @@ "TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpshl\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseishft") - (set_attr "prefix_data16" "0") - (set_attr "prefix_extra" "2") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") (set_attr "mode" "TI")]) (define_expand "3" @@ -25733,6 +25764,8 @@ "TARGET_XOP" "vfrcz\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") (set_attr "mode" "")]) (define_expand "xop_vmfrcz2" @@ -25757,6 +25790,8 @@ "TARGET_XOP" "vfrcz\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt1") + (set_attr "prefix" "vex") + (set_attr "prefix_extra" "1") (set_attr "mode" "")]) (define_insn "xop_maskcmp3" From patchwork Thu Aug 3 08:13:17 2023 Content-Type: text/plain; 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(avx512fp16_sh_v8hf): Likewise. --- Talking of "prefix": Shouldn't at least V32HF and V32BF have it also default to "evex"? (It won't matter right here, but it may matter elsewhere.) --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -6790,6 +6790,7 @@ return "v\t{%2, %1, %0|%0, %1, %2}"; } [(set_attr "type" "ssemul") + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_expand "avx512fp16_fmaddcsh_v8hf_maskz" @@ -6993,6 +6994,7 @@ return "vsh\t{%2, %1, %0|%0, %1, %2}"; } [(set_attr "type" "ssemul") + (set_attr "prefix" "evex") (set_attr "mode" "V8HF")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; From patchwork Thu Aug 3 08:13:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 130385 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp989886vqx; Thu, 3 Aug 2023 01:15:36 -0700 (PDT) X-Google-Smtp-Source: APBJJlE00mXqvgdw/t0/dHnF9ThxiNlUnADbUaYU+lfeOwaRNdXkHXUtrjM5WqEExzzEv9dkgugp X-Received: by 2002:a05:6512:ad3:b0:4fe:3a57:7c98 with SMTP id n19-20020a0565120ad300b004fe3a577c98mr7735231lfu.32.1691050535648; Thu, 03 Aug 2023 01:15:35 -0700 (PDT) Received: from server2.sourceware.org (server2.sourceware.org. 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The attribute was plain missing. Subsequent changes adding more alternatives then generously extended the bogus pattern. Apparently something similar happened to the two mmx_pblendvb_* insns. gcc/ * config/i386/i386.md (sse4_1_round2): Make "length_immediate" uniformly 1. * config/i386/mmx.md (mmx_pblendvb_v8qi): Likewise. (mmx_pblendvb_): Likewise. --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -21594,7 +21594,7 @@ vrndscale\t{%2, %1, %d0|%d0, %1, %2}" [(set_attr "type" "ssecvt") (set_attr "prefix_extra" "1,1,1,*,*") - (set_attr "length_immediate" "*,*,*,1,1") + (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,evex,evex") (set_attr "isa" "noavx512f,noavx512f,noavx512f,avx512f,avx512f") (set_attr "avx_partial_xmm_update" "false,false,true,false,true") --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -3094,7 +3094,7 @@ [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "*,*,1") + (set_attr "length_immediate" "1") (set_attr "prefix" "orig,orig,vex") (set_attr "btver2_decode" "vector") (set_attr "mode" "TI")]) @@ -3114,7 +3114,7 @@ [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "*,*,1") + (set_attr "length_immediate" "1") (set_attr "prefix" "orig,orig,vex") (set_attr "btver2_decode" "vector") (set_attr "mode" "TI")]) From patchwork Thu Aug 3 08:14:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 130398 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp990937vqx; Thu, 3 Aug 2023 01:17:58 -0700 (PDT) X-Google-Smtp-Source: APBJJlGovuJppmQWQjlqdktGRobIYK0UOtWpX24umeyRiUWEXbR734dxu78hNUwjW58v80tUJVFX X-Received: by 2002:a05:6512:2151:b0:4fe:1d5c:318d with SMTP id s17-20020a056512215100b004fe1d5c318dmr5951063lfr.3.1691050678119; Thu, 03 Aug 2023 01:17:58 -0700 (PDT) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. 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In *v8hi3 [smaxmin] and *v16qi3 [umaxmin] also drop the similarly stray "prefix_extra" at this occasion. These two max/min flavors are encoded in 0f space. gcc/ * config/i386/mmx.md (*mmx_pinsrd): Drop "prefix_data16". (*mmx_pinsrb): Likewise. (*mmx_pextrb): Likewise. (*mmx_pextrb_zext): Likewise. (mmx_pshufbv8qi3): Likewise. (mmx_pshufbv4qi3): Likewise. (mmx_pswapdv2si2): Likewise. (*pinsrb): Likewise. (*pextrb): Likewise. (*pextrb_zext): Likewise. * config/i386/sse.md (*sse4_1_mulv2siv2di3): Likewise. (*sse2_eq3): Likewise. (*sse2_gt3): Likewise. (_pinsr): Likewise. (*vec_extract): Likewise. (*vec_extract_zext): Likewise. (*vec_extractv16qi_zext): Likewise. (ssse3_phwv8hi3): Likewise. (ssse3_pmaddubsw128): Likewise. (*_pmulhrsw3): Likewise. (_pshufb3): Likewise. (_psign3): Likewise. (_palignr): Likewise. (*abs2): Likewise. (sse4_2_pcmpestr): Likewise. (sse4_2_pcmpestri): Likewise. (sse4_2_pcmpestrm): Likewise. (sse4_2_pcmpestr_cconly): Likewise. (sse4_2_pcmpistr): Likewise. (sse4_2_pcmpistri): Likewise. (sse4_2_pcmpistrm): Likewise. (sse4_2_pcmpistr_cconly): Likewise. (vgf2p8affineinvqb_): Likewise. (vgf2p8affineqb_): Likewise. (vgf2p8mulb_): Likewise. (*v8hi3 [smaxmin]): Drop "prefix_data16" and "prefix_extra". (*v16qi3 [umaxmin]): Likewise. --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -3863,7 +3863,6 @@ } } [(set_attr "isa" "noavx,avx") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "type" "sselog") (set_attr "length_immediate" "1") @@ -3950,7 +3949,6 @@ } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "orig,vex") @@ -4002,7 +4000,6 @@ %vpextrb\t{%2, %1, %k0|%k0, %1, %2} %vpextrb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog1") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -4017,7 +4014,6 @@ "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE" "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "sselog1") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -4035,7 +4031,6 @@ vpshufb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog1") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") (set_attr "btver2_decode" "vector") @@ -4053,7 +4048,6 @@ vpshufb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog1") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") (set_attr "btver2_decode" "vector") @@ -4191,7 +4185,6 @@ (set_attr "mmx_isa" "native,*") (set_attr "type" "mmxcvt,sselog1") (set_attr "prefix_extra" "1,*") - (set_attr "prefix_data16" "*,1") (set_attr "length_immediate" "*,1") (set_attr "mode" "DI,TI")]) @@ -4531,7 +4524,6 @@ } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "orig,vex") @@ -4575,7 +4567,6 @@ %vpextrb\t{%2, %1, %k0|%k0, %1, %2} %vpextrb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog1") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -4590,7 +4581,6 @@ "TARGET_SSE4_1" "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "sselog1") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15614,7 +15614,6 @@ vpmuldq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseimul") - (set_attr "prefix_data16" "1,1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "TI")]) @@ -16688,8 +16687,6 @@ vpw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") - (set_attr "prefix_data16" "1,*") - (set_attr "prefix_extra" "*,1") (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) @@ -16772,8 +16769,6 @@ vpb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") - (set_attr "prefix_data16" "1,*") - (set_attr "prefix_extra" "*,1") (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) @@ -17001,7 +16996,6 @@ vpcmpeq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "ssecmp") - (set_attr "prefix_data16" "1,*") (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) @@ -17063,7 +17057,6 @@ vpcmpgt\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "ssecmp") - (set_attr "prefix_data16" "1,*") (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) @@ -18819,12 +18812,6 @@ (match_test "GET_MODE_NUNITS (mode) == 2")) (const_string "1") (const_string "*"))) - (set (attr "prefix_data16") - (if_then_else - (and (not (match_test "TARGET_AVX")) - (match_test "GET_MODE_NUNITS (mode) == 8")) - (const_string "1") - (const_string "*"))) (set (attr "prefix_extra") (if_then_else (ior (eq_attr "prefix" "evex") @@ -19985,7 +19972,6 @@ %vpextr\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "*,sse4") (set_attr "type" "sselog1") - (set_attr "prefix_data16" "1") (set (attr "prefix_extra") (if_then_else (eq (const_string "mode") (const_string "V8HImode")) @@ -20006,7 +19992,6 @@ "TARGET_SSE2" "%vpextr\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "sselog1") - (set_attr "prefix_data16" "1") (set (attr "prefix_extra") (if_then_else (eq (const_string "mode") (const_string "V8HImode")) @@ -20026,7 +20011,6 @@ "TARGET_SSE4_1" "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "sselog1") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -21240,7 +21224,6 @@ [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") (set_attr "atom_unit" "complex") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) @@ -21511,7 +21494,6 @@ [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") (set_attr "atom_unit" "simul") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) @@ -21639,7 +21621,6 @@ vpmulhrsw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseimul") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")]) @@ -21763,7 +21744,6 @@ vpshufb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog1") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") (set_attr "btver2_decode" "vector") @@ -21830,7 +21810,6 @@ vpsign\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog1") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) @@ -21898,7 +21877,6 @@ [(set_attr "isa" "noavx,avx") (set_attr "type" "sseishft") (set_attr "atom_unit" "sishuf") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "orig,vex") @@ -21992,7 +21970,6 @@ "TARGET_SSSE3" "%vpabs\t{%1, %0|%0, %1}" [(set_attr "type" "sselog1") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) @@ -24244,7 +24221,6 @@ DONE; } [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,load") @@ -24270,7 +24246,6 @@ "TARGET_SSE4_2" "%vpcmpestri\t{%5, %3, %1|%1, %3, %5}" [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "length_immediate" "1") @@ -24298,7 +24273,6 @@ "TARGET_SSE4_2" "%vpcmpestrm\t{%5, %3, %1|%1, %3, %5}" [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -24324,7 +24298,6 @@ %vpcmpestri\t{%6, %4, %2|%2, %4, %6} %vpcmpestri\t{%6, %4, %2|%2, %4, %6}" [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,load,none,load") @@ -24379,7 +24352,6 @@ DONE; } [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,load") @@ -24401,7 +24373,6 @@ "TARGET_SSE4_2" "%vpcmpistri\t{%3, %2, %1|%1, %2, %3}" [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -24425,7 +24396,6 @@ "TARGET_SSE4_2" "%vpcmpistrm\t{%3, %2, %1|%1, %2, %3}" [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -24449,7 +24419,6 @@ %vpcmpistri\t{%4, %3, %2|%2, %3, %4} %vpcmpistri\t{%4, %3, %2|%2, %3, %4}" [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,load,none,load") @@ -29268,7 +29237,6 @@ gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3} vgf2p8affineinvqb\t{%3, %2, %1, %0| %0, %1, %2, %3}" [(set_attr "isa" "noavx,avx") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")]) @@ -29285,7 +29253,6 @@ gf2p8affineqb\t{%3, %2, %0| %0, %2, %3} vgf2p8affineqb\t{%3, %2, %1, %0| %0, %1, %2, %3}" [(set_attr "isa" "noavx,avx") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")]) @@ -29301,7 +29268,6 @@ gf2p8mulb\t{%2, %0| %0, %2} vgf2p8mulb\t{%2, %1, %0| %0, %1, %2}" [(set_attr "isa" "noavx,avx") - (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")])