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[8.43.85.97]) by mx.google.com with ESMTPS id u13-20020a1709064acd00b009892044ecb7si11116922ejt.496.2023.08.02.23.13.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 23:13:56 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=C0ADxbCl; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D9DC03857B8E for ; Thu, 3 Aug 2023 06:13:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D9DC03857B8E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691043226; bh=TIArCLKPVByb07G5qIBdBJgbLqIkS2FalNTkq5FtP0I=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=C0ADxbClkhrdZQqhrC5hTA46FwJNse5zNT+h3NWwZSafNJizffd8rrWa6oy/9XT3z hxjs1eeORaKCz6nqpZoVIdKfveRwI7tDIGJdSU6sqZB+RderVXeE+c4QtGwJLp/EQI zsltQj+SuANh56OTo0ujgY17OpVHEc5C7V0wb9aE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (unknown [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 12B673858D35 for ; Thu, 3 Aug 2023 06:13:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 12B673858D35 X-IronPort-AV: E=McAfee;i="6600,9927,10790"; a="368680223" X-IronPort-AV: E=Sophos;i="6.01,251,1684825200"; d="scan'208,217";a="368680223" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2023 23:12:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10790"; a="975952609" X-IronPort-AV: E=Sophos;i="6.01,251,1684825200"; d="scan'208,217";a="975952609" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga006.fm.intel.com with ESMTP; 02 Aug 2023 23:12:57 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 40F2210083C0; Thu, 3 Aug 2023 14:12:57 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFWMUL rounding mode intrinsic API Date: Thu, 3 Aug 2023 13:28:44 +0800 Message-Id: <20230803052844.1178854-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773187352679253709 X-GMAIL-MSGID: 1773187352679253709 From: Pan Li This patch would like to support the rounding mode API for the VFWMUL for the below samples. * __riscv_vfwmul_vv_f64m2_rm * __riscv_vfwmul_vv_f64m2_rm_m * __riscv_vfwmul_vf_f64m2_rm * __riscv_vfwmul_vf_f64m2_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (vfwmul_frm_obj): New declaration. (vfwmul_frm): Ditto. * config/riscv/riscv-vector-builtins-bases.h: (vfwmul_frm): Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfwmul_frm): New function definition. * config/riscv/vector.md: (frm_mode) Add vfwmul to frm_mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-widening-mul.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li > --- .../riscv/riscv-vector-builtins-bases.cc | 3 ++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + gcc/config/riscv/vector.md | 2 +- .../riscv/rvv/base/float-point-widening-mul.c | 44 +++++++++++++++++++ 5 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 95ec9ccb481..8d689f0c935 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -321,6 +321,7 @@ public: /* Implements below instructions for frm - vfwadd - vfwsub + - vfwmul */ template class widen_binop_frm : public function_base @@ -2112,6 +2113,7 @@ static CONSTEXPR const binop_frm
vfdiv_frm_obj; static CONSTEXPR const reverse_binop
vfrdiv_obj; static CONSTEXPR const reverse_binop_frm
vfrdiv_frm_obj; static CONSTEXPR const widen_binop vfwmul_obj; +static CONSTEXPR const widen_binop_frm vfwmul_frm_obj; static CONSTEXPR const vfmacc vfmacc_obj; static CONSTEXPR const vfnmsac vfnmsac_obj; static CONSTEXPR const vfmadd vfmadd_obj; @@ -2346,6 +2348,7 @@ BASE (vfdiv_frm) BASE (vfrdiv) BASE (vfrdiv_frm) BASE (vfwmul) +BASE (vfwmul_frm) BASE (vfmacc) BASE (vfnmsac) BASE (vfmadd) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index f35fd3d27cf..2d2b52a312c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -158,6 +158,7 @@ extern const function_base *const vfdiv_frm; extern const function_base *const vfrdiv; extern const function_base *const vfrdiv_frm; extern const function_base *const vfwmul; +extern const function_base *const vfwmul_frm; extern const function_base *const vfmacc; extern const function_base *const vfnmsac; extern const function_base *const vfmadd; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index e7e6c7d8ed8..d43b33ded17 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -328,6 +328,8 @@ DEF_RVV_FUNCTION (vfrdiv_frm, alu_frm, full_preds, f_vvf_ops) // 13.5. Vector Widening Floating-Point Multiply DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops) DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvf_ops) +DEF_RVV_FUNCTION (vfwmul_frm, alu_frm, full_preds, f_wvv_ops) +DEF_RVV_FUNCTION (vfwmul_frm, alu_frm, full_preds, f_wvf_ops) // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions DEF_RVV_FUNCTION (vfmacc, alu, full_preds, f_vvvv_ops) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 4b6c3859947..750b2de8df9 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -866,7 +866,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" - (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv") + (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul") (cond [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") (const_string "rne") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c new file mode 100644 index 00000000000..893fa866a31 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat64m2_t +test_vfwmul_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwmul_vv_f64m2_rm (op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwmul_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwmul_vv_f64m2_rm_m (mask, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwmul_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfwmul_vf_f64m2_rm (op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwmul_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfwmul_vf_f64m2_rm_m (mask, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwmul_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwmul_vv_f64m2 (op1, op2, vl); +} + +vfloat64m2_t +test_vfwmul_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwmul_vv_f64m2_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwmul\.[vw][vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */