From patchwork Thu Aug 3 02:32:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 130259 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp863857vqx; Wed, 2 Aug 2023 19:33:02 -0700 (PDT) X-Google-Smtp-Source: APBJJlGFsTtFhSdpoY36N3TiRzs/BmD/dd6OPM5TU+TlZdEG6hP0+144E+2ny2mxoa6z4DoYNt/2 X-Received: by 2002:a17:907:9686:b0:98d:ebb7:a8b0 with SMTP id hd6-20020a170907968600b0098debb7a8b0mr9582575ejc.14.1691029982696; Wed, 02 Aug 2023 19:33:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691029982; cv=none; d=google.com; s=arc-20160816; b=pQToiPM/BAoeXWgPgwqvY9z7Xr6HALf9SGfqfjdDGNoX7nqkPcRALp1AfMTy79MrYe C0UW4e1QKs1s5x8NE3xMAcINXj/Hp/GISw8WahDLfqpdY7CH+J3OgTkL3i/EPTD1YYPB l2HLy81ybjQUryHIzUQppMdZyG70qCRwU5HsZWF/Bsex/7SqRV+dUkxu1smrM+yh7tTw leHTLQI1oLFdW2hPJc73DGI4mWVkO4OXHo+liAo6D70VavFkbLKfMGW3KVzqgSnaY12p FQKqqzzvYXPCphtlOTJkcxXOeemAhz4HLGynzsK7vq1A5+uCiK0hVGdItn0zZZVNrn/q WU6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=biQu6BSWuBLfu/9+X27So0M5xeTKo3YAa786VoPN2Jc=; fh=/JJEj+I5j40/Spkll6HT+Gte92Mjc5mpTnWowlKfaJ8=; b=gPSEMzaD6VjVqOp+qkZgIpweM083i2ebRrJQY6+3owLFJ1GC1U3GLvp1JcR8HOtCi4 +TglFO6u4Ug7ii0cvZwy8pOxO1nJQri/CaeiCQBzFdy5uiF01cPw5aoDxRks7aY5oWHd Smrp3N28PUtgDtw1SAyMMdcG6gPhbCHEX3FFr9S6Y/61bpeXwzYvn2rNwd7MqYPwvR4M wvDSYrighZPVA8hgBsY/YQuCtymXk7GQICTtirOns+nw82zMV4q5veFodwEcTGW2vKmM Oc50Hu6iAYvD7EKQ3gdE1kbU3SucluYwMLIy2FBfRZaw+BlktrWzmnGAuS8jPpQMddX5 gJKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=o5NqFgQI; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id w25-20020a056402071900b0052237839228si10951010edx.562.2023.08.02.19.33.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 19:33:02 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=o5NqFgQI; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 829D63858C2A for ; Thu, 3 Aug 2023 02:33:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 829D63858C2A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691029981; bh=biQu6BSWuBLfu/9+X27So0M5xeTKo3YAa786VoPN2Jc=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=o5NqFgQI4mZ4U7/7z8gW5MXj18+qaFrTTRLh7oEpzj3PtSVRzvoQrKelc/mmFdRrX hP/05k+z4YfEyoFELSw9NVO52FIWRsWhnIb9qeC3zlfXnP4unZSJQyjZmj0M8yMif3 Dm4hYAgWhgcwSH9G3c604L+7nJhO1bAdr4pMG0v4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (unknown [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id B5EA33857C41 for ; Thu, 3 Aug 2023 02:32:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B5EA33857C41 X-IronPort-AV: E=McAfee;i="6600,9927,10790"; a="354666797" X-IronPort-AV: E=Sophos;i="6.01,250,1684825200"; d="scan'208,217";a="354666797" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2023 19:32:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10790"; a="729367753" X-IronPort-AV: E=Sophos;i="6.01,250,1684825200"; d="scan'208,217";a="729367753" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga002.jf.intel.com with ESMTP; 02 Aug 2023 19:32:12 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id AC0D2100516B; Thu, 3 Aug 2023 10:32:11 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v2] RISC-V: Support RVV VFMUL rounding mode intrinsic API Date: Thu, 3 Aug 2023 10:32:10 +0800 Message-Id: <20230803023210.530982-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230803013807.3967176-1-pan2.li@intel.com> References: <20230803013807.3967176-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773170056515194885 X-GMAIL-MSGID: 1773173454940926644 From: Pan Li Update in v2: * Sync with upstream for the vfmul duplicated declaration. Original log: This patch would like to support the rounding mode API for the VFMUL for the below samples. * __riscv_vfmul_vv_f32m1_rm * __riscv_vfmul_vv_f32m1_rm_m * __riscv_vfmul_vf_f32m1_rm * __riscv_vfmul_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (vfmul_frm_obj): New declaration. (Base): Likewise. * config/riscv/riscv-vector-builtins-bases.h: Likewise. * config/riscv/riscv-vector-builtins-functions.def (vfmul_frm): New function definition. * config/riscv/vector.md: Add vfmul to frm_mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-mul.c: New test. Signed-off-by: Pan Li --- .../riscv/riscv-vector-builtins-bases.cc | 3 ++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + gcc/config/riscv/vector.md | 2 +- .../riscv/rvv/base/float-point-single-mul.c | 44 +++++++++++++++++++ 5 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index ddf694c771c..3adc11138a3 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -277,6 +277,7 @@ public: /* Implements below instructions for now. - vfadd + - vfmul */ template class binop_frm : public function_base @@ -2103,6 +2104,7 @@ static CONSTEXPR const widen_binop_frm vfwadd_frm_obj; static CONSTEXPR const widen_binop vfwsub_obj; static CONSTEXPR const widen_binop_frm vfwsub_frm_obj; static CONSTEXPR const binop vfmul_obj; +static CONSTEXPR const binop_frm vfmul_frm_obj; static CONSTEXPR const binop
vfdiv_obj; static CONSTEXPR const reverse_binop
vfrdiv_obj; static CONSTEXPR const widen_binop vfwmul_obj; @@ -2334,6 +2336,7 @@ BASE (vfwadd_frm) BASE (vfwsub) BASE (vfwsub_frm) BASE (vfmul) +BASE (vfmul_frm) BASE (vfdiv) BASE (vfrdiv) BASE (vfwmul) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index f40b022239d..9c12a6b4e8f 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -152,6 +152,7 @@ extern const function_base *const vfwadd_frm; extern const function_base *const vfwsub; extern const function_base *const vfwsub_frm; extern const function_base *const vfmul; +extern const function_base *const vfmul_frm; extern const function_base *const vfdiv; extern const function_base *const vfrdiv; extern const function_base *const vfwmul; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 58a7224fe0c..35a83ef239c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -319,6 +319,8 @@ DEF_RVV_FUNCTION (vfmul, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvv_ops) DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfrdiv, alu, full_preds, f_vvf_ops) +DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvv_ops) +DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvf_ops) // 13.5. Vector Widening Floating-Point Multiply DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 65f36744f54..5d3e4256cd5 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -866,7 +866,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" - (cond [(eq_attr "type" "vfalu,vfwalu") + (cond [(eq_attr "type" "vfalu,vfwalu,vfmul") (cond [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") (const_string "rne") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c new file mode 100644 index 00000000000..e6410ea3a37 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfmul_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfmul_vv_f32m1_rm (op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfmul_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmul_vv_f32m1_rm_m (mask, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfmul_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfmul_vf_f32m1_rm (op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfmul_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfmul_vf_f32m1_rm_m (mask, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfmul_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfmul_vv_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfmul_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmul_vv_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfmul\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */