From patchwork Thu Aug 3 00:04:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 130222 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp806208vqx; Wed, 2 Aug 2023 17:05:50 -0700 (PDT) X-Google-Smtp-Source: APBJJlFcENHG8Mw7CCYIJfakGNqA+9jklFYwfUuJ8cSyStc7iabat+irUNiu1GTsb88ahJHrKyEL X-Received: by 2002:ac2:4c28:0:b0:4fd:ddbc:158d with SMTP id u8-20020ac24c28000000b004fdddbc158dmr5417713lfq.17.1691021149831; Wed, 02 Aug 2023 17:05:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691021149; cv=none; d=google.com; s=arc-20160816; b=tEn73bVeKOzsESRg/reZ13ym+CqUadC9OVoVEENbPI/sq++jnsqg/seu5Bs+rsjxZI 2r494lSXJmyfb+XSs7Pd+c1Ix6Bg/IMlQyOEGWIG8MGym1n3/GKVSCD+JZqWki4VcnMc sd/D1oE0Zt6Lk0Boqf8TycQvRjGWgnx5SYAfRhSLq2dGGmHbj29H2WPiseMyRaEjYYJv RgCk+9y/tMLdf0Vcty2FOK0cQhNRacqoKweAL2ecUIbFs5ah9DOENyI303HwU5q6jEwz I8ZST7yz86EgEbPsTNND4tQnE6c9PX6gRgczfwxMlfEuZ3P1JMa7CzY0m215EKRVuNa9 YhTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=bc5n27cv4TFQBeYm7Q3Gc4HVy0bi14vvt6pm2tkzp7g=; fh=oLBbkpKGrMjsAiDUocfN7mW0LEnMJsqDdFE8uCs7/vo=; b=wMWk5gHEWq0FUZDXX+kXkojeEVVs/h9jy/Aix9vBL8X6CubUx9NaX9/DRqDH/NzX76 AFM3aRudVFQeoE4c3IOpTBOpPZ9cOAv94FwfSoY5qBOo1UqkDnTwbSOz0zrCzAEiYDPy nHnET+he2ypfxL0LZAzP5LCegZYKpb/SjYCBzr+b4Ab5FJELSww2OqycrMiM5d5DvFt5 DH5KZo3gemPi7MXBFHhb6kbxQT3+grAiNOEz2ytFsStGJMgYbgLSXtH7Dgty+AARGI7c TjAN2z/7cmYpKHjIPW/JSAUas1c8pYWXhcWjAYKkcKiwrSSEDQl01JkwEa8ykYmKXTCj 2ajg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=h6iuAAmM; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id b17-20020aa7df91000000b005225522e9a0si1219251edy.597.2023.08.02.17.05.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 17:05:49 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=h6iuAAmM; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 681183857027 for ; Thu, 3 Aug 2023 00:05:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 681183857027 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1691021122; bh=bc5n27cv4TFQBeYm7Q3Gc4HVy0bi14vvt6pm2tkzp7g=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=h6iuAAmMRfNhTlZBpO9Je897JZHFjl7eCUmdJ2zuE8IlEycZS6nEd5mWtROZV8Ale Dq/YIaz/9uDkonuHBh8JilOMWZ/M4ccxMjq8sD1xziTcmrx3r1CWJFHWi7JEGBm1bZ YLxsK7CeOvfyyPKhlScFjRttuyC5xMHCSeFL9Moo= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 4BDB038582A3 for ; Thu, 3 Aug 2023 00:05:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4BDB038582A3 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 7A378300089; Thu, 3 Aug 2023 00:05:10 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [REVIEW ONLY 1/4] UNRATIFIED RISC-V: Add 'Zfbfmin' extension Date: Thu, 3 Aug 2023 00:04:53 +0000 Message-ID: <6c69c88bbca589e29567a4aa406c04ca2eaf11d6.1691021079.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773164193502536146 X-GMAIL-MSGID: 1773164193502536146 From: Tsukasa OI [DO NOT MERGE] Until RISC-V BF16 extensions are frozen/ratified and the final version number is determined, this patch should not be merged upstream. This commit uses unratified version 0.8 as in the latest PDF documentation (instead of possible 1.0 after ratification). This commit adds support for the 'Zfbfmin' extension, the scalar BF16 conversion extension. It consists of two new instructions and four previously 'Zfhmin'-only instructions. This commit is based on the following specification: bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets) Add 'Zfbfmin' -> 'F'. (riscv_supported_std_z_ext): Add 'Zfbfmin'. (riscv_multi_subset_supports): Recategory INSN_CLASS_ZFHMIN to mean 'Zfhmin' or 'Zfbfmin'. Add support to INSN_CLASS_ZFBFMIN. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zfbfmin.s: New test. * testsuite/gas/riscv/zfbfmin.d: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) New. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZFBFMIN. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add 'Zfbfmin'-only instructions. --- bfd/elfxx-riscv.c | 11 +++++++++-- gas/testsuite/gas/riscv/zfbfmin.d | 15 +++++++++++++++ gas/testsuite/gas/riscv/zfbfmin.s | 10 ++++++++++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 5 +++++ 6 files changed, 48 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index ba5165766b2b..edc2b17f5d3a 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1136,6 +1136,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zcf", "f", check_implicit_always}, {"zfa", "f", check_implicit_always}, {"d", "f", check_implicit_always}, + {"zfbfmin", "f", check_implicit_always}, {"zfh", "zfhmin", check_implicit_always}, {"zfhmin", "f", check_implicit_always}, {"f", "zicsr", check_implicit_always}, @@ -1254,6 +1255,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 0, 8, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2422,11 +2424,14 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_Q_INX: return (riscv_subset_supports (rps, "q") || riscv_subset_supports (rps, "zqinx")); + case INSN_CLASS_ZFBFMIN: + return riscv_subset_supports (rps, "zfbfmin"); case INSN_CLASS_ZFH_INX: return (riscv_subset_supports (rps, "zfh") || riscv_subset_supports (rps, "zhinx")); case INSN_CLASS_ZFHMIN: - return riscv_subset_supports (rps, "zfhmin"); + return (riscv_subset_supports (rps, "zfhmin") + || riscv_subset_supports (rps, "zfbfmin")); case INSN_CLASS_ZFHMIN_INX: return (riscv_subset_supports (rps, "zfhmin") || riscv_subset_supports (rps, "zhinxmin")); @@ -2625,10 +2630,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("d' or `zdinx"); case INSN_CLASS_Q_INX: return _("q' or `zqinx"); + case INSN_CLASS_ZFBFMIN: + return "zfbfmin"; case INSN_CLASS_ZFH_INX: return _("zfh' or `zhinx"); case INSN_CLASS_ZFHMIN: - return "zfhmin"; + return _("zfhmin' or `zfbfmin"); case INSN_CLASS_ZFHMIN_INX: return _("zfhmin' or `zhinxmin"); case INSN_CLASS_ZFHMIN_AND_D_INX: diff --git a/gas/testsuite/gas/riscv/zfbfmin.d b/gas/testsuite/gas/riscv/zfbfmin.d new file mode 100644 index 000000000000..28675457a0a9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfbfmin.d @@ -0,0 +1,15 @@ +#as: -march=rv32i_zfbfmin +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt\.bf16\.s[ ]+fa0,fa1 +[ ]+[0-9a-f]+:[ ]+44859553[ ]+fcvt\.bf16\.s[ ]+fa0,fa1,rtz +[ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt\.s\.bf16[ ]+fa0,fa1 +[ ]+[0-9a-f]+:[ ]+00059507[ ]+flh[ ]+fa0,0\(a1\) +[ ]+[0-9a-f]+:[ ]+00a59027[ ]+fsh[ ]+fa0,0\(a1\) +[ ]+[0-9a-f]+:[ ]+e4058553[ ]+fmv\.x\.h[ ]+a0,fa1 +[ ]+[0-9a-f]+:[ ]+f4058553[ ]+fmv\.h\.x[ ]+fa0,a1 diff --git a/gas/testsuite/gas/riscv/zfbfmin.s b/gas/testsuite/gas/riscv/zfbfmin.s new file mode 100644 index 000000000000..a0670a33ce69 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfbfmin.s @@ -0,0 +1,10 @@ +target: + # Zfbfmin only instructions + fcvt.bf16.s fa0, fa1 + fcvt.bf16.s fa0, fa1, rtz + fcvt.s.bf16 fa0, fa1 + # Instructions shared with Zfhmin + flh fa0, 0(a1) + fsh fa0, 0(a1) + fmv.x.h a0, fa1 + fmv.h.x fa0, a1 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 53f5f2005085..864faddcc6a5 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2121,6 +2121,11 @@ #define MASK_VDOTUVV 0xfc00707f #define MATCH_VFDOTVV 0xe4001057 #define MASK_VFDOTVV 0xfc00707f +/* Zfbfmin instructions. */ +#define MATCH_FCVT_BF16_S 0x44800053 +#define MASK_FCVT_BF16_S 0xfff0007f +#define MATCH_FCVT_S_BF16 0x40600053 +#define MASK_FCVT_S_BF16 0xfff0007f /* Zvbb instructions. */ #define MATCH_VANDN_VV 0x4000057 #define MASK_VANDN_VV 0xfc00707f @@ -3344,6 +3349,9 @@ DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ) /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) +/* Zfbfmin instructions. */ +DECLARE_INSN(fcvt_bf16_s, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S) +DECLARE_INSN(fcvt_s_bf16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) /* Zvbb instructions. */ DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 808f36573030..4db29287ebe9 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -398,6 +398,7 @@ enum riscv_insn_class INSN_CLASS_F_INX, INSN_CLASS_D_INX, INSN_CLASS_Q_INX, + INSN_CLASS_ZFBFMIN, INSN_CLASS_ZFH_INX, INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_INX, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6a854736fec0..5c9809c3c4f7 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -974,6 +974,11 @@ const struct riscv_opcode riscv_opcodes[] = {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, +/* Zfbfmin instructions. */ +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 }, +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 }, +{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 }, + /* Zfa instructions. */ {"fli.s", 0, INSN_CLASS_ZFA, "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 }, {"fli.d", 0, INSN_CLASS_D_AND_ZFA, "D,Wfv", MATCH_FLI_D, MASK_FLI_D, match_opcode, 0 }, From patchwork Thu Aug 3 00:04:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 130223 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp806380vqx; Wed, 2 Aug 2023 17:06:07 -0700 (PDT) X-Google-Smtp-Source: APBJJlGEwn2Tb1ovV5Xm8RPB21LsMMzWBDoxR/GUvtPSXhCvTFte7UMnW0iakyiNnCclba1Qxxor X-Received: by 2002:a17:907:7631:b0:993:f9b2:93c1 with SMTP id jy17-20020a170907763100b00993f9b293c1mr6157957ejc.9.1691021167131; Wed, 02 Aug 2023 17:06:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691021167; cv=none; d=google.com; s=arc-20160816; b=MQmojHMDAKdYX8oWuUVRMf5racjI1eEOuz1oO6rpOtmxS1nBLcoD3kaQkz5wQ0wHAw SD0alT2FoR3ALtPDuMHiDu8bIBBXitkDsY48MMwN2T7T443lrv+C4tnmaxoSxWn4YbXg bJwrjrHqpT7XEhzUx5npDvXMt1ylY1+Tr0oqwOkg+Q2sli2Q0JNm9yzqgvgKpQZXaL0v Mo9KR7wXq+zvvdliqaVe3km3ZY75Ol9C4zDOntt7lU1I1ngLsfTTq1qwU3/xk2fjJQrj E5x6K0rMGbuu7QYxO5eZM1nEAM8r1FnRV0BUW04yrzNKzB6EuA1RUsdHTTZlVUH1/464 nTwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=Ogvhnjr6zOgKPscT4ozR+Go5LsFniR+ULotW0joDIF8=; fh=oLBbkpKGrMjsAiDUocfN7mW0LEnMJsqDdFE8uCs7/vo=; b=M+KHnrBdE84L+BwWeOwH3v8ZxVGSNo+SWHuw+H2XhzZbTaDL+/QBS9RsLa1iyrZj0J 0obYTqczSwHqz2/2IXEs+/y2ffi6IbXJ/V1yEbSYprhX5GP7G7myrpB/VCcPHUp603l0 arPZ2K+/hfymOeHHQZJemXKRALabqEQLoGo1wyxy2LM4Mvpj/64GtI5W4TpOCoxeiD+d q3vOLbfGTn4VfRmceuers1FHXm0uABqsTph9QhwZVTX8xmG2RI0rPBwNBXwsu8e+4b8k OZb1j3AGfiG067xPBiANtAF2buxdgLGhS82WcXBmrAArGM/K5vVqhvRQefAWGwa6g29r RGyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=s1pxSad7; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id i23-20020a1709061cd700b0098d5b21121dsi6905281ejh.804.2023.08.02.17.06.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 17:06:07 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=s1pxSad7; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5663D3856943 for ; Thu, 3 Aug 2023 00:05:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5663D3856943 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1691021132; bh=Ogvhnjr6zOgKPscT4ozR+Go5LsFniR+ULotW0joDIF8=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=s1pxSad7GMfb5s/fGcSjCAPrtoZfWTooiOqB/rz45IsCaVEoaulBccUQ/xezfPpxX XiSms0eQNLYJh/FEQZ718p3fVP9Y4FuRRwrrALDGO+u+hdkPG25W3nnNr4mO/vK7+H zpHs6+pp2tLKINZE/GrrayV/eDKbVgWtdLD+Shes= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 0F3F63858000 for ; Thu, 3 Aug 2023 00:05:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0F3F63858000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 3E73B300089; Thu, 3 Aug 2023 00:05:21 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [REVIEW ONLY 2/4] UNRATIFIED RISC-V: Add 'Zvfbfmin' extension Date: Thu, 3 Aug 2023 00:04:54 +0000 Message-ID: <344ce2ac264b2af9b99b13be37f8e144670dc82e.1691021079.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773164211814202979 X-GMAIL-MSGID: 1773164211814202979 From: Tsukasa OI [DO NOT MERGE] Until RISC-V BF16 extensions are frozen/ratified and the final version number is determined, this patch should not be merged upstream. This commit uses unratified version 0.8 as in the latest PDF documentation (instead of possible 1.0 after ratification). This commit adds support for the 'Zvfbfmin' extension, the vector BF16 conversion only extension, consisting of two narrowing / widening conversion instructions between BF16 and FP32. This commit is based on the following specification: bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets) Add implications 'Zvfbfmin' -> 'Zfbfmin' and 'Zve32f'. (riscv_supported_std_z_ext): Add 'Zvfbfmin'. (riscv_multi_subset_supports): Add support to INSN_CLASS_ZVFBFMIN. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvfbfmin.s: New test. * testsuite/gas/riscv/zvfbfmin.d: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V) New. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZVFBFMIN. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add 'Zvfbfmin' instructions. --- bfd/elfxx-riscv.c | 7 +++++++ gas/testsuite/gas/riscv/zvfbfmin.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zvfbfmin.s | 5 +++++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 6 files changed, 37 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.d create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index edc2b17f5d3a..daf60010640a 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1110,6 +1110,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, {"v", "zvl128b", check_implicit_always}, + {"zvfbfmin", "zfbfmin", check_implicit_always}, + {"zvfbfmin", "zve32f", check_implicit_always}, {"zve64d", "d", check_implicit_always}, {"zve64d", "zve64f", check_implicit_always}, {"zve64f", "zve32f", check_implicit_always}, @@ -1288,6 +1290,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 0, 8, 0 }, {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkng", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2502,6 +2505,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvbb"); case INSN_CLASS_ZVBC: return riscv_subset_supports (rps, "zvbc"); + case INSN_CLASS_ZVFBFMIN: + return riscv_subset_supports (rps, "zvfbfmin"); case INSN_CLASS_ZVKG: return riscv_subset_supports (rps, "zvkg"); case INSN_CLASS_ZVKNED: @@ -2722,6 +2727,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("v' or `zve64d' or `zve64f' or `zve32f"); case INSN_CLASS_ZVBB: return _("zvbb"); + case INSN_CLASS_ZVFBFMIN: + return "zvfbfmin"; case INSN_CLASS_ZVBC: return _("zvbc"); case INSN_CLASS_ZVKG: diff --git a/gas/testsuite/gas/riscv/zvfbfmin.d b/gas/testsuite/gas/riscv/zvfbfmin.d new file mode 100644 index 000000000000..b15cff818716 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfmin.d @@ -0,0 +1,12 @@ +#as: -march=rv32i_zvfbfmin +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+4a8e9257[ ]+vfncvtbf16\.f\.f\.w[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+488e9257[ ]+vfncvtbf16\.f\.f\.w[ ]+v4,v8,v0\.t +[ ]+[0-9a-f]+:[ ]+4a869257[ ]+vfwcvtbf16\.f\.f\.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48869257[ ]+vfwcvtbf16\.f\.f\.v[ ]+v4,v8,v0\.t diff --git a/gas/testsuite/gas/riscv/zvfbfmin.s b/gas/testsuite/gas/riscv/zvfbfmin.s new file mode 100644 index 000000000000..e732e6ba99b2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfmin.s @@ -0,0 +1,5 @@ +target: + vfncvtbf16.f.f.w v4, v8 + vfncvtbf16.f.f.w v4, v8, v0.t + vfwcvtbf16.f.f.v v4, v8 + vfwcvtbf16.f.f.v v4, v8, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 864faddcc6a5..2a631a871ecd 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2168,6 +2168,11 @@ #define MASK_VCLMULH_VV 0xfc00707f #define MATCH_VCLMULH_VX 0x34006057 #define MASK_VCLMULH_VX 0xfc00707f +/* Zvfbfmin instructions. */ +#define MATCH_VFNCVTBF16_F_F_W 0x480e9057 +#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f +#define MATCH_VFWCVTBF16_F_F_V 0x48069057 +#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f /* Zvkg instructions. */ #define MATCH_VGHSH_VV 0xb2002077 #define MASK_VGHSH_VV 0xfe00707f @@ -3374,6 +3379,9 @@ DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV) DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX) DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV) DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX) +/* Zvfbfmin instructions. */ +DECLARE_INSN(vfncvtbf16_f_f_w, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W) +DECLARE_INSN(vfwcvtbf16_f_f_v, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V) /* Zvkg instructions. */ DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV) DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 4db29287ebe9..44105ba8698b 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -427,6 +427,7 @@ enum riscv_insn_class INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, + INSN_CLASS_ZVFBFMIN, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED, INSN_CLASS_ZVKNHA_OR_ZVKNHB, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 5c9809c3c4f7..c2f90c900bd1 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1926,6 +1926,10 @@ const struct riscv_opcode riscv_opcodes[] = {"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0}, {"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0}, +/* Zvfbfmin instructions. */ +{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0}, +{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0}, + /* Zvkg instructions. */ {"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0}, {"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0}, From patchwork Thu Aug 3 00:04:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 130227 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp807305vqx; Wed, 2 Aug 2023 17:07:56 -0700 (PDT) X-Google-Smtp-Source: APBJJlGmOaHZRpTaPofkouQIUNK36oH6s95zFZl1mxVTEhbrryYwSHOM3Xqvmq8sW7mh2vJfPEMM X-Received: by 2002:ac2:4985:0:b0:4f8:71bf:a259 with SMTP id f5-20020ac24985000000b004f871bfa259mr5482380lfl.67.1691021275946; Wed, 02 Aug 2023 17:07:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691021275; cv=none; d=google.com; s=arc-20160816; b=VEi3Df1fIiuij/cvOcJ7Efu03+Zw2+9/UbIsAip/M2fDdVfpjT9hdOFYO+2vg/1UKD ZBAcfdwIG9MeFdv5uS0NMG20ipt1DHsBWN9B2T/gDZYSrJGtG3k5icBDvkBkVHJvcnZl XPuebgM7Eiu9uhIDaXdj8M0WJOrL04OGKBNGtoMgr+qzOdbSQ8PSVwKKsipP6qdY22wu KbOd41N47YgUQLXlu7o8Ot1jaDUwtBoQmNyxjKv8e6Qb7zXxIC1PdZAqjcSmfBhjYW8q MsuDYBzrxJ7Jk4ohzGDHKwsQ18EUFuqq+UyTvRLdGgttcRWl2gmYWQXwmvPScj8lv3m1 Iyzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=zWmAeD2UUVksa5FIXwjupCawU8au/5OHaB0c+dhWXgY=; fh=oLBbkpKGrMjsAiDUocfN7mW0LEnMJsqDdFE8uCs7/vo=; b=E1BmcpPH0G9xdI34u6spNWJZ7Cyct00f9sUoB8I71um9KDE+eWsBUL3MrWA8jJOVP8 9omi9sP+O4YvQ0Om42q/ra8Imt4LyTgXwaLmMZczSOoqNoBXo8I6JJB/2eSn7iAJedwc dpvR9ZXA5/DX4WM3/YV6jrlCSQ1TAvJKYr6EWbl6L+xLw8KDXGSfawThwtN8EoiGhGiE eInTjLIMH9vQeb4OHgkddUcFAw3yIf80RV/QsX63FK7Tf/htZ8vofTcQXk6lXwfJL2VG dkL8lDB5F+PzoLCyJi+TMlW2e9LFyyp1gFpXVuOS467tVGq/31ks/dA1u/pMSaMJoPNB Ni3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=EYcGwNOF; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id h19-20020a17090634d300b009935d9765fasi10719328ejb.1013.2023.08.02.17.07.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 17:07:55 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=EYcGwNOF; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9A5343850216 for ; Thu, 3 Aug 2023 00:06:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9A5343850216 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1691021192; bh=zWmAeD2UUVksa5FIXwjupCawU8au/5OHaB0c+dhWXgY=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=EYcGwNOFoR1UL/jZeTFuFJXGIa5h8xWP2252nkSJGRabrHzUY3Jjv04pCBu904pqK eYYD7w5RwltWyXQWFv2XwwdveasQsstNoYOqmlutLjXLqgDGPOSYBWJweuGndi1YKE WdJvg5Pm4MmSlX860c7iKd6Ko3Ci/5QBMOis2tx0= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id BD4D93856964 for ; Thu, 3 Aug 2023 00:05:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BD4D93856964 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 0240B300089; Thu, 3 Aug 2023 00:05:31 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [REVIEW ONLY 3/4] UNRATIFIED RISC-V: Add 'Zvfbfwma' extension Date: Thu, 3 Aug 2023 00:04:55 +0000 Message-ID: <407c1a1b2b8ba154e50906360bdf44953eef153d.1691021079.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773164325264431442 X-GMAIL-MSGID: 1773164325264431442 From: Tsukasa OI [DO NOT MERGE] Until RISC-V BF16 extensions are frozen/ratified and the final version number is determined, this patch should not be merged upstream. This commit uses unratified version 0.8 as in the latest PDF documentation (instead of possible 1.0 after ratification). This commit adds support for the 'Zvfbfwma' extension, the vector BF16 multiply then FP32 accumlation extension, consisting of two widening multiply-accumulate instructions. This commit is based on the following specification: bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets) Add 'Zvfbfwma' -> 'Zvfbfmin' implication. (riscv_supported_std_z_ext): Add 'Zvfbfwma'. (riscv_multi_subset_supports): Add support to INSN_CLASS_ZVFBFWMA. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvfbfwma.s: New test. * testsuite/gas/riscv/zvfbfwma.d: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF, MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV) New. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZVFBFWMA. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add 'Zvfbfwma' instructions. --- bfd/elfxx-riscv.c | 6 ++++++ gas/testsuite/gas/riscv/zvfbfwma.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zvfbfwma.s | 5 +++++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 6 files changed, 36 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.d create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index daf60010640a..57bbc82f7f7f 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1110,6 +1110,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, {"v", "zvl128b", check_implicit_always}, + {"zvfbfwma", "zvfbfmin", check_implicit_always}, {"zvfbfmin", "zfbfmin", check_implicit_always}, {"zvfbfmin", "zve32f", check_implicit_always}, {"zve64d", "d", check_implicit_always}, @@ -1291,6 +1292,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 0, 8, 0 }, + {"zvfbfwma", ISA_SPEC_CLASS_DRAFT, 0, 8, 0 }, {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkng", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2507,6 +2509,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvbc"); case INSN_CLASS_ZVFBFMIN: return riscv_subset_supports (rps, "zvfbfmin"); + case INSN_CLASS_ZVFBFWMA: + return riscv_subset_supports (rps, "zvfbfwma"); case INSN_CLASS_ZVKG: return riscv_subset_supports (rps, "zvkg"); case INSN_CLASS_ZVKNED: @@ -2729,6 +2733,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvbb"); case INSN_CLASS_ZVFBFMIN: return "zvfbfmin"; + case INSN_CLASS_ZVFBFWMA: + return "zvfbfwma"; case INSN_CLASS_ZVBC: return _("zvbc"); case INSN_CLASS_ZVKG: diff --git a/gas/testsuite/gas/riscv/zvfbfwma.d b/gas/testsuite/gas/riscv/zvfbfwma.d new file mode 100644 index 000000000000..3597bde0e4af --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfwma.d @@ -0,0 +1,12 @@ +#as: -march=rv32i_zvfbfwma +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+ee861257[ ]+vfwmaccbf16.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+ee865257[ ]+vfwmaccbf16.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+ec861257[ ]+vfwmaccbf16.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+ec865257[ ]+vfwmaccbf16.vf[ ]+v4,v8,fa2,v0.t diff --git a/gas/testsuite/gas/riscv/zvfbfwma.s b/gas/testsuite/gas/riscv/zvfbfwma.s new file mode 100644 index 000000000000..d44c09c27f10 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfwma.s @@ -0,0 +1,5 @@ +target: + vfwmaccbf16.vv v4, v8, v12 + vfwmaccbf16.vf v4, v8, fa2 + vfwmaccbf16.vv v4, v8, v12, v0.t + vfwmaccbf16.vf v4, v8, fa2, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 2a631a871ecd..f57aca4c6498 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2173,6 +2173,11 @@ #define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f #define MATCH_VFWCVTBF16_F_F_V 0x48069057 #define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f +/* Zvfbfwma instructions. */ +#define MATCH_VFWMACCBF16_VF 0xec005057 +#define MASK_VFWMACCBF16_VF 0xfc00707f +#define MATCH_VFWMACCBF16_VV 0xec001057 +#define MASK_VFWMACCBF16_VV 0xfc00707f /* Zvkg instructions. */ #define MATCH_VGHSH_VV 0xb2002077 #define MASK_VGHSH_VV 0xfe00707f @@ -3382,6 +3387,9 @@ DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX) /* Zvfbfmin instructions. */ DECLARE_INSN(vfncvtbf16_f_f_w, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W) DECLARE_INSN(vfwcvtbf16_f_f_v, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V) +/* Zvfbfwma instructions. */ +DECLARE_INSN(vfwmaccbf16_vf, MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF) +DECLARE_INSN(vfwmaccbf16_vv, MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV) /* Zvkg instructions. */ DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV) DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 44105ba8698b..9fbe5392a45e 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -428,6 +428,7 @@ enum riscv_insn_class INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, INSN_CLASS_ZVFBFMIN, + INSN_CLASS_ZVFBFWMA, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED, INSN_CLASS_ZVKNHA_OR_ZVKNHB, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index c2f90c900bd1..f8001b601d90 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1930,6 +1930,10 @@ const struct riscv_opcode riscv_opcodes[] = {"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0}, {"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0}, +/* Zvfbfwma instructions. */ +{"vfwmaccbf16.vv", 0, INSN_CLASS_ZVFBFWMA, "Vd,Vt,VsVm", MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV, match_opcode, 0}, +{"vfwmaccbf16.vf", 0, INSN_CLASS_ZVFBFWMA, "Vd,Vt,SVm", MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF, match_opcode, 0}, + /* Zvkg instructions. */ {"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0}, {"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0}, From patchwork Thu Aug 3 00:04:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 130226 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp807220vqx; Wed, 2 Aug 2023 17:07:44 -0700 (PDT) X-Google-Smtp-Source: APBJJlFjWoh/7sfe3C9nAbPgNMNoxEJn48xGBDw0ceFIIFmo6YAs4CC6Dvtw80l0772muljrwSsP X-Received: by 2002:a17:907:7711:b0:991:bf04:2047 with SMTP id kw17-20020a170907771100b00991bf042047mr6003362ejc.14.1691021264388; Wed, 02 Aug 2023 17:07:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691021264; cv=none; d=google.com; s=arc-20160816; b=EzckRq3yJOF7aJ74/L28orxw8dl7M8+JKonGUm8uqtpEo7H4TGDk+duEzZWGnzFPoI js9564q66vXf8+uo1dY1RnKQZHVqc8WvJVcIbtMM+a1KOG5LzVt135Tcp/v6eRbKFvDm OdRAI7W2C1YHVoIy0DiaSKBzrhZkoITkw2hfmiqle86M+EJwYBN8K3cJ2Evf4t+asia0 db8O8gEd/pfDmPPzX10ssH2n/rvettzIVEAsHOM5S6AT8v1zwV/p2Rnozppw5eCG+Gwb 0IInPchG0KLF5oyU+BgQS0+TZrZVGTZ3uVb8BE5afdCHtrZpgJGKA3pKZ+gVHtkAt61U yxIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=ytzT+mX+Mzu7i8LT5ZOw26NaZmw+oX0yegYWYA7ME8g=; fh=oLBbkpKGrMjsAiDUocfN7mW0LEnMJsqDdFE8uCs7/vo=; b=viMP0ImYbIcfd0BwmOXbrkEvCHNrTPNKqYFOHudkkLGZfQdnLGsmTAZpxkWWRd+YjC aqAHxMSnit/aa83AZIb9Mn44nRQWJO+/fwTSS/mRLxtcuqwInPJEwxljdgJ413jGDE86 4MmIRBYwE9/QCvUule0LggOyZewYKCnrjtcBDZUdnyfHiDV7+acx0+M1kANUQF93c6t3 q9aHsaHsbv/qq9eSx271dhhzCG7wbb7GG2PTuG7pcPyivkFyOHPfnHYHmGG18h5rV4Up IfzDIlIVsYMNhbXq8lxTZqL8V11lqVavcmNddGz0PBKnFMKiF6ldOLKz6KAYs10vItbY 4owA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=doGdgSZT; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id u27-20020a1709063b9b00b00992a096678fsi10991810ejf.813.2023.08.02.17.07.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 17:07:44 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=doGdgSZT; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C96AC3857355 for ; Thu, 3 Aug 2023 00:06:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C96AC3857355 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1691021183; bh=ytzT+mX+Mzu7i8LT5ZOw26NaZmw+oX0yegYWYA7ME8g=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=doGdgSZTervpbnPDt9+BANe0JIZqsCWrpK5/UxtTubGA9tCC6QkBKXnmuQAsn5ZfV 0qX3x+xh/ubkIsop+W9B7ZZU9XcYufhyrEsRjSA/5Ii5+ATESwUKdgenmuxfZM79ID S5PA+Nk1sARMxoRulvNfn8P8HQyts6X7FuI24AYs= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 6CEEE3857702 for ; Thu, 3 Aug 2023 00:05:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6CEEE3857702 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id BA2FC300089; Thu, 3 Aug 2023 00:05:42 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [REVIEW ONLY 4/4] RISC-V: Tentative ".bfloat16" assembly support Date: Thu, 3 Aug 2023 00:04:56 +0000 Message-ID: <7fbfd7ca7fdc34afc0111af0f7beb7c69839fc04.1691021079.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773164312918050817 X-GMAIL-MSGID: 1773164312918050817 From: Tsukasa OI This commit adds an assembler directive ".bfloat16" to help BFloat16 extensions ('Zfbfmin', 'Zvfbfmin' and 'Zvfbfwma') users. gas/ChangeLog: * config/tc-riscv.c (FLT_CHARS): Add BFloat16 'b' to supported floating point formats. (riscv_pseudo_table) Add ".bfloat16" directive. * testsuite/gas/riscv/bfloat16.s: Copied from testsuite/gas/aarch64/bfloat16-directive.s. * testsuite/gas/riscv/bfloat16-be.d: New test ported from testsuite/gas/aarch64/bfloat16-directive-be.d and float16-be.d. * testsuite/gas/riscv/bfloat16-le.d: New test ported from testsuite/gas/aarch64/bfloat16-directive-le.d and float16-le.d. --- gas/config/tc-riscv.c | 3 ++- gas/testsuite/gas/riscv/bfloat16-be.d | 10 ++++++++++ gas/testsuite/gas/riscv/bfloat16-le.d | 10 ++++++++++ gas/testsuite/gas/riscv/bfloat16.s | 19 +++++++++++++++++++ 4 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/bfloat16-be.d create mode 100644 gas/testsuite/gas/riscv/bfloat16-le.d create mode 100644 gas/testsuite/gas/riscv/bfloat16.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index aaf8b9be64fd..9f15233c7b99 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -437,7 +437,7 @@ const char EXP_CHARS[] = "eE"; /* Chars that mean this number is a floating point constant. As in 0f12.456 or 0d1.2345e12. */ -const char FLT_CHARS[] = "rRsSfFdDxXpPhH"; +const char FLT_CHARS[] = "rRsSfFdDxXpPhHb"; /* Indicate we are already assemble any instructions or not. */ static bool start_assemble = false; @@ -5178,6 +5178,7 @@ static const pseudo_typeS riscv_pseudo_table[] = {"attribute", s_riscv_attribute, 0}, {"variant_cc", s_variant_cc, 0}, {"float16", float_cons, 'h'}, + {"bfloat16", float_cons, 'b'}, { NULL, NULL, 0 }, }; diff --git a/gas/testsuite/gas/riscv/bfloat16-be.d b/gas/testsuite/gas/riscv/bfloat16-be.d new file mode 100644 index 000000000000..8775ab035f6c --- /dev/null +++ b/gas/testsuite/gas/riscv/bfloat16-be.d @@ -0,0 +1,10 @@ +# source: bfloat16.s +# objdump: -sj .data +# as: -mbig-endian + +.*: +file format .* + +Contents of section \.data: + 0000 41403dfc 000042f7 8000c2f7 7fff7f80 .* + 0010 ff807f7f ff7f0080 80800001 8001007f .* + 0020 807f3f80 bf804000 c000.* diff --git a/gas/testsuite/gas/riscv/bfloat16-le.d b/gas/testsuite/gas/riscv/bfloat16-le.d new file mode 100644 index 000000000000..4de8b2fed68b --- /dev/null +++ b/gas/testsuite/gas/riscv/bfloat16-le.d @@ -0,0 +1,10 @@ +# source: bfloat16.s +# objdump: -sj .data +# as: -mlittle-endian + +.*: +file format .* + +Contents of section \.data: + 0000 4041fc3d 0000f742 0080f7c2 ff7f807f .* + 0010 80ff7f7f 7fff8000 80800100 01807f00 .* + 0020 7f80803f 80bf0040 00c0.* diff --git a/gas/testsuite/gas/riscv/bfloat16.s b/gas/testsuite/gas/riscv/bfloat16.s new file mode 100644 index 000000000000..66e17e4fc7da --- /dev/null +++ b/gas/testsuite/gas/riscv/bfloat16.s @@ -0,0 +1,19 @@ +.data + .bfloat16 12.0 + .bfloat16 0.123 + .bfloat16 +0.0 + .bfloat16 123.4 + .bfloat16 -0.0 + .bfloat16 -123.4 + .bfloat16 NaN + .bfloat16 Inf + .bfloat16 -Inf + .bfloat16 3.390e+38 + .bfloat16 -3.390e+38 + .bfloat16 1.175e-38 + .bfloat16 -1.175e-38 + .bfloat16 9.194e-41 + .bfloat16 -9.194e-41 + .bfloat16 1.167e-38 + .bfloat16 -1.167e-38 + .bfloat16 1.0, -1, 2.0, -2