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[8.43.85.97]) by mx.google.com with ESMTPS id u23-20020a1709064ad700b00992f1a3b9d9si9552586ejt.415.2023.08.02.03.20.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 03:20:03 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=mgVsIVps; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 52AE2385840B for ; Wed, 2 Aug 2023 10:20:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 52AE2385840B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690971602; bh=gA2akZ17t5cddG27ifOtuHWPQkSbevpu1gCEL84V3D4=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=mgVsIVpskQ+XCS0C+WtfsTQKS9yVIgZ2sLnoGqa99WnJKrJjWCbeh8Xz4jR19a0Mh cPcSOEagh1nUvqenMnzoHMnsSgdJH/NmfTDQ4lgAb46Bgb09AdWfiabSsBsc7kJVlm wkZrNaS6epYdqORTF86Cbj3RjuzwvjqaruqI9HPY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (unknown [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 1425D3858D1E for ; Wed, 2 Aug 2023 10:19:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1425D3858D1E X-IronPort-AV: E=McAfee;i="6600,9927,10789"; a="400490708" X-IronPort-AV: E=Sophos;i="6.01,248,1684825200"; d="scan'208,217";a="400490708" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2023 03:19:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10789"; a="732327710" X-IronPort-AV: E=Sophos;i="6.01,248,1684825200"; d="scan'208,217";a="732327710" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga007.fm.intel.com with ESMTP; 02 Aug 2023 03:19:09 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 6CB961007EC7; Wed, 2 Aug 2023 18:19:08 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFWSUB rounding mode intrinsic API Date: Wed, 2 Aug 2023 18:19:07 +0800 Message-Id: <20230802101907.3772871-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773112239648930391 X-GMAIL-MSGID: 1773112239648930391 From: Pan Li This patch would like to support the rounding mode API for the VFWSUB for the below samples. * __riscv_vfwsub_vv_f64m2_rm * __riscv_vfwsub_vv_f64m2_rm_m * __riscv_vfwsub_vf_f64m2_rm * __riscv_vfwsub_vf_f64m2_rm_m * __riscv_vfwsub_wv_f64m2_rm * __riscv_vfwsub_wv_f64m2_rm_m * __riscv_vfwsub_wf_f64m2_rm * __riscv_vfwsub_wf_f64m2_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (BASE): Add vfwsub frm. * config/riscv/riscv-vector-builtins-bases.h: Add declaration. * config/riscv/riscv-vector-builtins-functions.def (vfwsub_frm): Add vfwsub function definitions. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-widening-sub.c: New test. Signed-off-by: Pan Li > --- .../riscv/riscv-vector-builtins-bases.cc | 3 + .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 4 ++ .../riscv/rvv/base/float-point-widening-sub.c | 66 +++++++++++++++++++ 4 files changed, 74 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 981a4a7ede8..ddf694c771c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -317,6 +317,7 @@ public: /* Implements below instructions for frm - vfwadd + - vfwsub */ template class widen_binop_frm : public function_base @@ -2100,6 +2101,7 @@ static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj; static CONSTEXPR const widen_binop vfwadd_obj; static CONSTEXPR const widen_binop_frm vfwadd_frm_obj; static CONSTEXPR const widen_binop vfwsub_obj; +static CONSTEXPR const widen_binop_frm vfwsub_frm_obj; static CONSTEXPR const binop vfmul_obj; static CONSTEXPR const binop
vfdiv_obj; static CONSTEXPR const reverse_binop
vfrdiv_obj; @@ -2330,6 +2332,7 @@ BASE (vfrsub_frm) BASE (vfwadd) BASE (vfwadd_frm) BASE (vfwsub) +BASE (vfwsub_frm) BASE (vfmul) BASE (vfdiv) BASE (vfrdiv) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index f9e1df5fe75..5800fca0169 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -150,6 +150,7 @@ extern const function_base *const vfrsub_frm; extern const function_base *const vfwadd; extern const function_base *const vfwadd_frm; extern const function_base *const vfwsub; +extern const function_base *const vfwsub_frm; extern const function_base *const vfmul; extern const function_base *const vfmul; extern const function_base *const vfdiv; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 743205a9b97..58a7224fe0c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -306,8 +306,12 @@ DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwv_ops) DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwf_ops) DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvv_ops) DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvf_ops) +DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wvv_ops) +DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wvf_ops) DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wwv_ops) DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wwf_ops) +DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wwv_ops) +DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wwf_ops) // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions DEF_RVV_FUNCTION (vfmul, alu, full_preds, f_vvv_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c new file mode 100644 index 00000000000..4325cc510a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat64m2_t +test_vfwsub_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwsub_vv_f64m2_rm (op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwsub_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwsub_vv_f64m2_rm_m (mask, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwsub_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfwsub_vf_f64m2_rm (op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfwsub_vf_f64m2_rm_m (mask, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwsub_wv_f32m1_rm (vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwsub_wv_f64m2_rm (op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwsub_wv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwsub_wv_f64m2_rm_m (mask, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwsub_wf_f32m1_rm (vfloat64m2_t op1, float32_t op2, size_t vl) { + return __riscv_vfwsub_wf_f64m2_rm (op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwsub_wf_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, float32_t op2, + size_t vl) { + return __riscv_vfwsub_wf_f64m2_rm_m (mask, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwsub_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwsub_vv_f64m2 (op1, op2, vl); +} + +vfloat64m2_t +test_vfwsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwsub_vv_f64m2_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwsub\.[vw][vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 10 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 8 } } */