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[8.43.85.97]) by mx.google.com with ESMTPS id sb10-20020a170906edca00b00993116b01f9si6585583ejb.120.2023.08.01.23.36.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Aug 2023 23:36:40 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=khWwUYN6; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9ED76385802F for ; Wed, 2 Aug 2023 06:36:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9ED76385802F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690958198; bh=M4OBCWs0U0ZWy7s+1uZVUBjs89BZ+pZOkHM9ZtNbXDA=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=khWwUYN6K6IrLOEGI8a2Eagc3sJ5PpPj1i05qtp947KXrGe2xXSt3pA5haWlppMvM V2FucjXhKkXrA9Vk6ACQP8UKDbBup+0ZkwQJGu1fQ8/ThJgV1h3e9SxK3tgC80zWwe cJOZlzmPFe9gkYJejdAnm9hbT2hrg7ybwr1aP9w8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (unknown [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 244A33858D39 for ; Wed, 2 Aug 2023 06:35:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 244A33858D39 X-IronPort-AV: E=McAfee;i="6600,9927,10789"; a="435820226" X-IronPort-AV: E=Sophos;i="6.01,248,1684825200"; d="scan'208";a="435820226" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2023 23:35:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="872350905" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga001.fm.intel.com with ESMTP; 01 Aug 2023 23:35:51 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id E35AC10079D3; Wed, 2 Aug 2023 14:35:47 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v2] RISC-V: Support RVV VFWADD rounding mode intrinsic API Date: Wed, 2 Aug 2023 14:35:47 +0800 Message-Id: <20230802063547.2663520-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802023621.1954111-1-pan2.li@intel.com> References: <20230802023621.1954111-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773083120968319165 X-GMAIL-MSGID: 1773098186455057827 From: Pan Li Update in v2: 1. Add vfwalu type to frm_mode. 2. Enhance the test cases for frm. Original log: This patch would like to support the rounding mode API for the VFWADD VFSUB and VFRSUB as below samples. * __riscv_vfwadd_vv_f64m2_rm * __riscv_vfwadd_vv_f64m2_rm_m * __riscv_vfwadd_vf_f64m2_rm * __riscv_vfwadd_vf_f64m2_rm_m * __riscv_vfwadd_wv_f64m2_rm * __riscv_vfwadd_wv_f64m2_rm_m * __riscv_vfwadd_wf_f64m2_rm * __riscv_vfwadd_wf_f64m2_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class widen_binop_frm): New class for binop frm. (BASE): Add vfwadd_frm. * config/riscv/riscv-vector-builtins-bases.h: New declaration. * config/riscv/riscv-vector-builtins-functions.def (vfwadd_frm): New function definition. * config/riscv/riscv-vector-builtins-shapes.cc (BASE_NAME_MAX_LEN): New macro. (struct alu_frm_def): Leverage new base class. (struct build_frm_base): New build base for frm. (struct widen_alu_frm_def): New struct for widen alu frm. (SHAPE): Add widen_alu_frm shape. * config/riscv/riscv-vector-builtins-shapes.h: New declaration. * config/riscv/vector.md (frm_mode): Add vfwalu type. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-widening-add.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li > --- .../riscv/riscv-vector-builtins-bases.cc | 37 +++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 4 ++ .../riscv/riscv-vector-builtins-shapes.cc | 66 +++++++++++++++---- .../riscv/riscv-vector-builtins-shapes.h | 1 + gcc/config/riscv/vector.md | 2 +- .../riscv/rvv/base/float-point-widening-add.c | 66 +++++++++++++++++++ 7 files changed, 164 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-add.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 035cafc43b3..981a4a7ede8 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -315,6 +315,41 @@ public: } }; +/* Implements below instructions for frm + - vfwadd +*/ +template +class widen_binop_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + rtx expand (function_expander &e) const override + { + switch (e.op_info->op) + { + case OP_TYPE_vv: + return e.use_exact_insn ( + code_for_pred_dual_widen (CODE, e.vector_mode ())); + case OP_TYPE_vf: + return e.use_exact_insn ( + code_for_pred_dual_widen_scalar (CODE, e.vector_mode ())); + case OP_TYPE_wv: + if (CODE == PLUS) + return e.use_exact_insn ( + code_for_pred_single_widen_add (e.vector_mode ())); + else + return e.use_exact_insn ( + code_for_pred_single_widen_sub (e.vector_mode ())); + case OP_TYPE_wf: + return e.use_exact_insn ( + code_for_pred_single_widen_scalar (CODE, e.vector_mode ())); + default: + gcc_unreachable (); + } + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2063,6 +2098,7 @@ static CONSTEXPR const binop_frm vfsub_frm_obj; static CONSTEXPR const reverse_binop vfrsub_obj; static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj; static CONSTEXPR const widen_binop vfwadd_obj; +static CONSTEXPR const widen_binop_frm vfwadd_frm_obj; static CONSTEXPR const widen_binop vfwsub_obj; static CONSTEXPR const binop vfmul_obj; static CONSTEXPR const binop
vfdiv_obj; @@ -2292,6 +2328,7 @@ BASE (vfsub_frm) BASE (vfrsub) BASE (vfrsub_frm) BASE (vfwadd) +BASE (vfwadd_frm) BASE (vfwsub) BASE (vfmul) BASE (vfdiv) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 5c6b239c274..f9e1df5fe75 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -148,6 +148,7 @@ extern const function_base *const vfsub_frm; extern const function_base *const vfrsub; extern const function_base *const vfrsub_frm; extern const function_base *const vfwadd; +extern const function_base *const vfwadd_frm; extern const function_base *const vfwsub; extern const function_base *const vfmul; extern const function_base *const vfmul; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index fa1c2cef970..743205a9b97 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -304,6 +304,10 @@ DEF_RVV_FUNCTION (vfwadd, widen_alu, full_preds, f_wwv_ops) DEF_RVV_FUNCTION (vfwadd, widen_alu, full_preds, f_wwf_ops) DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwv_ops) DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwf_ops) +DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvv_ops) +DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvf_ops) +DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wwv_ops) +DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wwf_ops) // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions DEF_RVV_FUNCTION (vfmul, alu, full_preds, f_vvv_ops) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 6af57c22bfb..1d14fa21e81 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -75,6 +75,8 @@ build_all (function_builder &b, const function_group_info &group) static CONSTEXPR const DEF##_def VAR##_obj; \ namespace shapes { const function_shape *const VAR = &VAR##_obj; } +#define BASE_NAME_MAX_LEN 16 + /* Base class for for build. */ struct build_base : public function_shape { @@ -226,8 +228,8 @@ struct alu_def : public build_base } }; -/* alu_frm_def class. */ -struct alu_frm_def : public build_base +/* The base class for frm build. */ +struct build_frm_base : public build_base { /* Normalize vf_frm to vf. */ static void normalize_base_name (char *to, const char *from, int limit) @@ -241,10 +243,29 @@ struct alu_frm_def : public build_base to[limit - 1] = '\0'; } + bool check (function_checker &c) const override + { + gcc_assert (c.any_type_float_p ()); + + /* Check whether rounding mode argument is a valid immediate. */ + if (c.base->has_rounding_mode_operand_p ()) + { + unsigned int frm_num = c.arg_num () - 2; + + return c.require_immediate (frm_num, FRM_STATIC_MIN, FRM_STATIC_MAX); + } + + return true; + } +}; + +/* alu_frm_def class. */ +struct alu_frm_def : public build_frm_base +{ char *get_name (function_builder &b, const function_instance &instance, bool overloaded_p) const override { - char base_name[16] = {}; + char base_name[BASE_NAME_MAX_LEN] = {}; /* Return nullptr if it can not be overloaded. */ if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred)) @@ -275,20 +296,40 @@ struct alu_frm_def : public build_base return b.finish_name (); } +}; - bool check (function_checker &c) const override +/* widen_alu_frm_def class. */ +struct widen_alu_frm_def : public build_frm_base +{ + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override { - gcc_assert (c.any_type_float_p ()); + char base_name[BASE_NAME_MAX_LEN] = {}; - /* Check whether rounding mode argument is a valid immediate. */ - if (c.base->has_rounding_mode_operand_p ()) - { - unsigned int frm_num = c.arg_num () - 2; + normalize_base_name (base_name, instance.base_name, sizeof (base_name)); - return c.require_immediate (frm_num, FRM_STATIC_MIN, FRM_STATIC_MAX); - } + b.append_base_name (base_name); - return true; + /* vop --> vop_. */ + b.append_name (operand_suffixes[instance.op_info->op]); + + /* vop_ --> vop__. */ + if (!overloaded_p) + b.append_name (type_suffixes[instance.type.index].vector); + + /* According to rvv-intrinsic-doc, it does not add "_rm" suffix + for vop_rm C++ overloaded API. */ + if (!overloaded_p) + b.append_name ("_rm"); + + /* According to rvv-intrinsic-doc, it does not add "_m" suffix + for vop_m C++ overloaded API. */ + if (overloaded_p && instance.pred == PRED_TYPE_m) + return b.finish_name (); + + b.append_name (predication_suffixes[instance.pred]); + + return b.finish_name (); } }; @@ -811,6 +852,7 @@ SHAPE(indexed_loadstore, indexed_loadstore) SHAPE(alu, alu) SHAPE(alu_frm, alu_frm) SHAPE(widen_alu, widen_alu) +SHAPE(widen_alu_frm, widen_alu_frm) SHAPE(no_mask_policy, no_mask_policy) SHAPE(return_mask, return_mask) SHAPE(narrow_alu, narrow_alu) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h index 15fef8342ec..841b930b547 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.h +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h @@ -31,6 +31,7 @@ extern const function_shape *const indexed_loadstore; extern const function_shape *const alu; extern const function_shape *const alu_frm; extern const function_shape *const widen_alu; +extern const function_shape *const widen_alu_frm; extern const function_shape *const no_mask_policy; extern const function_shape *const return_mask; extern const function_shape *const narrow_alu; diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index b3c0c3dd45d..65f36744f54 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -866,7 +866,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" - (cond [(eq_attr "type" "vfalu") + (cond [(eq_attr "type" "vfalu,vfwalu") (cond [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") (const_string "rne") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-add.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-add.c new file mode 100644 index 00000000000..19ce1e1829d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-add.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat64m2_t +test_vfwadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwadd_vv_f64m2_rm (op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwadd_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwadd_vv_f64m2_rm_m (mask, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwadd_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfwadd_vf_f64m2_rm (op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwadd_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfwadd_vf_f64m2_rm_m (mask, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwadd_wv_f32m1_rm (vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwadd_wv_f64m2_rm (op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwadd_wv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwadd_wv_f64m2_rm_m (mask, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwadd_wf_f32m1_rm (vfloat64m2_t op1, float32_t op2, size_t vl) { + return __riscv_vfwadd_wf_f64m2_rm (op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwadd_wf_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, float32_t op2, + size_t vl) { + return __riscv_vfwadd_wf_f64m2_rm_m (mask, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwadd_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwadd_vv_f64m2 (op1, op2, vl); +} + +vfloat64m2_t +test_vfwadd_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwadd_vv_f64m2_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwadd\.[vw][vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 10 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 8 } } */