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[2620:137:e000::1:20]) by mx.google.com with ESMTP id cr10-20020a056a000f0a00b00687589211c7si508518pfb.143.2023.08.01.06.44.00; Tue, 01 Aug 2023 06:44:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=L4QKPnB2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233313AbjHAL7H (ORCPT + 99 others); Tue, 1 Aug 2023 07:59:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232022AbjHAL7E (ORCPT ); Tue, 1 Aug 2023 07:59:04 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 255B0A1 for ; Tue, 1 Aug 2023 04:59:03 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 152E06607187; Tue, 1 Aug 2023 12:59:01 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690891141; bh=yEFNmriytfzFlnNR03nQnEhTvtOxc2/EEUJg2NG5628=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L4QKPnB2XwaoMlLjaTWMwN/F/Oxb6IlRkxf0aQhJv6Y/iCN6VzORF0WV9pNVPeSya zHBTSvZQjGQYdPKLnGaPGADUAPjaRd4IdE9dwUQ3KfHJ7ZD5kKJ/rMa7If/bEAtFwu vAXDgHmom3Z5G2q/hs451Fut5tp6ivEiooMCvZzlY5J1HdQxeqDVb3Naf9tET5tL4N lCTvH3XJ/SvQ+aLutd/k414pwxu57eKZGTSML5yI1WoUhukJ8wH2zOJLS4oM1HfWYB zMM6SrHVFm2BlgHUDrhOv8aQEk4SBYIbLc/rr8m2ULyfmJKUhaFeIIWDXZjQQrswca dZhn6s8y/GI/A== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH.Lin" , Alexandre Mergnat Subject: [PATCH v8 01/13] drm/mediatek: gamma: Adjust mtk_drm_gamma_set_common parameters Date: Tue, 1 Aug 2023 13:58:42 +0200 Message-ID: <20230801115854.150346-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773034489081294549 X-GMAIL-MSGID: 1773034489081294549 From: "Jason-JH.Lin" Adjust the parameters in mtk_drm_gamma_set_common() - add (struct device *dev) to get lut_diff from gamma's driver data - remove (bool lut_diff) and use false as default value in the function Signed-off-by: Jason-JH.Lin Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 18 ++++++++++++------ 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index cdbec79474d1..2f602f1f1c49 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -66,7 +66,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) struct mtk_disp_aal *aal = dev_get_drvdata(dev); if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(aal->regs, state, false); + mtk_gamma_set_common(NULL, aal->regs, state); } void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 2254038519e1..75045932353e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -54,7 +54,7 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool lut_diff); +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 7746dceadb20..d42cc0698d83 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -54,14 +54,24 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool lut_diff) +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { + struct mtk_disp_gamma *gamma; unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; + bool lut_diff; u32 word; u32 diff[3] = {0}; + /* If we're called from AAL, dev is NULL */ + gamma = dev ? dev_get_drvdata(dev) : NULL; + + if (gamma && gamma->data) + lut_diff = gamma->data->lut_diff; + else + lut_diff = false; + if (state->gamma_lut) { reg = readl(regs + DISP_GAMMA_CFG); reg = reg | GAMMA_LUT_EN; @@ -91,12 +101,8 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); - bool lut_diff = false; - - if (gamma->data) - lut_diff = gamma->data->lut_diff; - mtk_gamma_set_common(gamma->regs, state, lut_diff); + mtk_gamma_set_common(dev, gamma->regs, state); } void mtk_gamma_config(struct device *dev, unsigned int w, From patchwork Tue Aug 1 11:58:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129262 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2638002vqg; Tue, 1 Aug 2023 05:38:05 -0700 (PDT) X-Google-Smtp-Source: APBJJlFUD8JAG9rYgqoYAYBq85OdvhFeyrBk25F1uS6D7Ca4PC6bi7oRYEUPZIwbLZJ6Wrl1KD3n X-Received: by 2002:a05:6512:612:b0:4fb:89cd:9616 with SMTP id b18-20020a056512061200b004fb89cd9616mr2087569lfe.0.1690893485541; Tue, 01 Aug 2023 05:38:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893485; cv=none; d=google.com; s=arc-20160816; b=hEaajWECJSOy4UBWI2IB4G2wMW1w9Bp7491qwFLUlw+u6OJiVI9W3cPSwAMMugLYbK /nsJr4cyojBUdsMArNb4A+lp4lyEUUnOpYbP2Ixta2h/iEiUMR7x77PLhRuXisFK04OK t2SVw5PetLsM/bn85FpRQGosR0ShgSy3ZEXm/PlhpuzY99vXVkpScX4JjbiFvrjA9Wao QaMTEDs2OpB2rXZRrAZNXs5ZyyGwOYuf6J8cGK1LWtDrDG67E7vcjdIohX0OfTd9RmLt GhqX+9QsZBDD2u2krPCEA7g+BgZ4//ZLvyjX3yD1kHis3s2e9Xjf6541hTPe8NSSaHEy EWSw== ARC-Message-Signature: i=1; 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Lin" , Alexandre Mergnat Subject: [PATCH v8 02/13] drm/mediatek: gamma: Reduce indentation in mtk_gamma_set_common() Date: Tue, 1 Aug 2023 13:58:43 +0200 Message-ID: <20230801115854.150346-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773030327155454741 X-GMAIL-MSGID: 1773030327155454741 Invert the check for state->gamma_lut and move it at the beginning of the function to reduce indentation: this prepares the code for keeping readability on later additions. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 45 ++++++++++++----------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index d42cc0698d83..47751864bd5c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -64,6 +64,10 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt u32 word; u32 diff[3] = {0}; + /* If there's no gamma lut there's nothing to do here. */ + if (!state->gamma_lut) + return; + /* If we're called from AAL, dev is NULL */ gamma = dev ? dev_get_drvdata(dev) : NULL; @@ -72,29 +76,26 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt else lut_diff = false; - if (state->gamma_lut) { - reg = readl(regs + DISP_GAMMA_CFG); - reg = reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); - lut_base = regs + DISP_GAMMA_LUT; - lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < MTK_LUT_SIZE; i++) { - - if (!lut_diff || (i % 2 == 0)) { - word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); - } else { - diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); - - word = ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); - } - writel(word, (lut_base + i * 4)); + reg = readl(regs + DISP_GAMMA_CFG); + reg = reg | GAMMA_LUT_EN; + writel(reg, regs + DISP_GAMMA_CFG); + lut_base = regs + DISP_GAMMA_LUT; + lut = (struct drm_color_lut *)state->gamma_lut->data; + for (i = 0; i < MTK_LUT_SIZE; i++) { + if (!lut_diff || (i % 2 == 0)) { + word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + + ((lut[i].blue >> 6) & LUT_10BIT_MASK); + } else { + diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); + diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); + diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + + word = ((diff[0] & LUT_10BIT_MASK) << 20) + + ((diff[1] & LUT_10BIT_MASK) << 10) + + (diff[2] & LUT_10BIT_MASK); } + writel(word, (lut_base + i * 4)); } } From patchwork Tue Aug 1 11:58:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129257 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2633592vqg; Tue, 1 Aug 2023 05:30:14 -0700 (PDT) X-Google-Smtp-Source: APBJJlEUDHsEAv80YXCQGxGEWDwkDpjftDDrguXj7IHc1BDvnozEftC4INlqUfxSADPUGVSIMZHq X-Received: by 2002:a05:6e02:1288:b0:348:dd48:e9d4 with SMTP id y8-20020a056e02128800b00348dd48e9d4mr10739346ilq.1.1690893014449; Tue, 01 Aug 2023 05:30:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893014; cv=none; d=google.com; s=arc-20160816; b=UPkZEIaBMX6dR3Vwyo6g5ukUzVEsfKn1jWVOVQGdq0L3/g5PdIAGL6qV8/bNbyLTDK E3Est67aXu6RfI2gmXgFNsvAZxu3DGFFbaBVLD1lIp0ykSha9YRSZGrpysFZw0XOtuCA j526qVsFaztkwtc2T28vaPKYkek3nJ7JNt1cNaqwv6vdulEN7gLfY/SRy306mlWBUaEE 2+R6so9pTa+5X4ro6KeVAFsPfZG9OQNelmiOQkuIlmQsWsg5yfPE1NAFKtSuaSxqr8q9 +n9Oww/IcZS5nx/EDHDp5cpzjo8XdqPTaqpXYWkPiHaNriQEhU/oknBX9ufG8S5eAkw7 x8lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PWoSwFjG7rgHKj+hwnk9WzTII4uES9Ilel8KWGig5EY=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=F7VqWuxU0zZKms0Jwo/3IL2qLma60pRlMqVBGh8MJ9tocIoFv5NwaunfwBNhyGzwl3 StYZROEx09kq9k5FvkSRQYt7dmlJIp2aTDdcqaymZg8f8RWjOslMVQjZyskVoiJItl2B jMv/uwcVYRyGIx+L8z9YDQWszpGU0HD4KvbPUbgnMog+8g9E1hTGINNWNsqSYx71+fu7 HiKIJCQYsXRmF6Gzluq7uphrGx93fYhHvgVvmWEGaEQxmc5Q/3xpQ7C7lnSdKupa5Qgz lI/ddhLw1C8TY2WbVcE+H3hxEWn8nIytB4AEVdfYeorylAevrR86zuX39fAx/GYKI0ZJ lDSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=DHoU9Cd4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v8 03/13] drm/mediatek: gamma: Support SoC specific LUT size Date: Tue, 1 Aug 2023 13:58:44 +0200 Message-ID: <20230801115854.150346-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773029833443805175 X-GMAIL-MSGID: 1773029833443805175 Newer SoCs support a bigger Gamma LUT table: wire up a callback to retrieve the correct LUT size for each different Gamma IP. Co-developed-by: Jason-JH.Lin Signed-off-by: Jason-JH.Lin [Angelo: Rewritten commit message/description + porting] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 19 +++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 5 ++++- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 17 ++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 8 ++++++-- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 - drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++++++ 7 files changed, 52 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index 2f602f1f1c49..e390ccfdee18 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -19,7 +19,7 @@ #define AAL_EN BIT(0) #define DISP_AAL_SIZE 0x0030 #define DISP_AAL_OUTPUT_SIZE 0x04d8 - +#define DISP_AAL_LUT_SIZE 512 struct mtk_disp_aal_data { bool has_gamma; @@ -61,12 +61,27 @@ void mtk_aal_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); } +/** + * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL + * @dev: Pointer to struct device + * + * Return: 0 if gamma control not supported in AAL or gamma LUT size + */ +unsigned int mtk_aal_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_aal *aal = dev_get_drvdata(dev); + + if (aal->data && aal->data->has_gamma) + return DISP_AAL_LUT_SIZE; + return 0; +} + void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_aal *aal = dev_get_drvdata(dev); if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(NULL, aal->regs, state); + mtk_gamma_set_common(NULL, aal->regs, state, DISP_AAL_LUT_SIZE); } void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 75045932353e..f57aec688e25 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -17,6 +17,7 @@ void mtk_aal_clk_disable(struct device *dev); void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_aal_gamma_get_lut_size(struct device *dev); void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_aal_start(struct device *dev); void mtk_aal_stop(struct device *dev); @@ -53,8 +54,10 @@ void mtk_gamma_clk_disable(struct device *dev); void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, + struct drm_crtc_state *state, u16 lut_size); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 47751864bd5c..bfdecb278b45 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -28,6 +28,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_size; }; /* @@ -54,7 +55,15 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } -void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) +unsigned int mtk_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + return gamma->data->lut_size; +} + +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, + struct drm_crtc_state *state, u16 lut_size) { struct mtk_disp_gamma *gamma; unsigned int i, reg; @@ -81,7 +90,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt writel(reg, regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < MTK_LUT_SIZE; i++) { + for (i = 0; i < lut_size; i++) { if (!lut_diff || (i % 2 == 0)) { word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + @@ -103,7 +112,7 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); - mtk_gamma_set_common(dev, gamma->regs, state); + mtk_gamma_set_common(dev, gamma->regs, state, gamma->data->lut_size); } void mtk_gamma_config(struct device *dev, unsigned int w, @@ -198,10 +207,12 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { .lut_diff = true, + .lut_size = 512, }; static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 8a43656ecc30..ebe0cc3a1a4c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -959,8 +959,12 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, mtk_crtc->ddp_comp[i] = comp; if (comp->funcs) { - if (comp->funcs->gamma_set) - gamma_lut_size = MTK_LUT_SIZE; + if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) { + unsigned int lut_sz = mtk_ddp_gamma_get_lut_size(comp); + + if (lut_sz) + gamma_lut_size = lut_sz; + } if (comp->funcs->ctm_set) has_ctm = true; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h index 3e9046993d09..b2e50292e57d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -10,7 +10,6 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_plane.h" -#define MTK_LUT_SIZE 512 #define MTK_MAX_BPC 10 #define MTK_MIN_BPC 3 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index f114da4d36a9..f3212e08f2cd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -271,6 +271,7 @@ static void mtk_ufoe_start(struct device *dev) static const struct mtk_ddp_comp_funcs ddp_aal = { .clk_enable = mtk_aal_clk_enable, .clk_disable = mtk_aal_clk_disable, + .gamma_get_lut_size = mtk_aal_gamma_get_lut_size, .gamma_set = mtk_aal_gamma_set, .config = mtk_aal_config, .start = mtk_aal_start, @@ -322,6 +323,7 @@ static const struct mtk_ddp_comp_funcs ddp_dsi = { static const struct mtk_ddp_comp_funcs ddp_gamma = { .clk_enable = mtk_gamma_clk_enable, .clk_disable = mtk_gamma_clk_disable, + .gamma_get_lut_size = mtk_gamma_get_lut_size, .gamma_set = mtk_gamma_set, .config = mtk_gamma_config, .start = mtk_gamma_start, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index febcaeef16a1..c1355960e195 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -67,6 +67,7 @@ struct mtk_ddp_comp_funcs { void (*layer_config)(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); + unsigned int (*gamma_get_lut_size)(struct device *dev); void (*gamma_set)(struct device *dev, struct drm_crtc_state *state); void (*bgclr_in_on)(struct device *dev); @@ -186,6 +187,14 @@ static inline void mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp, comp->funcs->layer_config(comp->dev, idx, state, cmdq_pkt); } +static inline unsigned int mtk_ddp_gamma_get_lut_size(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->gamma_get_lut_size) + return comp->funcs->gamma_get_lut_size(comp->dev); + + return 0; +} + static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { From patchwork Tue Aug 1 11:58:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129292 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2651110vqg; Tue, 1 Aug 2023 06:02:50 -0700 (PDT) X-Google-Smtp-Source: APBJJlEKdHVcA8xinz2ew6iycppwx+X7S/gMjuvRsyOfTxDyQ7PV3/NT68t+iNVgf7mzZGm8Pzd2 X-Received: by 2002:a17:902:d382:b0:1bb:aa83:f848 with SMTP id e2-20020a170902d38200b001bbaa83f848mr12507712pld.43.1690894969524; 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Lin" , Alexandre Mergnat Subject: [PATCH v8 04/13] drm/mediatek: gamma: Improve and simplify HW LUT calculation Date: Tue, 1 Aug 2023 13:58:45 +0200 Message-ID: <20230801115854.150346-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773031883899897523 X-GMAIL-MSGID: 1773031883899897523 Use drm_color_lut_extract() to avoid open-coding the bits reduction calculations for each color channel and use a struct drm_color_lut to temporarily store the information instead of an array of u32. Also, slightly improve the precision of the HW LUT calculation in the LUT DIFF case by performing the subtractions on the 16-bits values and doing the 10 bits conversion later. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 30 +++++++++++++++-------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index bfdecb278b45..1e21dd92c88b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -71,7 +71,6 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, void __iomem *lut_base; bool lut_diff; u32 word; - u32 diff[3] = {0}; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -91,18 +90,29 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; for (i = 0; i < lut_size; i++) { + struct drm_color_lut diff, hwlut; + + hwlut.red = drm_color_lut_extract(lut[i].red, 10); + hwlut.green = drm_color_lut_extract(lut[i].green, 10); + hwlut.blue = drm_color_lut_extract(lut[i].blue, 10); + if (!lut_diff || (i % 2 == 0)) { - word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); + word = hwlut.red << 20 + + hwlut.green << 10 + + hwlut.red; } else { - diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + diff.red = lut[i].red - lut[i - 1].red; + diff.red = drm_color_lut_extract(diff.red, 10); + + diff.green = lut[i].green - lut[i - 1].green; + diff.green = drm_color_lut_extract(diff.green, 10); + + diff.blue = lut[i].blue - lut[i - 1].blue; + diff.blue = drm_color_lut_extract(diff.blue, 10); - word = ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); + word = diff.blue << 20 + + diff.green << 10 + + diff.red; } writel(word, (lut_base + i * 4)); } From patchwork Tue Aug 1 11:58:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129266 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2639870vqg; Tue, 1 Aug 2023 05:41:57 -0700 (PDT) X-Google-Smtp-Source: APBJJlGaSxZ02bAzCsLttzjtu+mj/aQFI+GW1uljN5DJuD8wShshPUXzj1v4VnguS8WbWu6n3LXU X-Received: by 2002:a17:906:1c:b0:99b:658e:3941 with SMTP id 28-20020a170906001c00b0099b658e3941mr2269430eja.70.1690893716942; Tue, 01 Aug 2023 05:41:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893716; cv=none; d=google.com; s=arc-20160816; b=w3WO9Ewlc3zYKsSckDJ8Ji/KxRH/SBLtFCu4lQ0wPGIRTfTT+GvKKf7qIb/wNFO87Q IewhLYdtHOi9/g9POPQ0phZxEvrhD3wqw69JC+kdw2X5za5tRmxtYgTJR4lQOUS2uOtS nx5dfZwpD94RHc8dyjDOBVhyrrQtS2i/K6pp18t1mIrjWfkq3rG9U1nTYowgZ/MQ7Mbg iIffW6SqdadjjghwoQWZ19b+n9ax//UC6H2EgkBJGxSPfyEIw1xwD2wszhYDPGCGvPIj yz5cLEb79fEXhxlAnxCkTDwnXGdmfxUoAXwp0So6h+prO1eTvsB8jymtqzhZMOViniOq KKSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Pf70fvzsJsLSLLCAyU+4FIZliXpAbtyiev+VloddWXU=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=RDyYpXH6bf4inrIsdmTRHIykxvdQF85SKT1Bk33+XU98fBvz7GSqHhiBkjn6/ZPD4D /F5rk9Ss6xAyyL2XG6Ci4zoWry5vYlQQ/GZBgznhaPu8DHioG1YJmbd3EQSzDm5gxlfF 3Dv9WyZMOG1zRuRihTlkb1E4hjkyTs+P4Xo6E7KMXwdFeomiNn93sAcbgtuqqiDSJ+D9 rvljhHhMWoSwdcW4+SYgWbHevtDaY0YChh0z3F9oWvdE63HL1+cK5WFHj8/BzkTK/9FC JqfdmhMbjj9yr8NU6s2Zky+Ay0Ia3bJoCT0+fksVEUh3rGJVAemQN8sC2DmyLDc5tHAr 2NhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=VdVADUYa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v8 05/13] drm/mediatek: gamma: Enable the Gamma LUT table only after programming Date: Tue, 1 Aug 2023 13:58:46 +0200 Message-ID: <20230801115854.150346-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773030569891841547 X-GMAIL-MSGID: 1773030569891841547 Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after programming the actual table to avoid potential visual glitches during table modification. Note: GAMMA should get enabled in between vblanks, but this requires many efforts in order to make this happen, as that requires migrating all of the writes to make use of CMDQ instead of cpu writes and that's not trivial. For this reason, this patch only moves the LUT enable. The CMDQ rework will come at a later time. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 1e21dd92c88b..b9dc8754187d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -66,11 +66,11 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state, u16 lut_size) { struct mtk_disp_gamma *gamma; - unsigned int i, reg; + unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; - u32 word; + u32 cfg_val, word; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -84,9 +84,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, else lut_diff = false; - reg = readl(regs + DISP_GAMMA_CFG); - reg = reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); + cfg_val = readl(regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; for (i = 0; i < lut_size; i++) { @@ -116,6 +114,11 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, } writel(word, (lut_base + i * 4)); } + + /* Enable the gamma table */ + cfg_val = cfg_val | GAMMA_LUT_EN; + + writel(cfg_val, regs + DISP_GAMMA_CFG); } void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) From patchwork Tue Aug 1 11:58:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129272 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2640894vqg; Tue, 1 Aug 2023 05:43:56 -0700 (PDT) X-Google-Smtp-Source: APBJJlHshYqTA9m3KxnAaggeioqT8MWOLQulMvMEsYQ4chovUeJcOzZYyyDIoAdGfGbl4ewWwICC X-Received: by 2002:aa7:c616:0:b0:522:2711:863 with SMTP id h22-20020aa7c616000000b0052227110863mr2684699edq.1.1690893836150; Tue, 01 Aug 2023 05:43:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893836; cv=none; d=google.com; s=arc-20160816; b=Ff/Z/VQ6sDusFm3c5cExMpI7O++gDNHeFP2+0SThrmzr9EW7ytjAtfoCQtGbeHZTdl Qwhfw3E0rbNrW/qhZWRFheXN4yVimUvf2wcs+oYchlukYEFtsiqsCl/nLorXGChTcviU FFzIS3iqkx9xGtZAa8AE/yLilm5UnlPB0xFWcmrDs4bsIQb9c91SKJNrEiYoGYqfxqt5 bJmeVc4Ob0v3a+WVTyAeM0C866fEmesFJ3edJwlPvRH+UwcILSwVVOqL2m30U61nGBkv x2680p/82zIuveYoIFovWdxAdRoiioUVfMZteYF/tgVKUpdvEtpOOJJ6sunSKQD3u5IX ZKSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=o9Pu/IQwVvSKv7AS8sSkHsMqYz5XPVZGxLsslDDucN8=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=yHLiMXiRfwQRBiPa0OlTlYC9oKNyA2YBjA5IFAVNL1cAzw4+2j3tUQE/rtf7V+YeZo YEw0wQzpVeWOyhgtHFZ5aybM5isFdNlkxZ3T6okau5jPFBlV19Q60EoIY2yf+yn0zyz2 RHxzVczEpW4AqoP1AAZHyVOpJY/Jv/e2pOAa9eU6XtwElByxAjrJvBY4vfjvUIdD+ThU /jaI5o14fGVD21TJmhHbbVpPzG59ebclMHjXHnmo40uwx/CGCRAZQJSMhKKtbHktWio3 ZewPG/Bfr22vhbbXybHLyR+e/G3mVXXxt48mQwfNgUs10O7MR+CZwF7j4jlUaGXfGk3B 7rmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=fG5q2AQX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v8 06/13] drm/mediatek: gamma: Use bitfield macros Date: Tue, 1 Aug 2023 13:58:47 +0200 Message-ID: <20230801115854.150346-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773030694989154108 X-GMAIL-MSGID: 1773030694989154108 Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. While at it, also add a definition for LUT_BITS_DEFAULT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 41 ++++++++++++++--------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index b9dc8754187d..4f642fed432f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ +#include #include #include #include @@ -21,9 +22,16 @@ #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 +#define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) +#define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) +#define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) +#define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) + #define LUT_10BIT_MASK 0x03ff +#define LUT_BITS_DEFAULT 10 struct mtk_disp_gamma_data { bool has_dither; @@ -90,33 +98,33 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, for (i = 0; i < lut_size; i++) { struct drm_color_lut diff, hwlut; - hwlut.red = drm_color_lut_extract(lut[i].red, 10); - hwlut.green = drm_color_lut_extract(lut[i].green, 10); - hwlut.blue = drm_color_lut_extract(lut[i].blue, 10); + hwlut.red = drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); + hwlut.green = drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); + hwlut.blue = drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); if (!lut_diff || (i % 2 == 0)) { - word = hwlut.red << 20 + - hwlut.green << 10 + - hwlut.red; + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red = lut[i].red - lut[i - 1].red; - diff.red = drm_color_lut_extract(diff.red, 10); + diff.red = drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); diff.green = lut[i].green - lut[i - 1].green; - diff.green = drm_color_lut_extract(diff.green, 10); + diff.green = drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); diff.blue = lut[i].blue - lut[i - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, 10); + diff.blue = drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); - word = diff.blue << 20 + - diff.green << 10 + - diff.red; + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); } writel(word, (lut_base + i * 4)); } /* Enable the gamma table */ - cfg_val = cfg_val | GAMMA_LUT_EN; + cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); writel(cfg_val, regs + DISP_GAMMA_CFG); } @@ -133,9 +141,12 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + u32 sz; + + sz = FIELD_PREP(DISP_GAMMA_SIZE_HSIZE, w); + sz |= FIELD_PREP(DISP_GAMMA_SIZE_VSIZE, h); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, - DISP_GAMMA_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZE); if (gamma->data && gamma->data->has_dither) mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, GAMMA_DITHERING, cmdq_pkt); From patchwork Tue Aug 1 11:58:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129291 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2651073vqg; Tue, 1 Aug 2023 06:02:47 -0700 (PDT) X-Google-Smtp-Source: APBJJlGWhMTw0x4XzZdOSWenaCjGJEoLqHRy7EMh31vfWqsVVH4ri08wlo9daNMjai/TtJSRxYyG X-Received: by 2002:a17:90b:23ce:b0:262:e589:678f with SMTP id md14-20020a17090b23ce00b00262e589678fmr16435732pjb.10.1690894967212; Tue, 01 Aug 2023 06:02:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690894967; cv=none; d=google.com; s=arc-20160816; b=lfj2ADEJTtlQGfs8vy8L7lzUQI6cyQgCIhD8203SDJQz6AQwh+nLmb17CvIT0kwLCG Q/3sEIVItKF9CJcMvLiz4dmauYDUdDfFW3rnR8uNkAi+vOr3vvQOKTI8dIKJ4hdLQyS8 SGP2cMLwsNgvl3v1NAgX5GNSiblv/g2YLPEBlAm9KIC5rqGGHe0YFG/AIqAiPKEt/UYN R5P04gAflEOwn7GBVH/KQD1sCCcnY0OMhuYTmQv/R/0FZMoKx5RPNS+ckmAEN/rr/4ut BOg4+ATysbrfGasoIkWU4JfRPlywCYRSQFTEh5rnHD4PqSyHVc6Wfh1NXKnQKAJNl1G8 UNqg== ARC-Message-Signature: i=1; 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Lin" , Alexandre Mergnat Subject: [PATCH v8 07/13] drm/mediatek: gamma: Support specifying number of bits per LUT component Date: Tue, 1 Aug 2023 13:58:48 +0200 Message-ID: <20230801115854.150346-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773031880832548534 X-GMAIL-MSGID: 1773031880832548534 New SoCs, like MT8195, not only may support bigger lookup tables, but have got a different register layout to support bigger precision: support specifying the number of `lut_bits` for each SoC and use it in mtk_gamma_set_common() to perform the right calculation. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 4f642fed432f..a6f7af1a9e8e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -37,6 +37,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; u16 lut_size; + u8 lut_bits; }; /* @@ -78,6 +79,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; + u8 lut_bits; u32 cfg_val, word; /* If there's no gamma lut there's nothing to do here. */ @@ -87,10 +89,13 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, /* If we're called from AAL, dev is NULL */ gamma = dev ? dev_get_drvdata(dev) : NULL; - if (gamma && gamma->data) + if (gamma && gamma->data) { lut_diff = gamma->data->lut_diff; - else + lut_bits = gamma->data->lut_bits; + } else { lut_diff = false; + lut_bits = LUT_BITS_DEFAULT; + } cfg_val = readl(regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; @@ -98,9 +103,9 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, for (i = 0; i < lut_size; i++) { struct drm_color_lut diff, hwlut; - hwlut.red = drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); - hwlut.green = drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); - hwlut.blue = drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); + hwlut.red = drm_color_lut_extract(lut[i].red, lut_bits); + hwlut.green = drm_color_lut_extract(lut[i].green, lut_bits); + hwlut.blue = drm_color_lut_extract(lut[i].blue, lut_bits); if (!lut_diff || (i % 2 == 0)) { word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); @@ -108,13 +113,13 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red = lut[i].red - lut[i - 1].red; - diff.red = drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); + diff.red = drm_color_lut_extract(diff.red, lut_bits); diff.green = lut[i].green - lut[i - 1].green; - diff.green = drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); + diff.green = drm_color_lut_extract(diff.green, lut_bits); diff.blue = lut[i].blue - lut[i - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); + diff.blue = drm_color_lut_extract(diff.blue, lut_bits); word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); @@ -231,10 +236,12 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_bits = 10, .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { + .lut_bits = 10, .lut_diff = true, .lut_size = 512, }; From patchwork Tue Aug 1 11:58:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129261 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2637888vqg; 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Lin" , Alexandre Mergnat Subject: [PATCH v8 08/13] drm/mediatek: gamma: Support multi-bank gamma LUT Date: Tue, 1 Aug 2023 13:58:49 +0200 Message-ID: <20230801115854.150346-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773030314063348825 X-GMAIL-MSGID: 1773030314063348825 Newer Gamma IP have got multiple LUT banks: support specifying the size of the LUT banks and handle bank-switching before programming the LUT in mtk_gamma_set_common() in preparation for adding support for MT8195 and newer SoCs. Suggested-by: Jason-JH.Lin [Angelo: Refactored original commit] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 73 +++++++++++++++-------- 1 file changed, 47 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index a6f7af1a9e8e..fb7c3650a9f7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -24,6 +24,8 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) +#define DISP_GAMMA_BANK 0x0100 +#define DISP_GAMMA_BANK_BANK GENMASK(1, 0) #define DISP_GAMMA_LUT 0x0700 #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) @@ -32,10 +34,12 @@ #define LUT_10BIT_MASK 0x03ff #define LUT_BITS_DEFAULT 10 +#define LUT_BANK_SIZE_DEFAULT 512 struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_bank_size; u16 lut_size; u8 lut_bits; }; @@ -80,7 +84,9 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, void __iomem *lut_base; bool lut_diff; u8 lut_bits; - u32 cfg_val, word; + u16 lut_bank_size; + u32 cfg_val, lbank_val, word; + int cur_bank, num_lut_banks; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -91,41 +97,54 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, if (gamma && gamma->data) { lut_diff = gamma->data->lut_diff; + lut_bank_size = gamma->data->lut_bank_size; lut_bits = gamma->data->lut_bits; } else { lut_diff = false; + lut_bank_size = LUT_BANK_SIZE_DEFAULT; lut_bits = LUT_BITS_DEFAULT; } + num_lut_banks = lut_size / lut_bank_size; cfg_val = readl(regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < lut_size; i++) { - struct drm_color_lut diff, hwlut; - - hwlut.red = drm_color_lut_extract(lut[i].red, lut_bits); - hwlut.green = drm_color_lut_extract(lut[i].green, lut_bits); - hwlut.blue = drm_color_lut_extract(lut[i].blue, lut_bits); - - if (!lut_diff || (i % 2 == 0)) { - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); - } else { - diff.red = lut[i].red - lut[i - 1].red; - diff.red = drm_color_lut_extract(diff.red, lut_bits); - - diff.green = lut[i].green - lut[i - 1].green; - diff.green = drm_color_lut_extract(diff.green, lut_bits); - - diff.blue = lut[i].blue - lut[i - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, lut_bits); - - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + for (cur_bank = 0; cur_bank < num_lut_banks; cur_bank++) { + + /* Switch gamma bank and set data mode before writing LUT */ + if (num_lut_banks > 1) { + lbank_val = FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + writel(lbank_val, regs + DISP_GAMMA_BANK); + } + + for (i = 0; i < lut_bank_size; i++) { + int n = (cur_bank * lut_bank_size) + i; + struct drm_color_lut diff, hwlut; + + hwlut.red = drm_color_lut_extract(lut[n].red, lut_bits); + hwlut.green = drm_color_lut_extract(lut[n].green, lut_bits); + hwlut.blue = drm_color_lut_extract(lut[n].blue, lut_bits); + + if (!lut_diff || (i % 2 == 0)) { + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } else { + diff.red = lut[n].red - lut[n - 1].red; + diff.red = drm_color_lut_extract(diff.red, lut_bits); + + diff.green = lut[n].green - lut[n - 1].green; + diff.green = drm_color_lut_extract(diff.green, lut_bits); + + diff.blue = lut[n].blue - lut[n - 1].blue; + diff.blue = drm_color_lut_extract(diff.blue, lut_bits); + + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } + writel(word, (lut_base + i * 4)); } - writel(word, (lut_base + i * 4)); } /* Enable the gamma table */ @@ -236,11 +255,13 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_bank_size = 512, .lut_bits = 10, .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { + .lut_bank_size = 512, .lut_bits = 10, .lut_diff = true, .lut_size = 512, From patchwork Tue Aug 1 11:58:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129351 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2749586vqg; Tue, 1 Aug 2023 08:32:46 -0700 (PDT) X-Google-Smtp-Source: APBJJlHI9UuuUwfcJ/tF9IXTboZiigffvWm0pAkJH/ypCunBxubemacDg9S4QPZBURT969oIeyw2 X-Received: by 2002:a17:90b:e15:b0:268:6060:c184 with SMTP id ge21-20020a17090b0e1500b002686060c184mr10816486pjb.45.1690903966307; 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Lin" , Alexandre Mergnat Subject: [PATCH v8 09/13] drm/mediatek: gamma: Add support for 12-bit LUT and MT8195 Date: Tue, 1 Aug 2023 13:58:50 +0200 Message-ID: <20230801115854.150346-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773041317631061757 X-GMAIL-MSGID: 1773041317631061757 Add support for 12-bit gamma lookup tables and introduce the first user for it: MT8195. While at it, also reorder the variables in mtk_gamma_set_common() and rename `lut_base` to `lut0_base` to improve readability. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 77 +++++++++++++++++++---- 1 file changed, 64 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index fb7c3650a9f7..12614cc26bf8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -26,12 +26,20 @@ #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_BANK 0x0100 #define DISP_GAMMA_BANK_BANK GENMASK(1, 0) +#define DISP_GAMMA_BANK_DATA_MODE BIT(2) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT1 0x0b00 +/* For 10 bit LUT layout, R/G/B are in the same register */ #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) #define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) #define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) +/* For 12 bit LUT layout, R/G are in LUT, B is in LUT1 */ +#define DISP_GAMMA_LUT_12BIT_R GENMASK(11, 0) +#define DISP_GAMMA_LUT_12BIT_G GENMASK(23, 12) +#define DISP_GAMMA_LUT_12BIT_B GENMASK(11, 0) + #define LUT_10BIT_MASK 0x03ff #define LUT_BITS_DEFAULT 10 #define LUT_BANK_SIZE_DEFAULT 512 @@ -75,18 +83,34 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return gamma->data->lut_size; } +/* + * SoCs supporting 12-bits LUTs are using a new register layout that does + * always support (by HW) both 12-bits and 10-bits LUT but, on those, we + * ignore the support for 10-bits in this driver and always use 12-bits. + * + * Summarizing: + * - SoC HW support 9/10-bits LUT only + * - Old register layout + * - 10-bits LUT supported + * - 9-bits LUT not supported + * - SoC HW support both 10/12bits LUT + * - New register layout + * - 12-bits LUT supported + * - 10-its LUT not supported + */ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state, u16 lut_size) { struct mtk_disp_gamma *gamma; - unsigned int i; + void __iomem *lut0_base = regs + DISP_GAMMA_LUT; + void __iomem *lut1_base = regs + DISP_GAMMA_LUT1; + u32 cfg_val, data_mode, lbank_val, word[2]; + int cur_bank, num_lut_banks; struct drm_color_lut *lut; - void __iomem *lut_base; + u16 lut_bank_size; + unsigned int i; bool lut_diff; u8 lut_bits; - u16 lut_bank_size; - u32 cfg_val, lbank_val, word; - int cur_bank, num_lut_banks; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -107,13 +131,17 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, num_lut_banks = lut_size / lut_bank_size; cfg_val = readl(regs + DISP_GAMMA_CFG); - lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; + + /* Switch to 12 bits data mode if supported */ + data_mode = FIELD_PREP(DISP_GAMMA_BANK_DATA_MODE, !!(lut_bits == 12)); + for (cur_bank = 0; cur_bank < num_lut_banks; cur_bank++) { /* Switch gamma bank and set data mode before writing LUT */ if (num_lut_banks > 1) { lbank_val = FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + lbank_val |= data_mode; writel(lbank_val, regs + DISP_GAMMA_BANK); } @@ -126,9 +154,15 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, hwlut.blue = drm_color_lut_extract(lut[n].blue, lut_bits); if (!lut_diff || (i % 2 == 0)) { - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + if (lut_bits == 12) { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, hwlut.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, hwlut.green); + word[1] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, hwlut.blue); + } else { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } } else { diff.red = lut[n].red - lut[n - 1].red; diff.red = drm_color_lut_extract(diff.red, lut_bits); @@ -139,11 +173,19 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, diff.blue = lut[n].blue - lut[n - 1].blue; diff.blue = drm_color_lut_extract(diff.blue, lut_bits); - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + if (lut_bits == 12) { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, diff.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, diff.green); + word[1] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, diff.blue); + } else { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } } - writel(word, (lut_base + i * 4)); + writel(word[0], (lut0_base + i * 4)); + if (lut_bits == 12) + writel(word[1], (lut1_base + i * 4)); } } @@ -267,11 +309,20 @@ static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { .lut_size = 512, }; +static const struct mtk_disp_gamma_data mt8195_gamma_driver_data = { + .lut_bank_size = 256, + .lut_bits = 12, + .lut_diff = true, + .lut_size = 1024, +}; + static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { { .compatible = "mediatek,mt8173-disp-gamma", .data = &mt8173_gamma_driver_data}, { .compatible = "mediatek,mt8183-disp-gamma", .data = &mt8183_gamma_driver_data}, + { .compatible = "mediatek,mt8195-disp-gamma", + .data = &mt8195_gamma_driver_data}, {}, }; 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Lin" , Alexandre Mergnat Subject: [PATCH v8 10/13] drm/mediatek: gamma: Make sure relay mode is disabled Date: Tue, 1 Aug 2023 13:58:51 +0200 Message-ID: <20230801115854.150346-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773031107545473914 X-GMAIL-MSGID: 1773031107545473914 Disable relay mode at the end of LUT programming to make sure that the processed image goes through. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 12614cc26bf8..6591797ed10c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -19,6 +19,7 @@ #define DISP_GAMMA_EN 0x0000 #define GAMMA_EN BIT(0) #define DISP_GAMMA_CFG 0x0020 +#define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 @@ -192,6 +193,9 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); + /* Disable RELAY mode to pass the processed image */ + cfg_val &= ~GAMMA_RELAY_MODE; + writel(cfg_val, regs + DISP_GAMMA_CFG); } From patchwork Tue Aug 1 11:58:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129335 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2731701vqg; Tue, 1 Aug 2023 08:06:47 -0700 (PDT) X-Google-Smtp-Source: APBJJlEcVnXL38MCKxDPUEhK9hAN2ZxIPEhL4edP8oEYq8bo/lWukJl0/dk3U+RZsrjNYVAuQfdF X-Received: by 2002:a05:6a20:394d:b0:134:a4e2:4ac8 with SMTP id r13-20020a056a20394d00b00134a4e24ac8mr13674493pzg.39.1690902407055; Tue, 01 Aug 2023 08:06:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690902406; cv=none; d=google.com; s=arc-20160816; b=ZcGFxGfP1AIQefhlnBX8WQ1phycBPV6YRmX8fI9onphuyMm0OUmk+inLHjoJ7bUZg/ HSHQdjGYkVIdJ9DuEcW/lRD93a6zSvk7gBvTU5eXLmhJkATn57WHqJ1PcRLiuts8gBSc W1ERvUrZmeYInQRrmwNGvhDe39vCS2cgrkoYTIO7SV3n1QlfUNrFUYYhWl2DtTyf69EQ IwcjgrP6qdDgmpWKzdIGoXYCAzEqiXqDmWQc2bZfV13f8iuu8qrPC3WqCQvl0DPi+r7M VaAe54SFi3UZjCTx7tRnqIxPDUW3PTORKJktr5LQK8mdfBYE5LVF9x1MGGNP3aPs7TGU YzAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UNihVARbpmZ5nC9MOnplVf6/4JU0g8pcltwHqI+PhG8=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=fzj5Ybz8ArGjwWLT2t+YN76LnzNZxugEaVndvHHGrT9Ho2KDhAy7oGIn0qfgP78p69 eamKHcyypZKVcpWm8hxA9ia4qvjJzRjmbW9ltm7V/WGVychk8hd6afJgMgpstVgVrm7E wJDT1HQpoehD+awO2GrY2JNhEdBnsv5/9tlET4GMyA+xT1TseEgIhZu7yanZOUW4OIKe Am2wEE1E7NwqQzR86JZyDxCyVePQxZ5h097MrRxNhjcZH3BrRzaZKwuNi4781tqAGlQU IhMZxYNDKLGfrqMk7EovoeqfKIqKex03vIb4kMUF+TWN4XC3TIO9sDDuY9H5lcyEsKHQ QY5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=hI5DV91Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v8 11/13] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Tue, 1 Aug 2023 13:58:52 +0200 Message-ID: <20230801115854.150346-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773039682264726789 X-GMAIL-MSGID: 1773039682264726789 All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 6591797ed10c..c6b77ca3e655 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -22,6 +22,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -84,6 +85,16 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return gamma->data->lut_size; } +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut_size) +{ + u64 first, last; + + first = lut[0].red + lut[0].green + lut[0].blue; + last = lut[lut_size].red + lut[lut_size].green + lut[lut_size].blue; + + return !!(first > last); +} + /* * SoCs supporting 12-bits LUTs are using a new register layout that does * always support (by HW) both 12-bits and 10-bits LUT but, on those, we @@ -190,6 +201,14 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, } } + if (gamma && gamma->data && !gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, lut_size)) + cfg_val |= FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &= ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); From patchwork Tue Aug 1 11:58:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129308 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2679456vqg; Tue, 1 Aug 2023 06:46:15 -0700 (PDT) X-Google-Smtp-Source: APBJJlGbkzrPeVBgkDJElgIEAlFxAbEV8UOUk3maVROSOcV9z4zaD1/NAsLd8k759wis/VgPBHnd X-Received: by 2002:a17:902:dad2:b0:1b8:9b1b:ae7a with SMTP id q18-20020a170902dad200b001b89b1bae7amr13481890plx.34.1690897574626; Tue, 01 Aug 2023 06:46:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690897574; cv=none; d=google.com; s=arc-20160816; b=hjOdjFpB3C+gzw8y6L+vJY2h+VEWwpEKVsLqI5RMpuj/0zAwcwGde9nk/EfWYQEr8d BFxBzvJGCnIX7UapdagH/LnesqwWKfo2Jiky8FXOh/bneoQ3PXauOpC3k/Pgd4lrQ+/J NMTB+us48kHwT3W/fR2KJb/e2SIx1vat/qMtUE0j2NfmVl2s9h/DVyREFb38Tsvo0W2B XCUwrK0fKgnZh5d5j+DCdDAFJ6ubR32LYKCU+tNgxMKABRvvzKCI6W6ZsR3eEZ9U9mQg 8VpId/aoSmKpQKhmrxYmFTEg8Vsz2mBf+7cL3yg838NSy10IcJnydT8vwBS3dtzfGsAz ZXvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NFfPkXqxCAcxhlsCO3lvEUTNIXpbZ/6XZFJ4TN9K6OY=; fh=9Aon3jQEVE1p+dS8p5fghxMOlPjmNOu/O0E5mCMmCJg=; b=paQ44LREQeKz6E1Q6OywZnD5AoYTvuWlmL3fcJhGMmv+Jov9INTeZH/YuBrR07pcBy BkMkNi2L13xHpntSuFNOA1RdFuWEs8lw4iYtW4MO7lC9omibWovRcm4y7mV91Yl+NjId CLnMT6n4pe4hfcw7jXLh39DiEW2idwX9QidRL8j1yW1/72ZaGsHItXdTJJcCR84Pzmic PSr4eN/xM5+MwPslY8pO19e98YWUjZKE11iyvmrsmGvyr4pYDWuVngpWMUBA7q/V6lfv /KYTf7zzCLG9YSaIpXn0D6cs6+S4lrnqYNyMhLEyMHpx7Fppw5GjnIi9i6CUa2pj65XQ Q9lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=B5a0ffn+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j12-20020a170902da8c00b001b9e9ef7e1fsi3582312plx.346.2023.08.01.06.45.57; Tue, 01 Aug 2023 06:46:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=B5a0ffn+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234427AbjHAL7q (ORCPT + 99 others); Tue, 1 Aug 2023 07:59:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234425AbjHAL7X (ORCPT ); Tue, 1 Aug 2023 07:59:23 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 046821BF8 for ; Tue, 1 Aug 2023 04:59:13 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id EFAAB660718F; Tue, 1 Aug 2023 12:59:10 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690891151; bh=206jZKMDUUUvALUeIajtTnxov5G04xrQ/ztlKez7bcg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B5a0ffn+rzU/UghUYP4Y0t1LhRwtJPYH0jf6F5W8jRvG5y9/aQkJBS5xZyx7NLJD0 fsQEuh1Rzg1DnoMDJ83q1DNQPykpRjVBm3EXVgGFR9HdsBUXRlBV/1KRM53eTdsOUB iYNnedFRHcR4TZVkjD3vSkt+NenffRe/Kk6Aiw5lSPs7OwP0UAELpmyA9x8U/r6Q1E jV4/doB88QiIl98pZuJaz7Rga0Wb026My+EtP8LQkivf9QspWbcPsBgXEjC5GwRG7/ W9m0yZ3hQDK06uimHFp0UXcu9qYfTbRxQrBxtOyzrlYDlfrMwdATxg7xHHXpJG3rvX JLBQBm2Qoc+yA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v8 12/13] drm/mediatek: mtk_disp_aal: Rewrite kerneldoc for struct mtk_disp_aal Date: Tue, 1 Aug 2023 13:58:53 +0200 Message-ID: <20230801115854.150346-13-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773034615182013959 X-GMAIL-MSGID: 1773034615182013959 The kerneldoc for struct mtk_disp_aal was entirely wrong: rewrite it to actually document the structure. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index e390ccfdee18..d93b97a84825 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -26,9 +26,11 @@ struct mtk_disp_aal_data { }; /** - * struct mtk_disp_aal - DISP_AAL driver structure - * @ddp_comp - structure containing type enum and hardware resources - * @crtc - associated crtc to report irq events to + * struct mtk_disp_aal - Display Adaptive Ambient Light driver structure + * @clk: clock for DISP_AAL controller + * @regs: MMIO registers base + * @cmdq_reg: CMDQ Client register + * @data: platform specific data for DISP_AAL */ struct mtk_disp_aal { struct clk *clk; From patchwork Tue Aug 1 11:58:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129268 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2640378vqg; Tue, 1 Aug 2023 05:42:59 -0700 (PDT) X-Google-Smtp-Source: APBJJlGcA9qfdQhQw2kVp1ChA31Esh4bkXVhUNWKxNnifTbfn7vC7m+7I1QIG058+/sJ+E+nxe16 X-Received: by 2002:aa7:c2d8:0:b0:51f:f079:875f with SMTP id m24-20020aa7c2d8000000b0051ff079875fmr3304780edp.4.1690893779268; Tue, 01 Aug 2023 05:42:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893779; cv=none; d=google.com; s=arc-20160816; b=IujiawgCBmIfGF73rQn6cP5asp/cRFE7jrzv/yXANJx2cIdN2CA3HIwXPFgBtiJtIv xy5+BpLRFzns0UFavxHteghVy8ZEkh/maJnEoz2vApyftNpV3tAVvzuXamDEdndNqGQk 3G5nJL5O0s/rT/WER74JFUaT+OKsA9jfq2ySd2EXcjDF913ZmqP8BDyRvU6Oye75knrF WdaqO1Ly6K55Y/UNkZ/gTIqnuQRZHpZJfalvotJIP9MzbVfYP06xC5PDMokqI7y8fhHA 8eOT++gjbsgXKPtdcOxvGAxwR21U+ByZNulRfOv22fTi+BpF8ZZKtkDNSEEbt8jw/fbP 1FXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tQTAYDiE+GfEtCgeFY9JHF01J93fSPWmXQearA4iWSs=; fh=9Aon3jQEVE1p+dS8p5fghxMOlPjmNOu/O0E5mCMmCJg=; b=QYv5NB83X+XoygqCyrsF1bcmh9GzJ46LzGJ120+NuJRbOHM7Kmsm7/z+D61Bz4ssIp sWXnb32fzEddadZHgfR8HxLKkuI0hK6OzrGVivurjw0owC4968CJ+FDQX/KVrNp3r5Wk IOuBP+vT23Zo4lufzKuXxgy5wJRCGKJ2DXppRIa/Gv0zcioFREA/xaBUMZbPZlJa+nYZ m5qdRlhfotMKHNjtA8RntICnz7rA3gSzKa6iDJqpXmjWSuFBwIp226vYwLH2ipextLdC J3sx7CgXEEecpha8a0Ye+/KKzcDJHlOBDTPSRNqdGah7Grangd9B9VCrxWxWTH62I/DO XJQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=a3R6cqlK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c22-20020a056402121600b0052239083be7si8765611edw.636.2023.08.01.05.42.34; Tue, 01 Aug 2023 05:42:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=a3R6cqlK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234441AbjHAL7s (ORCPT + 99 others); Tue, 1 Aug 2023 07:59:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234426AbjHAL7X (ORCPT ); Tue, 1 Aug 2023 07:59:23 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E10331FC6 for ; Tue, 1 Aug 2023 04:59:13 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id C19D8660719E; Tue, 1 Aug 2023 12:59:11 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690891152; bh=0jjC3Fg5s2rO0VQ/mVis11uZqJIg4LIgSGY5cW68WVw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a3R6cqlK085xUWcXg6UptkC6YQqgymple26EyBKjt8cibwdgFJLxSMb0TBo0TN9PG J9q54fpBncBXTs8/k7du/CgnSaitIeQ5LB5p+Pp3d0r3rPygOT6Kiyx5d+SpYYWz1H cSpSwaoX5rPj/yproq3zCXGXnIm9v+uDIeIQjyYTzLP9juHfwFrpGe2fIDupS4+poF GjUYeYnDVAk2WPPFmXF6QC/nFXKI+dXAyUExbLnjM1r6jp8wmZg2A+RLfSdZaIzgV9 Wa81e+0VxsNYQ59vj54uxwiu1Vd1XWhhmWN4+zGspDYbLLM6XwE03Sjn2eDZRWK3Xn eEd/Q+2OaRhCA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v8 13/13] drm/mediatek: mtk_disp_gamma: Add kerneldoc for struct mtk_disp_gamma Date: Tue, 1 Aug 2023 13:58:54 +0200 Message-ID: <20230801115854.150346-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773030635343855147 X-GMAIL-MSGID: 1773030635343855147 The mtk_disp_gamma structure was completely undocumented: add some kerneldoc documentation to it. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index c6b77ca3e655..9be1efa9766c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -54,8 +54,12 @@ struct mtk_disp_gamma_data { u8 lut_bits; }; -/* - * struct mtk_disp_gamma - DISP_GAMMA driver structure +/** + * struct mtk_disp_gamma - Display Gamma driver structure + * @clk: clock for DISP_GAMMA block + * @regs: MMIO registers base + * @cmdq_reg: CMDQ Client register + * @data: platform data for DISP_GAMMA */ struct mtk_disp_gamma { struct clk *clk;