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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t7-20020aa7d707000000b005216d397e43si4804487edq.494.2023.08.01.04.24.41; Tue, 01 Aug 2023 04:25:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3EKtAsaV; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232917AbjHAKqs (ORCPT + 99 others); Tue, 1 Aug 2023 06:46:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231462AbjHAKqp (ORCPT ); Tue, 1 Aug 2023 06:46:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 455DAF1 for ; Tue, 1 Aug 2023 03:46:44 -0700 (PDT) Message-ID: <20230801103815.207107339@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886802; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=b1myCBgZLHok+K09N26MfWzhxCP4cilngo+YbfwnshU=; b=3EKtAsaVLbSQ76mjgNoPZaN8a0q+gpf2LxDkyy04g4PJ9G4irT3JrD++brfcdfLo0clkCL MBF5nBUdLdY9uZLnJgoSVcSQA3AQnYjrXgCkwDYm9AkwfcxgWMMzHExeTXirQ+98RkahWV h1vzs/Hon5HOQFr6EJsaibwqg+yXhOrt1u9N6lCXRwDsmecSdxWS2c/6P9QjqC5Fl9pljY q9R9nvl+EZtoK9LPizB55znZF6Vat8YSntUeqS+FJrZmFopwBRwGpgFQXB6IF3Oxt+bEyN kp0/ITUptkMAWdHwzpvTuDLI4c4hxN2V0mBZ/75SvLVNSB/C2GJfdAss/ynS7w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886802; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=b1myCBgZLHok+K09N26MfWzhxCP4cilngo+YbfwnshU=; b=za6iITAafiEVp9sEOLVT4gyhWQGbxcplqujeeSs7jZCSkhpf52074QL+QC1mnYEs4IRo6/ 6yf+VwgXS47zlmCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 01/60] x86/cpu: Make identify_boot_cpu() static References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:46:42 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025733036079399 X-GMAIL-MSGID: 1773025733036079399 It's not longer used outside the source file. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/processor.h | 1 - arch/x86/kernel/cpu/common.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -190,7 +190,6 @@ static inline unsigned long long l1tf_pf } extern void early_cpu_init(void); -extern void identify_boot_cpu(void); extern void identify_secondary_cpu(struct cpuinfo_x86 *); extern void print_cpu_info(struct cpuinfo_x86 *); void print_cpu_msr(struct cpuinfo_x86 *); --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1937,7 +1937,7 @@ void enable_sep_cpu(void) } #endif -void __init identify_boot_cpu(void) +static __init void identify_boot_cpu(void) { identify_cpu(&boot_cpu_data); if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) From patchwork Tue Aug 1 10:46:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129231 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2614264vqg; Tue, 1 Aug 2023 04:57:46 -0700 (PDT) X-Google-Smtp-Source: APBJJlHAng8PDN3gnkrYY9CJCroaw3sSToChWX72Noo6I9ZeorB/Ak3oPKjg0FZG5REs1LK8bXnV X-Received: by 2002:a05:6e02:1b83:b0:348:fa75:b47b with SMTP id h3-20020a056e021b8300b00348fa75b47bmr15253333ili.19.1690891066027; Tue, 01 Aug 2023 04:57:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690891065; cv=none; d=google.com; s=arc-20160816; b=ufFlW7ossw7kHpevCdyzeiXVuqW1Tj9FhsIqwA8aIu8hFzC9ua4BH7pcw9n72ZY4Wk oNZCKaDzyf40op8uGf60IDNWwW3eQ/2ChgLb+/fbOcrVU8uvtVvaDtCzxMmO5hyIQXAW IvNVvfO8+jyfXQgbYuB+f1qUGk+vW91/tMrwe9o6u1orbcyhLFN0V7wa1ddwWFcL2LHR GHlAqgKdvSlLMYreKd03Rb0wfHUD5QaVIIxcZCVlMMRaRhXDmbVWOibylcJ2QIpyMslw 4Fuor3cbxRHd2W4RhLL7QkGTKVswaW/mL1xLVwsfaDSd8AbYNcUGOHcBpQIAPYXOAMYY jmSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=m8e6Afq1AsXnY+J/aZyhI7sMOyGQSw3ozTHH0I0x4W4=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=aYZgZ00ZpeD/R68NruT6ubv7ohfCl+XFuD0i2cKlniDhlpFcj0FygXmzPavoqfYrz/ VtY1tuZyxk2Vgefh256EspdTgzXg4YrprT3yx3NsoBdlQm+GQVBh7Zx5al7mjvyfOWwJ 8jdlA9gOSmoKmMxPdvexeYAQk9DXqRkFyGYsoTfHNjVvg57YvohPx3yKn7i+wW5NiiTo 3Gg4XwoKJcKJASQ0u+neWeQfjKFaF2ba0k+2ZKXHaW69wGQl7Ndiq674Idp8DOfvNjsn ByNfUkJcxlVcOjeA32JHJLJju+jg21MXzkUHjOS58+G/TthIavOzuTbGVE/T+hP/cxzj +HFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=A83zeqdC; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m65-20020a633f44000000b0056401aef836si8344284pga.822.2023.08.01.04.57.32; Tue, 01 Aug 2023 04:57:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=A83zeqdC; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233005AbjHAKqx (ORCPT + 99 others); Tue, 1 Aug 2023 06:46:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232474AbjHAKqq (ORCPT ); Tue, 1 Aug 2023 06:46:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A568E9 for ; Tue, 1 Aug 2023 03:46:45 -0700 (PDT) Message-ID: <20230801103815.262993621@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886804; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=m8e6Afq1AsXnY+J/aZyhI7sMOyGQSw3ozTHH0I0x4W4=; b=A83zeqdCvkwiIHahWHf9dHZtnuLP5BjrQMaHFG7yp1bCFfarwNO78PQ6fjVw8eD+1VFwrw fTQ4ns96QNS3KXnB0Akou6k/QeYit2kTBy8cH+Ksqv837WQpDa0ddQ40mEa88QtL55XY9q MY4PY/okglnfO3KtDnLIRMxGHBfplcxV8VO1Zy3yBfyV8TnK29wWFDU5VQbbNk+/8ZOPyg hfNfcWsS7mm2XI6A5lqYh60PxbzIACEgYPHVUTqxSycHwcEqQ2GtnstL75a5+RiiPOtRBz TueZNc+8NkJysVCyrfxuHTfaaSwbKjhZVC0PSQFLD4WWqDEwRA7VH/fPAiSE5w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886804; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=m8e6Afq1AsXnY+J/aZyhI7sMOyGQSw3ozTHH0I0x4W4=; b=aCmI3iiMN5es+AKUFUcjzXl3E/higAd7xogP3Aw/PM7bE7ipS6x2mO1LH7c9Vk7kOZB08V KbEK9g2up9HlPjDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 02/60] x86/cpu: Remove unused physid_*() nonsense References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:46:43 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773027790529454807 X-GMAIL-MSGID: 1773027790529454807 Tons of silly unused bitmap wrappers... Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/mpspec.h | 26 -------------------------- 1 file changed, 26 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -87,13 +87,7 @@ struct physid_mask { typedef struct physid_mask physid_mask_t; #define physid_set(physid, map) set_bit(physid, (map).mask) -#define physid_clear(physid, map) clear_bit(physid, (map).mask) #define physid_isset(physid, map) test_bit(physid, (map).mask) -#define physid_test_and_set(physid, map) \ - test_and_set_bit(physid, (map).mask) - -#define physids_and(dst, src1, src2) \ - bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC) #define physids_or(dst, src1, src2) \ bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC) @@ -101,29 +95,9 @@ typedef struct physid_mask physid_mask_t #define physids_clear(map) \ bitmap_zero((map).mask, MAX_LOCAL_APIC) -#define physids_complement(dst, src) \ - bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC) - #define physids_empty(map) \ bitmap_empty((map).mask, MAX_LOCAL_APIC) -#define physids_equal(map1, map2) \ - bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC) - -#define physids_weight(map) \ - bitmap_weight((map).mask, MAX_LOCAL_APIC) - -#define physids_shift_right(d, s, n) \ - bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC) - -#define physids_shift_left(d, s, n) \ - bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC) - -static inline unsigned long physids_coerce(physid_mask_t *map) -{ - return map->mask[0]; -} - static inline void physids_promote(unsigned long physids, physid_mask_t *map) { physids_clear(*map); From patchwork Tue Aug 1 10:46:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129240 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2617417vqg; Tue, 1 Aug 2023 05:02:52 -0700 (PDT) X-Google-Smtp-Source: APBJJlFa5FGqygoUl/6xLs+XCK34eXf4hCOhpd0OEbXiXXjaivLfaBK9CZRWlrAU/canvgDWSjkT X-Received: by 2002:a17:90b:1c87:b0:268:abf:6431 with SMTP id oo7-20020a17090b1c8700b002680abf6431mr13137534pjb.24.1690891372282; Tue, 01 Aug 2023 05:02:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690891372; cv=none; d=google.com; s=arc-20160816; b=onfkqWD4OTpEBvA2KXFbl9HMH0vSpO4sA9F0YNkhBj2PEKHvxC5pEg8Ayjs7KectPv AUKaE42j8ejdrAmwVEoA1Gt7pj95n//yKq5rT4+BnYs83I4uPHKRnPhfQ0uNkuJHxIod Qkp1I5sL8P48ZphL+V8LvBaY6WOAxT8pi96s8WWmfG7ERfC0naWZHUiaRAhNFFrB+NF8 3SX7sZr3Prc6eEZQyjcKeldVvMwZx3BhTKsZTNJTU1lcZv9rX2WK2ofRPyZhn/DY8LL1 MPftRiRCaNjeufMMc+4mk5lXczn7p/wSz/dbAjHAk5eADZskynilq38HH5OppYlgZXgJ qMiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=N2qRiZb8v2jTNGf2U89OytfeZ4DEwa0WFTfs8zeFafY=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=iLE+kfjdS79CdyEJp32XYgfh7MmKRfBw9e3E02Hr+cUVJeE/c7mLfVsZZlxhkhaoJQ H7YSyr+GfNx1f5q0ftssK9xkrKIYtsNw3YdQF7nhwt+zqU32JexQAwrY19ZB9WRsnpsX Qb87IswKYh7rR92SGZUflFXL29Wu450GUPTSA90z53vlarLSCVFpVL+9FKIjBzJ9pTmH g5FArgTtjxNe4gu3HF1rUAK77oc/JtLCU3uDuGCKa/NipjO+/r2KYohw7dCzki5EYTaI RrIsDi6EkSNTnyM493JZIwkLEXSA6Y+Zz2FiB+jlwdZ8YVg6bkmmGmQ3P+gKNweNQWb0 GZtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=hBySySXI; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id oc5-20020a17090b1c0500b00268278c51e3si149043pjb.49.2023.08.01.05.02.38; Tue, 01 Aug 2023 05:02:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=hBySySXI; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233417AbjHAKrB (ORCPT + 99 others); Tue, 1 Aug 2023 06:47:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232839AbjHAKqr (ORCPT ); Tue, 1 Aug 2023 06:46:47 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 867BDDB for ; Tue, 1 Aug 2023 03:46:46 -0700 (PDT) Message-ID: <20230801103815.318316474@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886805; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=N2qRiZb8v2jTNGf2U89OytfeZ4DEwa0WFTfs8zeFafY=; b=hBySySXITPSRAuddvTRYk7P8AsDfagY3q+oVO4ZZZtBnrMBScSm0Yt1MXvPex7x0hguwFr lR3S6gSFsghb5NLF0NEpV1JTEcGtA1Z9qZqcG+Nci/2GgSWjOVxXSMlHFVx/sI2tMfRroy ZA782q9KuuMqrfdN3PMIL1RYSZ0wqJoDJd1lO2atJzvkS1eU20mgaqr5kIDWVnnChYpbU1 yi3a0lYbExH0fn3RELSkCn3E901hOW6SJa9V6Pwj5DG9szhkuvj/PGu4elY7zxGVJWyyXK 88Xw/0/UGyaH5p08AOGbOEoIUV4XVIJuzSeAhK0cFDw6lXucpC2o2m3CJMcyzw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886805; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=N2qRiZb8v2jTNGf2U89OytfeZ4DEwa0WFTfs8zeFafY=; b=SDNS3E6r4QHLABs4rKXspJQpWQHn0LrrrFad1dG1B2NHzj3F8hKFac7g47n6u1DGNHAiUL LTTMbSdJ5tSNn4AA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 03/60] x86/apic: Rename disable_apic References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:46:45 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773028111708831404 X-GMAIL-MSGID: 1773028111708831404 It reflects a state and not a command. Make it bool while at it. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 4 ++-- arch/x86/kernel/apic/apic.c | 22 +++++++++++----------- arch/x86/kernel/apic/apic_noop.c | 6 +++--- arch/x86/kernel/apic/msi.c | 2 +- arch/x86/kernel/apic/vector.c | 2 +- arch/x86/kernel/setup.c | 2 +- arch/x86/pci/xen.c | 2 +- 7 files changed, 20 insertions(+), 20 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -52,7 +52,7 @@ static inline void generic_apic_probe(vo extern int apic_verbosity; extern int local_apic_timer_c2_ok; -extern int disable_apic; +extern bool apic_is_disabled; extern unsigned int lapic_timer_period; extern int cpuid_to_apicid[]; @@ -90,7 +90,7 @@ static inline void default_inquire_remot */ static inline bool apic_from_smp_config(void) { - return smp_found_config && !disable_apic; + return smp_found_config && !apic_is_disabled; } /* --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -180,7 +180,7 @@ static __init int setup_apicpmtimer(char #endif unsigned long mp_lapic_addr __ro_after_init; -int disable_apic __ro_after_init; +bool apic_is_disabled __ro_after_init; /* Disable local APIC timer from the kernel commandline or via dmi quirk */ static int disable_apic_timer __initdata; /* Local APIC timer works in C2 */ @@ -810,7 +810,7 @@ bool __init apic_needs_pit(void) return true; /* Is there an APIC at all or is it disabled? */ - if (!boot_cpu_has(X86_FEATURE_APIC) || disable_apic) + if (!boot_cpu_has(X86_FEATURE_APIC) || apic_is_disabled) return true; /* @@ -1299,7 +1299,7 @@ enum apic_intr_mode_id apic_intr_mode __ static int __init __apic_intr_mode_select(void) { /* Check kernel option */ - if (disable_apic) { + if (apic_is_disabled) { pr_info("APIC disabled via kernel command line\n"); return APIC_PIC; } @@ -1308,7 +1308,7 @@ static int __init __apic_intr_mode_selec #ifdef CONFIG_X86_64 /* On 64-bit, the APIC must be integrated, Check local APIC only */ if (!boot_cpu_has(X86_FEATURE_APIC)) { - disable_apic = 1; + apic_is_disabled = true; pr_info("APIC disabled by BIOS\n"); return APIC_PIC; } @@ -1317,14 +1317,14 @@ static int __init __apic_intr_mode_selec /* Neither 82489DX nor integrated APIC ? */ if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { - disable_apic = 1; + apic_is_disabled = true; return APIC_PIC; } /* If the BIOS pretends there is an integrated APIC ? */ if (!boot_cpu_has(X86_FEATURE_APIC) && APIC_INTEGRATED(boot_cpu_apic_version)) { - disable_apic = 1; + apic_is_disabled = true; pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", boot_cpu_physical_apicid); return APIC_PIC; @@ -1567,7 +1567,7 @@ static void setup_local_APIC(void) int cpu = smp_processor_id(); unsigned int value; - if (disable_apic) { + if (apic_is_disabled) { disable_ioapic_support(); return; } @@ -1943,7 +1943,7 @@ void __init check_x2apic(void) pr_err("Kernel does not support x2APIC, please recompile with CONFIG_X86_X2APIC.\n"); pr_err("Disabling APIC, expect reduced performance and functionality.\n"); - disable_apic = 1; + apic_is_disabled = true; setup_clear_cpu_cap(X86_FEATURE_APIC); } @@ -2037,7 +2037,7 @@ int __init apic_force_enable(unsigned lo { u32 h, l; - if (disable_apic) + if (apic_is_disabled) return -1; /* @@ -2064,7 +2064,7 @@ int __init apic_force_enable(unsigned lo static int __init detect_init_APIC(void) { /* Disabled by kernel option? */ - if (disable_apic) + if (apic_is_disabled) return -1; switch (boot_cpu_data.x86_vendor) { @@ -2919,7 +2919,7 @@ int apic_is_clustered_box(void) */ static int __init setup_disableapic(char *arg) { - disable_apic = 1; + apic_is_disabled = true; setup_clear_cpu_cap(X86_FEATURE_APIC); return 0; } --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -71,13 +71,13 @@ static int noop_apic_id_registered(void) static u32 noop_apic_read(u32 reg) { - WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !disable_apic); + WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !apic_is_disabled); return 0; } -static void noop_apic_write(u32 reg, u32 v) +static void noop_apic_write(u32 reg, u32 val) { - WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !disable_apic); + WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !apic_is_disabled); } #ifdef CONFIG_X86_32 --- a/arch/x86/kernel/apic/msi.c +++ b/arch/x86/kernel/apic/msi.c @@ -269,7 +269,7 @@ static const struct msi_parent_ops x86_v struct irq_domain * __init native_create_pci_msi_domain(void) { - if (disable_apic) + if (apic_is_disabled) return NULL; x86_vector_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -536,7 +536,7 @@ static int x86_vector_alloc_irqs(struct struct irq_data *irqd; int i, err, node; - if (disable_apic) + if (apic_is_disabled) return -ENXIO; /* --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1020,7 +1020,7 @@ void __init setup_arch(char **cmdline_p) if (acpi_mps_check()) { #ifdef CONFIG_X86_LOCAL_APIC - disable_apic = 1; + apic_is_disabled = true; #endif setup_clear_cpu_cap(X86_FEATURE_APIC); } --- a/arch/x86/pci/xen.c +++ b/arch/x86/pci/xen.c @@ -517,7 +517,7 @@ int __init pci_xen_init(void) #ifdef CONFIG_PCI_MSI static void __init xen_hvm_msi_init(void) { - if (!disable_apic) { + if (!apic_is_disabled) { /* * If hardware supports (x2)APIC virtualization (as indicated * by hypervisor's leaf 4) then we don't need to use pirqs/ From patchwork Tue Aug 1 10:46:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129279 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2644302vqg; Tue, 1 Aug 2023 05:50:58 -0700 (PDT) X-Google-Smtp-Source: APBJJlGlwwEdLqQGnn0dRGtfnfoeE7Bo/o+3t2LmrGp/90u2uET+cYyXO4lnkIb+rQU/Yk4DrRJA X-Received: by 2002:a19:711a:0:b0:4fb:77d6:89c3 with SMTP id m26-20020a19711a000000b004fb77d689c3mr2012840lfc.12.1690894258300; Tue, 01 Aug 2023 05:50:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690894258; cv=none; d=google.com; s=arc-20160816; b=SUQklebMdUwDxA+GaU1OomvV3MSH44bplJIhmkZTSlkDY4jXwVtTzQ8IziK61v+7xx vc/szzroHYJVkM1NaChZLzj4g3ErX+ZUw9CO7486uDh+BRXrt5MCAP8CrTiFccOx+PnV OSmW1g+2+jOdT2SfYwodpSAhYZ5bdCibh3UZSgIUGdgyRrSQU8lvXcGrJgf8aeIZmMou VZBoKyKNftyZEJOBiohE4mggytVJDUbrXFDdVHutuJd37TDfu9EsoWOvYQncjXX/c/k3 fNAcL7vgnmpeaugTjHM3zQIaqLiUkTtPRcZIxiIiHgwPUTT1cYitwUavaJVN8zCe28lM r0sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=tcMO4j7nWxW6U4cF/hN8bFLKuWgR9Qfu6PLPNlHZoXg=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=ElcS6qZ24U207IGmdT7wVkWlQWm0d8dBJjkQy+6PGllEbEwNthbPplC3uHho3RqplV +yhXhJ2qs8L4Su7ddPPqQpljWYse6qooRHi8zQ46FRZ8TnoQH7cPAcsOlUPIRFhnO3Pl lsMP3R3MiKu5302X4OyJieR3vlG7nyzliaTVlAeO1HVKlegdTawByxugClC+e0i/mUsj 40mcX0RMqghmrBiVz6LHIaqIFhjP3YWWr+kGmu5a0SLYrO9Qyu3+lz565io4eteNMumf eRA4lA6AtTLQUllOsVUr1vt/x2RaQ0hM+2fqnJXQf+GZ7ZaSJnQFhMmtZLFpjbQ/7guC bL+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=eNM3lR+4; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Convert to bool. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/io_apic.h | 7 ++++--- arch/x86/kernel/acpi/boot.c | 2 +- arch/x86/kernel/apic/apic.c | 12 ++++++------ arch/x86/kernel/apic/io_apic.c | 12 ++++++------ arch/x86/xen/smp_pv.c | 2 +- 5 files changed, 18 insertions(+), 17 deletions(-) --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -109,8 +109,8 @@ extern int mp_irq_entries; /* MP IRQ source entries */ extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; -/* 1 if "noapic" boot option passed */ -extern int skip_ioapic_setup; +/* True if "noapic" boot option passed */ +extern bool ioapic_is_disabled; /* 1 if "noapic" boot option passed */ extern int noioapicquirk; @@ -129,7 +129,7 @@ extern unsigned long io_apic_irqs; * assignment of PCI IRQ's. */ #define io_apic_assign_pci_irqs \ - (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) + (mp_irq_entries && !ioapic_is_disabled && io_apic_irqs) struct irq_cfg; extern void ioapic_insert_resources(void); @@ -179,6 +179,7 @@ extern void print_IO_APICs(void); #define IO_APIC_IRQ(x) 0 #define io_apic_assign_pci_irqs 0 #define setup_ioapic_ids_from_mpc x86_init_noop +#define nr_ioapics (0) static inline void ioapic_insert_resources(void) { } static inline int arch_early_ioapic_init(void) { return 0; } static inline void print_IO_APICs(void) {} --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -1275,7 +1275,7 @@ static int __init acpi_parse_madt_ioapic /* * if "noapic" boot option, don't look for IO-APICs */ - if (skip_ioapic_setup) { + if (ioapic_is_disabled) { pr_info("Skipping IOAPIC probe due to 'noapic' option.\n"); return -ENODEV; } --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1691,7 +1691,7 @@ static void setup_local_APIC(void) * TODO: set up through-local-APIC from through-I/O-APIC? --macro */ value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; - if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { + if (!cpu && (pic_mode || !value || ioapic_is_disabled)) { value = APIC_DM_EXTINT; apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); } else { @@ -1956,7 +1956,7 @@ void __init enable_IR_x2apic(void) unsigned long flags; int ret, ir_stat; - if (skip_ioapic_setup) { + if (ioapic_is_disabled) { pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); return; } @@ -2956,11 +2956,11 @@ early_param("nolapic_timer", parse_nolap static int __init apic_set_verbosity(char *arg) { if (!arg) { -#ifdef CONFIG_X86_64 - skip_ioapic_setup = 0; + if (IS_ENABLED(CONFIG_X86_32)) + return -EINVAL; + + ioapic_is_disabled = false; return 0; -#endif - return -EINVAL; } if (strcmp("debug", arg) == 0) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -178,7 +178,7 @@ int mp_bus_id_to_type[MAX_MP_BUSSES]; DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); -int skip_ioapic_setup; +bool ioapic_is_disabled __ro_after_init; /** * disable_ioapic_support() - disables ioapic support at runtime @@ -189,7 +189,7 @@ void disable_ioapic_support(void) noioapicquirk = 1; noioapicreroute = -1; #endif - skip_ioapic_setup = 1; + ioapic_is_disabled = true; } static int __init parse_noapic(char *str) @@ -831,7 +831,7 @@ static int __acpi_get_override_irq(u32 g { int ioapic, pin, idx; - if (skip_ioapic_setup) + if (ioapic_is_disabled) return -1; ioapic = mp_find_ioapic(gsi); @@ -1366,7 +1366,7 @@ void __init enable_IO_APIC(void) int i8259_apic, i8259_pin; int apic, pin; - if (skip_ioapic_setup) + if (ioapic_is_disabled) nr_ioapics = 0; if (!nr_legacy_irqs() || !nr_ioapics) @@ -2399,7 +2399,7 @@ void __init setup_IO_APIC(void) { int ioapic; - if (skip_ioapic_setup || !nr_ioapics) + if (ioapic_is_disabled || !nr_ioapics) return; io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; @@ -2715,7 +2715,7 @@ void __init io_apic_init_mappings(void) "address found in MPTABLE, " "disabling IO/APIC support!\n"); smp_found_config = 0; - skip_ioapic_setup = 1; + ioapic_is_disabled = true; goto fake_ioapic_page; } #endif --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -209,7 +209,7 @@ static void __init xen_pv_smp_prepare_cp { unsigned cpu; - if (skip_ioapic_setup) { + if (ioapic_is_disabled) { char *m = (max_cpus == 0) ? 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l10-20020aa7c30a000000b00522aaf71df1si5990745edq.687.2023.08.01.05.40.10; Tue, 01 Aug 2023 05:40:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ipc2YrT3; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233678AbjHAKrI (ORCPT + 99 others); Tue, 1 Aug 2023 06:47:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232936AbjHAKqu (ORCPT ); Tue, 1 Aug 2023 06:46:50 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FF94119 for ; Tue, 1 Aug 2023 03:46:49 -0700 (PDT) Message-ID: <20230801103815.428310033@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886807; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=SEdHGmVEi1bYp03gPNqEFMS5i4ouVhk/JVGxKX8FQ3E=; b=ipc2YrT37g3/XjlUhINac9z7KthNEyQYwGUAeDFSHOOi9PjOXDUiu58gmHqdOhIa/P135O NwpTdrGX8gxcDdjSfwfz75vkfCLmqndiJsRY6WWE49ekJfQPChWiGa65hj9Ca71FHP7tSf UGZH72dpWSkFloGovDzFHWq1mCmh8HvjXsqyf/9dKWzUvsCuTpEytg2joaVKO2a+423lka 452z/LKd8wsoEDORSGmmx8jOGeDOTNnEmuH7+5YPABlW3zQpW9YI4ipzGwNF17BemgqM7A /LLCUwbK5OPfT/yf6URFLeXW6nGyDbLnx6mpe5zDZViY9JjBfL6dcxsuHBnF0Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886807; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=SEdHGmVEi1bYp03gPNqEFMS5i4ouVhk/JVGxKX8FQ3E=; b=UlakeLhfegSN4n+rpYkzag87YnKTV7/sWiz1PkWGonIM4gbY+6a/bTb+665BU0WpxOPKzM 9Y6fCuJ1Wh9/V4Dg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 05/60] x86/apic: Remove pointless x86_bios_cpu_apicid References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:46:47 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773030483167907508 X-GMAIL-MSGID: 1773030483167907508 It's a useless copy of x86_cpu_to_apicid. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 -- arch/x86/include/asm/smp.h | 1 - arch/x86/kernel/apic/apic.c | 5 +---- arch/x86/kernel/apic/apic_common.c | 2 +- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/probe_64.c | 4 +--- arch/x86/kernel/setup_percpu.c | 3 --- 7 files changed, 4 insertions(+), 15 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -477,8 +477,6 @@ extern void generic_bigsmp_probe(void); #define APIC_DFR_VALUE (APIC_DFR_FLAT) -DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); - extern struct apic apic_noop; static inline unsigned int read_apic_id(void) --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -22,7 +22,6 @@ DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_l2c DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid); DECLARE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid); -DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) DECLARE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid); #endif --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -108,10 +108,8 @@ unsigned long apic_mmio_base __ro_after_ * Map cpu index to physical APIC ID */ DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); -DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); -EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); #ifdef CONFIG_X86_32 @@ -2511,7 +2509,7 @@ int generic_processor_info(int apicid, i if (apicid == boot_cpu_physical_apicid) { /* - * x86_bios_cpu_apicid is required to have processors listed + * x86_cpu_to_apicid is required to have processors listed * in same order as logical cpu numbers. Hence the first * entry is BSP, and so on. * boot_cpu_init() already hold bit 0 in cpu_present_mask @@ -2548,7 +2546,6 @@ int generic_processor_info(int apicid, i #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; - early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; #endif #ifdef CONFIG_X86_32 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -29,7 +29,7 @@ void default_ioapic_phys_id_map(physid_m int default_cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) - return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); + return (int)per_cpu(x86_cpu_to_apicid, mps_cpu); else return BAD_APICID; } --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -52,7 +52,7 @@ static void bigsmp_setup_apic_routing(vo static int bigsmp_cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < nr_cpu_ids) - return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu); + return (int) per_cpu(x86_cpu_to_apicid, mps_cpu); return BAD_APICID; } --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -13,9 +13,7 @@ #include "local.h" -/* - * Check the APIC IDs in bios_cpu_apicid and choose the APIC mode. - */ +/* Select the appropriate APIC driver */ void __init default_setup_apic_routing(void) { struct apic **drv; --- a/arch/x86/kernel/setup_percpu.c +++ b/arch/x86/kernel/setup_percpu.c @@ -181,8 +181,6 @@ void __init setup_per_cpu_areas(void) #ifdef CONFIG_X86_LOCAL_APIC per_cpu(x86_cpu_to_apicid, cpu) = early_per_cpu_map(x86_cpu_to_apicid, cpu); - per_cpu(x86_bios_cpu_apicid, cpu) = - early_per_cpu_map(x86_bios_cpu_apicid, cpu); per_cpu(x86_cpu_to_acpiid, cpu) = early_per_cpu_map(x86_cpu_to_acpiid, cpu); #endif @@ -214,7 +212,6 @@ void __init setup_per_cpu_areas(void) /* indicate the early static arrays will soon be gone */ #ifdef CONFIG_X86_LOCAL_APIC early_per_cpu_ptr(x86_cpu_to_apicid) = NULL; - early_per_cpu_ptr(x86_bios_cpu_apicid) = NULL; early_per_cpu_ptr(x86_cpu_to_acpiid) = NULL; #endif #ifdef CONFIG_X86_32 From patchwork Tue Aug 1 10:46:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129195 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2595680vqg; Tue, 1 Aug 2023 04:17:33 -0700 (PDT) X-Google-Smtp-Source: APBJJlGLaQZq2V4jxaigwwcWHERM6Quw6NPlag9LbQJGYIbOA9TW6rHIRktF1Y/IitDH19Sb80wY X-Received: by 2002:a17:902:e88f:b0:1b5:26d4:517d with SMTP id w15-20020a170902e88f00b001b526d4517dmr12773495plg.29.1690888653254; Tue, 01 Aug 2023 04:17:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888653; cv=none; d=google.com; s=arc-20160816; b=mJFIaVhwUGsnFO5OoVhXb6ABiEsTVRA1lQ+sqLo6v/DO7Jy96SXQeAoqqcjkUhObQw rPzdqHKT1LBKGiYO1TCjw/cwyQtGPsiGjMoA13jq3rm9cd2j4Vnx6eJmUlSFvkyiPN2T CE9Sdvbx9+VmnJQcZsCW2zm9pUqi9gt3v82t5zWOGsK7RqrZNpj4Or/6NtgQ/jUrCWBC 55ZR4cv5SJRgjO36mf7ecSq7pMNBXUgEaQtFGkUD7jjLxtgHBiOiTQmnEErK7waVIFnM StpKIegc73ajdGsdxXUTH9dJc7aLv2DZs4A2m87VZLQBuQNZ1W58h47C/A3310d0lSP1 0abw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=w+6TyYrLF2RT85aC+yUd6AtExsVROY5NcF6dtBByybw=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=DRPnRVNzPgBxe5fQMo3NsSI4+uwBKdUPFNT2b4UxlBHDlJf72P5lnDp7gwhd72bSbh y+h0zHpAFIflwFybsofmR9Zo40d/r5u7Ku8onGGVcc0QQ8qvUdOkV6RvdZI2qnxpP/0q 2k1wokGLFvzPGggLkexM09IuvIbVsXkDo/3ZS2Og9oIv+7o1fjwotMEAcqOpPcZaBlKt lwb0z9Q2xW6GhSxnE7EIkxdtZ6Gq/SuhmYAMm9OwSQ2v36ZfbKRDSnbhjdZRW+sDDNaJ pS15CvBQ4DzKb7sBqhoeXQ4z+UHA3X8Q0Lj1lI+U7q54Ife5jH1M7XyaRZXtvAGCstWh cXfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=rnTTbuAd; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 6 +++++- arch/x86/include/asm/smp.h | 7 ------- arch/x86/kernel/apic/apic.c | 5 ----- arch/x86/kernel/apic/io_apic.c | 2 +- arch/x86/kernel/apic/ipi.c | 2 +- arch/x86/kernel/apic/vector.c | 2 +- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kernel/cpu/hygon.c | 3 ++- arch/x86/kernel/smpboot.c | 10 +++++----- arch/x86/kernel/vsmp_64.c | 2 +- 10 files changed, 17 insertions(+), 24 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -503,7 +503,11 @@ extern void default_ioapic_phys_id_map(p extern int default_cpu_present_to_apicid(int mps_cpu); extern int default_check_phys_apicid_present(int phys_apicid); -#endif /* CONFIG_X86_LOCAL_APIC */ +#else /* CONFIG_X86_LOCAL_APIC */ + +static inline unsigned int read_apic_id(void) { return 0; } + +#endif /* !CONFIG_X86_LOCAL_APIC */ #ifdef CONFIG_SMP void apic_smt_update(void); --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -185,13 +185,6 @@ static inline struct cpumask *cpu_llc_sh extern unsigned disabled_cpus; -#ifdef CONFIG_X86_LOCAL_APIC -extern int hard_smp_processor_id(void); - -#else /* CONFIG_X86_LOCAL_APIC */ -#define hard_smp_processor_id() 0 -#endif /* CONFIG_X86_LOCAL_APIC */ - #ifdef CONFIG_DEBUG_NMI_SELFTEST extern void nmi_selftest(void); #else --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2562,11 +2562,6 @@ int generic_processor_info(int apicid, i return cpu; } -int hard_smp_processor_id(void) -{ - return read_apic_id(); -} - void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, bool dmar) { --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -2095,7 +2095,7 @@ static inline void __init unlock_ExtINT_ entry0 = ioapic_read_entry(apic, pin); clear_IO_APIC_pin(apic, pin); - apic_id = hard_smp_processor_id(); + apic_id = read_apic_id(); memset(&entry1, 0, sizeof(entry1)); entry1.dest_mode_logical = true; --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -320,7 +320,7 @@ int safe_smp_processor_id(void) if (!boot_cpu_has(X86_FEATURE_APIC)) return 0; - apicid = hard_smp_processor_id(); + apicid = read_apic_id(); if (apicid == BAD_APICID) return 0; --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -1150,7 +1150,7 @@ static void __init print_local_APIC(void u64 icr; pr_debug("printing local APIC contents on CPU#%d/%d:\n", - smp_processor_id(), hard_smp_processor_id()); + smp_processor_id(), read_apic_id()); v = apic_read(APIC_ID); pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); v = apic_read(APIC_LVR); --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -934,7 +934,7 @@ static void init_amd(struct cpuinfo_x86 set_cpu_cap(c, X86_FEATURE_FSRS); /* get apicid instead of initial apic id from cpuid */ - c->apicid = hard_smp_processor_id(); + c->apicid = read_apic_id(); /* K6s reports MCEs but don't actually have all the MSRs */ if (c->x86 < 6) --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -300,7 +301,7 @@ static void init_hygon(struct cpuinfo_x8 set_cpu_cap(c, X86_FEATURE_REP_GOOD); /* get apicid instead of initial apic id from cpuid */ - c->apicid = hard_smp_processor_id(); + c->apicid = read_apic_id(); /* * XXX someone from Hygon needs to confirm this DTRT --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1220,11 +1220,11 @@ static void __init smp_sanity_check(void } #endif - if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { + if (!physid_isset(read_apic_id(), phys_cpu_present_map)) { pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", - hard_smp_processor_id()); + read_apic_id()); - physid_set(hard_smp_processor_id(), phys_cpu_present_map); + physid_set(read_apic_id(), phys_cpu_present_map); } /* @@ -1234,7 +1234,7 @@ static void __init smp_sanity_check(void if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", boot_cpu_physical_apicid); - physid_set(hard_smp_processor_id(), phys_cpu_present_map); + physid_set(read_apic_id(), phys_cpu_present_map); } preempt_enable(); } @@ -1431,7 +1431,7 @@ early_param("possible_cpus", _setup_poss if (!num_processors) { if (boot_cpu_has(X86_FEATURE_APIC)) { int apicid = boot_cpu_physical_apicid; - int cpu = hard_smp_processor_id(); + int cpu = read_apic_id(); pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); --- a/arch/x86/kernel/vsmp_64.c +++ b/arch/x86/kernel/vsmp_64.c @@ -129,7 +129,7 @@ static void __init vsmp_cap_cpus(void) static int apicid_phys_pkg_id(int initial_apic_id, int index_msb) { - return hard_smp_processor_id() >> index_msb; + return read_apic_id() >> index_msb; } static void vsmp_apic_post_init(void) From patchwork Tue Aug 1 10:46:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129236 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2614879vqg; Tue, 1 Aug 2023 04:59:31 -0700 (PDT) X-Google-Smtp-Source: APBJJlG0cLFGJP+roJt/4HE3z2KuK2gBv/3UT/P5u7G+xv9jfXFq7BsxLnqZXmcS7Us7m43A0HdL X-Received: by 2002:a17:90a:fe1:b0:267:ffcf:e9e3 with SMTP id 88-20020a17090a0fe100b00267ffcfe9e3mr12331401pjz.46.1690891170798; Tue, 01 Aug 2023 04:59:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690891170; cv=none; d=google.com; s=arc-20160816; b=AVaNKNIH5Xc6Ow+mgaHkRGsTCtpVscT847js5I6GWC34JpL0eHZyph3caGHtbQ4Df7 1cHFVNiUXN9ldCMllwRIaKv1qBGU00DaR3ogvueX4DGACXoORWuOxcl9S4O9V+lanRQ5 h8YMyPK8EDpYDqr/epq64B+QYYcRV6dAGwII+6Hdh3NRP8mHddRXkyoCnhZVHGNqc48L Pq07nj139r8R11yeNWXvSDFbla/ZXnsyzcJaIi0uuOsGk0RbAyKiwdEWzGDEzpbCXlmE kIq250aJ6vQ/PR7/p8iObc1OA4n+6n+sPDc1mG5MbMhwLNIXreP8Ujr9p0N2tXeT4ZSt 5GNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=ubhxg5lHvUPqEcRAdngDyy9xlfFoerwPBN8zo0sYJDE=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=RRjrTaoakQDmIR8Ale6GlGUgElaujkkk8KWbJ/kAs2MSWUznNZ5p5R0qbLLSy+r2qq 4FBtdOUamavHVlsIuiu2knvU5ccTRZ4+wNRI3fkjnhFSxM7kvjFvw4I23y/oOw0Xhx7q s7uuKTwPopDz+AHZNJ+lT2S78wXXkF8XYr2SJHr458haiBQSrYpFpYuK5xlY3jwx/CFi cvHyyoBjV4QahozK8dmlM/AyVAnWkyhyB2V4LPjpFQRcLNdwb9HKmfnexXlZlborDi0p VZy0eSyGwoNWiHPZJoQNe8TIvVhY76UM5thICthoyp2M2GLcZwH0g7PHCQDIlhB55m+l aTFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Hljuyfyl; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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/* - * The highest APIC ID seen during enumeration. - */ -static unsigned int max_physical_apicid; - -/* * Bitmask of physically existing CPUs: */ physid_mask_t phys_cpu_present_map; @@ -2541,9 +2536,6 @@ int generic_processor_info(int apicid, i boot_cpu_apic_version, cpu, version); } - if (apicid > max_physical_apicid) - max_physical_apicid = apicid; - #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; #endif From patchwork Tue Aug 1 10:46:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129225 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2609913vqg; Tue, 1 Aug 2023 04:47:56 -0700 (PDT) X-Google-Smtp-Source: APBJJlHrXpYzX3qK1WqzhuptuP1xHJUK0DOjq4oNo3FgtIyuxItTz05oL2CPV2BMHoSWeYakNIzC X-Received: by 2002:a17:906:21a:b0:99c:1b9a:b09e with SMTP id 26-20020a170906021a00b0099c1b9ab09emr2369512ejd.75.1690890476251; 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Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 16 -------------- arch/x86/kernel/apic/apic_flat_64.c | 4 --- arch/x86/kernel/apic/apic_noop.c | 2 - arch/x86/kernel/apic/apic_numachip.c | 2 - arch/x86/kernel/apic/bigsmp_32.c | 2 - arch/x86/kernel/apic/probe_32.c | 2 - arch/x86/kernel/apic/x2apic_cluster.c | 2 - arch/x86/kernel/apic/x2apic_phys.c | 2 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 arch/x86/kernel/smpboot.c | 38 ---------------------------------- arch/x86/xen/apic.c | 7 ------ 11 files changed, 78 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -66,20 +66,6 @@ enum apic_intr_mode_id { APIC_SYMMETRIC_IO_NO_ROUTING }; -#ifdef CONFIG_SMP -extern void __inquire_remote_apic(int apicid); -#else /* CONFIG_SMP */ -static inline void __inquire_remote_apic(int apicid) -{ -} -#endif /* CONFIG_SMP */ - -static inline void default_inquire_remote_apic(int apicid) -{ - if (apic_verbosity >= APIC_DEBUG) - __inquire_remote_apic(apicid); -} - /* * With 82489DX we can't rely on apic feature bit * retrieved via cpuid but still have to deal with @@ -330,8 +316,6 @@ struct apic { /* wakeup secondary CPU using 64-bit wakeup point */ int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); - void (*inquire_remote_apic)(int apicid); - #ifdef CONFIG_X86_32 /* * Called very early during boot from get_smp_config(). It should --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -139,8 +139,6 @@ static struct apic apic_flat __ro_after_ .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, - .inquire_remote_apic = default_inquire_remote_apic, - .read = native_apic_mem_read, .write = native_apic_mem_write, .eoi_write = native_apic_mem_write, @@ -230,8 +228,6 @@ static struct apic apic_physflat __ro_af .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, - .inquire_remote_apic = default_inquire_remote_apic, - .read = native_apic_mem_read, .write = native_apic_mem_write, .eoi_write = native_apic_mem_write, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -125,8 +125,6 @@ struct apic apic_noop __ro_after_init = .wakeup_secondary_cpu = noop_wakeup_secondary_cpu, - .inquire_remote_apic = NULL, - .read = noop_apic_read, .write = noop_apic_write, .eoi_write = noop_apic_write, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -273,7 +273,6 @@ static const struct apic apic_numachip1 .send_IPI_self = numachip_send_IPI_self, .wakeup_secondary_cpu = numachip_wakeup_secondary, - .inquire_remote_apic = NULL, /* REMRD not supported */ .read = native_apic_mem_read, .write = native_apic_mem_write, @@ -320,7 +319,6 @@ static const struct apic apic_numachip2 .send_IPI_self = numachip_send_IPI_self, .wakeup_secondary_cpu = numachip_wakeup_secondary, - .inquire_remote_apic = NULL, /* REMRD not supported */ .read = native_apic_mem_read, .write = native_apic_mem_write, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -153,8 +153,6 @@ static struct apic apic_bigsmp __ro_afte .send_IPI_all = bigsmp_send_IPI_all, .send_IPI_self = default_send_IPI_self, - .inquire_remote_apic = default_inquire_remote_apic, - .read = native_apic_mem_read, .write = native_apic_mem_write, .eoi_write = native_apic_mem_write, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -95,8 +95,6 @@ static struct apic apic_default __ro_aft .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, - .inquire_remote_apic = default_inquire_remote_apic, - .read = native_apic_mem_read, .write = native_apic_mem_write, .eoi_write = native_apic_mem_write, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -265,8 +265,6 @@ static struct apic apic_x2apic_cluster _ .send_IPI_all = x2apic_send_IPI_all, .send_IPI_self = x2apic_send_IPI_self, - .inquire_remote_apic = NULL, - .read = native_apic_msr_read, .write = native_apic_msr_write, .eoi_write = native_apic_msr_eoi_write, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -189,8 +189,6 @@ static struct apic apic_x2apic_phys __ro .send_IPI_all = x2apic_send_IPI_all, .send_IPI_self = x2apic_send_IPI_self, - .inquire_remote_apic = NULL, - .read = native_apic_msr_read, .write = native_apic_msr_write, .eoi_write = native_apic_msr_eoi_write, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -862,7 +862,6 @@ static struct apic apic_x2apic_uv_x __ro .send_IPI_self = uv_send_IPI_self, .wakeup_secondary_cpu = uv_wakeup_secondary, - .inquire_remote_apic = NULL, .read = native_apic_msr_read, .write = native_apic_msr_write, --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -774,44 +774,6 @@ static void impress_friends(void) pr_debug("Before bogocount - setting activated=1\n"); } -void __inquire_remote_apic(int apicid) -{ - unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; - const char * const names[] = { "ID", "VERSION", "SPIV" }; - int timeout; - u32 status; - - pr_info("Inquiring remote APIC 0x%x...\n", apicid); - - for (i = 0; i < ARRAY_SIZE(regs); i++) { - pr_info("... APIC 0x%x %s: ", apicid, names[i]); - - /* - * Wait for idle. - */ - status = safe_apic_wait_icr_idle(); - if (status) - pr_cont("a previous APIC delivery may have failed\n"); - - apic_icr_write(APIC_DM_REMRD | regs[i], apicid); - - timeout = 0; - do { - udelay(100); - status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; - } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); - - switch (status) { - case APIC_ICR_RR_VALID: - status = apic_read(APIC_RRR); - pr_cont("%08x\n", status); - break; - default: - pr_cont("failed\n"); - } - } -} - /* * The Multiprocessor Specification 1.4 (1997) example code suggests * that there should be a 10ms delay between the BSP asserting INIT --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -129,10 +129,6 @@ static void xen_noop(void) { } -static void xen_silent_inquire(int apicid) -{ -} - static int xen_cpu_present_to_apicid(int cpu) { if (cpu_present(cpu)) @@ -173,9 +169,6 @@ static struct apic xen_pv_apic = { .send_IPI_all = xen_send_IPI_all, .send_IPI_self = xen_send_IPI_self, #endif - /* .wait_for_init_deassert- used by AP bootup - smp_callin which we don't use */ - .inquire_remote_apic = xen_silent_inquire, - .read = xen_apic_read, .write = xen_apic_write, .eoi_write = xen_apic_write, From patchwork Tue Aug 1 10:46:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129198 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2596265vqg; Tue, 1 Aug 2023 04:18:45 -0700 (PDT) X-Google-Smtp-Source: APBJJlGSShFzIHsin3QntSZo3tEw++Ezb5o5HiwjJIwGbQJbdYKV9/WVPFq/V6+DtijIYOxGCjDG X-Received: by 2002:a17:902:d2cd:b0:1bc:239:a7bd with SMTP id n13-20020a170902d2cd00b001bc0239a7bdmr10154999plc.6.1690888725239; Tue, 01 Aug 2023 04:18:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888725; cv=none; d=google.com; s=arc-20160816; b=b+Q6UzmxC85fpOWmGPHBuhsiXuo0GpVvotsJupjoH5cUkK85ZGUeqQWzcVCxpJyfzZ 4i3EIYi1v3qHPc6SUcZ4pl4Z8cZ7B20eHkP2kxS92UwV8oDUO/iK73D0f+MKXJa9h8E4 L5z2rE5OnRJbvXoLJDdb7DpNR7+gu0BBtLFSAqITh5t1zTzwyXrJwgsfKgNJcAYnQNi9 bq2cDfCXQi3VdxPzYNir2THV65lXKvw/Dt4ZRrqIRoDL1KS6vHDFR6njwS1FlZkYsrB0 zIgYiY/V5cjGD6q2rgvljfIwMiaoUnJ29BoDrFRSgmtRDZ2nGN/g4gLrNl5nkyLcp5+M zEkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=eoSypAN2UkpamuEPl9Sov61uZb2Xz+SJDJBt/P4aUAg=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=xMjGx4JOfGKYosxOJ4siNgJFaMC+Vcxtz9Vo/0eDWxJAgHqLM5qR7vpU09jHMawcuE XhJk/BX2Mmp6gOiDReLZfQgtuUGJcXD4ySnAwaqzFwb+PdqeN5bKazToUJqGygp+MtNn 5eyzIfuGMCGzLKg7zQdTY34ZET9276T5pI0vzASrl1hXGL3AmLIL95o4D7Yoes1FyqtI kNHMIMCJl6yVSrD+S1YSQVGRX0RDUT0ch+8fILC1eCnPci6EhkCjcRPvPVt93nOtMx/R BoYy+Kb9I6c/DVRyhn1RAFWQ12FrbuwkPEWAs/q0jW0bV5SiN4HO4FWNK/7hSArw5n/6 birQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=N3zGXA0n; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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That causes it to have inconsistent state when the MPTABLE is broken. As a consequence tons of moronic checks are sprinkled all over the place. Consolidate the code and read it exactly once when either X2APIC mode is detected early or when the APIC mapping is established. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 arch/x86/kernel/apic/apic.c | 102 +++++++++++++------------------------------- arch/x86/kernel/mpparse.c | 4 - 3 files changed, 34 insertions(+), 74 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -247,7 +247,7 @@ static inline int x2apic_enabled(void) #else /* !CONFIG_X86_X2APIC */ static inline void x2apic_setup(void) { } static inline int x2apic_enabled(void) { return 0; } - +static inline u32 native_apic_msr_read(u32 reg) { BUG(); } #define x2apic_mode (0) #define x2apic_supported() (0) #endif /* !CONFIG_X86_X2APIC */ --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1318,8 +1318,7 @@ static int __init __apic_intr_mode_selec if (!boot_cpu_has(X86_FEATURE_APIC) && APIC_INTEGRATED(boot_cpu_apic_version)) { apic_is_disabled = true; - pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", - boot_cpu_physical_apicid); + pr_err(FW_BUG "Local APIC not detected, force emulation\n"); return APIC_PIC; } #endif @@ -1340,12 +1339,6 @@ static int __init __apic_intr_mode_selec pr_info("APIC: SMP mode deactivated\n"); return APIC_SYMMETRIC_IO_NO_ROUTING; } - - if (read_apic_id() != boot_cpu_physical_apicid) { - panic("Boot APIC ID in local APIC unexpected (%d vs %d)", - read_apic_id(), boot_cpu_physical_apicid); - /* Or can we switch back to PIC here? */ - } #endif return APIC_SYMMETRIC_IO; @@ -1741,6 +1734,23 @@ void apic_ap_setup(void) end_local_APIC_setup(); } +static __init void apic_read_boot_cpu_id(bool x2apic) +{ + /* + * This can be invoked from check_x2apic() before the APIC has been + * selected. But that code knows for sure that the BIOS enabled + * X2APIC. + */ + if (x2apic) { + boot_cpu_physical_apicid = native_apic_msr_read(APIC_ID); + boot_cpu_apic_version = GET_APIC_VERSION(native_apic_msr_read(APIC_LVR)); + } else { + boot_cpu_physical_apicid = read_apic_id(); + boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); + } +} + + #ifdef CONFIG_X86_X2APIC int x2apic_mode; EXPORT_SYMBOL_GPL(x2apic_mode); @@ -1921,6 +1931,7 @@ void __init check_x2apic(void) x2apic_state = X2APIC_ON_LOCKED; else x2apic_state = X2APIC_ON; + apic_read_boot_cpu_id(true); } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { x2apic_state = X2APIC_DISABLED; } @@ -2109,15 +2120,11 @@ static int __init detect_init_APIC(void) */ void __init init_apic_mappings(void) { - unsigned int new_apicid; - if (apic_validate_deadline_timer()) pr_info("TSC deadline timer available\n"); - if (x2apic_mode) { - boot_cpu_physical_apicid = read_apic_id(); + if (x2apic_mode) return; - } /* If no local APIC can be found return early */ if (!smp_found_config && detect_init_APIC()) { @@ -2134,39 +2141,19 @@ void __init init_apic_mappings(void) if (!acpi_lapic && !smp_found_config) register_lapic_address(apic_phys); } - - /* - * Fetch the APIC ID of the BSP in case we have a - * default configuration (or the MP table is broken). - */ - new_apicid = read_apic_id(); - if (boot_cpu_physical_apicid != new_apicid) { - boot_cpu_physical_apicid = new_apicid; - /* - * yeah -- we lie about apic_version - * in case if apic was disabled via boot option - * but it's not a problem for SMP compiled kernel - * since apic_intr_mode_select is prepared for such - * a case and disable smp mode - */ - boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); - } } void __init register_lapic_address(unsigned long address) { mp_lapic_addr = address; - if (!x2apic_mode) { - set_fixmap_nocache(FIX_APIC_BASE, address); - apic_mmio_base = APIC_BASE; - apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", - APIC_BASE, address); - } - if (boot_cpu_physical_apicid == -1U) { - boot_cpu_physical_apicid = read_apic_id(); - boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); - } + if (x2apic_mode) + return; + + set_fixmap_nocache(FIX_APIC_BASE, address); + apic_mmio_base = APIC_BASE; + apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", APIC_BASE, address); + apic_read_boot_cpu_id(false); } /* @@ -2446,31 +2433,15 @@ int generic_processor_info(int apicid, i phys_cpu_present_map); /* - * boot_cpu_physical_apicid is designed to have the apicid - * returned by read_apic_id(), i.e, the apicid of the - * currently booting-up processor. However, on some platforms, - * it is temporarily modified by the apicid reported as BSP - * through MP table. Concretely: - * - * - arch/x86/kernel/mpparse.c: MP_processor_info() - * - arch/x86/mm/amdtopology.c: amd_numa_init() - * - * This function is executed with the modified - * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel - * parameter doesn't work to disable APs on kdump 2nd kernel. - * - * Since fixing handling of boot_cpu_physical_apicid requires - * another discussion and tests on each platform, we leave it - * for now and here we use read_apic_id() directly in this - * function, generic_processor_info(). + * boot_cpu_physical_apicid is guaranteed to contain the boot CPU + * APIC ID read from the local APIC when this function is invoked. */ - if (disabled_cpu_apicid != BAD_APICID && - disabled_cpu_apicid != read_apic_id() && + if (disabled_cpu_apicid != boot_cpu_physical_apicid && disabled_cpu_apicid == apicid) { int thiscpu = num_processors + disabled_cpus; - pr_warn("APIC: Disabling requested cpu." - " Processor %d/0x%x ignored.\n", thiscpu, apicid); + pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", + thiscpu, apicid); disabled_cpus++; return -ENODEV; @@ -2626,15 +2597,6 @@ static void __init apic_bsp_up_setup(voi { #ifdef CONFIG_X86_64 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); -#else - /* - * Hack: In case of kdump, after a crash, kernel might be booting - * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid - * might be zero if read from MP tables. Get it from LAPIC. - */ -# ifdef CONFIG_CRASH_DUMP - boot_cpu_physical_apicid = read_apic_id(); -# endif #endif physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); } --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -58,10 +58,8 @@ static void __init MP_processor_info(str apicid = m->apicid; - if (m->cpuflag & CPU_BOOTPROCESSOR) { + if (m->cpuflag & CPU_BOOTPROCESSOR) bootup_cpu = " (Bootup-CPU)"; - boot_cpu_physical_apicid = m->apicid; - } pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); generic_processor_info(apicid, m->apicver); From patchwork Tue Aug 1 10:46:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129219 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2601839vqg; Tue, 1 Aug 2023 04:30:26 -0700 (PDT) X-Google-Smtp-Source: APBJJlHIDS7Pw/KGXHXRZMSwpTjd7HlAyr/Xbt/mDVuciCeYwbU2vVjeIhY6HFv9QQJk8IwirGvB X-Received: by 2002:a17:906:2112:b0:99b:b3a1:437b with SMTP id 18-20020a170906211200b0099bb3a1437bmr2173726ejt.40.1690889426665; Tue, 01 Aug 2023 04:30:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690889426; cv=none; d=google.com; s=arc-20160816; b=OUYxu4WzL7CiDkxCABb3kh1WMYrWm9vd9trSTxLr3ZRomjWHevPevi9eKzByaE+TJM zY3lCCcNsqcD+ZjKafN3BhaXuEJSsGjEvefzNOGGeuBd0BkBqBtrHmY9Sh4da8Go16jQ 5mKT6YJJXIWJvZoso2z/J65MK5trmCF8zLX6RGAObJYu4D5FMLNa839In/FfZCXOXse2 ncaBjSgeowKv6INV9vBrTLm2JY7j8whFo/voLiNeLoaAHc5XTGzZd0/UBQs5CGLszhCv 0l2a73eALt17PPQtb9UIFnC3T5jZ4927a8s1f2/XSYhpVezpvsbsNmA0i0jsU3DtSlY+ VRxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=tXQKKwpyD/5KWCvdmuzL9UCOi5F812bKdsX6A+OvjaI=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=BCdgl+U0epgWQT49elpi3fByrYg2GQ/hC+stG3qQ39HcgAXEDrLouJdrkOkLA+3DRG cE4FwXF1w66H4M+YvgYI2YeMkQjhHzrAMI9wFuzspcvfuQwUbGcg8GFCWqXLMt4VyTlc KFBKyMcGMmv8k8QfYYYCWo631nR1cTSvgza234z69wNnekf57gPuljQexUL9IlF3y2G8 u8McdNqJw+6FfidDFIi4d3ly7SkbNMHNEFvrCh2nsfHJVAx+zPv2n3OJCw8CPx2TkTw5 iulGWzbmINP5TJmKJyi3mMOg0v1LOU/WxWirRLc/qiIuGtXxsecFiaJHIrP6pjYL/IkU +gJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Mn9w4RJy; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l12-20020a1709065a8c00b0099bd2ac750fsi9023265ejq.770.2023.08.01.04.30.03; Tue, 01 Aug 2023 04:30:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Mn9w4RJy; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233927AbjHAKrb (ORCPT + 99 others); Tue, 1 Aug 2023 06:47:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233345AbjHAKrA (ORCPT ); Tue, 1 Aug 2023 06:47:00 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5126F1BF0 for ; Tue, 1 Aug 2023 03:46:55 -0700 (PDT) Message-ID: <20230801103815.707466941@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886813; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tXQKKwpyD/5KWCvdmuzL9UCOi5F812bKdsX6A+OvjaI=; b=Mn9w4RJyrHBhyieWkk9u0q52FPjCH9y2Zr91JEAbjpj1hUuZyRhsrJyOpEpF9LT+lPRXz5 gLHSeeoqpwR46IVVyuYAP6zYfrq5XMgoptLLgpZZJRr7G+88ek6RbmoRAaefP7p36MK+vm u6ymRBhNT1sd/0MI6/GN3juPfpjVBsA5KxjuAMaExahKpU7AuDdvNkzuT2yiGIcZq4C2wx RxPJVRpqPM7Pj3K+c7l0t1R866FVJlvMKcZDKJMFXXFkSqtZ/44bMdcIEkeD3oAUfCviwl Mz6t7BCnDtvHw7SszShT6qGj4CXkOVY6eMGWczlmGXh19Mjmd0icaeeUpa20IA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886813; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tXQKKwpyD/5KWCvdmuzL9UCOi5F812bKdsX6A+OvjaI=; b=KPaCfvKXD6FpJehHm2N0Z52D4OsXF745gCdHq0blGpbfmiLPN4b7Hy2P73VdxgzUTovPo4 EMMfgwpgm56I/ZCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 10/60] x86/apic: Register boot CPU APIC early References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:46:53 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773026071584261661 X-GMAIL-MSGID: 1773026071584261661 Register the boot CPU APIC right when the boot CPUs APIC is read from the hardware. No point is doing this on random places and having wild heuristics to save the boot CPU APIC ID slot and CPU number 0 reserved. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 120 ++++++++++++++++++-------------------------- 1 file changed, 50 insertions(+), 70 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1734,6 +1734,8 @@ void apic_ap_setup(void) end_local_APIC_setup(); } +static __init void cpu_set_boot_apic(void); + static __init void apic_read_boot_cpu_id(bool x2apic) { /* @@ -1748,9 +1750,9 @@ static __init void apic_read_boot_cpu_id boot_cpu_physical_apicid = read_apic_id(); boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); } + cpu_set_boot_apic(); } - #ifdef CONFIG_X86_X2APIC int x2apic_mode; EXPORT_SYMBOL_GPL(x2apic_mode); @@ -2426,76 +2428,8 @@ static int allocate_logical_cpuid(int ap return nr_logical_cpuids++; } -int generic_processor_info(int apicid, int version) +static void cpu_update_apic(int cpu, int apicid, int version) { - int cpu, max = nr_cpu_ids; - bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, - phys_cpu_present_map); - - /* - * boot_cpu_physical_apicid is guaranteed to contain the boot CPU - * APIC ID read from the local APIC when this function is invoked. - */ - if (disabled_cpu_apicid != boot_cpu_physical_apicid && - disabled_cpu_apicid == apicid) { - int thiscpu = num_processors + disabled_cpus; - - pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", - thiscpu, apicid); - - disabled_cpus++; - return -ENODEV; - } - - /* - * If boot cpu has not been detected yet, then only allow upto - * nr_cpu_ids - 1 processors and keep one slot free for boot cpu - */ - if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && - apicid != boot_cpu_physical_apicid) { - int thiscpu = max + disabled_cpus - 1; - - pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost" - " reached. Keeping one slot for boot cpu." - " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); - - disabled_cpus++; - return -ENODEV; - } - - if (num_processors >= nr_cpu_ids) { - int thiscpu = max + disabled_cpus; - - pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " - "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); - - disabled_cpus++; - return -EINVAL; - } - - if (apicid == boot_cpu_physical_apicid) { - /* - * x86_cpu_to_apicid is required to have processors listed - * in same order as logical cpu numbers. Hence the first - * entry is BSP, and so on. - * boot_cpu_init() already hold bit 0 in cpu_present_mask - * for BSP. - */ - cpu = 0; - - /* Logical cpuid 0 is reserved for BSP. */ - cpuid_to_apicid[0] = apicid; - } else { - cpu = allocate_logical_cpuid(apicid); - if (cpu < 0) { - disabled_cpus++; - return -EINVAL; - } - } - - /* - * Validate version - */ if (version == 0x0) { pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", cpu, apicid); @@ -2521,10 +2455,56 @@ int generic_processor_info(int apicid, i if (system_state != SYSTEM_BOOTING) cpu_mark_primary_thread(cpu, apicid); +} + +static __init void cpu_set_boot_apic(void) +{ + cpuid_to_apicid[0] = boot_cpu_physical_apicid; + cpu_update_apic(0, boot_cpu_physical_apicid, boot_cpu_apic_version); +} + +int generic_processor_info(int apicid, int version) +{ + int cpu, max = nr_cpu_ids; + + /* The boot CPU must be set before MADT/MPTABLE parsing happens */ + if (cpuid_to_apicid[0] == BAD_APICID) + panic("Boot CPU APIC not registered yet\n"); + + if (apicid == boot_cpu_physical_apicid) + return 0; + + if (disabled_cpu_apicid == apicid) { + int thiscpu = num_processors + disabled_cpus; + + pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", + thiscpu, apicid); + disabled_cpus++; + return -ENODEV; + } + + if (num_processors >= nr_cpu_ids) { + int thiscpu = max + disabled_cpus; + + pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " + "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); + + disabled_cpus++; + return -EINVAL; + } + + cpu = allocate_logical_cpuid(apicid); + if (cpu < 0) { + disabled_cpus++; + return -EINVAL; + } + + cpu_update_apic(cpu, apicid, version); return cpu; } + void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, bool dmar) { From patchwork Tue Aug 1 10:46:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129259 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2634020vqg; Tue, 1 Aug 2023 05:30:55 -0700 (PDT) X-Google-Smtp-Source: APBJJlEiaL80WqVXHv9EPHhy9dggvT0fxG8LRPSidgwTVp1K31xh07kWy61toVAJFlcJLQdYY7pN X-Received: by 2002:a05:6a20:7f8b:b0:135:32b1:b03d with SMTP id d11-20020a056a207f8b00b0013532b1b03dmr16123472pzj.42.1690893055535; Tue, 01 Aug 2023 05:30:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893055; cv=none; d=google.com; s=arc-20160816; b=hk2kPhm9bsDFvfZVcITv6jF05Gf4FsFF5wiska+DchGJ3vN2ag4Nd/weqhMEe8CHMs 9BDPfWWU87tDA4lV5VHzAH1oKQut3dU0mO6p/c5yt6RpL5zh4piqE5O+TkOhO3IrOHOs 8dVIDHuoc8mOoQ73alBm+OF2buUW7+SgTvyBBlDh3ShaPUV3wJyhITO52WWattj+s4eb MwrexOsz7Ydf74t8iSkfBdFjYxboAu/3eNq/9Rv38CG19ItjSgiypoEGLMgBfJXo+hch 6c4byL9pHIeWFSoH5AjWl796hWvvpjMyQ7dGQh7m+i44S5wrb/dIu1E4r8jb/qnv/DNi Opgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Fur2MYcjwG+kKe1RtThBHG7Ea2Bvm6lkExJ+ZubmnJg=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=Ydywugs2Fl+kmB5DQJKqnQm87/lnPz/OAuZhdLw+PQUcOMe7RuNp+Q4YnySFrPi1Nu ohnNC7n+SmKfVxpHiEHWQlkUamBeQvv2z+cYaT/0QF3jMm4ymPFrPeMcdSQPvB6fKLJ9 Cub0VzPtSfWn4/wyHEfTQ/tIjovfkhtvkRpu5Zxt4FluoySQgCzql9IfCD7tBwxYSNIt 2fIqIbJTrN+wJnU4pSkA2zwFh2V7HUBMOUXlaUP1IHcnU0GcIkowMiDCjP9K/5xv4TBN GK/TV6+0Bi3cN5x8kr3ofUUoByB7afbcJDb8RywSxTDh6bksm1NAGgxvT1Dgi/SBJOFF usYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=RjAScgiw; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Whatever MPTABLE or MADT delivers we only trust the hardware anyway. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/mpspec.h | 2 +- arch/x86/kernel/acpi/boot.c | 6 +----- arch/x86/kernel/apic/apic.c | 19 ++++--------------- arch/x86/kernel/devicetree.c | 5 ++--- arch/x86/kernel/jailhouse.c | 6 ++---- arch/x86/kernel/mpparse.c | 2 +- arch/x86/kernel/smpboot.c | 4 ++-- 7 files changed, 13 insertions(+), 31 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -76,7 +76,7 @@ static inline void e820__memblock_alloc_ #define default_get_smp_config x86_init_uint_noop #endif -int generic_processor_info(int apicid, int version); +int generic_processor_info(int apicid); #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC) --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -169,7 +169,6 @@ static int __init acpi_parse_madt(struct */ static int acpi_register_lapic(int id, u32 acpiid, u8 enabled) { - unsigned int ver = 0; int cpu; if (id >= MAX_LOCAL_APIC) { @@ -182,10 +181,7 @@ static int acpi_register_lapic(int id, u return -EINVAL; } - if (boot_cpu_physical_apicid != -1U) - ver = boot_cpu_apic_version; - - cpu = generic_processor_info(id, ver); + cpu = generic_processor_info(id); if (cpu >= 0) early_per_cpu(x86_cpu_to_acpiid, cpu) = acpiid; --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2428,19 +2428,8 @@ static int allocate_logical_cpuid(int ap return nr_logical_cpuids++; } -static void cpu_update_apic(int cpu, int apicid, int version) +static void cpu_update_apic(int cpu, int apicid) { - if (version == 0x0) { - pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", - cpu, apicid); - version = 0x10; - } - - if (version != boot_cpu_apic_version) { - pr_warn("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", - boot_cpu_apic_version, cpu, version); - } - #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; #endif @@ -2460,10 +2449,10 @@ static void cpu_update_apic(int cpu, int static __init void cpu_set_boot_apic(void) { cpuid_to_apicid[0] = boot_cpu_physical_apicid; - cpu_update_apic(0, boot_cpu_physical_apicid, boot_cpu_apic_version); + cpu_update_apic(0, boot_cpu_physical_apicid); } -int generic_processor_info(int apicid, int version) +int generic_processor_info(int apicid) { int cpu, max = nr_cpu_ids; @@ -2500,7 +2489,7 @@ int generic_processor_info(int apicid, i return -EINVAL; } - cpu_update_apic(cpu, apicid, version); + cpu_update_apic(cpu, apicid); return cpu; } --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -128,16 +128,15 @@ static void __init dtb_setup_hpet(void) static void __init dtb_cpu_setup(void) { struct device_node *dn; - u32 apic_id, version; + u32 apic_id; - version = GET_APIC_VERSION(apic_read(APIC_LVR)); for_each_of_cpu_node(dn) { apic_id = of_get_cpu_hwid(dn, 0); if (apic_id == ~0U) { pr_warn("%pOF: missing local APIC ID\n", dn); continue; } - generic_processor_info(apic_id, version); + generic_processor_info(apic_id); } } --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -101,10 +101,8 @@ static void __init jailhouse_get_smp_con register_lapic_address(0xfee00000); - for (cpu = 0; cpu < setup_data.v1.num_cpus; cpu++) { - generic_processor_info(setup_data.v1.cpu_ids[cpu], - boot_cpu_apic_version); - } + for (cpu = 0; cpu < setup_data.v1.num_cpus; cpu++) + generic_processor_info(setup_data.v1.cpu_ids[cpu]); smp_found_config = 1; --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -62,7 +62,7 @@ static void __init MP_processor_info(str bootup_cpu = " (Bootup-CPU)"; pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); - generic_processor_info(apicid, m->apicver); + generic_processor_info(apicid); } #ifdef CONFIG_X86_IO_APIC --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1389,7 +1389,7 @@ early_param("possible_cpus", _setup_poss { int i, possible; - /* No boot processor was found in mptable or ACPI MADT */ + /* No processor was found in mptable or ACPI MADT */ if (!num_processors) { if (boot_cpu_has(X86_FEATURE_APIC)) { int apicid = boot_cpu_physical_apicid; @@ -1400,7 +1400,7 @@ early_param("possible_cpus", _setup_poss /* Make sure boot cpu is enumerated */ if (apic->cpu_present_to_apicid(0) == BAD_APICID && apic->apic_id_valid(apicid)) - generic_processor_info(apicid, boot_cpu_apic_version); + generic_processor_info(apicid); } if (!num_processors) From patchwork Tue Aug 1 10:46:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129284 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2644990vqg; Tue, 1 Aug 2023 05:52:11 -0700 (PDT) X-Google-Smtp-Source: APBJJlGUoOmAMppPIGtv+NEocNEeZO97Qyu8KzthIpQGAKfHbqZSiw5/kjElI8lHer1Xo22mXboN X-Received: by 2002:a17:906:151:b0:99b:5689:1331 with SMTP id 17-20020a170906015100b0099b56891331mr2551108ejh.59.1690894330746; Tue, 01 Aug 2023 05:52:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690894330; cv=none; d=google.com; s=arc-20160816; b=lI1ygxGzGuTv6AUwUbqEfHeQtRXmWlsD0sxO6uGUCIpt9xNoe3niKSM1gK0eis1KNa gcrzpExm7KFRfsMt3ijSs6mv4jHpWvs/JxPN6PCmIKuKZEAfI8vEJtfDOwfH51wocPCL 4kdCymK72Ki3E3H5pLe2hOGNTWXrZ6mxurJGQowty0wxc43oQdB7QAz73QJAcwl88ctG pKWZywaMMdd1UXfqwyPoE1MxKcwCcK6kT2HQJKU+0eDkmw4YgxiedbVnnn404yDJopI8 t7x/KO8eQuxVS3WUH4SY+rppzstWYvlB9kRpuO7lr7Ih1apLSlXy+YwTY7neBvrfW8ZU GoTA== ARC-Message-Signature: i=1; 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If that succeeds then dtb_lapic_setup() registers the local APIC again eventually with a different address. Rewrite the code so that it only registers it once. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/devicetree.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -157,19 +157,15 @@ static void __init dtb_lapic_setup(void) /* Did the boot loader setup the local APIC ? */ if (!boot_cpu_has(X86_FEATURE_APIC)) { + /* Try force enabling, which registers the APIC address */ if (apic_force_enable(lapic_addr)) return; - } - smp_found_config = 1; - if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { - pr_info("Virtual Wire compatibility mode.\n"); - pic_mode = 0; } else { - pr_info("IMCR and PIC compatibility mode.\n"); - pic_mode = 1; + register_lapic_address(lapic_addr); } - - register_lapic_address(lapic_addr); + smp_found_config = 1; + pic_mode = !of_property_read_bool(dn, "intel,virtual-wire-mode"); + pr_info("%s compatibility mode.\n", pic_mode ? "IMCR and PIC" : "Virtual Wire"); } #endif /* CONFIG_X86_LOCAL_APIC */ From patchwork Tue Aug 1 10:46:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129278 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2644106vqg; Tue, 1 Aug 2023 05:50:33 -0700 (PDT) X-Google-Smtp-Source: APBJJlFXqxqHU77oo1r7n6IugwwntzCXoEkR0IdkfSbJI18pYBaRS0AOGeBWxmwF8ysRHGPyBnvy X-Received: by 2002:a17:907:9686:b0:98d:ebb7:a8b0 with SMTP id hd6-20020a170907968600b0098debb7a8b0mr3512043ejc.14.1690894233343; Tue, 01 Aug 2023 05:50:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690894233; cv=none; d=google.com; s=arc-20160816; b=rh9m5w/d3sI4V07O6OaLMNBjl53y7329CVHuCubzRCVJaJv4kV+cQ18N/ZPSjYQak3 GeZK4bH6ruFRe3MDJVdReP+qoksR+sZ2cFtfOO36Gkt1tGJvU/4nTwU9q7mkxa6rElhz i5zCTXSRoSTI1Kd56Ifuk1ZOl8+3txNFlTnNnxpxx4GecpnsrWXilqDV+szMr1xJ9jsV HBqcIAhpRY2wNaRWeABAIuCV/0G3clGTc5qidGZqixr/HzXvxKXSuysE/yv6wgiSSdPt C0oVtW5VSrd8ZcR95kuAsyMuUbILlNbrxo5kGslFyo5T4wunD00UGKK3VZ59rF9kzL56 UTXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=ny7Fxu7g7PBQMTLhRl8hSl0RLxzChrJ0DtIsWugH0fI=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=mXFDH0ghyFGL888kew1ZrWQkDpXYLEmML9zjVvlERCR4CtnOYkjVI1lN+aOof7IHOm /Ft18WaK1E1Iii31FU73gPp9juqezEB+j90XjJXrTUYfhiP5RR4kuHMhbdwwKiTQ56Yo +bifOPf9Gu/hbuuIQ0m/Z0awFR6QxLX+RcfYIk+8XX39EgSpzrGEkXP7T9/BJq7e461n K7wEHv5V+fmKL3fyYG3ylwNJDm3Fl/u8J3lPotNuqvc60J66xRy2RN12SEUXVUdZ9e4B DicODK/RDJSbtNrFruuPiH/lx572yF+eJExi65OkJ+5iyg4CA1cVFJZTcv7+zKKN+3cw /d4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=BPAjB4vd; dkim=neutral (no key) header.i=@linutronix.de header.b=VxUDSqkh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c8-20020a170906340800b00992ae2a902dsi7906612ejb.786.2023.08.01.05.50.09; Tue, 01 Aug 2023 05:50:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=BPAjB4vd; dkim=neutral (no key) header.i=@linutronix.de header.b=VxUDSqkh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234018AbjHAKrn (ORCPT + 99 others); Tue, 1 Aug 2023 06:47:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233322AbjHAKrD (ORCPT ); Tue, 1 Aug 2023 06:47:03 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 908BB198 for ; Tue, 1 Aug 2023 03:46:59 -0700 (PDT) Message-ID: <20230801103815.873683883@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886817; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ny7Fxu7g7PBQMTLhRl8hSl0RLxzChrJ0DtIsWugH0fI=; b=BPAjB4vdVAVpzkHQhq3RKknFBwLmqiC0PQPeBaGv2yI1+vqgsFSfeJVAkjBjXk932xKICx cjwDF/x/FR/Wa8/FPFs4YKeOkD+HUdrjCsZauvtlPo4sWry1R2R9uDqAWWtqfdP0xyGV3W dmsfBs2JsMMzx4GmRwOG/sKZBEnOGrS4k0QDdrFeiNPz7QnbJ6fdjjAVg4iv+h8x3hsodj SpIp0IbVsd28nECl3JtCSh9KARgn6a6IJi4psnng49S22I5Pap/3W0FWlbMgbxpmpsLe3h wnRp/Cd2kUTQNxt1Bak/aNxYfPWSEBaKMRX7X8yFD59XT+lVPxXP8S1gGvPsPg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886817; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ny7Fxu7g7PBQMTLhRl8hSl0RLxzChrJ0DtIsWugH0fI=; b=VxUDSqkhXaou4zUdSVLXZ/uaAtOAdPFDtjA6YJu+Zo3YsHYltJ0nPBqvvTWqVl1rpgoxYC BYnqVz62LO0p1cDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 13/60] x86/apic: Make some APIC init functions bool References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:46:57 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773031111845116119 X-GMAIL-MSGID: 1773031111845116119 Quite some APIC init functions are pure boolean, but use the success = 0, fail < 0 model. That's confusing as hell when reading through the code. Convert them to boolean. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 6 +++--- arch/x86/kernel/apic/apic.c | 36 ++++++++++++++++++------------------ arch/x86/kernel/devicetree.c | 2 +- 3 files changed, 22 insertions(+), 22 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -135,12 +135,12 @@ extern void setup_secondary_APIC_clock(v extern void lapic_update_tsc_freq(void); #ifdef CONFIG_X86_64 -static inline int apic_force_enable(unsigned long addr) +static inline bool apic_force_enable(unsigned long addr) { - return -1; + return false; } #else -extern int apic_force_enable(unsigned long addr); +extern bool apic_force_enable(unsigned long addr); #endif extern void apic_ap_setup(void); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2000,19 +2000,19 @@ void __init enable_IR_x2apic(void) * On AMD64 we trust the BIOS - if it says no APIC it is likely * not correctly set up (usually the APIC timer won't work etc.) */ -static int __init detect_init_APIC(void) +static bool __init detect_init_APIC(void) { if (!boot_cpu_has(X86_FEATURE_APIC)) { pr_info("No local APIC present\n"); - return -1; + return false; } mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; - return 0; + return true; } #else -static int __init apic_verify(void) +static bool __init apic_verify(void) { u32 features, h, l; @@ -2023,7 +2023,7 @@ static int __init apic_verify(void) features = cpuid_edx(1); if (!(features & (1 << X86_FEATURE_APIC))) { pr_warn("Could not enable APIC!\n"); - return -1; + return false; } set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; @@ -2036,15 +2036,15 @@ static int __init apic_verify(void) } pr_info("Found and enabled local APIC!\n"); - return 0; + return true; } -int __init apic_force_enable(unsigned long addr) +bool __init apic_force_enable(unsigned long addr) { u32 h, l; if (apic_is_disabled) - return -1; + return false; /* * Some BIOSes disable the local APIC in the APIC_BASE @@ -2067,11 +2067,11 @@ int __init apic_force_enable(unsigned lo /* * Detect and initialize APIC */ -static int __init detect_init_APIC(void) +static bool __init detect_init_APIC(void) { /* Disabled by kernel option? */ if (apic_is_disabled) - return -1; + return false; switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: @@ -2098,22 +2098,22 @@ static int __init detect_init_APIC(void) if (!force_enable_local_apic) { pr_info("Local APIC disabled by BIOS -- " "you can enable it with \"lapic\"\n"); - return -1; + return false; } - if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) - return -1; + if (!apic_force_enable(APIC_DEFAULT_PHYS_BASE)) + return false; } else { - if (apic_verify()) - return -1; + if (!apic_verify()) + return false; } apic_pm_activate(); - return 0; + return true; no_apic: pr_info("No local APIC present or hardware disabled\n"); - return -1; + return false; } #endif @@ -2129,7 +2129,7 @@ void __init init_apic_mappings(void) return; /* If no local APIC can be found return early */ - if (!smp_found_config && detect_init_APIC()) { + if (!smp_found_config && !detect_init_APIC()) { /* lets NOP'ify apic operations */ pr_info("APIC: disable apic facility\n"); apic_disable(); --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -158,7 +158,7 @@ static void __init dtb_lapic_setup(void) /* Did the boot loader setup the local APIC ? */ if (!boot_cpu_has(X86_FEATURE_APIC)) { /* Try force enabling, which registers the APIC address */ - if (apic_force_enable(lapic_addr)) + if (!apic_force_enable(lapic_addr)) return; } else { register_lapic_address(lapic_addr); From patchwork Tue Aug 1 10:46:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129258 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2633963vqg; Tue, 1 Aug 2023 05:30:47 -0700 (PDT) X-Google-Smtp-Source: APBJJlFpKjbXkNzXPor5k0AnFeQaceITWT7SoZJ5hvBCedwsvxV5QY/c489FhjgUpmRg5WfGiBIi X-Received: by 2002:a05:6a21:6811:b0:13d:ea25:9642 with SMTP id wr17-20020a056a21681100b0013dea259642mr4144449pzb.6.1690893047524; Tue, 01 Aug 2023 05:30:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893047; cv=none; d=google.com; s=arc-20160816; b=oQUWffKmG7ec21UNGpNMQuQp0wScCawJtActXwPcTnuQRPx1eVWT6wYHhWngaONza7 76rJjs0jCzPjmE73NrR4ahLluvmAhRgVlgZBDW3y0JarlWkejJGUeOBBvPUKR4HImIdn M9oQIPMP42eLpFvaDOIJ0OhxhbY3px30p7w9drQtq7IqXNUhH4s7MVXnlaWHWbLF6grv fHpBtfxQiJgCP+NP47u2Nw4+FtnIBziqtt6s73e+ln6DKpYrYz47FY2ZXJvZnGbODT6A H7qQZpsB8dpdV0a9uDHfELVvTa1RrLycc076lY7R04d2aphpx4mGV6vvg8dixVSAcafC iJQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=EJkw3wmb0xhqWNonEGYegw1kbsCG+7tuReZsQsrarng=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=rnqWZAyhCvrRv7hT8qlquD75SCIsB0NEf/5m4PjC/DsgMb3lRBdc5a7krnNgkdWxvJ SZ3/R/vflCjKHivkt+XkxLaBvouSBVdX6Whzo9fcdNB3FFeLQkJDk9OUH5kEgf2DAdNm vG7aQMPZ8tqwrX60AqjiR5ixhQ7gXf+eZE315eDMDfg+Tv5/D+/J/fIniGOBq6/efmGw xO7YeEp9iO4KT7/W4HJdOOkafaFEfurAvcXrCTGlzKqkREKyVexKCfpwa/3nCgi+u2HJ RkTxYQsbbOp4v8SEYTfZbeNiqbgXAcJFssXa7h15f8DJm5iXwYStxfWhnzJJ9nc1e2ui 6VVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=EDNg7MUM; dkim=neutral (no key) header.i=@linutronix.de header.b=u8G9h4g0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m21-20020a056a00081500b006875398611csi541200pfk.80.2023.08.01.05.30.32; Tue, 01 Aug 2023 05:30:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=EDNg7MUM; dkim=neutral (no key) header.i=@linutronix.de header.b=u8G9h4g0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233610AbjHAKrt (ORCPT + 99 others); Tue, 1 Aug 2023 06:47:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233582AbjHAKrF (ORCPT ); Tue, 1 Aug 2023 06:47:05 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5F9BE5C for ; Tue, 1 Aug 2023 03:47:00 -0700 (PDT) Message-ID: <20230801103815.927989749@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886818; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=EJkw3wmb0xhqWNonEGYegw1kbsCG+7tuReZsQsrarng=; b=EDNg7MUMxkWgPHgZUAro7549ueqK237B6jax7erstsq6P9g2AiA9vyAEBQvxt4IbNGpNTC 3Vc1Wb1LMRYQMlGOu5zvWHvY54yK0W8MXOjD3tWaQk1gfAI5AsWBXOWwbREouXU4uKiLf3 /YLaEqki/y0PKMFhskgcy9l/tyd/UybtjhuUvF7r2kn8zMwPdpl8ZCDF04eD7Rg3BfzjrU jVoLkLhHOBI5Bek5J88We4zFEcx7RK9vxb48sHFuc+vF8gdnDdg3fzblqPK8bR8VUztuyE 0W9l69TWclesYL4z56evQZaAeSDIURaKkeAmqWoZIQs9Xs9nQJYpY9RFNmUjtA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886818; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=EJkw3wmb0xhqWNonEGYegw1kbsCG+7tuReZsQsrarng=; b=u8G9h4g0Ze769QRkXmduC9mOPnQO93TsMo8Tu7hEaveDB5G9gNuqxTxYogShNgfhELF6Yl e5dkbXlT+zKt4FDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 14/60] x86/apic: Split register_apic_address() References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:46:58 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773029868376111906 X-GMAIL-MSGID: 1773029868376111906 Split the fixmap setup out of register_lapic_address() and reuse it when the X2APIC is disabled during setup. This avoids that the APIC ID is registered twice. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1852,6 +1852,8 @@ void x2apic_setup(void) __x2apic_enable(); } +static __init void apic_set_fixmap(void); + static __init void x2apic_disable(void) { u32 x2apic_id, state = x2apic_state; @@ -1872,7 +1874,7 @@ static __init void x2apic_disable(void) } __x2apic_disable(); - register_lapic_address(mp_lapic_addr); + apic_set_fixmap(); } static __init void x2apic_enable(void) @@ -2145,17 +2147,21 @@ void __init init_apic_mappings(void) } } +static __init void apic_set_fixmap(void) +{ + set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); + apic_mmio_base = APIC_BASE; + apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", + apic_mmio_base, mp_lapic_addr); + apic_read_boot_cpu_id(false); +} + void __init register_lapic_address(unsigned long address) { mp_lapic_addr = address; - if (x2apic_mode) - return; - - set_fixmap_nocache(FIX_APIC_BASE, address); - apic_mmio_base = APIC_BASE; - apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", APIC_BASE, address); - apic_read_boot_cpu_id(false); + if (!x2apic_mode) + apic_set_fixmap(); } /* From patchwork Tue Aug 1 10:46:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129322 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2693732vqg; Tue, 1 Aug 2023 07:08:11 -0700 (PDT) X-Google-Smtp-Source: APBJJlHyZmFrFfCcfas3MASQWbQXLcX0+Fkrsd/wGsvjaBv8zRcY+XNt/hTri1kLVbjjcWHWjr25 X-Received: by 2002:a17:906:221c:b0:997:deb1:ff6a with SMTP id s28-20020a170906221c00b00997deb1ff6amr2679565ejs.22.1690898890955; Tue, 01 Aug 2023 07:08:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690898890; cv=none; d=google.com; s=arc-20160816; b=YM/ng3Kmh7GYJZkEPC/CQpkWg6gXJBWBgBxBa8CtK6KGWdC1Pbq1gaOFkmIBZ5d8er gVNoVhjeanipxsk//CsaH/ZZbbin6t9yvMS0Dakv6uyMUybeoPA7yu3haqfcluy4FAMl 5NljzawhireqwuGnoQj0IVbZokjPWNjyMNVtSO4toF81lst7L5YwJ6/EAdtbp1EHLT5+ XagGpTIu5+ATxjzQGS1YshnmsHXUb76i5niAKUF8sea+y+GR9i8hmnqQ/WguZuIfRgVV pga6cG4UHaO1FT3d+ylrGPtD6PA7+OkbZwJ4YjGH/kbMd/wYgYCrzktl/nbjVQYN5PLh hZ+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=855ZylECG6DnmhUb4ZnT7LjFoXWMj2iP75o58u/ioxI=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=AgQv4+UxHMO65hvmlmjlBuX8zXf6NCjokDICEZSgAopFQAOXhK+u3hj9rWa9rJZVAf rGL7JNTQVlR2OrWEK1UQ3UH5YLCvoLAnqbQlPLLUioChklqlyEpb4KhqvX7HFNuB49dq SQ5KPqJ0L56RZPUOX9s2NVs8+zCBYON9VHgfS9uRcfuom1aCJcwKlD0RtXbszE3Au+Fw inYd+Nh+tzIzV+775gX2Th/2md9qvn63pKv5EvszuyuBcSp3o4+Zl+0SIdxU26UfUkXD U4plwNHcfw8cYkTtsYBVbNx1grAkjg8Cn5Ju9dt/YTFr44McnL3pafnnt2hqq7WLbNWL hPCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=pTCyVBX2; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=bUHVRteS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p2-20020a1709061b4200b00992acaba375si8811730ejg.842.2023.08.01.07.07.46; Tue, 01 Aug 2023 07:08:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=pTCyVBX2; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=bUHVRteS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233838AbjHAKrx (ORCPT + 99 others); Tue, 1 Aug 2023 06:47:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233814AbjHAKrP (ORCPT ); Tue, 1 Aug 2023 06:47:15 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E466010EA for ; Tue, 1 Aug 2023 03:47:01 -0700 (PDT) Message-ID: <20230801103815.982686364@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886820; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=855ZylECG6DnmhUb4ZnT7LjFoXWMj2iP75o58u/ioxI=; b=pTCyVBX29M3GOiFt59+IXxKYeqR/I67qvEB3ogvwJHvgo1vR5ALoFqn8DhOptKU7amoouY KROwf67itVrS6IjJBS03Dd3MMb2h9IhET4B/0BAKvZp/W+74ptemTjYjeQgfim/Tmw+pz0 Jb5PiNfHfHXT74pU5ORuDVLPQb9Y5rXv1Qr9fdoUGqMCsV33+aZTeTgHwSFgJ3L2WmvX5V L2muTzsXyTCwGCKTTabJh53dlWSxy0FwKy/cV9PGlq730qDc6V8jFn5xSvjJkDECrgr3k6 SfTggafIxJgrWNTOe02wl5KId1BrEvTW7uI6rnLuyZTFXTfAuMNVI0qRC9SZ+g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886820; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=855ZylECG6DnmhUb4ZnT7LjFoXWMj2iP75o58u/ioxI=; b=bUHVRteSCjoZrZuEDmFj0kyRe92hF6caXnfPMeisxnnloOmimG02wEaZxRj4erBW2pEVmw Qaj96anRp4QVryAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 15/60] x86/apic: Sanitize APIC address setup References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:46:59 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773035995594879572 X-GMAIL-MSGID: 1773035995594879572 Convert places which just write mp_lapic_addr and let them register the local APIC address directly instead of relying on magic other code to do so. Add a WARN_ON() into register_lapic_address() which is raised when register_lapic_address() is invoked more than once during boot. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/mpspec.h | 1 - arch/x86/kernel/apic/apic.c | 29 ++++++++++------------------- arch/x86/kernel/mpparse.c | 11 ++--------- 3 files changed, 12 insertions(+), 29 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -41,7 +41,6 @@ extern DECLARE_BITMAP(mp_bus_not_pci, MA extern unsigned int boot_cpu_physical_apicid; extern u8 boot_cpu_apic_version; -extern unsigned long mp_lapic_addr; #ifdef CONFIG_X86_LOCAL_APIC extern int smp_found_config; --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -172,7 +172,7 @@ static __init int setup_apicpmtimer(char __setup("apicpmtimer", setup_apicpmtimer); #endif -unsigned long mp_lapic_addr __ro_after_init; +static unsigned long mp_lapic_addr __ro_after_init; bool apic_is_disabled __ro_after_init; /* Disable local APIC timer from the kernel commandline or via dmi quirk */ static int disable_apic_timer __initdata; @@ -2009,12 +2009,12 @@ static bool __init detect_init_APIC(void return false; } - mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; + register_lapic_address(APIC_DEFAULT_PHYS_BASE); return true; } #else -static bool __init apic_verify(void) +static bool __init apic_verify(unsigned long addr) { u32 features, h, l; @@ -2028,15 +2028,15 @@ static bool __init apic_verify(void) return false; } set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); - mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; /* The BIOS may have set up the APIC at some other address */ if (boot_cpu_data.x86 >= 6) { rdmsr(MSR_IA32_APICBASE, l, h); if (l & MSR_IA32_APICBASE_ENABLE) - mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; + addr = l & MSR_IA32_APICBASE_BASE; } + register_lapic_address(addr); pr_info("Found and enabled local APIC!\n"); return true; } @@ -2063,7 +2063,7 @@ bool __init apic_force_enable(unsigned l enabled_via_apicbase = 1; } } - return apic_verify(); + return apic_verify(addr); } /* @@ -2105,7 +2105,7 @@ static bool __init detect_init_APIC(void if (!apic_force_enable(APIC_DEFAULT_PHYS_BASE)) return false; } else { - if (!apic_verify()) + if (!apic_verify(APIC_DEFAULT_PHYS_BASE)) return false; } @@ -2130,27 +2130,16 @@ void __init init_apic_mappings(void) if (x2apic_mode) return; - /* If no local APIC can be found return early */ if (!smp_found_config && !detect_init_APIC()) { - /* lets NOP'ify apic operations */ pr_info("APIC: disable apic facility\n"); apic_disable(); - } else { - apic_phys = mp_lapic_addr; - - /* - * If the system has ACPI MADT tables or MP info, the LAPIC - * address is already registered. - */ - if (!acpi_lapic && !smp_found_config) - register_lapic_address(apic_phys); } } static __init void apic_set_fixmap(void) { set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); - apic_mmio_base = APIC_BASE; + apic_phys = apic_mmio_base = APIC_BASE; apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", apic_mmio_base, mp_lapic_addr); apic_read_boot_cpu_id(false); @@ -2158,6 +2147,8 @@ static __init void apic_set_fixmap(void) void __init register_lapic_address(unsigned long address) { + /* This should only happen once */ + WARN_ON_ONCE(mp_lapic_addr); mp_lapic_addr = address; if (!x2apic_mode) --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -378,11 +378,6 @@ static inline void __init construct_defa int i; /* - * local APIC has default address - */ - mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; - - /* * 2 CPUs, numbered 0 & 1. */ processor.type = MP_PROCESSOR; @@ -523,10 +518,8 @@ void __init default_get_smp_config(unsig */ if (mpf->feature1) { if (early) { - /* - * local APIC has default address - */ - mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; + /* Local APIC has default address */ + register_lapic_address(APIC_DEFAULT_PHYS_BASE); goto out; } From patchwork Tue Aug 1 10:47:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129331 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2724637vqg; Tue, 1 Aug 2023 07:58:06 -0700 (PDT) X-Google-Smtp-Source: APBJJlHa0FmElPUzytgqYFgmMk1LC/C3BPvxkIbUIpPJpVps/upjtSrjL/QyHnCK2muKX/3JxAOX X-Received: by 2002:a17:902:ea05:b0:1b9:f9a1:85f1 with SMTP id s5-20020a170902ea0500b001b9f9a185f1mr14596357plg.19.1690901885665; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id kw7-20020a170902f90700b001b0450241d1si2175938plb.283.2023.08.01.07.57.43; Tue, 01 Aug 2023 07:58:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=U9fTojmo; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233613AbjHAKsO (ORCPT + 99 others); Tue, 1 Aug 2023 06:48:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233831AbjHAKrP (ORCPT ); Tue, 1 Aug 2023 06:47:15 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 253D31BC1 for ; Tue, 1 Aug 2023 03:47:03 -0700 (PDT) Message-ID: <20230801103816.037141488@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886821; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tJxhzLbo7FHsorrk3uDGkPGMiQ+vhYqtvOcmkhfQkMo=; b=U9fTojmo7YTcGSu2uGhvgsUHlJI8A0uXPv71+yTcZ/LYKQOKnqCp4KdCGgJw4v2lcxM49V ky/MTAMOsUJH7OUq3Mt8ct8bwPRSWMzi1TvSJYtXt4UWLaMEDFdNm53PnuZS6id+toeO3p AWABibgza6i0JB2Vhm3yy29WpSaJncxktS15YRbWrQdmvsS2RNXR/xD5ktZLv4omW3SmYB gWYj4EGJUdckSA7l0BdMDFpzSnhmuztNH6tmRYuhTxi/4Tyumy3IXtzoIBrWPg1v1Ov3IG TXQeAU2+ikWKRivcKd51/OROabMYmCR2CPk9TnISkZi+Cd+hwU0R18Kr2wzqPQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886821; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tJxhzLbo7FHsorrk3uDGkPGMiQ+vhYqtvOcmkhfQkMo=; b=5j0195GBEXYU0jCLsBplnJJCcn8j0+ScICey6/FPzt7J14hupnC5EaVN4bslJ03Ax9Sj6S RUFCFbJmI8gyp2Dw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt Subject: [patch V3 16/60] x86/xen/pv: Pretend that it found SMP configuration References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:01 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773039135507115983 X-GMAIL-MSGID: 1773039135507115983 Unlike all other SMP configuration "parsers" XEN/PV does not set smp_found_config which is inconsistent and prevents doing proper decision logic based on this flag. Make XEN/PV pretend that it found SMP configuration. Signed-off-by: Thomas Gleixner --- V3: New patch to address XEN/PV breakage - Juergen --- arch/x86/xen/smp_pv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -182,7 +182,8 @@ static void __init _get_smp_config(unsig if (subtract) set_nr_cpu_ids(nr_cpu_ids - subtract); #endif - + /* Pretend to be a proper enumerated system */ + smp_found_config = 1; } static void __init xen_pv_smp_prepare_boot_cpu(void) From patchwork Tue Aug 1 10:47:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129187 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2594538vqg; Tue, 1 Aug 2023 04:15:17 -0700 (PDT) X-Google-Smtp-Source: APBJJlE1mzQ2i9EoGdKWB2jNFuiIMKRMIR9tXgYTU2RMw7rq3BoltVetw1tRXosFZLe9kh/7b+Wf X-Received: by 2002:aa7:88cb:0:b0:682:713e:e510 with SMTP id k11-20020aa788cb000000b00682713ee510mr15403299pff.27.1690888516801; Tue, 01 Aug 2023 04:15:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888516; cv=none; d=google.com; s=arc-20160816; b=O8VgWCB5xMHIhTazRcTgoX3GRzXlNpfgXayH929vbfeGVRYWnSNEgQke5J/ur8mTU6 Qi53W8hhDeyvKADX88RiBl8NpaJMdFzWy2A1sLMATHgYl5k6ZlQEzP7gkmHFEmL4tWbZ 0trCQz2zOWwoYlnLhApDjGSPdw09L/GJSD7Bqfwc6li3rFphAFHJNjIFKCWWjgjfUwA5 xKWU34AL5oSgpfxk/tZxliHcGZwhPiVoStFPAYfRWsLQJYv5oItZj4OFLU81mTTLt1KA LglnzsFsAcN2fIy/cYlb+l0RbrOlMIf4cUxHf7w8W1ezYd3caDlekVtR8OpE7FBJFL13 ZpRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=c71eHbYg+VP7OJhjZCVHVzp0AtRxO5V4C+TDLxCJHes=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=L8HSwgDN6jwf5XNa2LyCPyQa1uaBF+4Ylr9x0iwLaoh5H8tSOzX4XLS50bHF579OTa lBuXTstapyRO2OJ1xnMZAxnjt/KrNHhF7Cly+N1EBCNPjjwH+tTdMVepQo3Xmy6N841Y 79+++VEzjzjaZFxtseO2WXmgAOKsP3tcV04bb7PNiMxeN46PUsuzx2pyxXnIS9zdyclc 4cc0TdCzMdPZoc+xL6+YF46rsEAo4b4EHeeQ/7An4qJQdqAH3l4FEe1Wivib+lqWkIQY vIkvx1c8G9vj1dWyinsULaiIRE8x2Oj5wYW6wqL8wYbWi1xCSi1HimMNdiSWcQAWKBfr dqYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=idVBIXa4; dkim=neutral (no key) header.i=@linutronix.de header.b=EeGtBu9Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Make init_apic_mappings(), which tries to enable the local APIC in the case that no SMP configuration was found set num_processors to 1. This allows to remove yet another check for the local APIC and yet another place which registers the boot CPUs local APIC ID. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 9 ++++++--- arch/x86/kernel/smpboot.c | 18 ------------------ 2 files changed, 6 insertions(+), 21 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2130,9 +2130,12 @@ void __init init_apic_mappings(void) if (x2apic_mode) return; - if (!smp_found_config && !detect_init_APIC()) { - pr_info("APIC: disable apic facility\n"); - apic_disable(); + if (!smp_found_config) { + if (!detect_init_APIC()) { + pr_info("APIC: disable apic facility\n"); + apic_disable(); + } + num_processors = 1; } } --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1397,24 +1397,6 @@ early_param("possible_cpus", _setup_poss { int i, possible; - /* No processor was found in mptable or ACPI MADT */ - if (!num_processors) { - if (boot_cpu_has(X86_FEATURE_APIC)) { - int apicid = boot_cpu_physical_apicid; - int cpu = read_apic_id(); - - pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); - - /* Make sure boot cpu is enumerated */ - if (apic->cpu_present_to_apicid(0) == BAD_APICID && - apic->apic_id_valid(apicid)) - generic_processor_info(apicid); - } - - if (!num_processors) - num_processors = 1; - } - i = setup_max_cpus ?: 1; if (setup_possible_cpus == -1) { possible = num_processors; From patchwork Tue Aug 1 10:47:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129184 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2592241vqg; Tue, 1 Aug 2023 04:10:35 -0700 (PDT) X-Google-Smtp-Source: APBJJlHWJmoBMlBCqLwxK3DgOdezMiNkAN8B16Ji7GZ7T9VR+/WuqEHPq1Rv1bVx9OTTak9Vzowf X-Received: by 2002:a17:906:58cc:b0:991:d414:d889 with SMTP id e12-20020a17090658cc00b00991d414d889mr3164789ejs.15.1690888235362; Tue, 01 Aug 2023 04:10:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888235; cv=none; d=google.com; s=arc-20160816; b=H6tHfl1SnEyi43ONvfrZzfH727ISknqWRv5nH5SAsUWZJHewsisVlS0/8yHsL85IBK Vbd9q8FCZM7QTrWqiG0L1+E1Jjt1IiY0lO6cFIzpqlivud50GYCyRQljGN8ogoj+Kb+j grmiaWEZC0F142oFfvaOdN0b9KQGPvuuB2ah2cuv7EFBqoBD/6pUUY9lg9ozJLx7k3AP SYMc3q/ml2YEzB2YAuGP8bZUTHp3YGuAVz1vpv9Gb+xenGKDYa+QHOhpV3pXBhC6dOb+ J+z5n7cj6p8TFkwl6ajO9YqNlUzmHeKPjffZp6XalyCLUsxMTQBUlpWmT9wZUddnqiZ5 H7dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=6qIRs7n/9rrrflFIJeawzXHaVLgyJbrokbfl4taony4=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=VhB7IgFveSFD/0+up5/YcNorJpsLwvMdzc6fTk/su1ZsgYkQHgBS5QGuiAy9XSt/SB 8RGpG9fvPBR7nz7b8I8SJ0U2Im4OusOsmefp/Vs9azJe5cS+5jqnl1nK1hmoXXuB7AAL cTz8f8FvbyWyl8LFG8zuorUlBQPrr528VeHU61NMY1JWZudjsVdsjk53rjfVpYoYmaRZ m7S/rtMyWXbZ3cMbVz5IPUbtVO1BlZOeuwooPLfLI0o5PSBifviLQOtU0F6VC0ucqdk/ cF7y8ctPwW1ce+jfNR7yQDxUIYhjdiWFAdHUzaa4AbYOAu+oUCSUUs3MvY+YFIdI6PNi Y5Hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=OLfUT9n1; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=31sXViTL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t7-20020a1709063e4700b0099bce8c04d8si8779311eji.141.2023.08.01.04.10.11; Tue, 01 Aug 2023 04:10:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=OLfUT9n1; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=31sXViTL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231761AbjHAKsV (ORCPT + 99 others); Tue, 1 Aug 2023 06:48:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233872AbjHAKrU (ORCPT ); Tue, 1 Aug 2023 06:47:20 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F5122133 for ; Tue, 1 Aug 2023 03:47:05 -0700 (PDT) Message-ID: <20230801103816.145455909@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886823; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6qIRs7n/9rrrflFIJeawzXHaVLgyJbrokbfl4taony4=; b=OLfUT9n1mUZyw5TECgbWAB5jfUJ52UrvxCKcdeBeSS+iYQgLuwWYiA3m6lc+1Bjd420tMf NvaC9yrqKrOYfGOiTgKeMDAHMSEC1NU2OZnm0I8KN5422y5ZIXCWFdQz04M2b76EmEPDTC 7HOsC3qZUM+W59b42id+MtTuQg0KlzTMrzD22AVJPJPdCrt70pzEfSgK+uq4PTLNe6d29Q PRMyGAb/KXuWxB5J/8pGP1kSO2DJXCa1G+00W0IE5mMrRS7fasluWbmKsZ2iHr5PZJMled 5iUdhst071WDCZ8dvAlRFyXaK1xSxnIPEQGl4MT4CJ+1kseIe2e5gHkN9SL0mg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886823; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6qIRs7n/9rrrflFIJeawzXHaVLgyJbrokbfl4taony4=; b=31sXViTLfNTTpcZVXA5t7x3tRVJZ2cGy49vy5qSl04ETXzv1N63xVYH/9ppPNU0ig73l6Q iqZMOqOaZVOJ3nCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 18/60] x86/apic: Nuke another processor check References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:03 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773024822237019440 X-GMAIL-MSGID: 1773024822237019440 The boot CPUs local APIC is now always registered, so there is no point to have another unreadable validatation for it. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/smpboot.c | 17 ----------------- 1 file changed, 17 deletions(-) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1181,23 +1181,6 @@ static void __init smp_sanity_check(void set_nr_cpu_ids(8); } #endif - - if (!physid_isset(read_apic_id(), phys_cpu_present_map)) { - pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", - read_apic_id()); - - physid_set(read_apic_id(), phys_cpu_present_map); - } - - /* - * Should not be necessary because the MP table should list the boot - * CPU too, but we do it for the sake of robustness anyway. - */ - if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { - pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", - boot_cpu_physical_apicid); - physid_set(read_apic_id(), phys_cpu_present_map); - } preempt_enable(); } From patchwork Tue Aug 1 10:47:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129274 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2641519vqg; Tue, 1 Aug 2023 05:45:17 -0700 (PDT) X-Google-Smtp-Source: APBJJlEFfnTEf0KfhKT33gIpMnsjgexoupfOZqbcRZhvGPiM6CU8WlY2kDA6xHl3YWWElECpwdak X-Received: by 2002:a17:90a:fd03:b0:25e:d013:c22c with SMTP id cv3-20020a17090afd0300b0025ed013c22cmr11489613pjb.47.1690893917214; Tue, 01 Aug 2023 05:45:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893917; cv=none; d=google.com; s=arc-20160816; b=dmH4v3SMgf+6mxrquSkoYoiozukEYEi2LDSsSHUe+lTlaS2HF0P2Ojdmf5lzW8EkvO iYhlbMzIQwOVnbpGAW/jUkbEP+6MVuac6wnhJUbXgp7A8JeZ+0naWgQLPLQEpCmm78wP cqIe7vylJpxt5tC1yMa+z3S+XRTvV9vxuUVDYE9SNWCwrX8hvE04D0QOpMmgaZEvJSz6 RwOtI5C5dKlpl0tgeNbAKI34wpGRbrFaIJNeLVtkScj4gBf/SRah5FZ7pwSgmluEKOam wutErA400QAra75+3l4AAik9iXIObh/YOIKPfmNKNpJE/iwviSyhkvpOJmr2zmLE12dE YT3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=xYutxZ9rMLywIqqTjqfZZaF9PJm3LP88T/JNH/GhwYU=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=luhq996L0nrDs0o/WgcNSmHhYNJnXDe7hExRB4rZLymYHopq2fo+0eIF3MY2XR11kv WUZ3TZ5Kui+BBLCfBZuPKpfc2zPewRbzXjBkktaefRIx8dQlF2UtTB30Ph8u+Kt7WnAF MKIfm+acOQ8MZkZIFtsGyvGC92XGscisJUUaufN9i8OiwmW2rIwweiHwvtIofZGJhLwo n3hy7QCwa1Yv8g9jnsiZNHrf17fLApSKtcWNppgNaI2kDU167lu5MrGM8rQ7NaEC8z6e lAVH8AEyguNWh8uGrnmR/ozscgp9AxZtMG935s18PYI6XqFbGv3LQboDZ7alwi7mmoXP Q2PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=X2JbTKyO; dkim=neutral (no key) header.i=@linutronix.de header.b=bIE1q7r5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Remove the gunk which was even outright wrong in the bigsmp_32 case which returned true unconditionally. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 -- arch/x86/kernel/apic/apic_common.c | 5 ----- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/apic_numachip.c | 2 -- arch/x86/kernel/apic/bigsmp_32.c | 6 ------ arch/x86/kernel/apic/probe_32.c | 1 - arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 1 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 - arch/x86/xen/apic.c | 1 - 11 files changed, 24 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -305,7 +305,6 @@ struct apic { void (*setup_apic_routing)(void); int (*cpu_present_to_apicid)(int mps_cpu); void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); - int (*check_phys_apicid_present)(int phys_apicid); int (*phys_pkg_id)(int cpuid_apic, int index_msb); u32 (*get_apic_id)(unsigned long x); @@ -485,7 +484,6 @@ extern u32 apic_flat_calc_apicid(unsigne extern bool default_check_apicid_used(physid_mask_t *map, int apicid); extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); extern int default_cpu_present_to_apicid(int mps_cpu); -extern int default_check_phys_apicid_present(int phys_apicid); #else /* CONFIG_X86_LOCAL_APIC */ --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -35,11 +35,6 @@ int default_cpu_present_to_apicid(int mp } EXPORT_SYMBOL_GPL(default_cpu_present_to_apicid); -int default_check_phys_apicid_present(int phys_apicid) -{ - return physid_isset(phys_apicid, phys_cpu_present_map); -} - int default_apic_id_valid(u32 apicid) { return (apicid < 255); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -124,7 +124,6 @@ static struct apic apic_flat __ro_after_ .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, - .check_phys_apicid_present = default_check_phys_apicid_present, .phys_pkg_id = flat_phys_pkg_id, .get_apic_id = flat_get_apic_id, @@ -213,7 +212,6 @@ static struct apic apic_physflat __ro_af .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, - .check_phys_apicid_present = default_check_phys_apicid_present, .phys_pkg_id = flat_phys_pkg_id, .get_apic_id = flat_get_apic_id, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -107,8 +107,6 @@ struct apic apic_noop __ro_after_init = .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = physid_set_mask_of_physid, - .check_phys_apicid_present = default_check_phys_apicid_present, - .phys_pkg_id = noop_phys_pkg_id, .get_apic_id = noop_get_apic_id, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -257,7 +257,6 @@ static const struct apic apic_numachip1 .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, - .check_phys_apicid_present = default_check_phys_apicid_present, .phys_pkg_id = numachip_phys_pkg_id, .get_apic_id = numachip1_get_apic_id, @@ -303,7 +302,6 @@ static const struct apic apic_numachip2 .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, - .check_phys_apicid_present = default_check_phys_apicid_present, .phys_pkg_id = numachip_phys_pkg_id, .get_apic_id = numachip2_get_apic_id, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -63,11 +63,6 @@ static void bigsmp_ioapic_phys_id_map(ph physids_promote(0xFFL, retmap); } -static int bigsmp_check_phys_apicid_present(int phys_apicid) -{ - return 1; -} - static int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb) { return cpuid_apic >> index_msb; @@ -138,7 +133,6 @@ static struct apic apic_bigsmp __ro_afte .setup_apic_routing = bigsmp_setup_apic_routing, .cpu_present_to_apicid = bigsmp_cpu_present_to_apicid, .apicid_to_cpu_present = physid_set_mask_of_physid, - .check_phys_apicid_present = bigsmp_check_phys_apicid_present, .phys_pkg_id = bigsmp_phys_pkg_id, .get_apic_id = bigsmp_get_apic_id, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -80,7 +80,6 @@ static struct apic apic_default __ro_aft .setup_apic_routing = setup_apic_flat_routing, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = physid_set_mask_of_physid, - .check_phys_apicid_present = default_check_phys_apicid_present, .phys_pkg_id = default_phys_pkg_id, .get_apic_id = default_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -250,7 +250,6 @@ static struct apic apic_x2apic_cluster _ .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, - .check_phys_apicid_present = default_check_phys_apicid_present, .phys_pkg_id = x2apic_phys_pkg_id, .get_apic_id = x2apic_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -174,7 +174,6 @@ static struct apic apic_x2apic_phys __ro .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, - .check_phys_apicid_present = default_check_phys_apicid_present, .phys_pkg_id = x2apic_phys_pkg_id, .get_apic_id = x2apic_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -846,7 +846,6 @@ static struct apic apic_x2apic_uv_x __ro .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, - .check_phys_apicid_present = default_check_phys_apicid_present, .phys_pkg_id = uv_phys_pkg_id, .get_apic_id = x2apic_get_apic_id, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -154,7 +154,6 @@ static struct apic xen_pv_apic = { .setup_apic_routing = NULL, .cpu_present_to_apicid = xen_cpu_present_to_apicid, .apicid_to_cpu_present = physid_set_mask_of_physid, /* Used on 32-bit */ - .check_phys_apicid_present = default_check_phys_apicid_present, /* smp_sanity_check needs it */ .phys_pkg_id = xen_phys_pkg_id, /* detect_ht */ .get_apic_id = xen_get_apic_id, From patchwork Tue Aug 1 10:47:05 2023 Content-Type: text/plain; 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Provide an inline for this and check apic_mmio_base which is only set when the local APIC has been mapped. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -99,6 +99,11 @@ static bool virt_ext_dest_id __ro_after_ /* For parallel bootup. */ unsigned long apic_mmio_base __ro_after_init; +static inline bool apic_accessible(void) +{ + return x2apic_mode || apic_mmio_base; +} + /* * Map cpu index to physical APIC ID */ @@ -199,8 +204,6 @@ unsigned int lapic_timer_period = 0; static void apic_pm_activate(void); -static unsigned long apic_phys __ro_after_init; - /* * Get the LAPIC version */ @@ -1127,8 +1130,7 @@ void clear_local_APIC(void) int maxlvt; u32 v; - /* APIC hasn't been mapped yet */ - if (!x2apic_mode && !apic_phys) + if (!apic_accessible()) return; maxlvt = lapic_get_maxlvt(); @@ -1218,8 +1220,7 @@ void apic_soft_disable(void) */ void disable_local_APIC(void) { - /* APIC hasn't been mapped yet */ - if (!x2apic_mode && !apic_phys) + if (!apic_accessible()) return; apic_soft_disable(); @@ -2142,7 +2143,7 @@ void __init init_apic_mappings(void) static __init void apic_set_fixmap(void) { set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); - apic_phys = apic_mmio_base = APIC_BASE; + apic_mmio_base = APIC_BASE; apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", apic_mmio_base, mp_lapic_addr); apic_read_boot_cpu_id(false); @@ -2896,11 +2897,11 @@ early_param("apic", apic_set_verbosity); static int __init lapic_insert_resource(void) { - if (!apic_phys) + if (!apic_mmio_base) return -1; /* Put local APIC into the resource map. */ - lapic_resource.start = apic_phys; + lapic_resource.start = apic_mmio_base; lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; insert_resource(&iomem_resource, &lapic_resource); From patchwork Tue Aug 1 10:47:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129216 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2599647vqg; Tue, 1 Aug 2023 04:25:49 -0700 (PDT) X-Google-Smtp-Source: APBJJlGRSfKVKQFf/WF5NAVnT9WZKJEiIMA/oNjbME59CPyu7rMQm3UHloEV68HexGg0eXxFbtVL X-Received: by 2002:a17:906:145:b0:98e:933:28fe with SMTP id 5-20020a170906014500b0098e093328femr2243416ejh.66.1690889149084; Tue, 01 Aug 2023 04:25:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690889149; cv=none; d=google.com; s=arc-20160816; b=JUmDGYhWaeg+SzGKl8Emcyx/B4TPIlKnBpXmfUu6Rys+CycnhukR+KdVNSd+s5UvrB H+WEdl8VEycHEhmzXPy+aRyWMpNdFp/wczJ0ogkDMEYgLXeOZXVUA9dBbQUj9VnlUE6U acKO/kPTBDe31NH1KrHN1tlHz7iKdVApFZCYB9C8kIYgTjan4I4xlpTOYcSo2P7ILgqh JLIKg6+lq+87kp47u777CfzlpYw0jdMuS64uinleZKQ8KRpQ9cgmx/Z8oTM+9i8O6s0u XHkWFt2izhe3LX5BpQHw4q/mzYT/oPD+zuRwbnm7DFCVwn3PEkOfich5btG8WCaqxjk5 IsJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=px8ty2iQZiEFzcpK/cPxq1ShjeuaXrZPHQ/rgezGckM=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=mojNqXvjt/w0bHDiFEG1Hz5LghTSVy7pvqXcWNzBfShojMngh4vl5Asb9dIqgRt9U4 DAFnscIS/gBFl+DUnPBNIS1zWBjSq8HBSOcj9KkLSgOAOrhcHFzUAeQz9xJFBEX5lFsp uyYBcG8D9YGG/0Gj7tcf1lotK9zgQ4vjYEqZRIES/oCeAi5u9VBCyhvqk07Nwe+qQirk 3Rvy1xv508VMb9dTgwZ7gW9qNqVWg86i4usfl9YiJNnzd2NBbvemta77sxBIrxXpVJVW 016uKjFGyONGolhklOFUYDx4xligiudiQyqVJYug7NFtqV0xQtbH9m7EvVY7n9bJZ/ct dD5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=fN4MSQP7; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h15-20020a1709063c0f00b00992e21b04aasi8605191ejg.720.2023.08.01.04.25.25; Tue, 01 Aug 2023 04:25:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=fN4MSQP7; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233948AbjHAKsb (ORCPT + 99 others); Tue, 1 Aug 2023 06:48:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234041AbjHAKrq (ORCPT ); Tue, 1 Aug 2023 06:47:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5048626B2 for ; Tue, 1 Aug 2023 03:47:09 -0700 (PDT) Message-ID: <20230801103816.311443621@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886827; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=px8ty2iQZiEFzcpK/cPxq1ShjeuaXrZPHQ/rgezGckM=; b=fN4MSQP7F8tFfrytV4MBVLdl8E64vOWXt1X+hSgy1xlPYmIAwUpQMDIuA9f1Q7jAnZECwc QjolT7Rh3eE4klE/3bk/PgLukJlTkQMbJClApoQFd2uMzHW7V9L9YMOwaK3dwRflkDIJcp K8EGJ4u16NSjR9L4GVoqMjDIeLAvGTMof8Vh49BH/QI/Ij+a9qSFArnj2A5XPQGpxcW8em EUU/HacVIqHP9Xfe7PnB6pBhHvjcBZKoDHqXjX570+TIwjo9QAUxrJAj5EUhoJ3s+3UtVa X4CAqVMh7hsd9Gj1f2Mxw4IPQ/mUXs7HV12dmUXhGAowyHtuS2zLhXPAJ4K4XA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886827; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=px8ty2iQZiEFzcpK/cPxq1ShjeuaXrZPHQ/rgezGckM=; b=EC0bGdFx/xnn0Qw1/zLOiD04Tf3Zy+yX8+wSoT2L1XAi7bitLunEwo5X9dd3NEKLfm+SMy u3/2RapJD4K9N0Bw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 21/60] x86/apic/32: Sanitize logical APIC ID handling References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:07 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025780557198640 X-GMAIL-MSGID: 1773025780557198640 apic::x86_32_early_logical_apicid() is yet another historical joke. It is used to preset the x86_cpu_to_logical_apicid per CPU variable during APIC enumeration with: - 1 shifted left by the CPU number - the physical APIC ID in case of bigsmp The latter is hillarious because bigsmp uses physical destination mode which never can use the logical APIC ID. It gets even worse. As bigsmp can be enforced late in the boot process the probe function overwrites the per CPU variable which is never used for this APIC type once again. Remove that gunk and store 1 << cpunr unconditionally if and only if the CPU number is less than 8, because the default logical destination mode only allows up to 8 CPUs. This is just an intermediate step before removing the per CPU insanity completely. Stay tuned. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 13 ------------- arch/x86/kernel/apic/apic.c | 4 ++-- arch/x86/kernel/apic/apic_noop.c | 11 ----------- arch/x86/kernel/apic/bigsmp_32.c | 18 ------------------ arch/x86/kernel/apic/probe_32.c | 7 ------- 5 files changed, 2 insertions(+), 51 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -315,19 +315,6 @@ struct apic { /* wakeup secondary CPU using 64-bit wakeup point */ int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); -#ifdef CONFIG_X86_32 - /* - * Called very early during boot from get_smp_config(). It should - * return the logical apicid. x86_[bios]_cpu_to_apicid is - * initialized before this function is called. - * - * If logical apicid can't be determined that early, the function - * may return BAD_APICID. Logical apicid will be configured after - * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity - * won't be applied properly during early boot in this case. - */ - int (*x86_32_early_logical_apicid)(int cpu); -#endif char *name; }; --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2435,8 +2435,8 @@ static void cpu_update_apic(int cpu, int early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; #endif #ifdef CONFIG_X86_32 - early_per_cpu(x86_cpu_to_logical_apicid, cpu) = - apic->x86_32_early_logical_apicid(cpu); + if (cpu < 8) + early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1U << cpu; #endif set_cpu_possible(cpu, true); physid_set(apicid, phys_cpu_present_map); --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -80,13 +80,6 @@ static void noop_apic_write(u32 reg, u32 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !apic_is_disabled); } -#ifdef CONFIG_X86_32 -static int noop_x86_32_early_logical_apicid(int cpu) -{ - return BAD_APICID; -} -#endif - struct apic apic_noop __ro_after_init = { .name = "noop", .probe = noop_probe, @@ -130,8 +123,4 @@ struct apic apic_noop __ro_after_init = .icr_write = noop_apic_icr_write, .wait_icr_idle = noop_apic_wait_icr_idle, .safe_wait_icr_idle = noop_safe_apic_wait_icr_idle, - -#ifdef CONFIG_X86_32 - .x86_32_early_logical_apicid = noop_x86_32_early_logical_apicid, -#endif }; --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -28,12 +28,6 @@ static bool bigsmp_check_apicid_used(phy return false; } -static int bigsmp_early_logical_apicid(int cpu) -{ - /* on bigsmp, logical apicid is the same as physical */ - return early_per_cpu(x86_cpu_to_apicid, cpu); -} - /* * bigsmp enables physical destination mode * and doesn't use LDR and DFR @@ -154,27 +148,15 @@ static struct apic apic_bigsmp __ro_afte .icr_write = native_apic_icr_write, .wait_icr_idle = native_apic_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, - - .x86_32_early_logical_apicid = bigsmp_early_logical_apicid, }; void __init generic_bigsmp_probe(void) { - unsigned int cpu; - if (!probe_bigsmp()) return; apic = &apic_bigsmp; - for_each_possible_cpu(cpu) { - if (early_per_cpu(x86_cpu_to_logical_apicid, - cpu) == BAD_APICID) - continue; - early_per_cpu(x86_cpu_to_logical_apicid, cpu) = - bigsmp_early_logical_apicid(cpu); - } - pr_info("Overriding APIC driver with %s\n", apic_bigsmp.name); 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id h15-20020a1709063c0f00b00992e21b04aasi8605191ejg.720.2023.08.01.04.24.24; Tue, 01 Aug 2023 04:24:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=dCbY2YZT; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=oxjsyLIM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233890AbjHAKs1 (ORCPT + 99 others); Tue, 1 Aug 2023 06:48:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233414AbjHAKru (ORCPT ); Tue, 1 Aug 2023 06:47:50 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD1ED2708 for ; Tue, 1 Aug 2023 03:47:10 -0700 (PDT) Message-ID: <20230801103816.367918118@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886828; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4wEhoY8ulym22Jw+bKw7ms+1bFblC+QNKvBDCbvuUFo=; b=dCbY2YZT60G2rsde34IwNmtYBaJ81PXPJDTMUhBMrpwnWNomBqggdXZAeUUez8BiTSAzV0 1wbCm8+9SkAzQzg38yCVR6/pOzZcRYTg4NsyqLcGQ7vIOXNk8SLd1IjrxYFZN5aZi/X0li AfZAtDN5oANbtSAIVPfCxkF3TT6vobRF1sqj1nsau+Ba4gblm/EjbVv2OOdmjoTqqv/1rz 9XkVhuic33ItvOL7tG7WPq9dyxD+mZFGyPJz3sRxZrYoAj7jSUxfB78NwxUZJgyPt4xctd TgkdK5f3AENufiE8Iljv/Vpay4kJ9XZs9ab4l8xwjWOlL3cuqv0273BVY4FZBA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886828; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4wEhoY8ulym22Jw+bKw7ms+1bFblC+QNKvBDCbvuUFo=; b=oxjsyLIMofNXlrH5sslsEIxt/iT8SzjQ3qWjrCT7To6vvEuQNxHoP4W105jhWgC5QBR/VD NcOSD/DDIDS3MLBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 22/60] x86/apic/32: Remove x86_cpu_to_logical_apicid References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:08 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025717312313507 X-GMAIL-MSGID: 1773025717312313507 This per CPU variable is just yet another form of voodoo programming. The boot ordering is: per_cpu(x86_cpu_to_logical_apicid, cpu) = 1U << cpu; ..... setup_apic() apic->init_apic_ldr() default_init_apic_ldr() apic_write(SET_APIC_LOGICAL_ID(1UL << smp_processor_id(), APIC_LDR); id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR); WARN_ON(id != per_cpu(x86_cpu_to_logical_apicid, cpu)); per_cpu(x86_cpu_to_logical_apicid, cpu) = id; So first write the default into LDR and then validate it against the same default which was set up during early boot APIC enumeration. Brilliant, isn't it? The comment above the per CPU variable declaration describes it well: 'Let's keep it ugly for now.' Remove the useless gunk and use '1U << cpu' consistently all over the place. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/smp.h | 3 --- arch/x86/kernel/apic/apic.c | 31 ------------------------------- arch/x86/kernel/apic/ipi.c | 36 +++++++++--------------------------- arch/x86/kernel/setup_percpu.c | 7 ------- 4 files changed, 9 insertions(+), 68 deletions(-) --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -22,9 +22,6 @@ DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_l2c DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid); DECLARE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid); -#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) -DECLARE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid); -#endif struct task_struct; --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -113,15 +113,6 @@ EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_a EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); #ifdef CONFIG_X86_32 - -/* - * On x86_32, the mapping between cpu and logical apicid may vary - * depending on apic in use. The following early percpu variable is - * used for the mapping. This is where the behaviors of x86_64 and 32 - * actually diverge. Let's keep it ugly for now. - */ -DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); - /* Local APIC was disabled by the BIOS and enabled by the kernel */ static int enabled_via_apicbase __ro_after_init; @@ -1589,24 +1580,6 @@ static void setup_local_APIC(void) */ apic->init_apic_ldr(); -#ifdef CONFIG_X86_32 - if (apic->dest_mode_logical) { - int logical_apicid, ldr_apicid; - - /* - * APIC LDR is initialized. If logical_apicid mapping was - * initialized during get_smp_config(), make sure it matches - * the actual value. - */ - logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); - ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); - if (logical_apicid != BAD_APICID) - WARN_ON(logical_apicid != ldr_apicid); - /* Always use the value from LDR. */ - early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; - } -#endif - /* * Set Task Priority to 'accept all except vectors 0-31'. An APIC * vector in the 16-31 range could be delivered if TPR == 0, but we @@ -2433,10 +2406,6 @@ static void cpu_update_apic(int cpu, int #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; #endif -#ifdef CONFIG_X86_32 - if (cpu < 8) - early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1U << cpu; -#endif set_cpu_possible(cpu, true); physid_set(apicid, phys_cpu_present_map); set_cpu_present(cpu, true); --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -243,50 +243,32 @@ void default_send_IPI_self(int vector) } #ifdef CONFIG_X86_32 - -void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, - int vector) +void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, int vector) { unsigned long flags; - unsigned int query_cpu; - - /* - * Hack. The clustered APIC addressing mode doesn't allow us to send - * to an arbitrary mask, so I do a unicasts to each CPU instead. This - * should be modified to do 1 message per cluster ID - mbligh - */ + unsigned int cpu; local_irq_save(flags); - for_each_cpu(query_cpu, mask) - __default_send_IPI_dest_field( - early_per_cpu(x86_cpu_to_logical_apicid, query_cpu), - vector, APIC_DEST_LOGICAL); + for_each_cpu(cpu, mask) + __default_send_IPI_dest_field(1U << cpu, vector, APIC_DEST_LOGICAL); local_irq_restore(flags); } void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, int vector) { + unsigned int cpu, this_cpu = smp_processor_id(); unsigned long flags; - unsigned int query_cpu; - unsigned int this_cpu = smp_processor_id(); - - /* See Hack comment above */ local_irq_save(flags); - for_each_cpu(query_cpu, mask) { - if (query_cpu == this_cpu) + for_each_cpu(cpu, mask) { + if (cpu == this_cpu) continue; - __default_send_IPI_dest_field( - early_per_cpu(x86_cpu_to_logical_apicid, query_cpu), - vector, APIC_DEST_LOGICAL); - } + __default_send_IPI_dest_field(1U << cpu, vector, APIC_DEST_LOGICAL); + } local_irq_restore(flags); } -/* - * This is only used on smaller machines. - */ void default_send_IPI_mask_logical(const struct cpumask *cpumask, int vector) { unsigned long mask = cpumask_bits(cpumask)[0]; --- a/arch/x86/kernel/setup_percpu.c +++ b/arch/x86/kernel/setup_percpu.c @@ -184,10 +184,6 @@ void __init setup_per_cpu_areas(void) per_cpu(x86_cpu_to_acpiid, cpu) = early_per_cpu_map(x86_cpu_to_acpiid, cpu); #endif -#ifdef CONFIG_X86_32 - per_cpu(x86_cpu_to_logical_apicid, cpu) = - early_per_cpu_map(x86_cpu_to_logical_apicid, cpu); -#endif #ifdef CONFIG_NUMA per_cpu(x86_cpu_to_node_map, cpu) = early_per_cpu_map(x86_cpu_to_node_map, cpu); @@ -214,9 +210,6 @@ void __init setup_per_cpu_areas(void) early_per_cpu_ptr(x86_cpu_to_apicid) = NULL; early_per_cpu_ptr(x86_cpu_to_acpiid) = NULL; #endif -#ifdef CONFIG_X86_32 - early_per_cpu_ptr(x86_cpu_to_logical_apicid) = NULL; -#endif #ifdef CONFIG_NUMA early_per_cpu_ptr(x86_cpu_to_node_map) = NULL; #endif From patchwork Tue Aug 1 10:47:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129249 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2623578vqg; Tue, 1 Aug 2023 05:11:58 -0700 (PDT) X-Google-Smtp-Source: APBJJlFXh7eGqGGGwWrZ/crwtwha4u44gqncAu2V5pLUecfa3/j5aO3MuGU7Uju2SWSr5ujPln04 X-Received: by 2002:a17:907:7745:b0:992:b9f4:85db with SMTP id kx5-20020a170907774500b00992b9f485dbmr2330278ejc.39.1690891918242; Tue, 01 Aug 2023 05:11:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690891918; cv=none; d=google.com; s=arc-20160816; b=a6wgbSiRfjCrqQfrBFuxKTAMKzVwp3k+a+JUCXR2eut0ie3xzGH4jbLkJS9l75llc6 ru1N8TcMvd87ymD9BN4JK8c2xNWEUInWmOVDjxERh2DENpjZFHsaV/qfrOLY1dVL4TZk JxSkrGUSikkAhylIpG1/CFvTZZL3n1elpBb2ExPA0mHlxuUfyUaoLjfjmS4DAVBvQPpO S5/1BwmWIkYZX+QltQoKWRpSKU2gtfhW1SJyFydCq0nk9GF10zVQ7cFGQUqYPwQHNEhv cYSVrqq9ProUNlI2hBoitup4RznMtTI24XglaNvl9EgKsH7pPO4L08nzt59VFGTAW5Q1 DQEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=b8Xt5cYn7tsxj5f5GzHs5GjoZDN6ZZKDqaLjg/BbaXY=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=GQLpKc9tzBYNeUWBYFmmujAwPMwNAmomqZfbiHBLriv1KTRzOeDFXRm31ZwpVTdWVa LR8dG9LOmIhRhmanQd/fg27UiI3ZkO/1ooQW37NNi8iCE8tx1Ip+uIclPmqnQx8PmIl4 zzfd87R0OE5B9KY+2qmOoJAFOtdlQy/ZsZIbqGyFs/JyhyHETMLKTKvUklsQa90lM3hY s3jY+AcZooYpnKfkouJgsm4UUUyYa4aIARedN0FuwOQaJ3Z6K57cOHfyDX/8kY30C4RD Vzs7zlkLP/tprtHYGPYfaCOTwXUpmFqcKY8WItcp4vYRRikg8Pdv0j195+5kt+a/3hWO A+Pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Z00TRirB; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="x92s/Qt/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/ipi.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -184,18 +184,13 @@ void default_send_IPI_single_phys(int cp void default_send_IPI_mask_sequence_phys(const struct cpumask *mask, int vector) { - unsigned long query_cpu; unsigned long flags; + unsigned long cpu; - /* - * Hack. The clustered APIC addressing mode doesn't allow us to send - * to an arbitrary mask, so I do a unicast to each CPU instead. - * - mbligh - */ local_irq_save(flags); - for_each_cpu(query_cpu, mask) { + for_each_cpu(cpu, mask) { __default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid, - query_cpu), vector, APIC_DEST_PHYSICAL); + cpu), vector, APIC_DEST_PHYSICAL); } local_irq_restore(flags); } @@ -203,18 +198,15 @@ void default_send_IPI_mask_sequence_phys void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask, int vector) { - unsigned int this_cpu = smp_processor_id(); - unsigned int query_cpu; + unsigned int cpu, this_cpu = smp_processor_id(); unsigned long flags; - /* See Hack comment above */ - local_irq_save(flags); - for_each_cpu(query_cpu, mask) { - if (query_cpu == this_cpu) + for_each_cpu(cpu, mask) { + if (cpu == this_cpu) continue; __default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid, - query_cpu), vector, APIC_DEST_PHYSICAL); + cpu), vector, APIC_DEST_PHYSICAL); } local_irq_restore(flags); } @@ -283,7 +275,6 @@ void default_send_IPI_mask_logical(const local_irq_restore(flags); } -/* must come after the send_IPI functions above for inlining */ static int convert_apicid_to_cpu(int apic_id) { int i; From patchwork Tue Aug 1 10:47:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129189 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2595025vqg; Tue, 1 Aug 2023 04:16:14 -0700 (PDT) X-Google-Smtp-Source: APBJJlFNsfVhO2MJAn0HPiXrV2PHg4eYuRnZ/Og51xyqhXAU6psKj6+Euq//ZlnxVgj3ly3SK29V X-Received: by 2002:a05:6830:148f:b0:6b1:d368:557c with SMTP id s15-20020a056830148f00b006b1d368557cmr13324677otq.30.1690888574126; Tue, 01 Aug 2023 04:16:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888574; cv=none; d=google.com; s=arc-20160816; b=zlDLwXz8SE893yrGS7C3d8IFTtS1l5FCNvUlR6jXuWwd6LAcwx/9ZmHyMYV+XBsda2 xGG0xoZQmmYtVvpROwq0aMFUVtZgaNk2KZ5sHngqjeF3TZAgo9iaCbZxFsSl0nGg7CVY 2UEzUimgjzEAtBoO0b2emMdKf1MtkfBiOIUxGDJXMNrp7rNre9BstMZXCubr8VBwo8J2 fkoOhZKpD0pzA77jIIF/ceepqvKEMXC1pow21OHOt9ZUDrVU89hGlKpp2rMiUhEkSkzN jEoAnS2af3Chb0v3WeyOykoyzfTKGRF/bYBMPKUrR5SLjVFAWB8MhVTpGytwP5j/f4P3 62Rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=1bhj7lWCPL93WVUL7hHxugShRN0AQvpospwY1BweZqQ=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=SjvFz+4d8OPj/zumPCS1VM4N8l3MzGa7VFz5IvzzGWKzHBzpMZ9v7rwPNE8/y+83LC yQOjl5opdXlzhsrjiKzIsRSNXV3IzeZe/Go5T2ySo/Yg8rEXzd65Q+PWLDh1796KwphN 6yYdOtoOgWyb1Jlmw5ahKd3Twm5lzImjydjz5cKycgO+ptYzt/y0Jh9eQF7LatWA4427 iBrFeovLXJ5TyyAaoTX+eYuSUekvTJOVhoRyTssgUD1HWYe3aSRYUFHG8hQTytGhnmqW Tt4ipDoizrijp8+a7oJPihIEUKwT1ER/6cJNUMQVUQwSL4GOyppKrZCAdcZmRGQA1ka2 mcAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=323dqJw9; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/x2apic_uv_x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -1843,7 +1843,7 @@ static void __init uv_system_init_hub(vo /* Initialize per CPU info: */ for_each_possible_cpu(cpu) { - int apicid = early_per_cpu(x86_cpu_to_apicid, cpu); + int apicid = per_cpu(x86_cpu_to_apicid, cpu); unsigned short bid; unsigned short pnode; From patchwork Tue Aug 1 10:47:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129190 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2595059vqg; Tue, 1 Aug 2023 04:16:17 -0700 (PDT) X-Google-Smtp-Source: APBJJlEp3KdYMWb4yNDOucI3edfpbvKFTPVLFZO+Ld7WHDBTH88Y4hro0rtjaqVeOEepfCFdBVbj X-Received: by 2002:a17:90a:cb17:b0:268:a61:ba86 with SMTP id z23-20020a17090acb1700b002680a61ba86mr10826611pjt.16.1690888577102; Tue, 01 Aug 2023 04:16:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888577; cv=none; d=google.com; s=arc-20160816; b=iPp2D844mg4/lsN+rrt/vfS5165SwFoQhFSDPER4mZIyeNDpsyv4Mrf8pj2DZxIdUp /wUG+yhPsmI0B3fR1fvuXG0+Ri04aR7Pv6RRDvKSAsMi6PpFavhZToyWp3n9jr/kam2h dTRtGnK2WzYsqKsO2+dRY22l03+WC29Qm6FhyPHqVgOBdBMiqVoZy2k0iYBv6d+bJoyz FegG6POZJ1P4Rs1/BsDM4tSPNTXetFSAlPjQUO8s1GfD7ECdu0/WyU7TR3gsa7KENSvc 7hDusGArcCG57FtfWr3VNbjYBmAJ6yIbFamf99e6wKysTgQ+9gYlkxlQw9mc8ogRqOQ6 W74g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=XBWDLku2nyQ5/5bJqq7OR3c/AtCppUf/8w42TtOLQ9Q=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=SEmJAvEbvmXCkxb2oZehpxU8onD5qckq6sbYeYY3wNHxSmKrqhEi6clnf0AC01Fx15 JF6T+hs3AR/hwc6gaFjyagdHBc1SHWDcRfCeZrlVFDnscnQh6NBDr/nBNOM+YpTgcngY WpIj9HP0ROqra4EL34FQrDrtd9VoIn/VRkZ2ajK8tODE8IMU4ro4rCHjRcI+A5gcAXkR ckNI6J93aLI0ShOvEAcrvrMGQ2fmCyjXFW8OqRfQ0lXm5keNFk5X0yIYMPXfnHzV7LMB +mQMYJzaCP9EK4nAxgERT48Q5yesT4DYsjXxUXoyDOGbGecjFnKoTQlxM3PEao1rkRR/ LmlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=fv6XXTgb; dkim=neutral (no key) header.i=@linutronix.de header.b=upHOIgKA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o16-20020a17090aac1000b00262ebe643a2si9016348pjq.186.2023.08.01.04.16.04; Tue, 01 Aug 2023 04:16:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=fv6XXTgb; dkim=neutral (no key) header.i=@linutronix.de header.b=upHOIgKA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233350AbjHAKtK (ORCPT + 99 others); Tue, 1 Aug 2023 06:49:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232332AbjHAKsN (ORCPT ); Tue, 1 Aug 2023 06:48:13 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEBDA2D74 for ; Tue, 1 Aug 2023 03:47:23 -0700 (PDT) Message-ID: <20230801103816.530238859@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886832; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XBWDLku2nyQ5/5bJqq7OR3c/AtCppUf/8w42TtOLQ9Q=; b=fv6XXTgbiuMw7DF4hMOzt257tpxSUPGhk02DK9z/KVc31PBjgyJcki9n3vSu5epiiNv434 2wkQhsadAgIyyg1z9j4vD9VNZSnnef0M8imRGIBzTCsiX5k5DRGV9PtR2evc16eTRtn7/x PSZYlmfGnciL33spLj1tluMsXtf1sjwt3Q1mkcGSdtQWDdOBnrv7sVnsfDDdyZmlVa+9nl IS+gp95tL627Q8wgxKQtTFIY4r+yRNaAaAWbcX5Jv5u8gn0OhHSGEAKotamaGAYMvIKzv4 al8wTinMUhs6vWz3KVCd5oskYmiTY67pQ1NXFdnTso7MOeluYqtVAzVQ5Pamgg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886832; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XBWDLku2nyQ5/5bJqq7OR3c/AtCppUf/8w42TtOLQ9Q=; b=upHOIgKAGgb3IkP0To5lssmpxjX0+PWKtXMrk7VappQ6BSjpmfegySoOdlGXCeIMj+K735 auM5OQkeOKvqZgBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 25/60] x86/apic/32: Remove pointless default_acpi_madt_oem_check() References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:12 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025180694497451 X-GMAIL-MSGID: 1773025180694497451 On 32bit there is no APIC implementing the acpi_madt_oem_check() except XEN PV, but that does not matter at all. generic_apic_probe() runs before ACPI tables are parsed. This selects the XEN APIC if there is no command line override because the XEN APIC driver is the first to be probed. If there is a command line override then the XEN PV driver won't be selected in the MADT OEM check either. As there is no other MADT check implemented for 32bit APICs, this whole excercise is a NOOP and can be removed. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 4 +++- arch/x86/kernel/apic/bigsmp_32.c | 1 - arch/x86/kernel/apic/probe_32.c | 22 ---------------------- 3 files changed, 3 insertions(+), 24 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -459,10 +459,12 @@ static inline unsigned int read_apic_id( #ifdef CONFIG_X86_64 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); +extern int default_acpi_madt_oem_check(char *, char *); +#else +static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } #endif extern int default_apic_id_valid(u32 apicid); -extern int default_acpi_madt_oem_check(char *, char *); extern void default_setup_apic_routing(void); extern u32 apic_default_calc_apicid(unsigned int cpu); --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -112,7 +112,6 @@ static struct apic apic_bigsmp __ro_afte .name = "bigsmp", .probe = probe_bigsmp, - .acpi_madt_oem_check = NULL, .apic_id_valid = default_apic_id_valid, .apic_id_registered = bigsmp_apic_id_registered, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -60,7 +60,6 @@ static struct apic apic_default __ro_aft .name = "default", .probe = probe_default, - .acpi_madt_oem_check = NULL, .apic_id_valid = default_apic_id_valid, .apic_id_registered = default_apic_id_registered, @@ -176,24 +175,3 @@ void __init generic_apic_probe(void) } printk(KERN_INFO "Using APIC driver %s\n", apic->name); } - -/* This function can switch the APIC even after the initial ->probe() */ -int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id) -{ - struct apic **drv; - - for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { - if (!(*drv)->acpi_madt_oem_check) - continue; - if (!(*drv)->acpi_madt_oem_check(oem_id, oem_table_id)) - continue; - - if (!cmdline_apic) { - apic = *drv; - printk(KERN_INFO "Switched to APIC driver `%s'.\n", - apic->name); - } - return 1; - } - return 0; -} From patchwork Tue Aug 1 10:47:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129237 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2615326vqg; Tue, 1 Aug 2023 05:00:18 -0700 (PDT) X-Google-Smtp-Source: APBJJlEsmy6jJwh0CghGprZBZ5SkIf3xtkYEryI8y3RYEbROhc9BH/1xJGuhmky5aNaTTfDUidct X-Received: by 2002:a17:902:a506:b0:1bc:2abb:4e77 with SMTP id s6-20020a170902a50600b001bc2abb4e77mr1165853plq.0.1690891218010; Tue, 01 Aug 2023 05:00:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690891217; cv=none; d=google.com; s=arc-20160816; b=kY/YxXy7PgUeKZ0/CcohW5uB3tFH/O5MC5Q1aNnzgjAIla5AsQmZ4U9CKLpVFkD0kN z7gmSSJY2pUB84EJAPCgElk34ek/VRHDk9adxnQRpNkS/p7r5N1gfJEbwae2k6i2Juu3 Mxc7KDVslMvKdfzMMOb3JXJAEeU3x4qJD8EQYN5bfIPJDb6/fvpMKVB8t4D0SRX+hMUN OnQtQLb+iM3rUkAv8ipwUQZKhpNruSNKJn6yCqueWEFOOu/jtro2u55bTqak3lUuH1SH N9WahyEj78y8jauf9hIiCp7KO8RyRrm9qH3p5rjwIp+kHZ3s74Rw94zV5fxaG5ySiDG9 yE2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=3wzkXh8ox2g+n/hDGbOA8stcRNol0QfZYe+X2pCSlC0=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=nhfh+z/8x1rKy2CLbjWUXKQIE79M5KosOXZHplJWx70t7fOr5hUXOPqnlhVeUinPMl 0YWpQSc84kAXjYH7uwzhENAyTWaKsEZP4gVFzN28WRSr/zfqsRV0FPJuFykDaqTbxnZQ HC7X6WbVQvRsujPcxSePn6Ya6I4+9xq0lczyRst7IkAGoxoR3kXGa0gZVHXFlr4dSjqs nKEbxg5fWqaHZMcrIOBQb9BfCNFBdwmtpy523j2nfO+iWNTk1KzwUachX/jwecYKESOI iag2oTL+xYsuLP3aPwEJtKuLugfmRN+Jo/UYoVD99x8KLcZnAayazFKO3RFOKYoMVrEG Y5MQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=lLSKEilw; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=5Trqhk6G; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g20-20020a170902c99400b001bba8f79ad0si8677527plc.109.2023.08.01.05.00.03; Tue, 01 Aug 2023 05:00:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=lLSKEilw; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=5Trqhk6G; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234089AbjHAKt1 (ORCPT + 99 others); Tue, 1 Aug 2023 06:49:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234074AbjHAKss (ORCPT ); Tue, 1 Aug 2023 06:48:48 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE63D3589 for ; Tue, 1 Aug 2023 03:47:31 -0700 (PDT) Message-ID: <20230801103816.584394452@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886833; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3wzkXh8ox2g+n/hDGbOA8stcRNol0QfZYe+X2pCSlC0=; b=lLSKEilwLXmnO7BmGJTNGP4KCiPhG/pCOrgDxZJ0EgYX5didwxBXPUH7Z3EjWfuBlmtjLQ 55sy7UePBumb0IR7dJZs0x2C6KRtxlfv49jchExvEivvSV73NggFawOCHKvyB3S2YOZiJJ EYNyjZTHjf1GKFVofpaYqEnnwQfTLRS8THJ2dgsyvliTil6gyrVtMShvTkTofFwWvysos9 P3er4qg+p0J1iix79rKe+IM5RXqlxtPb9B1G7JXFFNPHVg/+kRU/kM0frF14waeN1+d+jv Z7YCQyNQjWiwyIH9phwLNdTkXxzpCqySoqeq7H/KcboPlWTJJRBYiItuGGF1+g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886833; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3wzkXh8ox2g+n/hDGbOA8stcRNol0QfZYe+X2pCSlC0=; b=5Trqhk6GQb44c5DD1g42DFNoU9CU7ac5zowSC8uq2SCdsyOnm1SWdsNopRrmgdHFKpBfh4 PyzmnzzQWkxqEPBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 26/60] x86/apic/32: Decrapify the def_bigsmp mechanism References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:13 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773027948981737238 X-GMAIL-MSGID: 1773027948981737238 If the system has more than 8 CPUs then XAPIC and the bigsmp APIC driver is required. This is ensured via: 1) Enumerating all possible CPUs up to NR_CPUS 2) Checking at boot CPU APIC setup time whether the system has more than 8 CPUs and has an XAPIC. If that's the case then it's attempted to install the bigsmp APIC driver and a magic variable 'def_to_bigsmp' is set to one. 3) If that magic variable is set and CONFIG_X86_BIGSMP=n and the system has more than 8 CPUs smp_sanity_check() removes all CPUs >= #8 from the present and possible mask in the most convoluted way. This logic is completely broken for the case where the bigsmp driver is enabled, but not selected due to a command line option specifying the default APIC. In that case the system boots with default APIC in logical destination mode and fails to reduce the number of CPUs. That aside the above which is sprinkled over 3 different places is yet another piece of art. It would have been too obvious to check the requirements upfront and limit nr_cpu_ids _before_ enumerating tons of CPUs and then removing them again. Implement exactly this. Check the bigsmp requirement when the boot APIC is registered which happens _before_ ACPI/MPTABLE parsing and limit the number of CPUs to 8 if it can't be used. Switch it over when the boot CPU apic is set up if necessary. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/mpspec.h | 2 -- arch/x86/kernel/apic/apic.c | 3 +++ arch/x86/kernel/apic/bigsmp_32.c | 22 ++++++++++------------ arch/x86/kernel/apic/local.h | 11 +++++++++++ arch/x86/kernel/apic/probe_32.c | 35 +++++++++++++++++------------------ arch/x86/kernel/setup.c | 1 - arch/x86/kernel/smpboot.c | 37 ------------------------------------- 7 files changed, 41 insertions(+), 70 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -23,8 +23,6 @@ extern int pic_mode; #define MAX_IRQ_SOURCES 256 -extern unsigned int def_to_bigsmp; - #else /* CONFIG_X86_64: */ #define MAX_MP_BUSSES 256 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -63,6 +63,8 @@ #include #include +#include "local.h" + unsigned int num_processors; unsigned disabled_cpus; @@ -2420,6 +2422,7 @@ static __init void cpu_set_boot_apic(voi { cpuid_to_apicid[0] = boot_cpu_physical_apicid; cpu_update_apic(0, boot_cpu_physical_apicid); + x86_32_probe_bigsmp_early(); } int generic_processor_info(int apicid) --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -100,12 +100,7 @@ static const struct dmi_system_id bigsmp static int probe_bigsmp(void) { - if (def_to_bigsmp) - dmi_bigsmp = 1; - else - dmi_check_system(bigsmp_dmi_table); - - return dmi_bigsmp; + return dmi_check_system(bigsmp_dmi_table); } static struct apic apic_bigsmp __ro_after_init = { @@ -149,14 +144,17 @@ static struct apic apic_bigsmp __ro_afte .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, }; -void __init generic_bigsmp_probe(void) +bool __init apic_bigsmp_possible(bool cmdline_override) { - if (!probe_bigsmp()) - return; - - apic = &apic_bigsmp; + return apic == &apic_bigsmp || !cmdline_override; +} - pr_info("Overriding APIC driver with %s\n", apic_bigsmp.name); +void __init apic_bigsmp_force(void) +{ + if (apic != &apic_bigsmp) { + apic = &apic_bigsmp; + pr_info("Overriding APIC driver with bigsmp\n"); + } } apic_driver(apic_bigsmp); --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -66,4 +66,15 @@ void default_send_IPI_self(int vector); void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, int vector); void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, int vector); void default_send_IPI_mask_logical(const struct cpumask *mask, int vector); +void x86_32_probe_bigsmp_early(void); +#else +static inline void x86_32_probe_bigsmp_early(void) { } +#endif + +#ifdef CONFIG_X86_BIGSMP +bool apic_bigsmp_possible(bool cmdline_selected); +void apic_bigsmp_force(void); +#else +static inline bool apic_bigsmp_possible(bool cmdline_selected) { return false; }; +static inline void apic_bigsmp_force(void) { } #endif --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -10,6 +10,8 @@ #include #include +#include + #include #include #include @@ -123,36 +125,33 @@ static int __init parse_apic(char *arg) } early_param("apic", parse_apic); -void __init default_setup_apic_routing(void) +void __init x86_32_probe_bigsmp_early(void) { - int version = boot_cpu_apic_version; + if (nr_cpu_ids <= 8 || xen_pv_domain()) + return; - if (num_possible_cpus() > 8) { + if (IS_ENABLED(CONFIG_X86_BIGSMP)) { switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_INTEL: - if (!APIC_XAPIC(version)) { - def_to_bigsmp = 0; + if (!APIC_XAPIC(boot_cpu_apic_version)) break; - } /* P4 and above */ fallthrough; case X86_VENDOR_HYGON: case X86_VENDOR_AMD: - def_to_bigsmp = 1; + if (apic_bigsmp_possible(cmdline_apic)) + return; + break; } } + pr_info("Limiting to 8 possible CPUs\n"); + set_nr_cpu_ids(8); +} -#ifdef CONFIG_X86_BIGSMP - /* - * This is used to switch to bigsmp mode when - * - There is no apic= option specified by the user - * - generic_apic_probe() has chosen apic_default as the sub_arch - * - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support - */ - - if (!cmdline_apic && apic == &apic_default) - generic_bigsmp_probe(); -#endif +void __init default_setup_apic_routing(void) +{ + if (nr_cpu_ids >= 8 && !xen_pv_domain()) + apic_bigsmp_force(); if (apic->setup_apic_routing) apic->setup_apic_routing(); --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -114,7 +114,6 @@ static struct resource bss_resource = { #ifdef CONFIG_X86_32 /* CPU data as detected by the assembly code in head_32.S */ struct cpuinfo_x86 new_cpu_data; -unsigned int def_to_bigsmp; struct apm_info apm_info; EXPORT_SYMBOL(apm_info); --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1149,41 +1149,6 @@ static __init void disable_smp(void) cpumask_set_cpu(0, topology_die_cpumask(0)); } -/* - * Various sanity checks. - */ -static void __init smp_sanity_check(void) -{ - preempt_disable(); - -#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) - if (def_to_bigsmp && nr_cpu_ids > 8) { - unsigned int cpu; - unsigned nr; - - pr_warn("More than 8 CPUs detected - skipping them\n" - "Use CONFIG_X86_BIGSMP\n"); - - nr = 0; - for_each_present_cpu(cpu) { - if (nr >= 8) - set_cpu_present(cpu, false); - nr++; - } - - nr = 0; - for_each_possible_cpu(cpu) { - if (nr >= 8) - set_cpu_possible(cpu, false); - nr++; - } - - set_nr_cpu_ids(8); - } -#endif - preempt_enable(); -} - static void __init smp_cpu_index_default(void) { int i; @@ -1243,8 +1208,6 @@ void __init native_smp_prepare_cpus(unsi { smp_prepare_cpus_common(); - smp_sanity_check(); - switch (apic_intr_mode) { case APIC_PIC: case APIC_VIRTUAL_WIRE_NO_CONFIG: From patchwork Tue Aug 1 10:47:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129243 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2618943vqg; Tue, 1 Aug 2023 05:04:49 -0700 (PDT) X-Google-Smtp-Source: APBJJlGGfV+FahE9mWs7YYw56XqWge2z8Tb0QDl+zevf2P/eDKJStuRr8Gr0iu521AMlsNcODOG8 X-Received: by 2002:a05:6a21:6da1:b0:13d:697a:c31c with SMTP id wl33-20020a056a216da100b0013d697ac31cmr8476930pzb.27.1690891489379; Tue, 01 Aug 2023 05:04:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690891489; cv=none; d=google.com; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id k11-20020a056a00134b00b0067e5edde6eesi9316367pfu.302.2023.08.01.05.04.35; Tue, 01 Aug 2023 05:04:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ZLJEXzsJ; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233291AbjHAKtI (ORCPT + 99 others); Tue, 1 Aug 2023 06:49:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234234AbjHAKsL (ORCPT ); Tue, 1 Aug 2023 06:48:11 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A75332113 for ; Tue, 1 Aug 2023 03:47:20 -0700 (PDT) Message-ID: <20230801103816.638137038@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886834; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XhABCxwHPGY7DF2UNzN4o5WpsX1JegdIqFCLm4OuXKU=; b=ZLJEXzsJtJYGRrxFytcloiCsPbo6DqPVeh8GFOjdTD/P9EvePOxkscKnA6aOO9mvH1unrL Y5NLH2mAfWlBpAGsoWlacrOyInhzSmDcL1G9jravJrzZ0G8HR0Vjhn1LNETu3HM3l/IeC2 zjHqfO8nUHHhMi/6zsEwlAQV9pYRncra/NONW2RwLgxCpbAjnqCn7seCryVh2nI5FwcqNY /HKORR4B6yTSpzikvN6OLlu8u768Kh9bCbD81+SmQGYRwb593+V81ERkdQWBhKkhExgTER btvfRgyPUP+nsKov9XAGpyWCBza8QlujwuGrJH6KUdQLgWxF5MYHjt0DsL6smw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886834; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XhABCxwHPGY7DF2UNzN4o5WpsX1JegdIqFCLm4OuXKU=; b=Up0KUSj8J7MVjxiRALiNOwtofePybPN5BfjmopOobB8WDGZKPQm8PksdLK/zwX1Yutw08L qE5gagXEVSw4clBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 27/60] x86/apic/32: Remove bigsmp_cpu_present_to_apicid() References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:14 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773028234708600230 X-GMAIL-MSGID: 1773028234708600230 It's a copy of default_cpu_present_to_apicid() with the omission of the actual check whether the CPU is present. This APIC callback should die completely, but the XEN APIC implementation does something different which needs to be addressed first. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/bigsmp_32.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -43,14 +43,6 @@ static void bigsmp_setup_apic_routing(vo nr_ioapics); } -static int bigsmp_cpu_present_to_apicid(int mps_cpu) -{ - if (mps_cpu < nr_cpu_ids) - return (int) per_cpu(x86_cpu_to_apicid, mps_cpu); - - return BAD_APICID; -} - static void bigsmp_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) { /* For clustered we don't have a good way to do this yet - hack */ @@ -119,7 +111,7 @@ static struct apic apic_bigsmp __ro_afte .init_apic_ldr = bigsmp_init_apic_ldr, .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map, .setup_apic_routing = bigsmp_setup_apic_routing, - .cpu_present_to_apicid = bigsmp_cpu_present_to_apicid, + .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = physid_set_mask_of_physid, .phys_pkg_id = bigsmp_phys_pkg_id, From patchwork Tue Aug 1 10:47:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129276 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2643905vqg; Tue, 1 Aug 2023 05:50:12 -0700 (PDT) X-Google-Smtp-Source: APBJJlG+fuGo0TwOG+aeVQjfn4/OnW+fO8wqaoNB8iGP8e/zi29JSkTuw/ZRlrh5Cw0sch9LA6wp X-Received: by 2002:a05:6808:150d:b0:3a7:349d:35e3 with SMTP id u13-20020a056808150d00b003a7349d35e3mr8405833oiw.8.1690894212469; Tue, 01 Aug 2023 05:50:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690894212; cv=none; d=google.com; s=arc-20160816; b=xvd4qDZpCPpZXpGklGSFXv4vFJOs2U+Og7lB1vjML0vDL+kzFnvr2GZLZBDfmqJ/Ed X/P+/jsf5igNETVVbIg5U4EaajpYOwsmow4yojVDcbzt1FnR5IzOlE8hcvGLvPmJXeOE kpcbRYo9wwgvDoEu4SQXAVBeQoKZbW4UPNnY5xMKJu3cwGJuiA2QB6t32hYvYiFbnHTq YfUbXcs505FnBwyM7GFwlGtojXSdfa5zaou9pLx0To+BZu/hzdog91NgQ4V0Hprynqbq 5LVnSzHh1BwBQPyo1zPcQUIqdxx292CMurViUUa3dgOfqZ5cdml1fI3MkJyeyum6Ks5f cPyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=O00kb3ANDLPAWttSm0Yl7DwanzSJODjrzlZY67TMPn8=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=mnmducetEVu5soZnp+v53vj5hJphhaAMJWZWx1mo5yDHX9ocNe7815tUC8zE0a5zXp JdPSYfZtFxQzyBENLavK9Dn7Ls9YyWnE0PFabGHuK+IwcjocRqJmiAo1Jyqk010T7O4Q WhU5rEbj+9azwJ7xlFWmS6V+U3KjpoZiBaQaPrTd1V1zi9UEJHddfpxh6lHOqXW/WfCV vlbDxeCr+Cf73X9tgFcOUTJK9TJ0RqfwZLZnCQrCvjl67e3l+eLZz42nnP0/PgRdjLEr jYuKejqDcUV+skaLiHixN4lr+9NEqTp3SFohXRLg1LlVhFnxITwq3IQSjyt8L/fLbUhE sCtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="nZTx/qpd"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n7-20020a6543c7000000b00563fa953bc2si1796653pgp.419.2023.08.01.05.49.58; Tue, 01 Aug 2023 05:50:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="nZTx/qpd"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233773AbjHAKtO (ORCPT + 99 others); Tue, 1 Aug 2023 06:49:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233553AbjHAKsN (ORCPT ); Tue, 1 Aug 2023 06:48:13 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96DDE2D7B for ; Tue, 1 Aug 2023 03:47:24 -0700 (PDT) Message-ID: <20230801103816.692336580@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886836; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=O00kb3ANDLPAWttSm0Yl7DwanzSJODjrzlZY67TMPn8=; b=nZTx/qpda98XQpGOxar5sEuvHx2pz6oRkhtNM8AkHI9dz1wcgHpRcE3/+7UL5yptCIUqXX 6WGWXpUX7lEImcHEXY5GCUMGcQsCuwiwQVKgPThV4/pDUt9QvfRQC+aHvKZw68Q8yl62MC NiQDRRuLSewbifnGjl6uIYI/oVT2/EYocOLsxfcSyRS+U4szpD9hyKYoOodt6qLMFttWlc Ox3wxIQGdaJjfFpUznBD7mIqJnF+20SV54DAEYD75sl0BXBByEd6kOZTgdH/8l/10M162m pPa+1pZg8/nFZQqixKCXqRi+nBC2dZz5vZTjJETlwH3Ll2rqEC2ELJLDS9gjgw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886836; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=O00kb3ANDLPAWttSm0Yl7DwanzSJODjrzlZY67TMPn8=; b=LkvIB8qtIguA612odVwGu7nJYjleC1Ou/Yy4NJRnMHtM94erB2N2hL7KLPiHgPh77/btEK VkYN8AYiDGu0mJAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 28/60] x86/apic: Nuke empty init_apic_ldr() callbacks References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:15 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773031089584590157 X-GMAIL-MSGID: 1773031089584590157 apic::init_apic_ldr() is only invoked when the APIC is initialized. So there is really no point in having: - Default empty callbacks all over the place - Two implementations of the actual LDR init function where one is just unreadable gunk but does exactly the same as the other. Make the apic::init_apic_ldr() invocation conditional, remove the empty callbacks and consolidate the two implementation into one. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 -- arch/x86/kernel/apic/apic.c | 7 +++++-- arch/x86/kernel/apic/apic_common.c | 16 ++++++++++++++++ arch/x86/kernel/apic/apic_flat_64.c | 32 +------------------------------- arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/apic_numachip.c | 2 -- arch/x86/kernel/apic/bigsmp_32.c | 9 --------- arch/x86/kernel/apic/local.h | 5 ++--- arch/x86/kernel/apic/probe_32.c | 15 --------------- arch/x86/kernel/apic/x2apic_phys.c | 5 ----- arch/x86/kernel/apic/x2apic_uv_x.c | 5 ----- arch/x86/xen/apic.c | 1 - 12 files changed, 24 insertions(+), 77 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -445,8 +445,6 @@ extern void generic_bigsmp_probe(void); #include -#define APIC_DFR_VALUE (APIC_DFR_FLAT) - extern struct apic apic_noop; static inline unsigned int read_apic_id(void) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1578,9 +1578,12 @@ static void setup_local_APIC(void) /* * Intel recommends to set DFR, LDR and TPR before enabling * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel - * document number 292116). So here it goes... + * document number 292116). + * + * Except for APICs which operate in physical destination mode. */ - apic->init_apic_ldr(); + if (apic->init_apic_ldr) + apic->init_apic_ldr(); /* * Set Task Priority to 'accept all except vectors 0-31'. An APIC --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -6,6 +6,8 @@ #include #include +#include "local.h" + u32 apic_default_calc_apicid(unsigned int cpu) { return per_cpu(x86_cpu_to_apicid, cpu); @@ -39,3 +41,17 @@ int default_apic_id_valid(u32 apicid) { return (apicid < 255); } + +/* + * Set up the logical destination ID when the APIC operates in logical + * destination mode. + */ +void default_init_apic_ldr(void) +{ + unsigned long val; + + apic_write(APIC_DFR, APIC_DFR_FLAT); + val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; + val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); + apic_write(APIC_LDR, val); +} --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -28,26 +28,6 @@ static int flat_acpi_madt_oem_check(char return 1; } -/* - * Set up the logical destination ID. - * - * Intel recommends to set DFR, LDR and TPR before enabling - * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel - * document number 292116). So here it goes... - */ -void flat_init_apic_ldr(void) -{ - unsigned long val; - unsigned long num, id; - - num = smp_processor_id(); - id = 1UL << num; - apic_write(APIC_DFR, APIC_DFR_FLAT); - val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; - val |= SET_APIC_LOGICAL_ID(id); - apic_write(APIC_LDR, val); -} - static void _flat_send_IPI_mask(unsigned long mask, int vector) { unsigned long flags; @@ -119,7 +99,7 @@ static struct apic apic_flat __ro_after_ .disable_esr = 0, .check_apicid_used = NULL, - .init_apic_ldr = flat_init_apic_ldr, + .init_apic_ldr = default_init_apic_ldr, .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, @@ -175,15 +155,6 @@ static int physflat_acpi_madt_oem_check( return 0; } -static void physflat_init_apic_ldr(void) -{ - /* - * LDR and DFR are not involved in physflat mode, rather: - * "In physical destination mode, the destination processor is - * specified by its local APIC ID [...]." (Intel SDM, 10.6.2.1) - */ -} - static int physflat_probe(void) { if (apic == &apic_physflat || num_possible_cpus() > 8 || @@ -207,7 +178,6 @@ static struct apic apic_physflat __ro_af .disable_esr = 0, .check_apicid_used = NULL, - .init_apic_ldr = physflat_init_apic_ldr, .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -14,7 +14,6 @@ #include -static void noop_init_apic_ldr(void) { } static void noop_send_IPI(int cpu, int vector) { } static void noop_send_IPI_mask(const struct cpumask *cpumask, int vector) { } static void noop_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector) { } @@ -94,7 +93,6 @@ struct apic apic_noop __ro_after_init = .disable_esr = 0, .check_apicid_used = default_check_apicid_used, - .init_apic_ldr = noop_init_apic_ldr, .ioapic_phys_id_map = default_ioapic_phys_id_map, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -252,7 +252,6 @@ static const struct apic apic_numachip1 .disable_esr = 0, .check_apicid_used = NULL, - .init_apic_ldr = flat_init_apic_ldr, .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, @@ -297,7 +296,6 @@ static const struct apic apic_numachip2 .disable_esr = 0, .check_apicid_used = NULL, - .init_apic_ldr = flat_init_apic_ldr, .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -28,14 +28,6 @@ static bool bigsmp_check_apicid_used(phy return false; } -/* - * bigsmp enables physical destination mode - * and doesn't use LDR and DFR - */ -static void bigsmp_init_apic_ldr(void) -{ -} - static void bigsmp_setup_apic_routing(void) { printk(KERN_INFO @@ -108,7 +100,6 @@ static struct apic apic_bigsmp __ro_afte .disable_esr = 1, .check_apicid_used = bigsmp_check_apicid_used, - .init_apic_ldr = bigsmp_init_apic_ldr, .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map, .setup_apic_routing = bigsmp_setup_apic_routing, .cpu_present_to_apicid = default_cpu_present_to_apicid, --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -13,9 +13,6 @@ #include #include -/* APIC flat 64 */ -void flat_init_apic_ldr(void); - /* X2APIC */ int x2apic_apic_id_valid(u32 apicid); int x2apic_apic_id_registered(void); @@ -46,6 +43,8 @@ static inline unsigned int __prepare_ICR return icr; } +void default_init_apic_ldr(void); + void __default_send_IPI_shortcut(unsigned int shortcut, int vector); /* --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -32,21 +32,6 @@ static int default_apic_id_registered(vo return physid_isset(read_apic_id(), phys_cpu_present_map); } -/* - * Set up the logical destination ID. Intel recommends to set DFR, LDR and - * TPR before enabling an APIC. See e.g. "AP-388 82489DX User's Manual" - * (Intel document number 292116). - */ -static void default_init_apic_ldr(void) -{ - unsigned long val; - - apic_write(APIC_DFR, APIC_DFR_VALUE); - val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; - val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); - apic_write(APIC_LDR, val); -} - static int default_phys_pkg_id(int cpuid_apic, int index_msb) { return cpuid_apic >> index_msb; --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -91,10 +91,6 @@ static void x2apic_send_IPI_all(int vect __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC); } -static void init_x2apic_ldr(void) -{ -} - static int x2apic_phys_probe(void) { if (!x2apic_mode) @@ -169,7 +165,6 @@ static struct apic apic_x2apic_phys __ro .disable_esr = 0, .check_apicid_used = NULL, - .init_apic_ldr = init_x2apic_ldr, .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -788,10 +788,6 @@ static int uv_apic_id_registered(void) return 1; } -static void uv_init_apic_ldr(void) -{ -} - static u32 apic_uv_calc_apicid(unsigned int cpu) { return apic_default_calc_apicid(cpu); @@ -841,7 +837,6 @@ static struct apic apic_x2apic_uv_x __ro .disable_esr = 0, .check_apicid_used = NULL, - .init_apic_ldr = uv_init_apic_ldr, .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -149,7 +149,6 @@ static struct apic xen_pv_apic = { .disable_esr = 0, .check_apicid_used = default_check_apicid_used, /* Used on 32-bit */ - .init_apic_ldr = xen_noop, /* setup_local_APIC calls it */ .ioapic_phys_id_map = default_ioapic_phys_id_map, /* Used on 32-bit */ .setup_apic_routing = NULL, .cpu_present_to_apicid = xen_cpu_present_to_apicid, From patchwork Tue Aug 1 10:47:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129270 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2640770vqg; Tue, 1 Aug 2023 05:43:44 -0700 (PDT) X-Google-Smtp-Source: APBJJlGglJNdMHXh4vPULi8MiVN4wSryKEEEdxIKhhAqS02AYcRgAt64zx67iVTV7p+4dpO8jvTl X-Received: by 2002:a2e:8042:0:b0:2b9:f13b:6135 with SMTP id p2-20020a2e8042000000b002b9f13b6135mr2206507ljg.18.1690893824075; Tue, 01 Aug 2023 05:43:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893824; cv=none; d=google.com; s=arc-20160816; b=TEUzlRYZlQBMPOJYySEIxgnJMYQWDtxW8y+qXi7BiEQ2ZumJaxnJVovanhKKtrXgTK Occd09ljjHvRKegGVMMc3e3HQ4op7tiEKxJj08mZj20VHFjTYbeWCL8oqe2AoSmpKW3l x4IadyMsyaMTj6V1DqdizjQp6lMiOPltBcJorQsDOpKittCQZITMwz7a+nQVWo/7v4rl qeev+NWArpW0GUKnHxDgma+kEm+2sbc/mhnSCsAHGdU6ZmPpEL3OWudjssjNfgq5tvZO g+Oev/Xs2Z9WjhSshhwxWqgZ1BOC1BgCle0Els1FaMa9y90RIStGsMnLrnqsNwLbpR/Q ePSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=1MEDk0oUWD+OycA9uR7KeKJmXv9b1vvtIY5WeHz0Kk0=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=qJYtKZ/wo/0ndkNa056rSxovDZZVXt2a4d/3/d0WPQzFy4/mSGDPyudjF08wuoe5q+ yKf/qTMn8YiZxrnN1OfUpmyj/KPl/Rf3AQtQsbXU0r4sdHNInrpoLxATb6N11G20IHOt oBj4pRUKMlU1MQtFCgAhxH5ndGAjbqSPYcLe/kYSXfQ3YlN8/103NxyIJm4ELjlb++TJ N4gF6lZ3LiCnK9a0fonlGBGfcIXC3s4ubSN9M8AV1ttfiy7epgpi1+hgDMrOqDV8lFH+ vrT/rpP16+4olI7ZPmQJcX8GldGrfQ/7DNh+08ouNyKrVCl8pXJEa7WQe01MDakdk2qG CbCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Crff0pqI; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Remove the callback and use physid_set_mask_of_physid() in the code directly, Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 1 - arch/x86/kernel/apic/apic_numachip.c | 2 -- arch/x86/kernel/apic/bigsmp_32.c | 1 - arch/x86/kernel/apic/io_apic.c | 11 +++++------ arch/x86/kernel/apic/probe_32.c | 1 - arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 1 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 - arch/x86/xen/apic.c | 1 - 11 files changed, 5 insertions(+), 18 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -304,7 +304,6 @@ struct apic { void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); void (*setup_apic_routing)(void); int (*cpu_present_to_apicid)(int mps_cpu); - void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); int (*phys_pkg_id)(int cpuid_apic, int index_msb); u32 (*get_apic_id)(unsigned long x); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -103,7 +103,6 @@ static struct apic apic_flat __ro_after_ .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, - .apicid_to_cpu_present = NULL, .phys_pkg_id = flat_phys_pkg_id, .get_apic_id = flat_get_apic_id, @@ -181,7 +180,6 @@ static struct apic apic_physflat __ro_af .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, - .apicid_to_cpu_present = NULL, .phys_pkg_id = flat_phys_pkg_id, .get_apic_id = flat_get_apic_id, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -96,7 +96,6 @@ struct apic apic_noop __ro_after_init = .ioapic_phys_id_map = default_ioapic_phys_id_map, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, - .apicid_to_cpu_present = physid_set_mask_of_physid, .phys_pkg_id = noop_phys_pkg_id, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -255,7 +255,6 @@ static const struct apic apic_numachip1 .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, - .apicid_to_cpu_present = NULL, .phys_pkg_id = numachip_phys_pkg_id, .get_apic_id = numachip1_get_apic_id, @@ -299,7 +298,6 @@ static const struct apic apic_numachip2 .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, - .apicid_to_cpu_present = NULL, .phys_pkg_id = numachip_phys_pkg_id, .get_apic_id = numachip2_get_apic_id, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -103,7 +103,6 @@ static struct apic apic_bigsmp __ro_afte .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map, .setup_apic_routing = bigsmp_setup_apic_routing, .cpu_present_to_apicid = default_cpu_present_to_apicid, - .apicid_to_cpu_present = physid_set_mask_of_physid, .phys_pkg_id = bigsmp_phys_pkg_id, .get_apic_id = bigsmp_get_apic_id, --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1512,11 +1512,10 @@ void __init setup_ioapic_ids_from_mpc_no ioapics[ioapic_idx].mp_config.apicid = i; } else { physid_mask_t tmp; - apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), - &tmp); - apic_printk(APIC_VERBOSE, "Setting %d in the " - "phys_id_present_map\n", - mpc_ioapic_id(ioapic_idx)); + + physid_set_mask_of_physid(mpc_ioapic_id(ioapic_idx), &tmp); + apic_printk(APIC_VERBOSE, "Setting %d in the phys_id_present_map\n", + mpc_ioapic_id(ioapic_idx)); physids_or(phys_id_present_map, phys_id_present_map, tmp); } @@ -2546,7 +2545,7 @@ static int io_apic_get_unique_id(int ioa apic_id = i; } - apic->apicid_to_cpu_present(apic_id, &tmp); + physid_set_mask_of_physid(apic_id, &tmp); physids_or(apic_id_map, apic_id_map, tmp); if (reg_00.bits.ID != apic_id) { --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -60,7 +60,6 @@ static struct apic apic_default __ro_aft .ioapic_phys_id_map = default_ioapic_phys_id_map, .setup_apic_routing = setup_apic_flat_routing, .cpu_present_to_apicid = default_cpu_present_to_apicid, - .apicid_to_cpu_present = physid_set_mask_of_physid, .phys_pkg_id = default_phys_pkg_id, .get_apic_id = default_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -249,7 +249,6 @@ static struct apic apic_x2apic_cluster _ .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, - .apicid_to_cpu_present = NULL, .phys_pkg_id = x2apic_phys_pkg_id, .get_apic_id = x2apic_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -168,7 +168,6 @@ static struct apic apic_x2apic_phys __ro .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, - .apicid_to_cpu_present = NULL, .phys_pkg_id = x2apic_phys_pkg_id, .get_apic_id = x2apic_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -840,7 +840,6 @@ static struct apic apic_x2apic_uv_x __ro .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, - .apicid_to_cpu_present = NULL, .phys_pkg_id = uv_phys_pkg_id, .get_apic_id = x2apic_get_apic_id, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -152,7 +152,6 @@ static struct apic xen_pv_apic = { .ioapic_phys_id_map = default_ioapic_phys_id_map, /* Used on 32-bit */ .setup_apic_routing = NULL, .cpu_present_to_apicid = xen_cpu_present_to_apicid, - .apicid_to_cpu_present = physid_set_mask_of_physid, /* Used on 32-bit */ .phys_pkg_id = xen_phys_pkg_id, /* detect_ht */ .get_apic_id = xen_get_apic_id, From patchwork Tue Aug 1 10:47:18 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e184-20020a6369c1000000b00563e25c07c0si8832355pgc.270.2023.08.01.05.43.33; Tue, 01 Aug 2023 05:43:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=JzZ4pvGA; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234205AbjHAKtr (ORCPT + 99 others); Tue, 1 Aug 2023 06:49:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232871AbjHAKtH (ORCPT ); Tue, 1 Aug 2023 06:49:07 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C77DB3A9C for ; Tue, 1 Aug 2023 03:47:40 -0700 (PDT) Message-ID: <20230801103816.801427736@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886838; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1KrXZ6WN0UqKcYJn0Q3OLCj/xDPlvNt/2RBQorpLgnc=; b=JzZ4pvGAdAuoWfSspvr38QPDU5lVCe4tPQePPeYxM4DMwGJ4p0eJFfnRAViLUEwgJnLolL pW8fzgMUIFqBujJlSJyr2wBiuQ4R9O0oyG1ed0c7BiCKSxAtYesC4caXt47WmMox1CROFc +USO3RNyqJqALeNXO2MUu4bgXwKImP5lDx6ox6hBDiZrh2jzjvKZWIB4Vf6NUzrdXal+n6 8kbIqpJj2EktxnxySV9XeLVFAyYWNzYQK3hawi9F4M0wHnxAiLsvZWQxb7sgEPqVYNAaAn vs9VClaXQ1Tvt5XFI1He8wK/5+cWbcvXmHXMI0EDbhDc6Q+Ag8hbhGms2daNnA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886838; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1KrXZ6WN0UqKcYJn0Q3OLCj/xDPlvNt/2RBQorpLgnc=; b=q5LF6LwSb9xUUPmwXv0iQa39Fr3DpgZ2pvHJWEWAJn4oVPIRfA1Pnebzzid18PkmT8rQbT 2ZQSCzlPvF4UGZBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 30/60] x86/ioapic/32: Decrapify phys_id_present_map operation References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:18 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773030685160992406 X-GMAIL-MSGID: 1773030685160992406 The operation to set the IOAPIC ID in phys_id_present_map is as convoluted as it can be. 1) Allocate a bitmap of 32byte size on the stack 2) Zero the bitmap and set the IOAPIC ID bit 3) Or the temporary bitmap over phys_id_present_map The same functionality can be achieved by setting the IOAPIC ID bit directly in the phys_id_present_map. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/io_apic.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1511,12 +1511,9 @@ void __init setup_ioapic_ids_from_mpc_no physid_set(i, phys_id_present_map); ioapics[ioapic_idx].mp_config.apicid = i; } else { - physid_mask_t tmp; - - physid_set_mask_of_physid(mpc_ioapic_id(ioapic_idx), &tmp); apic_printk(APIC_VERBOSE, "Setting %d in the phys_id_present_map\n", mpc_ioapic_id(ioapic_idx)); - physids_or(phys_id_present_map, phys_id_present_map, tmp); + physid_set(mpc_ioapic_id(ioapic_idx), phys_id_present_map); } /* From patchwork Tue Aug 1 10:47:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129275 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2643725vqg; Tue, 1 Aug 2023 05:49:49 -0700 (PDT) X-Google-Smtp-Source: APBJJlE5xZrHTsaVBSln9CYAMogw4JAoVADxDQctHiG5/dVZeH91rklnXckXAkrgRoPDcINd6O3L X-Received: by 2002:a17:907:e9e:b0:98d:4b97:acc8 with SMTP id ho30-20020a1709070e9e00b0098d4b97acc8mr3332025ejc.25.1690894189551; Tue, 01 Aug 2023 05:49:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690894189; cv=none; d=google.com; s=arc-20160816; b=pQRVPc5lnMJBgCTosJBBitfWCJ6IcU3fs43TPU1qO169cZZOAVOHWKKDGZxC0HFPpi SLVWzkK2RbdjlvasiT1ADEkJ7ilrKVMaoHEExnDrMUBhSEoFaybWb5R7rWmjrt4FcT4+ b4PeN+w70tReQjPVOYfbV/1LhG6/x3IMefGZhDo1jLsPtZyUJyzx6KJMlCu/rVETi7LM UuzLIjBYSX0AI2c7dEkRYGLKL4ZH61JMJrqCOs8UYLay3gJHuaDA2gUGz3X0o8TGXwD4 xXZ/mU+wfsaG1xwDlfbl9SOj8XK1x28pMjketVd9J/vsmwYFXJJnwOAIsMGwpXmMp7fM lsuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=VD8E0eWfITI3SqlQ5XFWHaHK77hHBGW1xMWiR2dsiXE=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=T46p1IubmWyIDuPdHjTVWX2URGbCvh5+nvdZKJCaVYrS6xtt1yTuFlrqdYdpXdD67v aVCmSBR+xyp4jxRnoiCNUKL76ar+t1NnrGZE54wiCyjE1ffenymechuFy5wE4x2Q/4CI xbXfPM/UdRjGQeRNgBAGIZXplI5qkeghCJCbjmwZZeZbDQ2OCHSmYb3fKpVX9oxNXIJ2 65Bx2ZCS3qRyItMpizPA5+cFPjCEgXKOkIToECMsfUBCn3BgK3bKOPEhAi8EdB3yHapE 4WkdsWihraEkB52fpSghCv5VGJ9cr3+2onO0y9P8RDZ3CeiE7LXux9zr3wKq3vMyazeP vopg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=RQF6VHDN; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=Q+s8Kmed; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x7-20020a170906298700b0099bc80856f1si8286839eje.219.2023.08.01.05.49.25; Tue, 01 Aug 2023 05:49:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=RQF6VHDN; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=Q+s8Kmed; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230477AbjHAKtz (ORCPT + 99 others); Tue, 1 Aug 2023 06:49:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233814AbjHAKtK (ORCPT ); Tue, 1 Aug 2023 06:49:10 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5D31E6D for ; Tue, 1 Aug 2023 03:47:42 -0700 (PDT) Message-ID: <20230801103816.855755065@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886839; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VD8E0eWfITI3SqlQ5XFWHaHK77hHBGW1xMWiR2dsiXE=; b=RQF6VHDNvbdM42kvcV0timQEMy2HRclrr5FH417QfVPCILipz9xkDY/Gxbsho1TailAzcw hB/ILjHCOeiNtPlOV6hgi+vI922gT8yEChvVq/1k06Zuo9CzKkPIwfEbb4yN0TpveAH51p 7f8E/SxQCmsIL+v1bBN03JolEe9xU4ZVIvdGEtGNwuG89IDz/3CZfOWzVtqeFYP+/mGkJO Vlklc9SIIeiPArP4KiQ50JPHUMKzCJ0kxJ9Rv5NDsIBY4SQyBUDTXZUuoKhrNaApJk9iXA NOJGf2n4ycGRKYCAya67XFWZ7e2qZSqHdret0YHThyMuqhdx0ysywmuLCASDpg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886839; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VD8E0eWfITI3SqlQ5XFWHaHK77hHBGW1xMWiR2dsiXE=; b=Q+s8KmednA7RL3Cs5M/spCxfts4PDMwbp9ylAPwQieCsO6HSrFbK71uFUal0Hp73zaY+3B 0ws7ZCb6UDfmxQDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 31/60] x86/apic: Mop up *setup_apic_routing() References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:19 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773031065600527727 X-GMAIL-MSGID: 1773031065600527727 default_setup_apic_routing() is a complete misnomer. On 64bit it does the actual APIC probing and on 32bit it is used to force select the bigsmp APIC and to emit a redundant message in the apic::setup_apic_routing() callback. Rename the 64bit and 32bit function so they reflect what they are doing and remove the useless APIC callback. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 10 ++++------ arch/x86/kernel/apic/apic.c | 4 +++- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 1 - arch/x86/kernel/apic/apic_numachip.c | 2 -- arch/x86/kernel/apic/bigsmp_32.c | 8 -------- arch/x86/kernel/apic/local.h | 2 ++ arch/x86/kernel/apic/probe_32.c | 17 ++--------------- arch/x86/kernel/apic/probe_64.c | 2 +- arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 1 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 - arch/x86/kernel/setup.c | 2 +- arch/x86/xen/apic.c | 1 - 14 files changed, 13 insertions(+), 41 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -40,11 +40,9 @@ #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) -extern void generic_apic_probe(void); +extern void x86_32_probe_apic(void); #else -static inline void generic_apic_probe(void) -{ -} +static inline void x86_32_probe_apic(void) { } #endif #ifdef CONFIG_X86_LOCAL_APIC @@ -302,7 +300,6 @@ struct apic { bool (*check_apicid_used)(physid_mask_t *map, int apicid); void (*init_apic_ldr)(void); void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); - void (*setup_apic_routing)(void); int (*cpu_present_to_apicid)(int mps_cpu); int (*phys_pkg_id)(int cpuid_apic, int index_msb); @@ -457,12 +454,13 @@ static inline unsigned int read_apic_id( typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); extern int default_acpi_madt_oem_check(char *, char *); +extern void x86_64_probe_apic(void); #else static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } +static inline void x86_64_probe_apic(void) { } #endif extern int default_apic_id_valid(u32 apicid); -extern void default_setup_apic_routing(void); extern u32 apic_default_calc_apicid(unsigned int cpu); extern u32 apic_flat_calc_apicid(unsigned int cpu); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1419,7 +1419,9 @@ void __init apic_intr_mode_init(void) break; } - default_setup_apic_routing(); + x86_64_probe_apic(); + + x86_32_install_bigsmp(); if (x86_platform.apic_post_init) x86_platform.apic_post_init(); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -101,7 +101,6 @@ static struct apic apic_flat __ro_after_ .check_apicid_used = NULL, .init_apic_ldr = default_init_apic_ldr, .ioapic_phys_id_map = NULL, - .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = flat_phys_pkg_id, @@ -178,7 +177,6 @@ static struct apic apic_physflat __ro_af .check_apicid_used = NULL, .ioapic_phys_id_map = NULL, - .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = flat_phys_pkg_id, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -94,7 +94,6 @@ struct apic apic_noop __ro_after_init = .check_apicid_used = default_check_apicid_used, .ioapic_phys_id_map = default_ioapic_phys_id_map, - .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = noop_phys_pkg_id, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -253,7 +253,6 @@ static const struct apic apic_numachip1 .check_apicid_used = NULL, .ioapic_phys_id_map = NULL, - .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = numachip_phys_pkg_id, @@ -296,7 +295,6 @@ static const struct apic apic_numachip2 .check_apicid_used = NULL, .ioapic_phys_id_map = NULL, - .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = numachip_phys_pkg_id, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -28,13 +28,6 @@ static bool bigsmp_check_apicid_used(phy return false; } -static void bigsmp_setup_apic_routing(void) -{ - printk(KERN_INFO - "Enabling APIC mode: Physflat. Using %d I/O APICs\n", - nr_ioapics); -} - static void bigsmp_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) { /* For clustered we don't have a good way to do this yet - hack */ @@ -101,7 +94,6 @@ static struct apic apic_bigsmp __ro_afte .check_apicid_used = bigsmp_check_apicid_used, .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map, - .setup_apic_routing = bigsmp_setup_apic_routing, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = bigsmp_phys_pkg_id, --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -66,8 +66,10 @@ void default_send_IPI_mask_sequence_logi void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, int vector); void default_send_IPI_mask_logical(const struct cpumask *mask, int vector); void x86_32_probe_bigsmp_early(void); +void x86_32_install_bigsmp(void); #else static inline void x86_32_probe_bigsmp_early(void) { } +static inline void x86_32_install_bigsmp(void) { } #endif #ifdef CONFIG_X86_BIGSMP --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -18,15 +18,6 @@ #include "local.h" -static void setup_apic_flat_routing(void) -{ -#ifdef CONFIG_X86_IO_APIC - printk(KERN_INFO - "Enabling APIC mode: Flat. Using %d I/O APICs\n", - nr_ioapics); -#endif -} - static int default_apic_id_registered(void) { return physid_isset(read_apic_id(), phys_cpu_present_map); @@ -58,7 +49,6 @@ static struct apic apic_default __ro_aft .check_apicid_used = default_check_apicid_used, .init_apic_ldr = default_init_apic_ldr, .ioapic_phys_id_map = default_ioapic_phys_id_map, - .setup_apic_routing = setup_apic_flat_routing, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = default_phys_pkg_id, @@ -132,16 +122,13 @@ void __init x86_32_probe_bigsmp_early(vo set_nr_cpu_ids(8); } -void __init default_setup_apic_routing(void) +void __init x86_32_install_bigsmp(void) { if (nr_cpu_ids >= 8 && !xen_pv_domain()) apic_bigsmp_force(); - - if (apic->setup_apic_routing) - apic->setup_apic_routing(); } -void __init generic_apic_probe(void) +void __init x86_32_probe_apic(void) { if (!cmdline_apic) { struct apic **drv; --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -14,7 +14,7 @@ #include "local.h" /* Select the appropriate APIC driver */ -void __init default_setup_apic_routing(void) +void __init x86_64_probe_apic(void) { struct apic **drv; --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -247,7 +247,6 @@ static struct apic apic_x2apic_cluster _ .check_apicid_used = NULL, .init_apic_ldr = init_x2apic_ldr, .ioapic_phys_id_map = NULL, - .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = x2apic_phys_pkg_id, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -166,7 +166,6 @@ static struct apic apic_x2apic_phys __ro .check_apicid_used = NULL, .ioapic_phys_id_map = NULL, - .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = x2apic_phys_pkg_id, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -838,7 +838,6 @@ static struct apic apic_x2apic_uv_x __ro .check_apicid_used = NULL, .ioapic_phys_id_map = NULL, - .setup_apic_routing = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = uv_phys_pkg_id, --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1253,7 +1253,7 @@ void __init setup_arch(char **cmdline_p) map_vsyscall(); - generic_apic_probe(); + x86_32_probe_apic(); early_quirks(); --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -150,7 +150,6 @@ static struct apic xen_pv_apic = { .check_apicid_used = default_check_apicid_used, /* Used on 32-bit */ .ioapic_phys_id_map = default_ioapic_phys_id_map, /* Used on 32-bit */ - .setup_apic_routing = NULL, .cpu_present_to_apicid = xen_cpu_present_to_apicid, .phys_pkg_id = xen_phys_pkg_id, /* detect_ht */ From patchwork Tue Aug 1 10:47:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129287 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2647489vqg; Tue, 1 Aug 2023 05:57:38 -0700 (PDT) X-Google-Smtp-Source: APBJJlHYJ1mMRdcSlHl0Q2DEL5T/knE/k56TyrNHevfK9zDw9nvBq2WBLFOA5J/7wt17PBsRKK+c X-Received: by 2002:a05:6a20:1586:b0:139:8517:10b6 with SMTP id h6-20020a056a20158600b00139851710b6mr14453225pzj.30.1690894657761; Tue, 01 Aug 2023 05:57:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690894657; cv=none; d=google.com; s=arc-20160816; b=f5eCiKi/OBp1RYebqe/RFkXp5vhnqqFEFCCMgZf9WKr3q8Q/n1aDN4ItlBx3tjognf 5mBqEw47IiZ5kApQBaBy7ti/7o6JKjRWNQCzEw8jNv4eaJaS2gtrMXp4ErpAvSCR5Mgd WDO26mUXKjIN/9pUC8GfpHFnmSbBUf4q+ginpu6kHki7XoTJP3zThmIcISC7GApJclJf 2vnI/kKUIkePvmIR2+Exe8bZjneh9g68j96X+CQMap069ng1peyWX8FTUhy1SZEn4rXt LLIE4K1XQHyTLWEmRkJXRdJnIFR4u5GPOYN9lFuacSluOKTqk4rIGAYmm+Jp7PRaGa0a uotw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=KMlJ8GHAqxlGy3Usfux4GuD7eAy2oZuqB8vi82Tf9K0=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=SFZii91ZWt6JNAP662QXkbLLNCQjaYv7Om64+ChtOSpY0lslTlrqpUVgPrHlnaON3p mKuB9Cv0B1JMFcOoOs/zwszEpXitAVJU+rpRa7fDgPkyj89Rlu7SWTu7sY5OoWw2yPqq N/RkBxzu6B9kbspfFGaWTC8PuoswLSSbuT5YDbiHrbUqRL91eRVb+bgrbUB9VUDpsovi npa+MvH2Tf1n8ZX9sJx8A4tougGe9Q94ZQ95DCWmgWEi4q1Dl7F82UjH0fWZy55KZ8G+ q7wGbv128GYf0Q1/0MNnQN84Mzan0OYiZSK1EHrr7dVPS7/VS3J+Q/YUmQEUCYv3TzXP Li3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=UndwRvZL; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=VkpFBj3L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Make it return bool and provide one shared implementation for the remaining users. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 +- arch/x86/kernel/apic/apic.c | 7 ++----- arch/x86/kernel/apic/apic_common.c | 5 +++++ arch/x86/kernel/apic/apic_flat_64.c | 14 ++------------ arch/x86/kernel/apic/apic_noop.c | 12 ------------ arch/x86/kernel/apic/apic_numachip.c | 7 ------- arch/x86/kernel/apic/bigsmp_32.c | 6 ------ arch/x86/kernel/apic/local.h | 3 ++- arch/x86/kernel/apic/probe_32.c | 5 ----- arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 6 ------ arch/x86/kernel/apic/x2apic_uv_x.c | 6 ------ arch/x86/xen/apic.c | 6 ------ 13 files changed, 12 insertions(+), 68 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -295,7 +295,7 @@ struct apic { int (*probe)(void); int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); int (*apic_id_valid)(u32 apicid); - int (*apic_id_registered)(void); + bool (*apic_id_registered)(void); bool (*check_apicid_used)(physid_mask_t *map, int apicid); void (*init_apic_ldr)(void); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1571,11 +1571,8 @@ static void setup_local_APIC(void) apic_write(APIC_ESR, 0); } #endif - /* - * Double-check whether this APIC is really registered. - * This is meaningless in clustered apic mode, so we skip it. - */ - BUG_ON(!apic->apic_id_registered()); + /* Validate that the APIC is registered if required */ + BUG_ON(apic->apic_id_registered && !apic->apic_id_registered()); /* * Intel recommends to set DFR, LDR and TPR before enabling --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -42,6 +42,11 @@ int default_apic_id_valid(u32 apicid) return (apicid < 255); } +bool default_apic_id_registered(void) +{ + return physid_isset(read_apic_id(), phys_cpu_present_map); +} + /* * Set up the logical destination ID when the APIC operates in logical * destination mode. --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -66,16 +66,6 @@ static u32 set_apic_id(unsigned int id) return (id & 0xFF) << 24; } -static unsigned int read_xapic_id(void) -{ - return flat_get_apic_id(apic_read(APIC_ID)); -} - -static int flat_apic_id_registered(void) -{ - return physid_isset(read_xapic_id(), phys_cpu_present_map); -} - static int flat_phys_pkg_id(int initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; @@ -91,7 +81,7 @@ static struct apic apic_flat __ro_after_ .probe = flat_probe, .acpi_madt_oem_check = flat_acpi_madt_oem_check, .apic_id_valid = default_apic_id_valid, - .apic_id_registered = flat_apic_id_registered, + .apic_id_registered = default_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = true, @@ -168,7 +158,7 @@ static struct apic apic_physflat __ro_af .probe = physflat_probe, .acpi_madt_oem_check = physflat_acpi_madt_oem_check, .apic_id_valid = default_apic_id_valid, - .apic_id_registered = flat_apic_id_registered, + .apic_id_registered = default_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -57,17 +57,6 @@ static int noop_probe(void) return 0; } -static int noop_apic_id_registered(void) -{ - /* - * if we would be really "pedantic" - * we should pass read_apic_id() here - * but since NOOP suppose APIC ID = 0 - * lets save a few cycles - */ - return physid_isset(0, phys_cpu_present_map); -} - static u32 noop_apic_read(u32 reg) { WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !apic_is_disabled); @@ -85,7 +74,6 @@ struct apic apic_noop __ro_after_init = .acpi_madt_oem_check = NULL, .apic_id_valid = default_apic_id_valid, - .apic_id_registered = noop_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = true, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -62,11 +62,6 @@ static int numachip_apic_id_valid(u32 ap return 1; } -static int numachip_apic_id_registered(void) -{ - return 1; -} - static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; @@ -244,7 +239,6 @@ static const struct apic apic_numachip1 .probe = numachip1_probe, .acpi_madt_oem_check = numachip1_acpi_madt_oem_check, .apic_id_valid = numachip_apic_id_valid, - .apic_id_registered = numachip_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, @@ -286,7 +280,6 @@ static const struct apic apic_numachip2 .probe = numachip2_probe, .acpi_madt_oem_check = numachip2_acpi_madt_oem_check, .apic_id_valid = numachip_apic_id_valid, - .apic_id_registered = numachip_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -18,11 +18,6 @@ static unsigned bigsmp_get_apic_id(unsig return (x >> 24) & 0xFF; } -static int bigsmp_apic_id_registered(void) -{ - return 1; -} - static bool bigsmp_check_apicid_used(physid_mask_t *map, int apicid) { return false; @@ -85,7 +80,6 @@ static struct apic apic_bigsmp __ro_afte .name = "bigsmp", .probe = probe_bigsmp, .apic_id_valid = default_apic_id_valid, - .apic_id_registered = bigsmp_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -15,7 +15,6 @@ /* X2APIC */ int x2apic_apic_id_valid(u32 apicid); -int x2apic_apic_id_registered(void); void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest); unsigned int x2apic_get_apic_id(unsigned long id); u32 x2apic_set_apic_id(unsigned int id); @@ -61,6 +60,8 @@ void default_send_IPI_allbutself(int vec void default_send_IPI_all(int vector); void default_send_IPI_self(int vector); +bool default_apic_id_registered(void); + #ifdef CONFIG_X86_32 void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, int vector); void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, int vector); --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -18,11 +18,6 @@ #include "local.h" -static int default_apic_id_registered(void) -{ - return physid_isset(read_apic_id(), phys_cpu_present_map); -} - static int default_phys_pkg_id(int cpuid_apic, int index_msb) { return cpuid_apic >> index_msb; --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -237,7 +237,6 @@ static struct apic apic_x2apic_cluster _ .probe = x2apic_cluster_probe, .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, .apic_id_valid = x2apic_apic_id_valid, - .apic_id_registered = x2apic_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = true, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -111,11 +111,6 @@ int x2apic_apic_id_valid(u32 apicid) return 1; } -int x2apic_apic_id_registered(void) -{ - return 1; -} - void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest) { unsigned long cfg = __prepare_ICR(0, vector, dest); @@ -157,7 +152,6 @@ static struct apic apic_x2apic_phys __ro .probe = x2apic_phys_probe, .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, .apic_id_valid = x2apic_apic_id_valid, - .apic_id_registered = x2apic_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -783,11 +783,6 @@ static int uv_apic_id_valid(u32 apicid) return 1; } -static int uv_apic_id_registered(void) -{ - return 1; -} - static u32 apic_uv_calc_apicid(unsigned int cpu) { return apic_default_calc_apicid(cpu); @@ -829,7 +824,6 @@ static struct apic apic_x2apic_uv_x __ro .probe = uv_probe, .acpi_madt_oem_check = uv_acpi_madt_oem_check, .apic_id_valid = uv_apic_id_valid, - .apic_id_registered = uv_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -115,11 +115,6 @@ static int xen_id_always_valid(u32 apici return 1; } -static int xen_id_always_registered(void) -{ - return 1; -} - static int xen_phys_pkg_id(int initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; @@ -142,7 +137,6 @@ static struct apic xen_pv_apic = { .probe = xen_apic_probe_pv, .acpi_madt_oem_check = xen_madt_oem_check, .apic_id_valid = xen_id_always_valid, - .apic_id_registered = xen_id_always_registered, /* .delivery_mode and .dest_mode_logical not used by XENPV */ From patchwork Tue Aug 1 10:47:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129269 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2640677vqg; Tue, 1 Aug 2023 05:43:35 -0700 (PDT) X-Google-Smtp-Source: APBJJlHhWNhFJSOKKjID0vALDfi840yQNrbXsN+jKEd3qeIjEL5ydBtCVO9v2heGzndrevwcXvo3 X-Received: by 2002:a17:902:dacf:b0:1bb:c9e3:6d4f with SMTP id q15-20020a170902dacf00b001bbc9e36d4fmr17441175plx.10.1690893815153; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id a6-20020a170902ecc600b001bbabd5b14esi2006713plh.608.2023.08.01.05.43.21; Tue, 01 Aug 2023 05:43:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=O4gGV7ZO; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233551AbjHAKto (ORCPT + 99 others); Tue, 1 Aug 2023 06:49:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234142AbjHAKtH (ORCPT ); Tue, 1 Aug 2023 06:49:07 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7AF435BB for ; Tue, 1 Aug 2023 03:47:39 -0700 (PDT) Message-ID: <20230801103816.969106021@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886842; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gTGbbDL5HBuwEB2u+LxYM2ki0P05Jj6Bwt/DqClxZRM=; b=O4gGV7ZOTVqqbE6WSzsywAE5Cpx7g7mSLkc5363gGwi7+ahrylAyXCJPa9zNdfozz+j5UE 17tQSbwgejhr/4IjXgpWuImY0feIHZEcv47fhed5mlH5gT4HZ0ZO+1+H3w5Ifew1duomZK YLph3O3TvX68sg1OPZj8IitHGh9l+7F13b7IbbiinGXsflqEWvwRAC8vfK8i0sqjMtOSi3 lCEXKTb+MNEixXo2UqiWPXIMGqnqG8suKZJvmXhzhgkSGtL+osXBcW+NqBWs+AmWifzl9c lvMmaYe5nEMZhNUkjYl2S6loeHR5DzSiyFCPAz44ss080GeUvWzvGB/UF790Yw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886842; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gTGbbDL5HBuwEB2u+LxYM2ki0P05Jj6Bwt/DqClxZRM=; b=cM7usDf8nyzMnAL7AVpjBBqvxDJiBHwi0Mya4JKi36rmvsACYGj91OylKsdZEo6ZvfLQ1N P/RYVAgzEdrHLFCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 33/60] x86/apic/ipi: Tidy up the code and fixup comments References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:22 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773030672988289456 X-GMAIL-MSGID: 1773030672988289456 Replace the undecodable comment on top of the function, replace the space consuming zero content comments with useful ones and tidy up the implementation to prevent further eye bleed. Make __default_send_IPI_shortcut() static as it has no other users. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/ipi.c | 74 ++++++++++++++++++------------------------- arch/x86/kernel/apic/local.h | 2 - 2 files changed, 32 insertions(+), 44 deletions(-) --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -108,68 +108,58 @@ static inline void __xapic_wait_icr_idle cpu_relax(); } -void __default_send_IPI_shortcut(unsigned int shortcut, int vector) +/* + * This is safe against interruption because it only writes the lower 32 + * bits of the APIC_ICR register. The destination field is ignored for + * short hand IPIs. + * + * wait_icr_idle() + * write(ICR2, dest) + * NMI + * wait_icr_idle() + * write(ICR) + * wait_icr_idle() + * write(ICR) + * + * This function does not need to disable interrupts as there is no ICR2 + * interaction. The memory write is direct except when the machine is + * affected by the 11AP Pentium erratum, which turns the plain write into + * an XCHG operation. + */ +static void __default_send_IPI_shortcut(unsigned int shortcut, int vector) { /* - * Subtle. In the case of the 'never do double writes' workaround - * we have to lock out interrupts to be safe. As we don't care - * of the value read we use an atomic rmw access to avoid costly - * cli/sti. Otherwise we use an even cheaper single atomic write - * to the APIC. - */ - unsigned int cfg; - - /* - * Wait for idle. + * Wait for the previous ICR command to complete. Use + * safe_apic_wait_icr_idle() for the NMI vector as there have been + * issues where otherwise the system hangs when the panic CPU tries + * to stop the others before launching the kdump kernel. */ if (unlikely(vector == NMI_VECTOR)) safe_apic_wait_icr_idle(); else __xapic_wait_icr_idle(); - /* - * No need to touch the target chip field. Also the destination - * mode is ignored when a shorthand is used. - */ - cfg = __prepare_ICR(shortcut, vector, 0); - - /* - * Send the IPI. The write to APIC_ICR fires this off. - */ - native_apic_mem_write(APIC_ICR, cfg); + /* Destination field (ICR2) and the destination mode are ignored */ + native_apic_mem_write(APIC_ICR, __prepare_ICR(shortcut, vector, 0)); } /* * This is used to send an IPI with no shorthand notation (the destination is * specified in bits 56 to 63 of the ICR). */ -void __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest) +void __default_send_IPI_dest_field(unsigned int dest_mask, int vector, + unsigned int dest_mode) { - unsigned long cfg; - - /* - * Wait for idle. - */ + /* See comment in __default_send_IPI_shortcut() */ if (unlikely(vector == NMI_VECTOR)) safe_apic_wait_icr_idle(); else __xapic_wait_icr_idle(); - /* - * prepare target chip field - */ - cfg = __prepare_ICR2(mask); - native_apic_mem_write(APIC_ICR2, cfg); - - /* - * program the ICR - */ - cfg = __prepare_ICR(0, vector, dest); - - /* - * Send the IPI. The write to APIC_ICR fires this off. - */ - native_apic_mem_write(APIC_ICR, cfg); + /* Set the IPI destination field in the ICR */ + native_apic_mem_write(APIC_ICR2, __prepare_ICR2(dest_mask)); + /* Send it with the proper destination mode */ + native_apic_mem_write(APIC_ICR, __prepare_ICR(0, vector, dest_mode)); } void default_send_IPI_single_phys(int cpu, int vector) --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -44,8 +44,6 @@ static inline unsigned int __prepare_ICR void default_init_apic_ldr(void); -void __default_send_IPI_shortcut(unsigned int shortcut, int vector); - /* * This is used to send an IPI with no shorthand notation (the destination is * specified in bits 56 to 63 of the ICR). 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n19-20020a170906165300b0098dfb10f3a6si8207685ejd.107.2023.08.01.05.15.14; Tue, 01 Aug 2023 05:15:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=jYhhjFcs; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=lyFuWaDJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233984AbjHAKtu (ORCPT + 99 others); Tue, 1 Aug 2023 06:49:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233844AbjHAKtL (ORCPT ); Tue, 1 Aug 2023 06:49:11 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36C6F3AB8 for ; Tue, 1 Aug 2023 03:47:45 -0700 (PDT) Message-ID: <20230801103817.025388065@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886843; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XotObdBbNP3ucbQgBWCj/e0HCpzDGhDJU7P6fYqyeq4=; b=jYhhjFcsLCvW+/EDGAgzDQdpnkodJxfel+16jjleHFqHApDJQU6tD/+COmE9DkztwD85Pm N1dmNA7HAT8YzyVPMalVYkcc8VBV1cu1ujZrKeZvVC1d5SuHz7M0mjTfIIFHHOKUhPTCng b6yp0vHy4dX8zptK0QLZBA3lCkpVc1roa9QpnOr5iycBl1opJoA/tCiKpzK077GBl5pgmu XfJ7YfJqt7ENgtAxyZgXKpqrUwHLQc7GbZ95JTv2zQGtzS/5Wr3wRO65PKXEvLtHAy1AAh UInc9mFim0Dz2rlao/NHWSZN/+WPbv0SgWA5zedf7oPXgx/LKjHajCgJNuW7jw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886843; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XotObdBbNP3ucbQgBWCj/e0HCpzDGhDJU7P6fYqyeq4=; b=lyFuWaDJ5I/E6Q2YA7vXXaWucask2hDGUiiCu8FoIhvysnqkMFKYELTIUzHd0O1H+qplsw klKH/+B7Oxx6gDBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 34/60] x86/apic: Consolidate wait_icr_idle() implementations References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:23 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773028916540575733 X-GMAIL-MSGID: 1773028916540575733 Two copies and also needlessly public. Move it into ipi.c so it can be inlined. Rename it to apic_mem_wait_icr_idle(). Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic.c | 6 ------ arch/x86/kernel/apic/apic_flat_64.c | 4 ++-- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/ipi.c | 6 +++--- arch/x86/kernel/apic/local.h | 2 ++ arch/x86/kernel/apic/probe_32.c | 2 +- 7 files changed, 9 insertions(+), 14 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -98,7 +98,6 @@ static inline u32 native_apic_mem_read(u return *((volatile u32 *)(APIC_BASE + reg)); } -extern void native_apic_wait_icr_idle(void); extern u32 native_safe_apic_wait_icr_idle(void); extern void native_apic_icr_write(u32 low, u32 id); extern u64 native_apic_icr_read(void); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -240,12 +240,6 @@ static void __init apic_disable(void) apic = &apic_noop; } -void native_apic_wait_icr_idle(void) -{ - while (apic_read(APIC_ICR) & APIC_ICR_BUSY) - cpu_relax(); -} - u32 native_safe_apic_wait_icr_idle(void) { u32 send_status; --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -111,7 +111,7 @@ static struct apic apic_flat __ro_after_ .eoi_write = native_apic_mem_write, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, - .wait_icr_idle = native_apic_wait_icr_idle, + .wait_icr_idle = apic_mem_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, }; @@ -187,7 +187,7 @@ static struct apic apic_physflat __ro_af .eoi_write = native_apic_mem_write, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, - .wait_icr_idle = native_apic_wait_icr_idle, + .wait_icr_idle = apic_mem_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, }; --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -108,7 +108,7 @@ static struct apic apic_bigsmp __ro_afte .eoi_write = native_apic_mem_write, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, - .wait_icr_idle = native_apic_wait_icr_idle, + .wait_icr_idle = apic_mem_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, }; --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -102,7 +102,7 @@ static inline int __prepare_ICR2(unsigne return SET_XAPIC_DEST_FIELD(mask); } -static inline void __xapic_wait_icr_idle(void) +void apic_mem_wait_icr_idle(void) { while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY) cpu_relax(); @@ -137,7 +137,7 @@ static void __default_send_IPI_shortcut( if (unlikely(vector == NMI_VECTOR)) safe_apic_wait_icr_idle(); else - __xapic_wait_icr_idle(); + apic_mem_wait_icr_idle(); /* Destination field (ICR2) and the destination mode are ignored */ native_apic_mem_write(APIC_ICR, __prepare_ICR(shortcut, vector, 0)); @@ -154,7 +154,7 @@ void __default_send_IPI_dest_field(unsig if (unlikely(vector == NMI_VECTOR)) safe_apic_wait_icr_idle(); else - __xapic_wait_icr_idle(); + apic_mem_wait_icr_idle(); /* Set the IPI destination field in the ICR */ native_apic_mem_write(APIC_ICR2, __prepare_ICR2(dest_mask)); --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -44,6 +44,8 @@ static inline unsigned int __prepare_ICR void default_init_apic_ldr(void); +void apic_mem_wait_icr_idle(void); + /* * This is used to send an IPI with no shorthand notation (the destination is * specified in bits 56 to 63 of the ICR). --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -64,7 +64,7 @@ static struct apic apic_default __ro_aft .eoi_write = native_apic_mem_write, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, - .wait_icr_idle = native_apic_wait_icr_idle, + .wait_icr_idle = apic_mem_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, }; From patchwork Tue Aug 1 10:47:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129233 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2614522vqg; Tue, 1 Aug 2023 04:58:31 -0700 (PDT) X-Google-Smtp-Source: APBJJlHKNsbYxs884Br+oQ8ZhODm8/fmiQtSPW4TehNeMMObVOhG1eVoSLOTEZHuo6NL2Najcr+p X-Received: by 2002:a05:6808:1524:b0:3a7:2d21:2923 with SMTP id u36-20020a056808152400b003a72d212923mr8460864oiw.58.1690891110845; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w4-20020a656944000000b00534780446d9si8750046pgq.640.2023.08.01.04.58.17; Tue, 01 Aug 2023 04:58:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=L2VnB2bW; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234032AbjHAKt5 (ORCPT + 99 others); Tue, 1 Aug 2023 06:49:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233853AbjHAKtL (ORCPT ); Tue, 1 Aug 2023 06:49:11 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 557AC3ABA for ; Tue, 1 Aug 2023 03:47:45 -0700 (PDT) Message-ID: <20230801103817.079672072@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886844; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1p6M+HuhFutrVv6xarMScHVasdihs8aPDhQcOtKs0Y8=; b=L2VnB2bWVDToPq/sHERaiQL9m+S544m04dbw6ZcpksNGvjmkIBqnS9sa2l2p5qqgzeqry8 NqgoKldNSXWGF1vV4vS0ENt2c3KrzKN8n8LUmkTDQSvABNy6QPUuTEmJKz2EW2ert5ElDH kT9lh91caWM1h4lvgbZW2HTzknmbMDAO7RVWmplRA95utw15UL4RKxVY0hdi2XRGvBdY1P 2r6x4cqwJVHvRa09sKYAm932FLLuYr3cuzAfMOsx8heF/GjwUaSzn+8EySgw8945rFGXEA mjqABGDLqLi9UdnTO+VKmmuiALCjNHaUUQG5tilrHh4f79Go1zaVSjeZjvR1xg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886844; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1p6M+HuhFutrVv6xarMScHVasdihs8aPDhQcOtKs0Y8=; b=Zq4hg45uWsKnwNdFk4opDhUwOHSqmSyRD5HRCj5o9c6NJB58Ds12XzEcHEu6N7Fwmat1Nu yl/gleBkobULV9Aw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 35/60] x86/apic: Allow apic::wait_icr_idle() to be NULL References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:24 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773027837154044006 X-GMAIL-MSGID: 1773027837154044006 Nuke more NOOP callbacks and make the invocation conditional. Will be replaced with a static call later. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 9 ++------- arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/apic_numachip.c | 7 ------- arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 1 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 - arch/x86/xen/apic.c | 5 ----- 7 files changed, 2 insertions(+), 24 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -206,12 +206,6 @@ static inline u32 native_apic_msr_read(u return (u32)msr; } -static inline void native_x2apic_wait_icr_idle(void) -{ - /* no need to wait for icr idle in x2apic */ - return; -} - static inline u32 native_safe_x2apic_wait_icr_idle(void) { /* no need to wait for icr idle in x2apic */ @@ -376,7 +370,8 @@ static inline void apic_icr_write(u32 lo static inline void apic_wait_icr_idle(void) { - apic->wait_icr_idle(); + if (apic->wait_icr_idle) + apic->wait_icr_idle(); } static inline u32 safe_apic_wait_icr_idle(void) --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -20,7 +20,6 @@ static void noop_send_IPI_mask_allbutsel static void noop_send_IPI_allbutself(int vector) { } static void noop_send_IPI_all(int vector) { } static void noop_send_IPI_self(int vector) { } -static void noop_apic_wait_icr_idle(void) { } static void noop_apic_icr_write(u32 low, u32 id) { } static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip) @@ -105,6 +104,5 @@ struct apic apic_noop __ro_after_init = .eoi_write = noop_apic_write, .icr_read = noop_apic_icr_read, .icr_write = noop_apic_icr_write, - .wait_icr_idle = noop_apic_wait_icr_idle, .safe_wait_icr_idle = noop_safe_apic_wait_icr_idle, }; --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -223,11 +223,6 @@ static int numachip2_acpi_madt_oem_check return 1; } -/* APIC IPIs are queued */ -static void numachip_apic_wait_icr_idle(void) -{ -} - /* APIC NMI IPIs are queued */ static u32 numachip_safe_apic_wait_icr_idle(void) { @@ -269,7 +264,6 @@ static const struct apic apic_numachip1 .eoi_write = native_apic_mem_write, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, - .wait_icr_idle = numachip_apic_wait_icr_idle, .safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle, }; @@ -310,7 +304,6 @@ static const struct apic apic_numachip2 .eoi_write = native_apic_mem_write, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, - .wait_icr_idle = numachip_apic_wait_icr_idle, .safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle, }; --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -266,7 +266,6 @@ static struct apic apic_x2apic_cluster _ .eoi_write = native_apic_msr_eoi_write, .icr_read = native_x2apic_icr_read, .icr_write = native_x2apic_icr_write, - .wait_icr_idle = native_x2apic_wait_icr_idle, .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, }; --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -180,7 +180,6 @@ static struct apic apic_x2apic_phys __ro .eoi_write = native_apic_msr_eoi_write, .icr_read = native_x2apic_icr_read, .icr_write = native_x2apic_icr_write, - .wait_icr_idle = native_x2apic_wait_icr_idle, .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, }; --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -854,7 +854,6 @@ static struct apic apic_x2apic_uv_x __ro .eoi_write = native_apic_msr_eoi_write, .icr_read = native_x2apic_icr_read, .icr_write = native_x2apic_icr_write, - .wait_icr_idle = native_x2apic_wait_icr_idle, .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, }; --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -120,10 +120,6 @@ static int xen_phys_pkg_id(int initial_a return initial_apic_id >> index_msb; } -static void xen_noop(void) -{ -} - static int xen_cpu_present_to_apicid(int cpu) { if (cpu_present(cpu)) @@ -165,7 +161,6 @@ static struct apic xen_pv_apic = { .icr_read = xen_apic_icr_read, .icr_write = xen_apic_icr_write, - .wait_icr_idle = xen_noop, .safe_wait_icr_idle = xen_safe_apic_wait_icr_idle, }; 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Will be replaced by a static_call_cond() later. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 8 +------- arch/x86/kernel/apic/apic_noop.c | 6 ------ arch/x86/kernel/apic/apic_numachip.c | 8 -------- arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 1 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 - arch/x86/xen/apic.c | 6 ------ 7 files changed, 1 insertion(+), 30 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -206,12 +206,6 @@ static inline u32 native_apic_msr_read(u return (u32)msr; } -static inline u32 native_safe_x2apic_wait_icr_idle(void) -{ - /* no need to wait for icr idle in x2apic */ - return 0; -} - static inline void native_x2apic_icr_write(u32 low, u32 id) { wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); @@ -376,7 +370,7 @@ static inline void apic_wait_icr_idle(vo static inline u32 safe_apic_wait_icr_idle(void) { - return apic->safe_wait_icr_idle(); + return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; } extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -27,11 +27,6 @@ static int noop_wakeup_secondary_cpu(int return -1; } -static u32 noop_safe_apic_wait_icr_idle(void) -{ - return 0; -} - static u64 noop_apic_icr_read(void) { return 0; @@ -104,5 +99,4 @@ struct apic apic_noop __ro_after_init = .eoi_write = noop_apic_write, .icr_read = noop_apic_icr_read, .icr_write = noop_apic_icr_write, - .safe_wait_icr_idle = noop_safe_apic_wait_icr_idle, }; --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -223,12 +223,6 @@ static int numachip2_acpi_madt_oem_check return 1; } -/* APIC NMI IPIs are queued */ -static u32 numachip_safe_apic_wait_icr_idle(void) -{ - return 0; -} - static const struct apic apic_numachip1 __refconst = { .name = "NumaConnect system", .probe = numachip1_probe, @@ -264,7 +258,6 @@ static const struct apic apic_numachip1 .eoi_write = native_apic_mem_write, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, - .safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle, }; apic_driver(apic_numachip1); @@ -304,7 +297,6 @@ static const struct apic apic_numachip2 .eoi_write = native_apic_mem_write, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, - .safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle, }; apic_driver(apic_numachip2); --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -266,7 +266,6 @@ static struct apic apic_x2apic_cluster _ .eoi_write = native_apic_msr_eoi_write, .icr_read = native_x2apic_icr_read, .icr_write = native_x2apic_icr_write, - .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, }; apic_driver(apic_x2apic_cluster); --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -180,7 +180,6 @@ static struct apic apic_x2apic_phys __ro .eoi_write = native_apic_msr_eoi_write, .icr_read = native_x2apic_icr_read, .icr_write = native_x2apic_icr_write, - .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, }; apic_driver(apic_x2apic_phys); --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -854,7 +854,6 @@ static struct apic apic_x2apic_uv_x __ro .eoi_write = native_apic_msr_eoi_write, .icr_read = native_x2apic_icr_read, .icr_write = native_x2apic_icr_write, - .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, }; #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -92,11 +92,6 @@ static void xen_apic_icr_write(u32 low, WARN_ON(1); } -static u32 xen_safe_apic_wait_icr_idle(void) -{ - return 0; -} - static int xen_apic_probe_pv(void) { if (xen_pv_domain()) @@ -161,7 +156,6 @@ static struct apic xen_pv_apic = { .icr_read = xen_apic_icr_read, .icr_write = xen_apic_icr_write, - .safe_wait_icr_idle = xen_safe_apic_wait_icr_idle, }; static void __init xen_apic_check(void) From patchwork Tue Aug 1 10:47:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129201 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2597235vqg; Tue, 1 Aug 2023 04:20:53 -0700 (PDT) X-Google-Smtp-Source: APBJJlGEDmE8FuBS4LdsNncKivEPJWQ5ysVsqB2MesluQp3Ci+R4TzKkEO4lwDwcNCmRDR9YQBVm X-Received: by 2002:a05:6358:93a7:b0:135:499a:382b with SMTP id h39-20020a05635893a700b00135499a382bmr4048537rwb.7.1690888853282; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u24-20020a634718000000b00563f7525babsi8739419pga.485.2023.08.01.04.20.38; Tue, 01 Aug 2023 04:20:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="2tYLp/t2"; dkim=neutral (no key) header.i=@linutronix.de header.b=ZFjhVtiU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232705AbjHAKuH (ORCPT + 99 others); Tue, 1 Aug 2023 06:50:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234193AbjHAKtO (ORCPT ); Tue, 1 Aug 2023 06:49:14 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 128E23C05 for ; Tue, 1 Aug 2023 03:47:48 -0700 (PDT) Message-ID: <20230801103817.187956642@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886847; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tVQYxJN/DzHFa1cx/oRePw+d48kC6weMnZb4I/fSkGc=; b=2tYLp/t2UyhnHHtnu2aHDW541zXYxsMkHL7UmkJTaBhen2bRbb9DqXFytrajVhjdJ+dYTz XTVWf00e2zb7D/wdf645k3UGCYORM2EqXPEtt92gZM6g9JwxnqC8crt8kwg3cBUPWQN5sb NnEJ5t8Vw4VdGkfdSyIdGDR9RZbRImdPK+nZupypa8xdN+iDZnzc3huN+r9b4M8srop8Zp jMELHncycE24lEOs66hoFDx3BxWo1LaDpEjbtacWZAL6yg8ft1fszMHGMXHLJKjuupXZWN 6lEUPrtVz5ESlQYwIE3ehF6xzFyNXcBxtV2dxr/nJ2hd3/oP1Vy7WMbVfsTvwQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886847; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tVQYxJN/DzHFa1cx/oRePw+d48kC6weMnZb4I/fSkGc=; b=ZFjhVtiU4ouN/nG4sLxGvjh3RhJYtwqWgBDECEnH1Hoht0TjXywlFUiK/dhcpNZaof+Xvy r4AkRnqUp+cN2qDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 37/60] x86/apic: Move safe wait_icr_idle() next to apic_mem_wait_icr_idle() References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:26 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025470105632431 X-GMAIL-MSGID: 1773025470105632431 Move it next to apic_mem_wait_icr_idle(), rename it so that it's clear what it does and rewrite it in readable form. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic.c | 17 ----------------- arch/x86/kernel/apic/apic_flat_64.c | 4 ++-- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/ipi.c | 19 +++++++++++++++++-- arch/x86/kernel/apic/local.h | 1 + arch/x86/kernel/apic/probe_32.c | 2 +- 7 files changed, 22 insertions(+), 24 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -98,7 +98,6 @@ static inline u32 native_apic_mem_read(u return *((volatile u32 *)(APIC_BASE + reg)); } -extern u32 native_safe_apic_wait_icr_idle(void); extern void native_apic_icr_write(u32 low, u32 id); extern u64 native_apic_icr_read(void); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -240,23 +240,6 @@ static void __init apic_disable(void) apic = &apic_noop; } -u32 native_safe_apic_wait_icr_idle(void) -{ - u32 send_status; - int timeout; - - timeout = 0; - do { - send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; - if (!send_status) - break; - inc_irq_stat(icr_read_retry_count); - udelay(100); - } while (timeout++ < 1000); - - return send_status; -} - void native_apic_icr_write(u32 low, u32 id) { unsigned long flags; --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -112,7 +112,7 @@ static struct apic apic_flat __ro_after_ .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, .wait_icr_idle = apic_mem_wait_icr_idle, - .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, + .safe_wait_icr_idle = apic_mem_wait_icr_idle_timeout, }; /* @@ -188,7 +188,7 @@ static struct apic apic_physflat __ro_af .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, .wait_icr_idle = apic_mem_wait_icr_idle, - .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, + .safe_wait_icr_idle = apic_mem_wait_icr_idle_timeout, }; /* --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -109,7 +109,7 @@ static struct apic apic_bigsmp __ro_afte .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, .wait_icr_idle = apic_mem_wait_icr_idle, - .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, + .safe_wait_icr_idle = apic_mem_wait_icr_idle_timeout, }; bool __init apic_bigsmp_possible(bool cmdline_override) --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include + #include #include "local.h" @@ -102,6 +104,19 @@ static inline int __prepare_ICR2(unsigne return SET_XAPIC_DEST_FIELD(mask); } +u32 apic_mem_wait_icr_idle_timeout(void) +{ + int cnt; + + for (cnt = 0; cnt < 1000; cnt++) { + if (!(apic_read(APIC_ICR) & APIC_ICR_BUSY)) + return 0; + inc_irq_stat(icr_read_retry_count); + udelay(100); + } + return APIC_ICR_BUSY; +} + void apic_mem_wait_icr_idle(void) { while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY) @@ -135,7 +150,7 @@ static void __default_send_IPI_shortcut( * to stop the others before launching the kdump kernel. */ if (unlikely(vector == NMI_VECTOR)) - safe_apic_wait_icr_idle(); + apic_mem_wait_icr_idle_timeout(); else apic_mem_wait_icr_idle(); @@ -152,7 +167,7 @@ void __default_send_IPI_dest_field(unsig { /* See comment in __default_send_IPI_shortcut() */ if (unlikely(vector == NMI_VECTOR)) - safe_apic_wait_icr_idle(); + apic_mem_wait_icr_idle_timeout(); else apic_mem_wait_icr_idle(); --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -45,6 +45,7 @@ static inline unsigned int __prepare_ICR void default_init_apic_ldr(void); void apic_mem_wait_icr_idle(void); +u32 apic_mem_wait_icr_idle_timeout(void); /* * This is used to send an IPI with no shorthand notation (the destination is --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -65,7 +65,7 @@ static struct apic apic_default __ro_aft .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, .wait_icr_idle = apic_mem_wait_icr_idle, - .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, + .safe_wait_icr_idle = apic_mem_wait_icr_idle_timeout, }; apic_driver(apic_default); From patchwork Tue Aug 1 10:47:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129212 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2599241vqg; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g19-20020a17090670d300b0099bd655b725si7254643ejk.781.2023.08.01.04.24.38; Tue, 01 Aug 2023 04:25:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=SG+X5mlb; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=yl1bJg4z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229800AbjHAKux (ORCPT + 99 others); Tue, 1 Aug 2023 06:50:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234164AbjHAKuO (ORCPT ); Tue, 1 Aug 2023 06:50:14 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8011A26A1 for ; Tue, 1 Aug 2023 03:48:14 -0700 (PDT) Message-ID: <20230801103817.241792953@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886848; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=uHpiyIwnqkWBnjjWfT4MmD20MOeZo84Wu6JyGvenGyY=; b=SG+X5mlbJnOXiGx2gZKqTfQbTRbSUmwaAgesSjIWvPs5MNKdilDh/shBuO47Zw+7hO6hUl M7jfGjKJwEr/ehNvq7wYpg3FpmCBGoKeOtw3XH767mpHyadAp1LDq/m4YDHUqAjEMBkQTO 1+hubfM4slz5vJSm1raxiYh4jCYnfk/y+Len0b8/qc1EHV98CTlxi/AYirRHk2EXIFIBGz 0Whf+DKmQ4nS6xHe4VBX5ceWy/tKQRS6C1f4rPWRiFWyluEEmZcCn/nHgjynojKnG/Qx9u EgGViXxgWd75A+P35JZyyIHMZ9pn/yGD35ZkE5jrE8hTd+UKtcc2I4q30D0BeQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886848; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=uHpiyIwnqkWBnjjWfT4MmD20MOeZo84Wu6JyGvenGyY=; b=yl1bJg4zPYMaPphoMzr1CrxxtVLFqsXQufoew48WbsOUkCoF0t+dHhkSu0wHIuylmTOWoL GvmAZ2tL4PbS7RBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 38/60] x86/apic/uv: Get rid of wrapper callbacks References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:28 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025731064607484 X-GMAIL-MSGID: 1773025731064607484 Why on earth makes a wrapper around some common function sense? Just to be able to slap some vendor name on it... Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/x2apic_uv_x.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -783,11 +783,6 @@ static int uv_apic_id_valid(u32 apicid) return 1; } -static u32 apic_uv_calc_apicid(unsigned int cpu) -{ - return apic_default_calc_apicid(cpu); -} - static unsigned int x2apic_get_apic_id(unsigned long id) { return id; @@ -838,7 +833,7 @@ static struct apic apic_x2apic_uv_x __ro .get_apic_id = x2apic_get_apic_id, .set_apic_id = set_apic_id, - .calc_dest_apicid = apic_uv_calc_apicid, + .calc_dest_apicid = apic_default_calc_apicid, .send_IPI = uv_send_IPI_one, .send_IPI_mask = uv_send_IPI_mask, From patchwork Tue Aug 1 10:47:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129191 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2595105vqg; Tue, 1 Aug 2023 04:16:23 -0700 (PDT) X-Google-Smtp-Source: APBJJlHd4gOOk76FHnAdu0Iug2sERP38j9+B0aNyzZphsxECyKxqnKSg/vM9c3jteqovHjwAvCI1 X-Received: by 2002:a05:6830:20cd:b0:6b8:9a3a:ea12 with SMTP id z13-20020a05683020cd00b006b89a3aea12mr12492812otq.12.1690888583150; Tue, 01 Aug 2023 04:16:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888583; cv=none; d=google.com; s=arc-20160816; b=LkNeKpsY5OwfpnCgJxeNZIko4Y9VMkYfyBMLiTW2vMNUqJiFOs0Q+Y0JmCUIHQTp5I xuEwDFE8u0ligG5m2UkICO6qCRhSgBwuI0f1VUsOcoEe8mq+7OAMlJwKN+d5CcD+LhRN MQoRbaznZ7Td09XBoAizPNdnazlD2RQ7LPF0p3DaRmXnKaRkxw0wH9KIr64wPUFAkOCZ zLK/YYbQ8ep6hK2euEtkWx8l9lSk/JKI7pq736PL1XPA33bUVYrrnhqzevzU7YIYNN/5 TtBVXYElRWW0+3PLANWGMPj1htijT8HX9VEK6bO6BjaG2H3X9CBsUs/74wWW+lJpHODg jHow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=wooQjfivjf9g/FihTIdSMalhuVeQoOiGD7tnhzUY+hw=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=WcZ4jE/GzPUaOFu5WC72Q6H1ToZZIPZr7zhbIC6MHJb1iNDVfL/epc2A9RSJByaKGY 2vlFdgW3z/nb+RoayT9KguoYQBJs6vJ5h+WEU4X8z0CBj8W8svjaHVRXaAabJRkzbNhJ p/H6ls6+bYs7u8sQVNl6iRgKPlOrgN7uxwE4t/7cyMEePesX0EvpVcAkhI3dEfAeS2hD W7yNLqkvYUqF7LlmvTxXtoSjrn48jOYwpIB+/D5vDlN6adxP1HYRF5JyE/fIUcr9McFx S9Ethghs4ou+w7VnHchsMGARls2P0EjuZOZlpBZgauCVgz/zCVna3FPaMiBLp8lskygF bLeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=aZMVEsQn; dkim=neutral (no key) header.i=@linutronix.de header.b=bt4kwNT1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k3-20020a633d03000000b0055b0f40083csi6300072pga.639.2023.08.01.04.16.10; Tue, 01 Aug 2023 04:16:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=aZMVEsQn; dkim=neutral (no key) header.i=@linutronix.de header.b=bt4kwNT1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230368AbjHAKuL (ORCPT + 99 others); Tue, 1 Aug 2023 06:50:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232371AbjHAKtU (ORCPT ); Tue, 1 Aug 2023 06:49:20 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 317433C0D for ; Tue, 1 Aug 2023 03:47:48 -0700 (PDT) Message-ID: <20230801103817.296447715@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886849; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wooQjfivjf9g/FihTIdSMalhuVeQoOiGD7tnhzUY+hw=; b=aZMVEsQnwUeSnkh3VigeEz8F/NRqHIMLDfx/0Xcd+osVj8LjHhsO0fQTcIV2HhkW9neJUw /x1sOaHluauJAyAGo3jzvxsqsp9n2VqSBnBD6ahE0v96VJqHQFjxHPbq+8920WZzqvGB3H Al+nRiqGHsfPh14kgzGT9KHRr1Ef7Sf19GOkJ6MrsQumBxLffMFrvJWDh4VXnNb97OLQiB wGJHvd39ekpHOKR2C3Y3T8gpeeoeGtMTRD9ODxB90D6CL39D2e/5SVLX0Jji6sBCsYMP13 Ry5vnbP9vq/d7LnBXT9hBWJOU1bGIuPC9u9NpAMPTBofRphbsPR0bTi/fr8rZQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886849; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wooQjfivjf9g/FihTIdSMalhuVeQoOiGD7tnhzUY+hw=; b=bt4kwNT1oOkLK1zjKsW9urasQSxfYeU3jB8JbSxNJrqcxYg44TjJdEo35ksNvIz+nJclyD xVTm3Q+MHB5V+cAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 39/60] x86/apic/x2apic: Share all common IPI functions References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:29 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025186959906646 X-GMAIL-MSGID: 1773025186959906646 Yet more copy and pasta gone. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/local.h | 4 ++- arch/x86/kernel/apic/x2apic_cluster.c | 10 ------- arch/x86/kernel/apic/x2apic_phys.c | 44 +++++++++++++++++----------------- arch/x86/kernel/apic/x2apic_uv_x.c | 14 ++-------- 4 files changed, 28 insertions(+), 44 deletions(-) --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -19,8 +19,10 @@ void __x2apic_send_IPI_dest(unsigned int unsigned int x2apic_get_apic_id(unsigned long id); u32 x2apic_set_apic_id(unsigned int id); int x2apic_phys_pkg_id(int initial_apicid, int index_msb); + +void x2apic_send_IPI_all(int vector); +void x2apic_send_IPI_allbutself(int vector); void x2apic_send_IPI_self(int vector); -void __x2apic_send_IPI_shorthand(int vector, u32 which); /* IPI */ --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -83,16 +83,6 @@ x2apic_send_IPI_mask_allbutself(const st __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); } -static void x2apic_send_IPI_allbutself(int vector) -{ - __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLBUT); -} - -static void x2apic_send_IPI_all(int vector) -{ - __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC); -} - static u32 x2apic_calc_apicid(unsigned int cpu) { return x86_cpu_to_logical_apicid[cpu]; --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -81,16 +81,36 @@ static void __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); } -static void x2apic_send_IPI_allbutself(int vector) +static void __x2apic_send_IPI_shorthand(int vector, u32 which) +{ + unsigned long cfg = __prepare_ICR(which, vector, 0); + + /* x2apic MSRs are special and need a special fence: */ + weak_wrmsr_fence(); + native_x2apic_icr_write(cfg, 0); +} + +void x2apic_send_IPI_allbutself(int vector) { __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLBUT); } -static void x2apic_send_IPI_all(int vector) +void x2apic_send_IPI_all(int vector) { __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC); } +void x2apic_send_IPI_self(int vector) +{ + apic_write(APIC_SELF_IPI, vector); +} + +void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest) +{ + unsigned long cfg = __prepare_ICR(0, vector, dest); + native_x2apic_icr_write(cfg, apicid); +} + static int x2apic_phys_probe(void) { if (!x2apic_mode) @@ -111,21 +131,6 @@ int x2apic_apic_id_valid(u32 apicid) return 1; } -void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest) -{ - unsigned long cfg = __prepare_ICR(0, vector, dest); - native_x2apic_icr_write(cfg, apicid); -} - -void __x2apic_send_IPI_shorthand(int vector, u32 which) -{ - unsigned long cfg = __prepare_ICR(which, vector, 0); - - /* x2apic MSRs are special and need a special fence: */ - weak_wrmsr_fence(); - native_x2apic_icr_write(cfg, 0); -} - unsigned int x2apic_get_apic_id(unsigned long id) { return id; @@ -141,11 +146,6 @@ int x2apic_phys_pkg_id(int initial_apici return initial_apicid >> index_msb; } -void x2apic_send_IPI_self(int vector) -{ - apic_write(APIC_SELF_IPI, vector); -} - static struct apic apic_x2apic_phys __ro_after_init = { .name = "physical x2apic", --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -25,6 +25,8 @@ #include #include +#include "local.h" + static enum uv_system_type uv_system_type; static int uv_hubbed_system; static int uv_hubless_system; @@ -783,11 +785,6 @@ static int uv_apic_id_valid(u32 apicid) return 1; } -static unsigned int x2apic_get_apic_id(unsigned long id) -{ - return id; -} - static u32 set_apic_id(unsigned int id) { return id; @@ -803,11 +800,6 @@ static int uv_phys_pkg_id(int initial_ap return uv_read_apic_id() >> index_msb; } -static void uv_send_IPI_self(int vector) -{ - apic_write(APIC_SELF_IPI, vector); -} - static int uv_probe(void) { return apic == &apic_x2apic_uv_x; @@ -840,7 +832,7 @@ static struct apic apic_x2apic_uv_x __ro .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, .send_IPI_allbutself = uv_send_IPI_allbutself, .send_IPI_all = uv_send_IPI_all, - .send_IPI_self = uv_send_IPI_self, + .send_IPI_self = x2apic_send_IPI_self, .wakeup_secondary_cpu = uv_wakeup_secondary, From patchwork Tue Aug 1 10:47:30 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id dv22-20020a170906b81600b00992f7e90360si9008878ejb.727.2023.08.01.04.10.14; Tue, 01 Aug 2023 04:10:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=LGMIkIAv; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=VfpDmiSX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232440AbjHAKuQ (ORCPT + 99 others); Tue, 1 Aug 2023 06:50:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232523AbjHAKtV (ORCPT ); Tue, 1 Aug 2023 06:49:21 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 274DDE67 for ; Tue, 1 Aug 2023 03:47:50 -0700 (PDT) Message-ID: <20230801103817.350848224@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886850; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=BfaXC6qRGr8XWK4LjXyteInjeXWpDiNfshAXINVsujg=; b=LGMIkIAvrUcgGmyBK8dkv3QdDQbOaE8cKvA9mptEdM2JBVCAWkUvvSu4fWPBSvvIUBTwRh JhnQFArWVYX2yJLApZHViro8ax+4P1SwvVqJRKAjNSP5GDg5rYTIbRet3TOS1MltkZSgWg IK+fvkLaqyN86b09eTmJHNjSRQg+3bH72MRXM8BhqGa1eARTdwfZYNCgBS/QgbWWdSsb0C uv5uaLNOGBClzwuYS8rx+Vkc8dorxpindSMZyKUQXXn2geOmH4jp+sbkrSlwyT5KuaMJmJ OMDY6b8NsjE+czFA9I5q+mqfq6z/koIugwxws6Ejf+1JAGYqldfh/lXQayYi0Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886850; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=BfaXC6qRGr8XWK4LjXyteInjeXWpDiNfshAXINVsujg=; b=VfpDmiSXSmVKPFo2gWjCj0HaHmiuqXoJG4PKmbCMgoDXyTCdTcAGGwlUt5WztHwkUl2AER zRYUgRH0nV4nosBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 40/60] x86/apic/64: Uncopypaste probing References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:30 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773024826278994841 X-GMAIL-MSGID: 1773024826278994841 No need for the same thing twice. Also prepares for simplifying the APIC ID validation checks. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/probe_64.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -13,6 +13,15 @@ #include "local.h" +static __init void apic_install_driver(struct apic *driver) +{ + if (apic == driver) + return; + + apic = driver; + pr_info("Switched APIC routing to %s:\n", apic->name); +} + /* Select the appropriate APIC driver */ void __init x86_64_probe_apic(void) { @@ -22,11 +31,7 @@ void __init x86_64_probe_apic(void) for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { if ((*drv)->probe && (*drv)->probe()) { - if (apic != *drv) { - apic = *drv; - pr_info("Switched APIC routing to %s.\n", - apic->name); - } + apic_install_driver(*drv); break; } } @@ -38,11 +43,7 @@ int __init default_acpi_madt_oem_check(c for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { if ((*drv)->acpi_madt_oem_check(oem_id, oem_table_id)) { - if (apic != *drv) { - apic = *drv; - pr_info("Setting APIC routing to %s.\n", - apic->name); - } + apic_install_driver(*drv); return 1; } } From patchwork Tue Aug 1 10:47:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129244 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2619599vqg; Tue, 1 Aug 2023 05:05:49 -0700 (PDT) X-Google-Smtp-Source: APBJJlFnjkElEAPwCCvBTtGK/WSg3hlf341GYSgS8HUKyGfzwtpNDdwEGNPwHER/I2dbUzQsh6Va X-Received: by 2002:a05:6a21:71c1:b0:13d:f217:d318 with SMTP id ay1-20020a056a2171c100b0013df217d318mr4949890pzc.49.1690891549112; Tue, 01 Aug 2023 05:05:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690891549; cv=none; d=google.com; s=arc-20160816; b=ljBDY2xup06/dJB87gU41kaDWIAnuiq7JNGKanKgjnDNBeadyFNX6pVzDiDQ33K7xG hDp8BsHZW8PuvJqPZtblalPfuMs+KWsxpVkCU4rs30MHzG/lHqTXGRCGtftRMVD+S69v UVHdku8PNZUu7UbN5DUBkTCaCluqLfVE45837AthAd2xzhsxE4x9WtEHzGvrWjTCYR7g M92o8lSXQrsqbxFcRaPjjzHm7w4NQy5e0vZxTNY4fzfiZlTwiQGg7WzbjZwcGnpyOxLn 2QaaFSzaa9FlulVw3JztTQHNpiRytrfsoeRG7XMfP6NBWfxtb0f/1Mk3RYbcTP5RstKv pNjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=TA8RTRP76/X19cT18S7neKhRCl/b+EEGzlCWZ6ao1A4=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=WWTPulHE40jUmpW/Nm8f+jztuQmih9KSFCx1I/VG71pvLgYk/L9WLmykyD1lxobRJm +oJQgHixJLh9ME2XUDFpAlf+LE5PWga0un+XKBAhaYbEpbAn0EwPZPOwetgZXMAAFFb9 Ms4Jx78g14yetkqseieL4zlbAQ6vFzKUOxfQ3SuDFvx3HGX+EfoX3Fsrh4lXfBja4YFK +hq7zAYhb2GFfBh3tBFVsOjxMUEoYog/htv35QZkggoi00TGuhlsB2crvC5KyqQOF191 VHD4eE05kiIkDMvKsczn090abZTSjuUkJuh421sS0pzz6fxcwxVZM+JgWxi09MB+kZxR 2MCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Q7HmM1Ta; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 5 +++++ arch/x86/kernel/acpi/boot.c | 2 +- arch/x86/kernel/apic/vector.c | 2 +- arch/x86/kernel/smpboot.c | 5 ++--- arch/x86/mm/srat.c | 5 ++--- 5 files changed, 11 insertions(+), 8 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -372,6 +372,11 @@ static inline u32 safe_apic_wait_icr_idl return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; } +static inline bool apic_id_valid(u32 apic_id) +{ + return apic->apic_id_valid(apic_id); +} + extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); #else /* CONFIG_X86_LOCAL_APIC */ --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -235,7 +235,7 @@ acpi_parse_x2apic(union acpi_subtable_he * to not preallocating memory for all NR_CPUS * when we use CPU hotplug. */ - if (!apic->apic_id_valid(apic_id)) { + if (!apic_id_valid(apic_id)) { if (enabled) pr_warn("x2apic entry ignored\n"); return 0; --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -680,7 +680,7 @@ static int x86_vector_select(struct irq_ * if IRQ remapping is enabled. APIC IDs above 15 bits are * only permitted if IRQ remapping is enabled, so check that. */ - if (apic->apic_id_valid(32768)) + if (apic_id_valid(32768)) return 0; return x86_fwspec_is_ioapic(fwspec) || x86_fwspec_is_hpet(fwspec); --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1064,9 +1064,8 @@ int native_kick_ap(unsigned int cpu, str pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); - if (apicid == BAD_APICID || - !physid_isset(apicid, phys_cpu_present_map) || - !apic->apic_id_valid(apicid)) { + if (apicid == BAD_APICID || !physid_isset(apicid, phys_cpu_present_map) || + !apic_id_valid(apicid)) { pr_err("%s: bad cpu %d\n", __func__, cpu); return -EINVAL; } --- a/arch/x86/mm/srat.c +++ b/arch/x86/mm/srat.c @@ -40,9 +40,8 @@ acpi_numa_x2apic_affinity_init(struct ac return; pxm = pa->proximity_domain; apic_id = pa->apic_id; - if (!apic->apic_id_valid(apic_id)) { - printk(KERN_INFO "SRAT: PXM %u -> X2APIC 0x%04x ignored\n", - pxm, apic_id); + if (!apic_id_valid(apic_id)) { + pr_info("SRAT: PXM %u -> X2APIC 0x%04x ignored\n", pxm, apic_id); return; } node = acpi_map_pxm_to_node(pxm); From patchwork Tue Aug 1 10:47:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129232 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2614445vqg; Tue, 1 Aug 2023 04:58:15 -0700 (PDT) X-Google-Smtp-Source: APBJJlHVgnk2cu35Sge+mt6sdRGVd6fBcXfuv0R7rVrZkOF65OMtv8YQWXdwfbLQo+urco/fkDth X-Received: by 2002:a17:90a:a683:b0:268:6339:318 with SMTP id d3-20020a17090aa68300b0026863390318mr11360916pjq.30.1690891095497; Tue, 01 Aug 2023 04:58:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690891095; cv=none; d=google.com; s=arc-20160816; b=mNdYS4HxyLdrkn9abVphXJBmLiHH8LnRBO/mm3tpCZu98LLqT1D5YsUP9eK26ejYJf 1FV5JxF4T/zBRYjizopqxBA4/rWhd1KgqujvL89YBRUHFcSAw6W5Mub+ASIukHEVsfaF O4o7z0vDmEvGk/I1DTuZVjpPw8EYC6pdP6mr3ejFCeXBEYmwVn3gOIHrB1wzRihdd96M 1EERYvilzb6crdY5A0ziog7KECbFxuZ2BC8F4RScotRlDhhRKkvsRDPeLFulGyPFQSUw yD3QUUJMPgXBCxl9xXLVop951d9mHrmqxUtZ+fdhrxAZyDyqJjREe7j9Q1M0Lkkvzq+c dguw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Lzl2By5b2bK0JPapjkW1rKVMFogh5AbCCARtLT2XDn0=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=MX+tY7Cn1QkWhglSNBgEiAIPpzVvMYb1+dQezdbHmc4M3s8sNqluIuOH2MjslGJeoo vFk3WIoZ2ODmwghv4zFDJDGVkUQid74bCiqtTmK4ZC6jG14DofD0mEq4EIeFfKQi8I/6 T9L0wJzQAE8Veqj6GnnA+gbH28TZTmdVOl+CUKNhLIS0bO2mtzEj6lgfGYEjPm1b9hFx yRo1qVb7bmvnkpE5aovob0LPdc9sXJFADNJ5rOzS5c/CmpY6K6t+4VTiJN2npaRLLZsl Isw0vgWJsSW90sFCvAZoh157Re0b4eWG0XNlpq/9cRqWpwwQ/wPthQN9aRVIYJBVn+4h pSNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=DzetJA3W; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=DnLW3vYs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v10-20020a17090abb8a00b00267a487f014si10616008pjr.167.2023.08.01.04.58.02; Tue, 01 Aug 2023 04:58:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=DzetJA3W; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=DnLW3vYs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232319AbjHAKuS (ORCPT + 99 others); Tue, 1 Aug 2023 06:50:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234022AbjHAKtW (ORCPT ); Tue, 1 Aug 2023 06:49:22 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25EC410E7 for ; Tue, 1 Aug 2023 03:47:51 -0700 (PDT) Message-ID: <20230801103817.458525669@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886853; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Lzl2By5b2bK0JPapjkW1rKVMFogh5AbCCARtLT2XDn0=; b=DzetJA3W1HEBXA5hGVb3XX2q6jioVDELhQiIR23XJrxR4A4NWNphcmwXk/0BjjlTDc5Bgk nwo3RzkAjpC7VtqqzhBq8pasoOGtzFAjZMb6TOneVrTTCbBqibMYBvULG5e+Xr4ltFCtSl nbTP5ntNmCQNOV9ICWm+/V7Z94Ayx5qntvVTFHzFIy37i2zGDeSTo9jh/tNmXaXWFAaM7V ASUGOUbW6fJIQk6x8UoSaHxSqxosW3QrAJbEVFzpZ2/e/n08ss95kt0uET6+2bjeCutqzA gaY4gSoTBUJfVmeKVOOCZjenhlcqldLxDhpDQ8QgKy8iglLhBORSbGxAtbYPFg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886853; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Lzl2By5b2bK0JPapjkW1rKVMFogh5AbCCARtLT2XDn0=; b=DnLW3vYsFNTccQ40XXTsgkQT70jWn0dUADS3MHdwaF/LRSta8t+aMojfpECIj0hbyF4otO 03zbru3EkMWRcJAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 42/60] x86/apic: Add max_apic_id member References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:33 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773027820901519133 X-GMAIL-MSGID: 1773027820901519133 There is really no point to have a callback which compares numbers. Add a field which allows each APIC to store the maximum APIC ID supported and fill it in for all APIC incarnations. The next step will remove the callback. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 3 +++ arch/x86/kernel/apic/apic_flat_64.c | 2 ++ arch/x86/kernel/apic/apic_noop.c | 1 + arch/x86/kernel/apic/apic_numachip.c | 2 ++ arch/x86/kernel/apic/bigsmp_32.c | 1 + arch/x86/kernel/apic/probe_32.c | 1 + arch/x86/kernel/apic/x2apic_cluster.c | 1 + arch/x86/kernel/apic/x2apic_phys.c | 1 + arch/x86/kernel/apic/x2apic_uv_x.c | 1 + arch/x86/xen/apic.c | 1 + 10 files changed, 14 insertions(+) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -277,6 +277,9 @@ struct apic { u64 (*icr_read)(void); void (*icr_write)(u32 low, u32 high); + /* The limit of the APIC ID space. */ + u32 max_apic_id; + /* Probe, setup and smpboot functions */ int (*probe)(void); int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -94,6 +94,7 @@ static struct apic apic_flat __ro_after_ .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = flat_phys_pkg_id, + .max_apic_id = 0xFE, .get_apic_id = flat_get_apic_id, .set_apic_id = set_apic_id, @@ -170,6 +171,7 @@ static struct apic apic_physflat __ro_af .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = flat_phys_pkg_id, + .max_apic_id = 0xFE, .get_apic_id = flat_get_apic_id, .set_apic_id = set_apic_id, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -80,6 +80,7 @@ struct apic apic_noop __ro_after_init = .phys_pkg_id = noop_phys_pkg_id, + .max_apic_id = 0xFE, .get_apic_id = noop_get_apic_id, .set_apic_id = NULL, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -239,6 +239,7 @@ static const struct apic apic_numachip1 .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = numachip_phys_pkg_id, + .max_apic_id = UINT_MAX, .get_apic_id = numachip1_get_apic_id, .set_apic_id = numachip1_set_apic_id, @@ -278,6 +279,7 @@ static const struct apic apic_numachip2 .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = numachip_phys_pkg_id, + .max_apic_id = UINT_MAX, .get_apic_id = numachip2_get_apic_id, .set_apic_id = numachip2_set_apic_id, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -91,6 +91,7 @@ static struct apic apic_bigsmp __ro_afte .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = bigsmp_phys_pkg_id, + .max_apic_id = 0xFE, .get_apic_id = bigsmp_get_apic_id, .set_apic_id = NULL, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -47,6 +47,7 @@ static struct apic apic_default __ro_aft .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = default_phys_pkg_id, + .max_apic_id = 0xFE, .get_apic_id = default_get_apic_id, .set_apic_id = NULL, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -239,6 +239,7 @@ static struct apic apic_x2apic_cluster _ .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = x2apic_phys_pkg_id, + .max_apic_id = UINT_MAX, .get_apic_id = x2apic_get_apic_id, .set_apic_id = x2apic_set_apic_id, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -163,6 +163,7 @@ static struct apic apic_x2apic_phys __ro .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = x2apic_phys_pkg_id, + .max_apic_id = UINT_MAX, .get_apic_id = x2apic_get_apic_id, .set_apic_id = x2apic_set_apic_id, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -822,6 +822,7 @@ static struct apic apic_x2apic_uv_x __ro .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = uv_phys_pkg_id, + .max_apic_id = UINT_MAX, .get_apic_id = x2apic_get_apic_id, .set_apic_id = set_apic_id, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -138,6 +138,7 @@ static struct apic xen_pv_apic = { .cpu_present_to_apicid = xen_cpu_present_to_apicid, .phys_pkg_id = xen_phys_pkg_id, /* detect_ht */ + .max_apic_id = UINT_MAX, .get_apic_id = xen_get_apic_id, .set_apic_id = xen_set_apic_id, /* Can be NULL on 32-bit. */ From patchwork Tue Aug 1 10:47:34 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n7-20020a170906688700b00992e14a3655si4814840ejr.354.2023.08.01.04.20.58; Tue, 01 Aug 2023 04:21:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ugunpQLe; dkim=neutral (no key) header.i=@linutronix.de header.b=xb6MTZPu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231392AbjHAKvG (ORCPT + 99 others); Tue, 1 Aug 2023 06:51:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234179AbjHAKuc (ORCPT ); Tue, 1 Aug 2023 06:50:32 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29D784493 for ; Tue, 1 Aug 2023 03:48:20 -0700 (PDT) Message-ID: <20230801103817.514745407@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886854; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1t5AYKxWBGS5UIcYUily8whdBGpo1cGe3a+nedmnJoI=; b=ugunpQLez4IeCETdM/Imk81NmZS2V0dcD8qWAefO7TK4zD85zEVcQLKuL+Vn4dK+1SO50Q TewwhywfWxpN9I3kA5XEWwyQc9G69vat6KZJTyAN3ZKJ3aVwypmiwqDv6I+aKRAwNzuFoT vgwPb/Su18S8uQi+yKYAPcOf0jk5JZ7KzXHtf3ukEhJ12SaBk5HKyy2OsFtI9o/j/Sc187 VNhjKyGGsFZjiHjSuF9jkIT06FfPqJ33krfUS/YXpX0Z12WLcIIm7o6ne1ox3546Eqw1Fi hvh89Y6L67BurfP9xX/I/eYeLisl7NlMYH4JjYUGcFhWaWLzZahHcoOzZxeJ9A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886854; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1t5AYKxWBGS5UIcYUily8whdBGpo1cGe3a+nedmnJoI=; b=xb6MTZPu1mNmqYhL1B9Gy9GjhJAaFQqS5QO9ZB8eOXXipUlU9C8QK6bK+4pTrWur2RVc3S jamES18/YJ9mWjAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 43/60] x86/apic: Simplify X2APIC ID validation References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:34 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025500067835402 X-GMAIL-MSGID: 1773025500067835402 No point in doing the zero equals unlimited check and if not zero compare against the real number. Unlimited is UINT_MAX. So initialize the variable with UINT_MAX and compare less than or equal. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/x2apic_phys.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -8,7 +8,7 @@ int x2apic_phys; static struct apic apic_x2apic_phys; -static u32 x2apic_max_apicid __ro_after_init; +static u32 x2apic_max_apicid __ro_after_init = UINT_MAX; void __init x2apic_set_max_apicid(u32 apicid) { @@ -125,10 +125,7 @@ static int x2apic_phys_probe(void) /* Common x2apic functions, also used by x2apic_cluster */ int x2apic_apic_id_valid(u32 apicid) { - if (x2apic_max_apicid && apicid > x2apic_max_apicid) - return 0; - - return 1; + return apicid <= x2apic_max_apicid; } unsigned int x2apic_get_apic_id(unsigned long id) From patchwork Tue Aug 1 10:47:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129199 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2596396vqg; Tue, 1 Aug 2023 04:19:01 -0700 (PDT) X-Google-Smtp-Source: APBJJlHkiNicEr5RRAH5EKTE/ZHpw1OezdazO4s5OUYNUsNK2pPe2Q3DcDsR9iLkFDDM/jXO4YPJ X-Received: by 2002:a05:6830:da:b0:6b9:8ff8:e87c with SMTP id x26-20020a05683000da00b006b98ff8e87cmr13451963oto.24.1690888741181; Tue, 01 Aug 2023 04:19:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888741; cv=none; d=google.com; s=arc-20160816; b=dNnsc2pnEQ/OM4CGO7gbWxHL5YWyRiJFIb5iDFjWgjipLQZDDYTHg1ofhMscq6V7oW vPpq4RuyUQ8uBSm7+wIm4DePNkJ1xyJ5wqQ8IK91BGVov76qAq+r4uAZb1qGFw06i9OJ 2zGNNdtIAIIWFk6XyIFdsEDHOPUCcFXD5hx1zEjA3We+uM0lgjVVc4fLkjckPY5kMKmq RAnQqL+/DLMHRTp5prnE5suvGRo3E4w5KGcNo8cKmwKbQV1lolgf3dkSGny4fpU6FQ3F gA1BCPQGa59outCfzjQNn9BBN05HQaHRcWYAXrEi1OsYAvq78XHTBiQsEQCruBp6fsiP jN+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=szXoVyIugEhLQoBNKHeoJc9xg6are8RXmgk50QQTfEQ=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=Q+agqeg9n9yCvXFRI1nMDDgIi7Qo417B+3KXMVoqUNsfAqOgNSWIMr2TlD2Tsduwd0 ZjLQdp7HfQ3IRzFJ9hzR3TdJ87LZa57gVpPh1bTnCnQdhdZWEMRIXu7NzQJ1LN+9GCml 6/nPvETMWvzXFvIw4108cKiauCKBwDSaQEavsfGA+MSGFP5znNQhKhx8JavqNoykHbt3 kV0jP70efdhhIZkvn5ZRlWKd6hiQCM6JgBlvxD6NxlFjsG/F5nYnNj1iK25oMLSflnqF wgO/uEhhOn5297Qow33I38wQY0z7ACuNMUbijGkgYDuumxz84ybN8VONrOtX5HCgRU9u VLmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=bIBHaPcr; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l70-20020a639149000000b0056422e66789si5294302pge.136.2023.08.01.04.18.48; Tue, 01 Aug 2023 04:19:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=bIBHaPcr; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234086AbjHAKuV (ORCPT + 99 others); Tue, 1 Aug 2023 06:50:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232344AbjHAKtY (ORCPT ); Tue, 1 Aug 2023 06:49:24 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 293241BC1 for ; Tue, 1 Aug 2023 03:47:53 -0700 (PDT) Message-ID: <20230801103817.570055901@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886855; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=szXoVyIugEhLQoBNKHeoJc9xg6are8RXmgk50QQTfEQ=; b=bIBHaPcrmwpbzik4I7YAcB55JTzRt4OeY4DMuTb+rG1cn85y2OIsVJ/3ihFBtyyHIyX94Q fd+dbKdrdan30Sw55iXqS7qRUyrPRitGVwzxNfFbbPQ1eewKo9mFlT8RgBkkqb/txRtj77 lGujMDefaJYV3Pd1uZyRrDBoJ22TMbfDcNZE565md7fkC+cUNqsjubIIDHqoPhIcQpw98T /u7/IiGJyL17Mrzwe3+HkPqDV4qpdLflIX4sr63Lo3vrzeC4Ti4xnL6AMeRhtMp2ZLqFT5 OaTspxgE0GTbFv2jQuFTafyVjHVb84dvqko0hWwWnsp81cPI5L2ilYG4Uli2OA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886855; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=szXoVyIugEhLQoBNKHeoJc9xg6are8RXmgk50QQTfEQ=; b=otAaf0yDhNlcjwStZ9UGk+J/9gP7fhcbfA3ehDFdfE2zW4JZbBNioOgTGxzS0PYxfDCSjP +hw05cRjidMCoIAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 44/60] x86/apic: Prepare x2APIC for using apic::max_apic_id References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:35 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025352548489692 X-GMAIL-MSGID: 1773025352548489692 In order to remove the apic::apic_id_valid() callback and switch to checking apic::max_apic_id, it is required to update apic::max_apic_id when the APIC initialization code overrides it via x2apic_set_max_apicid(). Make the existing booleans a bitfield and add a flag which lets the update function and the core code which switches the driver detect whether the apic instance wants to have that update or not and apply it if required. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 7 ++++--- arch/x86/kernel/apic/local.h | 1 + arch/x86/kernel/apic/probe_64.c | 4 ++++ arch/x86/kernel/apic/x2apic_cluster.c | 1 + arch/x86/kernel/apic/x2apic_phys.c | 5 ++++- 5 files changed, 14 insertions(+), 4 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -266,10 +266,11 @@ struct apic { void (*send_IPI_all)(int vector); void (*send_IPI_self)(int vector); - u32 disable_esr; - enum apic_delivery_modes delivery_mode; - bool dest_mode_logical; + + u32 disable_esr : 1, + dest_mode_logical : 1, + x2apic_set_max_apicid : 1; u32 (*calc_dest_apicid)(unsigned int cpu); --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -23,6 +23,7 @@ int x2apic_phys_pkg_id(int initial_apici void x2apic_send_IPI_all(int vector); void x2apic_send_IPI_allbutself(int vector); void x2apic_send_IPI_self(int vector); +extern u32 x2apic_max_apicid; /* IPI */ --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -19,6 +19,10 @@ static __init void apic_install_driver(s return; apic = driver; + + if (IS_ENABLED(CONFIG_X86_X2APIC) && apic->x2apic_set_max_apicid) + apic->max_apic_id = x2apic_max_apicid; + pr_info("Switched APIC routing to %s:\n", apic->name); } --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -240,6 +240,7 @@ static struct apic apic_x2apic_cluster _ .phys_pkg_id = x2apic_phys_pkg_id, .max_apic_id = UINT_MAX, + .x2apic_set_max_apicid = true, .get_apic_id = x2apic_get_apic_id, .set_apic_id = x2apic_set_apic_id, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -8,11 +8,13 @@ int x2apic_phys; static struct apic apic_x2apic_phys; -static u32 x2apic_max_apicid __ro_after_init = UINT_MAX; +u32 x2apic_max_apicid __ro_after_init = UINT_MAX; void __init x2apic_set_max_apicid(u32 apicid) { x2apic_max_apicid = apicid; + if (apic->x2apic_set_max_apicid) + apic->max_apic_id = apicid; } static int __init set_x2apic_phys_mode(char *arg) @@ -161,6 +163,7 @@ static struct apic apic_x2apic_phys __ro .phys_pkg_id = x2apic_phys_pkg_id, .max_apic_id = UINT_MAX, + .x2apic_set_max_apicid = true, .get_apic_id = x2apic_get_apic_id, .set_apic_id = x2apic_set_apic_id, From patchwork Tue Aug 1 10:47:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129188 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2594609vqg; Tue, 1 Aug 2023 04:15:24 -0700 (PDT) X-Google-Smtp-Source: APBJJlH6xqWU/b4IXjYEzlu/tBU6EqVgc5dzLAtVfgbVvyU1aPIpCzyVvc/lY1tTFnWpH22B2ggW X-Received: by 2002:a17:90a:eb12:b0:268:2d92:55d3 with SMTP id j18-20020a17090aeb1200b002682d9255d3mr11038621pjz.39.1690888524443; Tue, 01 Aug 2023 04:15:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888524; cv=none; d=google.com; s=arc-20160816; b=Lt9AOs2iMSj6GwAid111P1jaqXjwFh93G3lwzRQ/w83LcKqEhtTtmFQu0esltS62fj gT3b4hpo1ysgXGmgnBCSrswfUwWjuXpEshdwOY4j5jZpQNd7KLrlsKZOFIR4+brA+2Cu etGPb0QDCIY3Fpdlgsig3t68wsT3NPnylSMHpQTI282rFi5NaUZXRNpZC+l4eJoQ9t0U HB33GfzOgOIi5gz1BepWHa9ezeHBWx6DRfTT/K2e0pEJifDPw5DfuhNcjsWTAkhbB1Fh gcwcKpaBiId8HhGFxKdBU5/HLe3PUOZItwrMImaBfaQnIbO4qVQ2GiTYbnXvKJuWHmGD K+ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=5u62JLRIdL35F8zaoRJUG8h+QUZ60VbjH6N1PcWK5uo=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=KJrnzD5JDB4OujJbQWbShuI/My6VVLU206MscwEVf/GmyiCKFn1SGX5QdjEgfJqTb6 YcJkLtdxMqc+N7jqNuJQ4H+mbkZ2zLrKvUE75XLLvsWXoK4rQtkmAUgVPx/TI1CcNGN2 bmiHqhjk7ZfKx4SGFGeaGf/Q/D5DzAXhkPcLazrNJBb4LXqBgrQWxYH5529o+Xso5hiB 7EFbD6/GM3uuKBnWXHru8clpns618j4Jg6I11cPuOGeiuXaBXdAg9sFCiSKPz6tdlyFm NJDo3B5Keg947K+nOp9n8j2D80HVB2fCIzw2HcAL4qZpxp0xiMcV/+pzOwPcrZiKBMN/ xzDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=u6ZY9bJr; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=QqarhKiZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id lt6-20020a17090b354600b002681f2a2c9esi8900378pjb.159.2023.08.01.04.15.11; Tue, 01 Aug 2023 04:15:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=u6ZY9bJr; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=QqarhKiZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234116AbjHAKu3 (ORCPT + 99 others); Tue, 1 Aug 2023 06:50:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234017AbjHAKtm (ORCPT ); Tue, 1 Aug 2023 06:49:42 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B37083C13 for ; Tue, 1 Aug 2023 03:47:59 -0700 (PDT) Message-ID: <20230801103817.624346203@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886857; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5u62JLRIdL35F8zaoRJUG8h+QUZ60VbjH6N1PcWK5uo=; b=u6ZY9bJrRSQ+k4bJFdZ6OVvjPiJhlQmi3Lr06wKnKrLkURdz73x6LHHg+S1s+iR21/6rKY 548MTrfGULtmX7NtLYwg6ligD1RZu9piCe3nxAKpmzuw8B3dztSiykcGC1dSU4YvEjJnZF deK8o4OtzbuVkiroWJ9NOMkgWlcsb2jCJImbOoaek5606csuk4ebCRVYqNsZn8WpXZ/A1v mUh0hDMt/tScqK8Zj1uj+e4quo2Ohp8TCEglDkpVxZUbttZ4OIRIuX+RCqXLKh/NhlRtNZ jSOlO+HKIEdAzoDlqyoP/aX3tNqzG65drbylg2MOm/p5A3N9fX7m1SAwZUi8CQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886857; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5u62JLRIdL35F8zaoRJUG8h+QUZ60VbjH6N1PcWK5uo=; b=QqarhKiZOM+665TtSZ3t7LC/Sdx7v610CwwNN3Vd7dXZ64y44nleO0E81WTU3V9Ssgd1Fl GskgHNGDVt8zaRDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 45/60] x86/apic: Sanitize APID ID range validation References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:36 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025125545078910 X-GMAIL-MSGID: 1773025125545078910 Now that everything has apic::max_apic_id set and the eventual update for the x2APIC case is in place, switch the apic_id_valid() helper to use apic::max_apic_id and remove the apic::apic_id_valid() callback. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 3 +-- arch/x86/kernel/apic/apic_common.c | 5 ----- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/apic_numachip.c | 8 -------- arch/x86/kernel/apic/bigsmp_32.c | 1 - arch/x86/kernel/apic/local.h | 1 - arch/x86/kernel/apic/probe_32.c | 1 - arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 7 ------- arch/x86/kernel/apic/x2apic_uv_x.c | 6 ------ arch/x86/xen/apic.c | 6 ------ 12 files changed, 1 insertion(+), 42 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -284,7 +284,6 @@ struct apic { /* Probe, setup and smpboot functions */ int (*probe)(void); int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); - int (*apic_id_valid)(u32 apicid); bool (*apic_id_registered)(void); bool (*check_apicid_used)(physid_mask_t *map, int apicid); @@ -378,7 +377,7 @@ static inline u32 safe_apic_wait_icr_idl static inline bool apic_id_valid(u32 apic_id) { - return apic->apic_id_valid(apic_id); + return apic_id <= apic->max_apic_id; } extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -37,11 +37,6 @@ int default_cpu_present_to_apicid(int mp } EXPORT_SYMBOL_GPL(default_cpu_present_to_apicid); -int default_apic_id_valid(u32 apicid) -{ - return (apicid < 255); -} - bool default_apic_id_registered(void) { return physid_isset(read_apic_id(), phys_cpu_present_map); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -80,7 +80,6 @@ static struct apic apic_flat __ro_after_ .name = "flat", .probe = flat_probe, .acpi_madt_oem_check = flat_acpi_madt_oem_check, - .apic_id_valid = default_apic_id_valid, .apic_id_registered = default_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, @@ -158,7 +157,6 @@ static struct apic apic_physflat __ro_af .name = "physical flat", .probe = physflat_probe, .acpi_madt_oem_check = physflat_acpi_madt_oem_check, - .apic_id_valid = default_apic_id_valid, .apic_id_registered = default_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -67,8 +67,6 @@ struct apic apic_noop __ro_after_init = .probe = noop_probe, .acpi_madt_oem_check = NULL, - .apic_id_valid = default_apic_id_valid, - .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = true, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -56,12 +56,6 @@ static u32 numachip2_set_apic_id(unsigne return id << 24; } -static int numachip_apic_id_valid(u32 apicid) -{ - /* Trust what bootloader passes in MADT */ - return 1; -} - static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; @@ -227,7 +221,6 @@ static const struct apic apic_numachip1 .name = "NumaConnect system", .probe = numachip1_probe, .acpi_madt_oem_check = numachip1_acpi_madt_oem_check, - .apic_id_valid = numachip_apic_id_valid, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, @@ -267,7 +260,6 @@ static const struct apic apic_numachip2 .name = "NumaConnect2 system", .probe = numachip2_probe, .acpi_madt_oem_check = numachip2_acpi_madt_oem_check, - .apic_id_valid = numachip_apic_id_valid, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -79,7 +79,6 @@ static struct apic apic_bigsmp __ro_afte .name = "bigsmp", .probe = probe_bigsmp, - .apic_id_valid = default_apic_id_valid, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -14,7 +14,6 @@ #include /* X2APIC */ -int x2apic_apic_id_valid(u32 apicid); void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest); unsigned int x2apic_get_apic_id(unsigned long id); u32 x2apic_set_apic_id(unsigned int id); --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -33,7 +33,6 @@ static struct apic apic_default __ro_aft .name = "default", .probe = probe_default, - .apic_id_valid = default_apic_id_valid, .apic_id_registered = default_apic_id_registered, .delivery_mode = APIC_DELIVERY_MODE_FIXED, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -226,7 +226,6 @@ static struct apic apic_x2apic_cluster _ .name = "cluster x2apic", .probe = x2apic_cluster_probe, .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, - .apic_id_valid = x2apic_apic_id_valid, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = true, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -124,12 +124,6 @@ static int x2apic_phys_probe(void) return apic == &apic_x2apic_phys; } -/* Common x2apic functions, also used by x2apic_cluster */ -int x2apic_apic_id_valid(u32 apicid) -{ - return apicid <= x2apic_max_apicid; -} - unsigned int x2apic_get_apic_id(unsigned long id) { return id; @@ -150,7 +144,6 @@ static struct apic apic_x2apic_phys __ro .name = "physical x2apic", .probe = x2apic_phys_probe, .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, - .apic_id_valid = x2apic_apic_id_valid, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -780,11 +780,6 @@ static void uv_send_IPI_all(int vector) uv_send_IPI_mask(cpu_online_mask, vector); } -static int uv_apic_id_valid(u32 apicid) -{ - return 1; -} - static u32 set_apic_id(unsigned int id) { return id; @@ -810,7 +805,6 @@ static struct apic apic_x2apic_uv_x __ro .name = "UV large system", .probe = uv_probe, .acpi_madt_oem_check = uv_acpi_madt_oem_check, - .apic_id_valid = uv_apic_id_valid, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = false, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -105,11 +105,6 @@ static int xen_madt_oem_check(char *oem_ return xen_pv_domain(); } -static int xen_id_always_valid(u32 apicid) -{ - return 1; -} - static int xen_phys_pkg_id(int initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; @@ -127,7 +122,6 @@ static struct apic xen_pv_apic = { .name = "Xen PV", .probe = xen_apic_probe_pv, .acpi_madt_oem_check = xen_madt_oem_check, - .apic_id_valid = xen_id_always_valid, /* .delivery_mode and .dest_mode_logical not used by XENPV */ From patchwork Tue Aug 1 10:47:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129220 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2602656vqg; Tue, 1 Aug 2023 04:31:43 -0700 (PDT) X-Google-Smtp-Source: APBJJlEFDfLJD/zT72Wi7hvo1sRDCCBptT5o3Rrtxi21b7pTT41eRmMwlCTsephDBaYCTIf8PEL6 X-Received: by 2002:a17:902:f80d:b0:1b9:e8e4:620e with SMTP id ix13-20020a170902f80d00b001b9e8e4620emr8805635plb.47.1690889503325; Tue, 01 Aug 2023 04:31:43 -0700 (PDT) ARC-Seal: i=1; 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Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/apic_numachip.c | 4 ---- arch/x86/kernel/apic/probe_32.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 2 -- arch/x86/kernel/apic/x2apic_uv_x.c | 2 -- 6 files changed, 13 deletions(-) --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -87,9 +87,7 @@ static struct apic apic_flat __ro_after_ .disable_esr = 0, - .check_apicid_used = NULL, .init_apic_ldr = default_init_apic_ldr, - .ioapic_phys_id_map = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = flat_phys_pkg_id, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -65,7 +65,6 @@ static void noop_apic_write(u32 reg, u32 struct apic apic_noop __ro_after_init = { .name = "noop", .probe = noop_probe, - .acpi_madt_oem_check = NULL, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = true, @@ -80,7 +79,6 @@ struct apic apic_noop __ro_after_init = .max_apic_id = 0xFE, .get_apic_id = noop_get_apic_id, - .set_apic_id = NULL, .calc_dest_apicid = apic_flat_calc_apicid, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -227,8 +227,6 @@ static const struct apic apic_numachip1 .disable_esr = 0, - .check_apicid_used = NULL, - .ioapic_phys_id_map = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = numachip_phys_pkg_id, @@ -266,8 +264,6 @@ static const struct apic apic_numachip2 .disable_esr = 0, - .check_apicid_used = NULL, - .ioapic_phys_id_map = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = numachip_phys_pkg_id, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -48,7 +48,6 @@ static struct apic apic_default __ro_aft .max_apic_id = 0xFE, .get_apic_id = default_get_apic_id, - .set_apic_id = NULL, .calc_dest_apicid = apic_flat_calc_apicid, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -150,8 +150,6 @@ static struct apic apic_x2apic_phys __ro .disable_esr = 0, - .check_apicid_used = NULL, - .ioapic_phys_id_map = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = x2apic_phys_pkg_id, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -811,8 +811,6 @@ static struct apic apic_x2apic_uv_x __ro .disable_esr = 0, - .check_apicid_used = NULL, - .ioapic_phys_id_map = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .phys_pkg_id = uv_phys_pkg_id, From patchwork Tue Aug 1 10:47:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129207 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2598080vqg; Tue, 1 Aug 2023 04:22:33 -0700 (PDT) X-Google-Smtp-Source: APBJJlGoryOF8YcJv8VNlE+x3hcvyT/GamsWGfAJZ6qfDyahrUHfUqRmwvojFE5aItMoYIoeXSds X-Received: by 2002:a17:907:75e7:b0:99b:40b5:1c3b with SMTP id jz7-20020a17090775e700b0099b40b51c3bmr2127574ejc.57.1690888953643; Tue, 01 Aug 2023 04:22:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888953; cv=none; d=google.com; s=arc-20160816; b=JOxRiKuF72Bdid3ndSGWBvEK+/13je6sCNoULkOz/NMcjO8qIY46FDXeRC1s3ayKov hTEV4OHJcD0HXoygzSZbu8KOSp2ijO5SCN1K6Sl7VwwQECsaOpkvQF3g4tGQxjbppRp+ SFvDxjXN+lOTp/f/97iy+/EAtMciVbVCGnKqoOyCJbAUJdCVS/Be7JWK+fhIS3h4i1cx 8cnwjn5wcgzS5StrZaAcWYFSzRZ3tHoMzpqggcc0gLzJpKfn3ZBcMyvY92GD4LFYrKp7 eyNqQBC1lJnTTOJ8ltHU9nvOtfs3jWFIBgL1KE1wcHerB/gOxod9UPpHmYxUirNjUhAV DBXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=QxJCd5EJ/bsG/9bO98P8hnP2UT09lEdt9hSBI73j59Y=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=adOs6R4VBXhtkQIO/kN/MrTPrOPdudLE9rSMVPFbqgl4O61pFuUuWc8M3xDXVWG3qP e0/Gtl6e9NOGpyXl+TwP6OdvXc6zTcqEeH3vVUwJ65MC0830u2BQX2HgepG49YkGWKtL PkLITLRzsMqTvKG/NZCDTEtM5BiaYN7hzcc2B1UtijIOGXeO4YH3Q6WRYGxW8ono3469 UgbjBwIOqPWaFmD1YuxD37mXWbkbQZTM2s1d3dspJHXrxP+4EkD1NZ+o/KZ4eMmDnfbm BZLJ+xwM+fzRFJ4pWMudjY0dyQlXh0KUrjHDePbGf96HJQQcTsbiWPjMEV3y+1vCjXBq Ao6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="xp5095/w"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=haGigiuL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u27-20020a1709063b9b00b00992a096678fsi8212330ejf.813.2023.08.01.04.22.09; Tue, 01 Aug 2023 04:22:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="xp5095/w"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=haGigiuL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233427AbjHAKuc (ORCPT + 99 others); Tue, 1 Aug 2023 06:50:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234139AbjHAKto (ORCPT ); Tue, 1 Aug 2023 06:49:44 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75BCD3C20 for ; Tue, 1 Aug 2023 03:48:02 -0700 (PDT) Message-ID: <20230801103817.732266247@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886859; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=QxJCd5EJ/bsG/9bO98P8hnP2UT09lEdt9hSBI73j59Y=; b=xp5095/wWIPT22pF6/LFAAyotE258cjR4zwJfjj/YUVo006GYifD3GnBpYK2zCoNcEioeK yZJn5e1UgrIrmYAz4xZluJAHEuh6PF9+PEUZPZXQBJoCKApm8waL8JhmzzFEKmI5FmRxLo 3pNE94sx9L9vfL5h21rWJhrbS2oAOhBprpZsbHSSUdz+qPmk20ibMJ037cFQTOMLNh2mNV JYp1C5E5XCUuDiKB1JMmFQ9pxdhyseH75TzHcciDYP474DanCCeDmva/LhW8JDZSlnihnd bGki4HiVMS3Oyram5TtD7ijnnJG08b+Q58QdC1YlomvtH7fjdPG5x8f19QjKsA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886859; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=QxJCd5EJ/bsG/9bO98P8hnP2UT09lEdt9hSBI73j59Y=; b=haGigiuLETeD/qzVpJCPStVNkd4JV8b1h/TNTLf4Ov9dTqFKxI/o7eQZjvBV5/URgSTALs 1XF7SaLGCcXRpFAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 47/60] x86/apic/noop: Tidy up the code References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:39 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025575558350602 X-GMAIL-MSGID: 1773025575558350602 First of all apic_noop can't be probed because it's not registered. So there is no point for implementing a probe callback. The machine is rightfully to die when that is invoked. Remove the gunk and tidy up the other space consuming dummy callbacks. This gunk should simply die. Nothing should ever invoke APIC callbacks once this is installed, But that's a differrent story for another round of cleanups. The comment on top of this file which was intentionally left in place tells exactly why this is needed: voodoo programming. In fact the kernel of today should just outright refuse to boot on a system with no (functional) local APIC. That would spare tons of #ifdeffery and other nonsense. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic_noop.c | 38 ++++++++------------------------------ 1 file changed, 8 insertions(+), 30 deletions(-) --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -8,6 +8,10 @@ * Though in case if apic is disabled (for some reason) we try * to not uglify the caller's code and allow to call (some) apic routines * like self-ipi, etc... + * + * FIXME: Remove this gunk. The above argument which was intentionally left + * in place is silly to begin with because none of the callbacks except for + * APIC::read/write() have a WARN_ON_ONCE() in them. Sigh... */ #include #include @@ -21,35 +25,10 @@ static void noop_send_IPI_allbutself(int static void noop_send_IPI_all(int vector) { } static void noop_send_IPI_self(int vector) { } static void noop_apic_icr_write(u32 low, u32 id) { } - -static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip) -{ - return -1; -} - -static u64 noop_apic_icr_read(void) -{ - return 0; -} - -static int noop_phys_pkg_id(int cpuid_apic, int index_msb) -{ - return 0; -} - -static unsigned int noop_get_apic_id(unsigned long x) -{ - return 0; -} - -static int noop_probe(void) -{ - /* - * NOOP apic should not ever be - * enabled via probe routine - */ - return 0; -} +static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip) { return -1; } +static u64 noop_apic_icr_read(void) { return 0; } +static int noop_phys_pkg_id(int cpuid_apic, int index_msb) { return 0; } +static unsigned int noop_get_apic_id(unsigned long x) { return 0; } static u32 noop_apic_read(u32 reg) { @@ -64,7 +43,6 @@ static void noop_apic_write(u32 reg, u32 struct apic apic_noop __ro_after_init = { .name = "noop", - .probe = noop_probe, .delivery_mode = APIC_DELIVERY_MODE_FIXED, .dest_mode_logical = true, From patchwork Tue Aug 1 10:47:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129196 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2595952vqg; Tue, 1 Aug 2023 04:18:07 -0700 (PDT) X-Google-Smtp-Source: APBJJlFdrNXdkTOv1em5t4/S0psvYjhlMXQ3q9R1Z34pZ3qNW+bh087n775iaxMCCGXcTsOSW9w3 X-Received: by 2002:a17:903:245:b0:1b8:abe7:5a80 with SMTP id j5-20020a170903024500b001b8abe75a80mr14745155plh.40.1690888687654; Tue, 01 Aug 2023 04:18:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888687; cv=none; d=google.com; s=arc-20160816; b=Yd+I8IEcnseeIgdlwvGrBPCsga6KZLtovsgS9Z0r0+i/32yGf18XBANKNwX280Z2Ek KPmZa8zLBldLwWvb2YQ+TFhzBsgJVpjBcuGFX4IlrQhughbgNUnEt9a747GegIdqR2Kc luSV7Z0mO/WatkkCsP9DGpUoQxmtIQK/aztpKp+fjin8P1vwBF/7lHujuHOMnpMFh5lS 4jyOQBgOxFZija9yCaaSk6/FeE2YP3B2z/x7uT7h4oFM4h2iomG9PaBBsCLcn62kuj/M 3lxNjpHY+DKApG/AF5VIEwCigJstNhHmQ/DtRPG/1w95wB1Mrmi9b554k0RNNKK68AlN TW0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=dj21GG+2OIX1Rs+wEX+47dOzfVF0PHc+KOqDglhdL7U=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=QKm9alcbOQCt8Hn9YILfFyxbcymH/beQVtQ2R/Conf9/KpJq1JW6Dy7RzBSG4M7h2R TtGfCRMAcpi82pAOURPSVF8NvvGEAVjCkYJD/CMf/p6GgA57fsNk04Azx3fFFOKEzq/Q qD5vdewBpsV/o3983pbcMtWjJSfIa3eMhuY8tV+8z6bkV5YKlomQuSQ2Jt9dBpxCU3RF TgpooX27UFdmMUNHLvB+PowAcPlqUPerfZ6X+j861GAX4HBKmOzPMfzQ776ZJnvHKJdy Gr4elXzZyUv9ga2kt2PkLiYVu9yiUrSuJXt/5Cji/hg8GThdkZ3mdGyml7uLIgqJ85ZN vT3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=XdQE6Zsn; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="/rYxxnBn"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Use the constants in the eoi() callbacks and remove the arguments. Signed-off-by: Thomas Gleixner Reviewed-by: Wei Liu Acked-by: Peter Zijlstra (Intel) --- arch/x86/hyperv/hv_apic.c | 6 +++--- arch/x86/include/asm/apic.h | 17 +++++++++++------ arch/x86/kernel/apic/apic.c | 8 ++++---- arch/x86/kernel/apic/apic_flat_64.c | 4 ++-- arch/x86/kernel/apic/apic_noop.c | 3 ++- arch/x86/kernel/apic/apic_numachip.c | 4 ++-- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/probe_32.c | 2 +- arch/x86/kernel/apic/x2apic_cluster.c | 2 +- arch/x86/kernel/apic/x2apic_phys.c | 2 +- arch/x86/kernel/apic/x2apic_uv_x.c | 2 +- arch/x86/kernel/kvm.c | 6 +++--- arch/x86/xen/apic.c | 7 ++++++- 13 files changed, 38 insertions(+), 27 deletions(-) --- a/arch/x86/hyperv/hv_apic.c +++ b/arch/x86/hyperv/hv_apic.c @@ -86,14 +86,14 @@ static void hv_apic_write(u32 reg, u32 v } } -static void hv_apic_eoi_write(u32 reg, u32 val) +static void hv_apic_eoi_write(void) { struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()]; if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1)) return; - wrmsr(HV_X64_MSR_EOI, val, 0); + wrmsr(HV_X64_MSR_EOI, APIC_EOI_ACK, 0); } static bool cpu_is_self(int cpu) @@ -310,7 +310,7 @@ void __init hv_apic_init(void) * lazy EOI when available, but the same accessor works for * both xapic and x2apic because the field layout is the same. */ - apic_set_eoi_write(hv_apic_eoi_write); + apic_set_eoi_cb(hv_apic_eoi_write); if (!x2apic_enabled()) { apic->read = hv_apic_read; apic->write = hv_apic_write; --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -98,6 +98,11 @@ static inline u32 native_apic_mem_read(u return *((volatile u32 *)(APIC_BASE + reg)); } +static inline void native_apic_mem_eoi(void) +{ + native_apic_mem_write(APIC_EOI, APIC_EOI_ACK); +} + extern void native_apic_icr_write(u32 low, u32 id); extern u64 native_apic_icr_read(void); @@ -189,7 +194,7 @@ static inline void native_apic_msr_write wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); } -static inline void native_apic_msr_eoi_write(u32 reg, u32 v) +static inline void native_apic_msr_eoi(void) { __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); } @@ -250,8 +255,8 @@ struct irq_data; */ struct apic { /* Hotpath functions first */ - void (*eoi_write)(u32 reg, u32 v); - void (*native_eoi_write)(u32 reg, u32 v); + void (*eoi)(void); + void (*native_eoi)(void); void (*write)(u32 reg, u32 v); u32 (*read)(u32 reg); @@ -351,7 +356,7 @@ static inline void apic_write(u32 reg, u static inline void apic_eoi(void) { - apic->eoi_write(APIC_EOI, APIC_EOI_ACK); + apic->eoi(); } static inline u64 apic_icr_read(void) @@ -380,7 +385,7 @@ static inline bool apic_id_valid(u32 api return apic_id <= apic->max_apic_id; } -extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); +extern void __init apic_set_eoi_cb(void (*eoi)(void)); #else /* CONFIG_X86_LOCAL_APIC */ @@ -391,7 +396,7 @@ static inline u64 apic_icr_read(void) { static inline void apic_icr_write(u32 low, u32 high) { } static inline void apic_wait_icr_idle(void) { } static inline u32 safe_apic_wait_icr_idle(void) { return 0; } -static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} +static inline void apic_set_eoi_cb(void (*eoi)(void)) {} #endif /* CONFIG_X86_LOCAL_APIC */ --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2502,15 +2502,15 @@ void __init acpi_wake_cpu_handler_update * interrupts disabled, so we know this does not race with actual APIC driver * use. */ -void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) +void __init apic_set_eoi_cb(void (*eoi)(void)) { struct apic **drv; for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { /* Should happen once for each apic */ - WARN_ON((*drv)->eoi_write == eoi_write); - (*drv)->native_eoi_write = (*drv)->eoi_write; - (*drv)->eoi_write = eoi_write; + WARN_ON((*drv)->eoi == eoi); + (*drv)->native_eoi = (*drv)->eoi; + (*drv)->eoi = eoi; } } --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -106,7 +106,7 @@ static struct apic apic_flat __ro_after_ .read = native_apic_mem_read, .write = native_apic_mem_write, - .eoi_write = native_apic_mem_write, + .eoi = native_apic_mem_eoi, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, .wait_icr_idle = apic_mem_wait_icr_idle, @@ -182,7 +182,7 @@ static struct apic apic_physflat __ro_af .read = native_apic_mem_read, .write = native_apic_mem_write, - .eoi_write = native_apic_mem_write, + .eoi = native_apic_mem_eoi, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, .wait_icr_idle = apic_mem_wait_icr_idle, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -29,6 +29,7 @@ static int noop_wakeup_secondary_cpu(int static u64 noop_apic_icr_read(void) { return 0; } static int noop_phys_pkg_id(int cpuid_apic, int index_msb) { return 0; } static unsigned int noop_get_apic_id(unsigned long x) { return 0; } +static void noop_apic_eoi(void) { } static u32 noop_apic_read(u32 reg) { @@ -71,7 +72,7 @@ struct apic apic_noop __ro_after_init = .read = noop_apic_read, .write = noop_apic_write, - .eoi_write = noop_apic_write, + .eoi = noop_apic_eoi, .icr_read = noop_apic_icr_read, .icr_write = noop_apic_icr_write, }; --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -247,7 +247,7 @@ static const struct apic apic_numachip1 .read = native_apic_mem_read, .write = native_apic_mem_write, - .eoi_write = native_apic_mem_write, + .eoi = native_apic_mem_eoi, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, }; @@ -284,7 +284,7 @@ static const struct apic apic_numachip2 .read = native_apic_mem_read, .write = native_apic_mem_write, - .eoi_write = native_apic_mem_write, + .eoi = native_apic_mem_eoi, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, }; --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -105,7 +105,7 @@ static struct apic apic_bigsmp __ro_afte .read = native_apic_mem_read, .write = native_apic_mem_write, - .eoi_write = native_apic_mem_write, + .eoi = native_apic_mem_eoi, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, .wait_icr_idle = apic_mem_wait_icr_idle, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -60,7 +60,7 @@ static struct apic apic_default __ro_aft .read = native_apic_mem_read, .write = native_apic_mem_write, - .eoi_write = native_apic_mem_write, + .eoi = native_apic_mem_eoi, .icr_read = native_apic_icr_read, .icr_write = native_apic_icr_write, .wait_icr_idle = apic_mem_wait_icr_idle, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -254,7 +254,7 @@ static struct apic apic_x2apic_cluster _ .read = native_apic_msr_read, .write = native_apic_msr_write, - .eoi_write = native_apic_msr_eoi_write, + .eoi = native_apic_msr_eoi, .icr_read = native_x2apic_icr_read, .icr_write = native_x2apic_icr_write, }; --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -169,7 +169,7 @@ static struct apic apic_x2apic_phys __ro .read = native_apic_msr_read, .write = native_apic_msr_write, - .eoi_write = native_apic_msr_eoi_write, + .eoi = native_apic_msr_eoi, .icr_read = native_x2apic_icr_read, .icr_write = native_x2apic_icr_write, }; --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -831,7 +831,7 @@ static struct apic apic_x2apic_uv_x __ro .read = native_apic_msr_read, .write = native_apic_msr_write, - .eoi_write = native_apic_msr_eoi_write, + .eoi = native_apic_msr_eoi, .icr_read = native_x2apic_icr_read, .icr_write = native_x2apic_icr_write, }; --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -332,7 +332,7 @@ static void kvm_register_steal_time(void static DEFINE_PER_CPU_DECRYPTED(unsigned long, kvm_apic_eoi) = KVM_PV_EOI_DISABLED; -static notrace void kvm_guest_apic_eoi_write(u32 reg, u32 val) +static notrace void kvm_guest_apic_eoi_write(void) { /** * This relies on __test_and_clear_bit to modify the memory @@ -343,7 +343,7 @@ static notrace void kvm_guest_apic_eoi_w */ if (__test_and_clear_bit(KVM_PV_EOI_BIT, this_cpu_ptr(&kvm_apic_eoi))) return; - apic->native_eoi_write(APIC_EOI, APIC_EOI_ACK); + apic->native_eoi(); } static void kvm_guest_cpu_init(void) @@ -825,7 +825,7 @@ static void __init kvm_guest_init(void) } if (kvm_para_has_feature(KVM_FEATURE_PV_EOI)) - apic_set_eoi_write(kvm_guest_apic_eoi_write); + apic_set_eoi_cb(kvm_guest_apic_eoi_write); if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF_INT) && kvmapf) { static_branch_enable(&kvm_async_pf_enabled); --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -81,6 +81,11 @@ static void xen_apic_write(u32 reg, u32 WARN(1,"register: %x, value: %x\n", reg, val); } +static void xen_apic_eoi(void) +{ + WARN_ON_ONCE(1); +} + static u64 xen_apic_icr_read(void) { return 0; @@ -147,7 +152,7 @@ static struct apic xen_pv_apic = { #endif .read = xen_apic_read, .write = xen_apic_write, - .eoi_write = xen_apic_write, + .eoi = xen_apic_eoi, .icr_read = xen_apic_icr_read, .icr_write = xen_apic_icr_write, From patchwork Tue Aug 1 10:47:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129197 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2596179vqg; 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Signed-off-by: Thomas Gleixner Reviewed-by: Wei Liu Acked-by: Peter Zijlstra (Intel) --- arch/x86/hyperv/hv_init.c | 2 +- arch/x86/include/asm/apic.h | 10 ---------- arch/x86/kernel/apic/apic.c | 10 +++++----- arch/x86/kernel/apic/io_apic.c | 4 ++-- arch/x86/kernel/apic/vector.c | 4 ++-- arch/x86/kernel/cpu/acrn.c | 2 +- arch/x86/kernel/cpu/mce/amd.c | 2 +- arch/x86/kernel/cpu/mce/threshold.c | 2 +- arch/x86/kernel/cpu/mshyperv.c | 4 ++-- arch/x86/kernel/irq.c | 14 +++++++------- arch/x86/kernel/irq_work.c | 2 +- arch/x86/kernel/kvm.c | 2 +- arch/x86/kernel/smp.c | 8 ++++---- arch/x86/xen/enlighten_hvm.c | 2 +- 14 files changed, 29 insertions(+), 39 deletions(-) --- a/arch/x86/hyperv/hv_init.c +++ b/arch/x86/hyperv/hv_init.c @@ -161,7 +161,7 @@ static inline bool hv_reenlightenment_av DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_reenlightenment) { - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(irq_hv_reenlightenment_count); schedule_delayed_work(&hv_reenlightenment_work, HZ/10); } --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -402,16 +402,6 @@ static inline void apic_set_eoi(void (*e extern void apic_ack_irq(struct irq_data *data); -static inline void ack_APIC_irq(void) -{ - /* - * ack_APIC_irq() actually gets compiled as a single instruction - * ... yummie. - */ - apic_eoi(); -} - - static inline bool lapic_vector_set_in_irr(unsigned int vector) { u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1076,7 +1076,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer { struct pt_regs *old_regs = set_irq_regs(regs); - ack_APIC_irq(); + apic_eoi(); trace_local_timer_entry(LOCAL_TIMER_VECTOR); local_apic_timer_interrupt(); trace_local_timer_exit(LOCAL_TIMER_VECTOR); @@ -1480,7 +1480,7 @@ static bool apic_check_and_ack(union api * per set bit. */ for_each_set_bit(bit, isr->map, APIC_IR_BITS) - ack_APIC_irq(); + apic_eoi(); return true; } @@ -1492,7 +1492,7 @@ static bool apic_check_and_ack(union api * interrupt from previous kernel might still have ISR bit set. * * Most probably by now the CPU has serviced that pending interrupt and it - * might not have done the ack_APIC_irq() because it thought, interrupt + * might not have done the apic_eoi() because it thought, interrupt * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear * the ISR bit and cpu thinks it has already serviced the interrupt. Hence * a vector might get locked. It was noticed for timer irq (vector @@ -2146,7 +2146,7 @@ static noinline void handle_spurious_int if (v & (1 << (vector & 0x1f))) { pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", vector, smp_processor_id()); - ack_APIC_irq(); + apic_eoi(); } else { pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", vector, smp_processor_id()); @@ -2197,7 +2197,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_error_inte if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ apic_write(APIC_ESR, 0); v = apic_read(APIC_ESR); - ack_APIC_irq(); + apic_eoi(); atomic_inc(&irq_err_count); apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1823,7 +1823,7 @@ static void ioapic_ack_level(struct irq_ * We must acknowledge the irq before we move it or the acknowledge will * not propagate properly. */ - ack_APIC_irq(); + apic_eoi(); /* * Tail end of clearing remote IRR bit (either by delivering the EOI @@ -2046,7 +2046,7 @@ static void unmask_lapic_irq(struct irq_ static void ack_lapic_irq(struct irq_data *data) { - ack_APIC_irq(); + apic_eoi(); } static struct irq_chip lapic_chip __read_mostly = { --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -885,7 +885,7 @@ static int apic_retrigger_irq(struct irq void apic_ack_irq(struct irq_data *irqd) { irq_move_irq(irqd); - ack_APIC_irq(); + apic_eoi(); } void apic_ack_edge(struct irq_data *irqd) @@ -940,7 +940,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_irq_move_c struct apic_chip_data *apicd; struct hlist_node *tmp; - ack_APIC_irq(); + apic_eoi(); /* Prevent vectors vanishing under us */ raw_spin_lock(&vector_lock); --- a/arch/x86/kernel/cpu/acrn.c +++ b/arch/x86/kernel/cpu/acrn.c @@ -51,7 +51,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_acrn_hv_ca * will block the interrupt whose vector is lower than * HYPERVISOR_CALLBACK_VECTOR. */ - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(irq_hv_callback_count); if (acrn_intr_handler) --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -759,7 +759,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_e inc_irq_stat(irq_deferred_error_count); deferred_error_int_vector(); trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); - ack_APIC_irq(); + apic_eoi(); } /* --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -27,5 +27,5 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_threshold) inc_irq_stat(irq_threshold_count); mce_threshold_vector(); trace_threshold_apic_exit(THRESHOLD_APIC_VECTOR); - ack_APIC_irq(); + apic_eoi(); } --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -119,7 +119,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_cal vmbus_handler(); if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) - ack_APIC_irq(); + apic_eoi(); set_irq_regs(old_regs); } @@ -147,7 +147,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_sti if (hv_stimer0_handler) hv_stimer0_handler(); add_interrupt_randomness(HYPERV_STIMER0_VECTOR); - ack_APIC_irq(); + apic_eoi(); set_irq_regs(old_regs); } --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -49,7 +49,7 @@ void ack_bad_irq(unsigned int irq) * completely. * But only ack when the APIC is enabled -AK */ - ack_APIC_irq(); + apic_eoi(); } #define irq_stats(x) (&per_cpu(irq_stat, x)) @@ -256,7 +256,7 @@ DEFINE_IDTENTRY_IRQ(common_interrupt) if (likely(!IS_ERR_OR_NULL(desc))) { handle_irq(desc, regs); } else { - ack_APIC_irq(); + apic_eoi(); if (desc == VECTOR_UNUSED) { pr_emerg_ratelimited("%s: %d.%u No irq handler for vector\n", @@ -280,7 +280,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platfo { struct pt_regs *old_regs = set_irq_regs(regs); - ack_APIC_irq(); + apic_eoi(); trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR); inc_irq_stat(x86_platform_ipis); if (x86_platform_ipi_callback) @@ -310,7 +310,7 @@ EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wa */ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_ipi) { - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(kvm_posted_intr_ipis); } @@ -319,7 +319,7 @@ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm */ DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted_intr_wakeup_ipi) { - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(kvm_posted_intr_wakeup_ipis); kvm_posted_intr_wakeup_handler(); } @@ -329,7 +329,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted */ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi) { - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(kvm_posted_intr_nested_ipis); } #endif @@ -401,6 +401,6 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_thermal) inc_irq_stat(irq_thermal_count); smp_thermal_vector(); trace_thermal_apic_exit(THERMAL_APIC_VECTOR); - ack_APIC_irq(); + apic_eoi(); } #endif --- a/arch/x86/kernel/irq_work.c +++ b/arch/x86/kernel/irq_work.c @@ -16,7 +16,7 @@ #ifdef CONFIG_X86_LOCAL_APIC DEFINE_IDTENTRY_SYSVEC(sysvec_irq_work) { - ack_APIC_irq(); + apic_eoi(); trace_irq_work_entry(IRQ_WORK_VECTOR); inc_irq_stat(apic_irq_work_irqs); irq_work_run(); --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -291,7 +291,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_asyncp struct pt_regs *old_regs = set_irq_regs(regs); u32 token; - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(irq_hv_callback_count); --- a/arch/x86/kernel/smp.c +++ b/arch/x86/kernel/smp.c @@ -135,7 +135,7 @@ static int smp_stop_nmi_callback(unsigne */ DEFINE_IDTENTRY_SYSVEC(sysvec_reboot) { - ack_APIC_irq(); + apic_eoi(); cpu_emergency_disable_virtualization(); stop_this_cpu(NULL); } @@ -268,7 +268,7 @@ static void native_stop_other_cpus(int w */ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_reschedule_ipi) { - ack_APIC_irq(); + apic_eoi(); trace_reschedule_entry(RESCHEDULE_VECTOR); inc_irq_stat(irq_resched_count); scheduler_ipi(); @@ -277,7 +277,7 @@ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_res DEFINE_IDTENTRY_SYSVEC(sysvec_call_function) { - ack_APIC_irq(); + apic_eoi(); trace_call_function_entry(CALL_FUNCTION_VECTOR); inc_irq_stat(irq_call_count); generic_smp_call_function_interrupt(); @@ -286,7 +286,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_call_funct DEFINE_IDTENTRY_SYSVEC(sysvec_call_function_single) { - ack_APIC_irq(); + apic_eoi(); trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR); inc_irq_stat(irq_call_count); generic_smp_call_function_single_interrupt(); --- a/arch/x86/xen/enlighten_hvm.c +++ b/arch/x86/xen/enlighten_hvm.c @@ -132,7 +132,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_xen_hvm_ca struct pt_regs *old_regs = set_irq_regs(regs); if (xen_percpu_upcall) - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(irq_hv_callback_count); From patchwork Tue Aug 1 10:47:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129230 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2614039vqg; Tue, 1 Aug 2023 04:57:14 -0700 (PDT) X-Google-Smtp-Source: APBJJlGISuqwExe7d2ukSum/aRFDZoX34PNRF5rsglPIhmwRILlSLzFNNkZ2Kenc4DtNNsZlc6PI X-Received: by 2002:a17:902:eccc:b0:1b3:d8ac:8db3 with SMTP id a12-20020a170902eccc00b001b3d8ac8db3mr11792185plh.6.1690891033826; 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Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 6 ++++++ arch/x86/kernel/kvm.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -359,6 +359,11 @@ static inline void apic_eoi(void) apic->eoi(); } +static inline void apic_native_eoi(void) +{ + apic->native_eoi(); +} + static inline u64 apic_icr_read(void) { return apic->icr_read(); @@ -397,6 +402,7 @@ static inline void apic_icr_write(u32 lo static inline void apic_wait_icr_idle(void) { } static inline u32 safe_apic_wait_icr_idle(void) { return 0; } static inline void apic_set_eoi_cb(void (*eoi)(void)) {} +static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } #endif /* CONFIG_X86_LOCAL_APIC */ --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -343,7 +343,7 @@ static notrace void kvm_guest_apic_eoi_w */ if (__test_and_clear_bit(KVM_PV_EOI_BIT, this_cpu_ptr(&kvm_apic_eoi))) return; - apic->native_eoi(); + apic_native_eoi(); } static void kvm_guest_cpu_init(void) From patchwork Tue Aug 1 10:47:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129208 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2598179vqg; Tue, 1 Aug 2023 04:22:49 -0700 (PDT) X-Google-Smtp-Source: APBJJlEVH2cuFRNcxyqJFBgx41bu0LPPIjX+D0dOmeH7qUmPh0aBmMJKg1yG6FauNQPGCKXS50He X-Received: by 2002:a05:6a20:9151:b0:13b:79dc:4538 with SMTP id x17-20020a056a20915100b0013b79dc4538mr12836086pzc.62.1690888969343; Tue, 01 Aug 2023 04:22:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888969; cv=none; d=google.com; s=arc-20160816; b=Elu2hVfU1+M6MZcIylychDoEwa5PhJd3WitsgbcgZ6deYRz/kiauSx0IADFrMBwwN6 s11ul1N7xYfZopJzw4WzUbCJw/XH4ePwfHJOrQIfarvGIMCilaG2lhaa4bpHp4AmXbj5 iahXsfodA9xGis4Y6XoI8Eud64EJ0cVqLnTFZADkgGS8W1LI1kF4b1QhA8VS6TE2LR16 4sK3yaDpA2Rccj6Irovna8AYqG9GYryYi82JQO/IsFT2rvIEaU2pTco2ESfLqq5I5VRB 0d6zTyPsuFBJonBqtwxAMmC4VZrJaxaHAp0Ic+859teBUlL6tI+q5gqUvZkCurOPvJb6 irqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=u1MBAiZCltHmWzuaN06FA6y4i5aqgal/njyPH8pNWsw=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=AWR3zfUZ3ZQwWA1Ck38at7UZ+pifav06oc8V+CvE2n6F1huDh4OSb+ezQkH3mpTagm 4pNT+l4JvMVaqykkoQdXd8MUw+RNeMdfwn8aUuh52kRYdQVQdzGT+6Op0w4hzQr/oZZR QvGdF64l7VjkbXuAYIbWO5bvsVw1kEKjSdp34YM1s7TAAYwm6pCqqhyYfcwZyrPV+dZQ fxCucyg8jFnConroCGWP5dwjYKmUQo2lyG3XpuilrsP62OdM7CB7WySLTXEMJkeFoPYX gsNhdF7m7k1Y+YagmVX+PnaKd/0IOTx/01gUhXZE+TajF4yqL8FGtRoLuIRQA1LYjXR7 x6qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Cw6Qaq9B; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cm5-20020a056a00338500b0067d204bf281si4895061pfb.3.2023.08.01.04.22.36; Tue, 01 Aug 2023 04:22:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Cw6Qaq9B; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230472AbjHAKwf (ORCPT + 99 others); Tue, 1 Aug 2023 06:52:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231696AbjHAKvf (ORCPT ); Tue, 1 Aug 2023 06:51:35 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14CE22D5F for ; Tue, 1 Aug 2023 03:49:11 -0700 (PDT) Message-ID: <20230801103817.944932383@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886864; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=u1MBAiZCltHmWzuaN06FA6y4i5aqgal/njyPH8pNWsw=; b=Cw6Qaq9BB9aFNsvc/8cvvK/utELD/Ja3avMU+A1jQW22pN95MwoOKUjSOxPMVPX2xaoBXu NPTe/ZlMvpb2qctfHPY1xDfqkT9UZUrhoqTvtY/8skXNiUMpWCFfVA73hm9McSogrFrvww 8H7e69qyKqWv42joDUkBsylTI9ECagwIG8yMw4p0mGSWVet7PEBWkPGUrs70JgJwhmBtts Lq0ZHL4d/IJSNNjqIwZ5daGsd/vnb/HVjGXbq1Kt2e0v6VaBJGu1ZSqnu243OH4lB7c46v 1GSbZvZpqobEbcX0/5S2MUF1vE4TQnWjLdZsXq5HrETkaPbCtTlEHEYsYlIh6g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886864; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=u1MBAiZCltHmWzuaN06FA6y4i5aqgal/njyPH8pNWsw=; b=aUCoJnyN0YEVX5l49jigXe6mgQjvNxESR70CN1npaJgsyaNgo2NLZbgRxGu6IS0SrSSLkZ ssdyhkQQOh/ivfAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 51/60] x86/apic: Provide common init infrastructure References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:44 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025592073277221 X-GMAIL-MSGID: 1773025592073277221 In preparation for converting the hotpath APIC callbacks to static keys, provide common initialization inforastructure. Lift apic_install_drivers() from probe_64.c and convert all places which switch the apic instance by storing the pointer to use apic_install_driver() as a first step. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 + arch/x86/kernel/apic/Makefile | 2 - arch/x86/kernel/apic/apic.c | 31 ----------------------- arch/x86/kernel/apic/apic_flat_64.c | 6 ---- arch/x86/kernel/apic/bigsmp_32.c | 6 +--- arch/x86/kernel/apic/init.c | 47 ++++++++++++++++++++++++++++++++++++ arch/x86/kernel/apic/probe_32.c | 5 +-- arch/x86/kernel/apic/probe_64.c | 13 --------- arch/x86/xen/apic.c | 10 ++----- 9 files changed, 59 insertions(+), 63 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -344,6 +344,8 @@ extern int lapic_can_unplug_cpu(void); #ifdef CONFIG_X86_LOCAL_APIC +void __init apic_install_driver(struct apic *driver); + static inline u32 apic_read(u32 reg) { return apic->read(reg); --- a/arch/x86/kernel/apic/Makefile +++ b/arch/x86/kernel/apic/Makefile @@ -7,7 +7,7 @@ # In particualr, smp_apic_timer_interrupt() is called in random places. KCOV_INSTRUMENT := n -obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_common.o apic_noop.o ipi.o vector.o +obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_common.o apic_noop.o ipi.o vector.o init.o obj-y += hw_nmi.o obj-$(CONFIG_X86_IO_APIC) += io_apic.o --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -236,8 +236,7 @@ static int modern_apic(void) */ static void __init apic_disable(void) { - pr_info("APIC: switched to apic NOOP\n"); - apic = &apic_noop; + apic_install_driver(&apic_noop); } void native_apic_icr_write(u32 low, u32 id) @@ -2486,34 +2485,6 @@ u32 x86_msi_msg_get_destid(struct msi_ms } EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid); -#ifdef CONFIG_X86_64 -void __init acpi_wake_cpu_handler_update(wakeup_cpu_handler handler) -{ - struct apic **drv; - - for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) - (*drv)->wakeup_secondary_cpu_64 = handler; -} -#endif - -/* - * Override the generic EOI implementation with an optimized version. - * Only called during early boot when only one CPU is active and with - * interrupts disabled, so we know this does not race with actual APIC driver - * use. - */ -void __init apic_set_eoi_cb(void (*eoi)(void)) -{ - struct apic **drv; - - for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { - /* Should happen once for each apic */ - WARN_ON((*drv)->eoi == eoi); - (*drv)->native_eoi = (*drv)->eoi; - (*drv)->eoi = eoi; - } -} - static void __init apic_bsp_up_setup(void) { #ifdef CONFIG_X86_64 --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -143,11 +143,7 @@ static int physflat_acpi_madt_oem_check( static int physflat_probe(void) { - if (apic == &apic_physflat || num_possible_cpus() > 8 || - jailhouse_paravirt()) - return 1; - - return 0; + return apic == &apic_physflat || num_possible_cpus() > 8 || jailhouse_paravirt(); } static struct apic apic_physflat __ro_after_init = { --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -119,10 +119,8 @@ bool __init apic_bigsmp_possible(bool cm void __init apic_bigsmp_force(void) { - if (apic != &apic_bigsmp) { - apic = &apic_bigsmp; - pr_info("Overriding APIC driver with bigsmp\n"); - } + if (apic != &apic_bigsmp) + apic_install_driver(&apic_bigsmp); } apic_driver(apic_bigsmp); --- /dev/null +++ b/arch/x86/kernel/apic/init.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +#define pr_fmt(fmt) "APIC: " fmt + +#include + +#include "local.h" + +void __init apic_install_driver(struct apic *driver) +{ + if (apic == driver) + return; + + apic = driver; + + if (IS_ENABLED(CONFIG_X86_X2APIC) && apic->x2apic_set_max_apicid) + apic->max_apic_id = x2apic_max_apicid; + + pr_info("Switched APIC routing to: %s\n", driver->name); +} + +#ifdef CONFIG_X86_64 +void __init acpi_wake_cpu_handler_update(wakeup_cpu_handler handler) +{ + struct apic **drv; + + for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) + (*drv)->wakeup_secondary_cpu_64 = handler; +} +#endif + +/* + * Override the generic EOI implementation with an optimized version. + * Only called during early boot when only one CPU is active and with + * interrupts disabled, so we know this does not race with actual APIC driver + * use. + */ +void __init apic_set_eoi_cb(void (*eoi)(void)) +{ + struct apic **drv; + + for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { + /* Should happen once for each apic */ + WARN_ON((*drv)->eoi == eoi); + (*drv)->native_eoi = (*drv)->eoi; + (*drv)->eoi = eoi; + } +} --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -82,7 +82,7 @@ static int __init parse_apic(char *arg) for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { if (!strcmp((*drv)->name, arg)) { - apic = *drv; + apic_install_driver(*drv); cmdline_apic = 1; return 0; } @@ -129,7 +129,7 @@ void __init x86_32_probe_apic(void) for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { if ((*drv)->probe()) { - apic = *drv; + apic_install_driver(*drv); break; } } @@ -137,5 +137,4 @@ void __init x86_32_probe_apic(void) if (drv == __apicdrivers_end) panic("Didn't find an APIC driver"); } - printk(KERN_INFO "Using APIC driver %s\n", apic->name); } --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -13,19 +13,6 @@ #include "local.h" -static __init void apic_install_driver(struct apic *driver) -{ - if (apic == driver) - return; - - apic = driver; - - if (IS_ENABLED(CONFIG_X86_X2APIC) && apic->x2apic_set_max_apicid) - apic->max_apic_id = x2apic_max_apicid; - - pr_info("Switched APIC routing to %s:\n", apic->name); -} - /* Select the appropriate APIC driver */ void __init x86_64_probe_apic(void) { --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -160,20 +160,16 @@ static struct apic xen_pv_apic = { static void __init xen_apic_check(void) { - if (apic == &xen_pv_apic) - return; - - pr_info("Switched APIC routing from %s to %s.\n", apic->name, - xen_pv_apic.name); - apic = &xen_pv_apic; + apic_install_driver(&xen_pv_apic); } + void __init xen_init_apic(void) { x86_apic_ops.io_apic_read = xen_io_apic_read; /* On PV guests the APIC CPUID bit is disabled so none of the * routines end up executing. */ if (!xen_initial_domain()) - apic = &xen_pv_apic; + apic_install_driver(&xen_pv_apic); x86_platform.apic_post_init = xen_apic_check; } From patchwork Tue Aug 1 10:47:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129293 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2651400vqg; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id by14-20020a056a00400e00b006862f5ac976si2044332pfb.379.2023.08.01.06.02.52; Tue, 01 Aug 2023 06:03:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YxBqGI1i; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=38ETvICZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234165AbjHAKvd (ORCPT + 99 others); Tue, 1 Aug 2023 06:51:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234227AbjHAKvD (ORCPT ); Tue, 1 Aug 2023 06:51:03 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A91A249D3 for ; Tue, 1 Aug 2023 03:48:43 -0700 (PDT) Message-ID: <20230801103817.996980460@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886865; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Q8bPz8OSR7Dw0div3KJHyiz5smjtpl0ETsImY01rMac=; b=YxBqGI1i1OUJtBhM2j5Ghxb2h7CmNslx+ErwQHf2TTWhmdHDc6EVk0tQ04BVFAc2fa8D+m M8Ot1DFQFNOL3OBXPpJpSQOetpgLK0xbAQFl3GgqQTJ24bRKJzs4ct0zqM4xQiLIQUCNe+ QgCmPOZuGFCcxKlOx/h0QoGpfXng24GKNlnkVM9l/P3kEhdzOPpDZ2I5pV3HtnsL0YWNkK CInABts2J+ViQ8Lbv55wfUxMTKhX7OGovUNnNQdsacyJTpVhc7+FtiD9Kt54xqDXqy/hLm dKcBtP14BfmI3ax9a7K9EOoZken0vr/MAHWqpaUy3PLxavg9eHuXHNSQQmq0lQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886865; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Q8bPz8OSR7Dw0div3KJHyiz5smjtpl0ETsImY01rMac=; b=38ETvICZ3PHedt8pZ667v+ToVqjm87wEQsWaFrWu9bPLMAN/c6ipdtNBwEJNEI2YsXviZ8 Y1qxF2E+UrrKqFCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt Subject: [patch V3 52/60] x86/xen/apic: Use standard apic driver mechanism for Xen PV References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:45 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773031901573181578 X-GMAIL-MSGID: 1773031901573181578 Instead of setting the Xen PV apic driver very early during boot, just use the standard apic driver probing by setting an appropriate x86_init.irqs.intr_mode_init callback. At the same time eliminate xen_apic_check() which has never been used. The #ifdef CONFIG_X86_LOCAL_APIC around the call of xen_init_apic() can be removed, too, as CONFIG_XEN depends on CONFIG_X86_LOCAL_APIC. Signed-off-by: Juergen Gross Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/lkml/aa086365-fd02-210f-67c6-5c9175c0dfee@suse.com --- V3: New patch to address the XenPV fallout --- arch/x86/xen/apic.c | 11 ----------- arch/x86/xen/enlighten_pv.c | 4 +--- 2 files changed, 1 insertion(+), 14 deletions(-) --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -158,19 +158,8 @@ static struct apic xen_pv_apic = { .icr_write = xen_apic_icr_write, }; -static void __init xen_apic_check(void) -{ - apic_install_driver(&xen_pv_apic); -} - void __init xen_init_apic(void) { x86_apic_ops.io_apic_read = xen_io_apic_read; - /* On PV guests the APIC CPUID bit is disabled so none of the - * routines end up executing. */ - if (!xen_initial_domain()) - apic_install_driver(&xen_pv_apic); - - x86_platform.apic_post_init = xen_apic_check; } apic_driver(xen_pv_apic); --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1326,7 +1326,7 @@ asmlinkage __visible void __init xen_sta x86_init.resources.memory_setup = xen_memory_setup; x86_init.irqs.intr_mode_select = x86_init_noop; - x86_init.irqs.intr_mode_init = x86_init_noop; + x86_init.irqs.intr_mode_init = x86_64_probe_apic; x86_init.oem.arch_setup = xen_arch_setup; x86_init.oem.banner = xen_banner; x86_init.hyper.init_platform = xen_pv_init_platform; @@ -1366,12 +1366,10 @@ asmlinkage __visible void __init xen_sta xen_init_capabilities(); -#ifdef CONFIG_X86_LOCAL_APIC /* * set up the basic apic ops. */ xen_init_apic(); -#endif machine_ops = xen_machine_ops; From patchwork Tue Aug 1 10:47:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129250 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2624173vqg; Tue, 1 Aug 2023 05:12:58 -0700 (PDT) X-Google-Smtp-Source: APBJJlGYLp1HFfotm1oTIKz4C/QCYLPyl/+uBRRkwppTFw6IWV2sIFGxBbMUJKIuRxF1tRZNrllR X-Received: by 2002:a17:906:8471:b0:99b:efc8:51d with SMTP id hx17-20020a170906847100b0099befc8051dmr2149243ejc.21.1690891977692; Tue, 01 Aug 2023 05:12:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690891977; cv=none; d=google.com; s=arc-20160816; b=JCXrPYF1g9Ohd0UQrs3v4j8f7jizXIyqcuoQgrFsC6vbOlY21heeoj+XJ53rsdaH+9 p7QHkXsWvWFSnhrLprFdrswbEXbZ+yoYrEuyZAozJB8Hja4eJevpUY0ArgtaMil12WCT a/Ns7AsrTG153Wc+whkRCaeDKdBzOTWWYEzbEtpBivPhhrbhVkTzmytoGaI4gKch9h1K 32xda/gz/621T+6rSaA9hzy5NceaFMUzrk9RANl5IDt80gdjcIpCgGNiHihi53p+fcHw Jqd9pGkPGml+oQ2ZXR9UbYHpkxxVZBg0D6r18RK5gSeHzcacoYTmxTMi+OOZRTA7/zeg 8Paw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=4GFxWOIrpTfqT5fCSkz52w3aacX6yQNA53PA8dS4E0E=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=0PI0d0pX4PSPxwl5a/xiCb5M6YQwG82MrOIVh4FbxaowcSezYW3PM+N016bCIcyZHd BjfxxdS04SMhEx2lOHie2IToednPUkmsgWZekbN8Y5DExpbU2bvW9gq8c/+nO4G3qvZo EotWKNlgiRgz7uC0+mDPgUQy/MTTGHTYx9lU1FZFg8QMhIUz8Vcf1sPHgWbVfIkxxxUz ud5d3TQ4po2N/womrgFnP8y07/5MYh0wF5D6iPyJf1Qk+aOY0c9f6KACrH1nbyVMm0dN Uaip2dUHkV3FMTuB9mpjwZ4slQxhxhuBT1LPwrA2Pt3A/2MEzmeAu1tvKrMeOuwGMxnI up/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="CSCyD+r/"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m15-20020a17090607cf00b00992d6e88081si83636ejc.956.2023.08.01.05.12.32; Tue, 01 Aug 2023 05:12:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="CSCyD+r/"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231879AbjHAKvi (ORCPT + 99 others); Tue, 1 Aug 2023 06:51:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234238AbjHAKvD (ORCPT ); Tue, 1 Aug 2023 06:51:03 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D126049E0 for ; Tue, 1 Aug 2023 03:48:44 -0700 (PDT) Message-ID: <20230801103818.049146509@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886866; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4GFxWOIrpTfqT5fCSkz52w3aacX6yQNA53PA8dS4E0E=; b=CSCyD+r/J6QigzVBMvh6pPAQX18CtRSNEkOquVIZgBge69OkoSNNO0Ts57dRDw5BshD4k6 Yswxo9CtHYOGZal62LszSf8ZYvPZ+fSgLdy/uXjhTDol7mD9Bbod9cHxIkdyTUgml/NbhX NJWDNYyzNA7Mz2YIdBAtFEOPLgednd6iocADIUegXfFnoMgHU2/DE8I+Hv21JsYwHjDSRH 6b7ZPrepn3vw1i8bTZWY7iKJFm8rkIblZ9CpHc4md1423q/n6AqSj1zUzzawa7j5JE+avx 53mfvXRnCUGDA0YSVDkDKzZ0td7b5jAKLESTL0FgbV5Cd4M6rQ5i8wEmn7huww== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886866; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4GFxWOIrpTfqT5fCSkz52w3aacX6yQNA53PA8dS4E0E=; b=pjr2s9x15ZhqVgD1vdPF/Xza0uqqjnDMGoYuyW1nSxJxJw3I2HdqxAOnNbFwc+UZOUozmj FZTQEmVS4foDN+Dw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 53/60] x86/apic: Provide apic_update_callback() References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:46 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773028746110792806 X-GMAIL-MSGID: 1773028746110792806 There are already two variants of update mechanism for particular callbacks and virtualization just writes into the data structure. Provide an interface and use a shadow data structure to preserve callbacks so they can be reapplied when the APIC driver is replaced. The extra data structure is intentional as any new callback needs to be also updated in the core code. This also prepares for static calls. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 28 ++++++++++++++++++++++++++++ arch/x86/kernel/apic/init.c | 39 ++++++++++++++++++++++++++++++++++++++- arch/x86/kernel/setup.c | 2 ++ 3 files changed, 68 insertions(+), 1 deletion(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -308,6 +308,23 @@ struct apic { char *name; }; +struct apic_override { + void (*eoi)(void); + void (*native_eoi)(void); + void (*write)(u32 reg, u32 v); + u32 (*read)(u32 reg); + void (*send_IPI)(int cpu, int vector); + void (*send_IPI_mask)(const struct cpumask *mask, int vector); + void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); + void (*send_IPI_allbutself)(int vector); + void (*send_IPI_all)(int vector); + void (*send_IPI_self)(int vector); + u64 (*icr_read)(void); + void (*icr_write)(u32 low, u32 high); + int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); + int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); +}; + /* * Pointer to the local APIC driver in use on this system (there's * always just one such driver in use - the kernel decides via an @@ -343,9 +360,17 @@ extern int lapic_can_unplug_cpu(void); #endif #ifdef CONFIG_X86_LOCAL_APIC +extern struct apic_override __x86_apic_override; +void __init apic_setup_apic_calls(void); void __init apic_install_driver(struct apic *driver); +#define apic_update_callback(_callback, _fn) { \ + __x86_apic_override._callback = _fn; \ + apic->_callback = _fn; \ + pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \ +} + static inline u32 apic_read(u32 reg) { return apic->read(reg); @@ -405,6 +430,9 @@ static inline void apic_wait_icr_idle(vo static inline u32 safe_apic_wait_icr_idle(void) { return 0; } static inline void apic_set_eoi_cb(void (*eoi)(void)) {} static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } +static inline void apic_setup_apic_calls(void) { } + +#define apic_update_callback(_callback, _fn) do { } while (0) #endif /* CONFIG_X86_LOCAL_APIC */ --- a/arch/x86/kernel/apic/init.c +++ b/arch/x86/kernel/apic/init.c @@ -5,6 +5,37 @@ #include "local.h" +/* The container for function call overrides */ +struct apic_override __x86_apic_override __initdata; + +#define apply_override(__cb) \ + if (__x86_apic_override.__cb) \ + apic->__cb = __x86_apic_override.__cb + +static __init void restore_override_callbacks(void) +{ + apply_override(eoi); + apply_override(native_eoi); + apply_override(write); + apply_override(read); + apply_override(send_IPI); + apply_override(send_IPI_mask); + apply_override(send_IPI_mask_allbutself); + apply_override(send_IPI_allbutself); + apply_override(send_IPI_all); + apply_override(send_IPI_self); + apply_override(icr_read); + apply_override(icr_write); + apply_override(wakeup_secondary_cpu); + apply_override(wakeup_secondary_cpu_64); +} + +void __init apic_setup_apic_calls(void) +{ + /* Ensure that the default APIC has native_eoi populated */ + apic->native_eoi = apic->eoi; +} + void __init apic_install_driver(struct apic *driver) { if (apic == driver) @@ -15,6 +46,13 @@ void __init apic_install_driver(struct a if (IS_ENABLED(CONFIG_X86_X2APIC) && apic->x2apic_set_max_apicid) apic->max_apic_id = x2apic_max_apicid; + /* Copy the original eoi() callback as KVM/HyperV might overwrite it */ + if (!apic->native_eoi) + apic->native_eoi = apic->eoi; + + /* Apply any already installed callback overrides */ + restore_override_callbacks(); + pr_info("Switched APIC routing to: %s\n", driver->name); } @@ -41,7 +79,6 @@ void __init apic_set_eoi_cb(void (*eoi)( for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { /* Should happen once for each apic */ WARN_ON((*drv)->eoi == eoi); - (*drv)->native_eoi = (*drv)->eoi; (*drv)->eoi = eoi; } } --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1017,6 +1017,8 @@ void __init setup_arch(char **cmdline_p) x86_report_nx(); + apic_setup_apic_calls(); + if (acpi_mps_check()) { #ifdef CONFIG_X86_LOCAL_APIC apic_is_disabled = true; From patchwork Tue Aug 1 10:47:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129286 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2646939vqg; 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Signed-off-by: Thomas Gleixner Reviewed-by: Wei Liu Acked-by: Peter Zijlstra (Intel) --- arch/x86/hyperv/hv_apic.c | 2 +- arch/x86/hyperv/hv_vtl.c | 2 +- arch/x86/include/asm/apic.h | 3 --- arch/x86/kernel/acpi/boot.c | 2 +- arch/x86/kernel/apic/init.c | 27 --------------------------- arch/x86/kernel/kvm.c | 4 ++-- 6 files changed, 5 insertions(+), 35 deletions(-) --- a/arch/x86/hyperv/hv_apic.c +++ b/arch/x86/hyperv/hv_apic.c @@ -310,7 +310,7 @@ void __init hv_apic_init(void) * lazy EOI when available, but the same accessor works for * both xapic and x2apic because the field layout is the same. */ - apic_set_eoi_cb(hv_apic_eoi_write); + apic_update_callback(eoi, hv_apic_eoi_write); if (!x2apic_enabled()) { apic->read = hv_apic_read; apic->write = hv_apic_write; --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -222,7 +222,7 @@ static int __init hv_vtl_early_init(void "Please add 'noxsave' to the kernel command line.\n"); real_mode_header = &hv_vtl_real_mode_header; - apic->wakeup_secondary_cpu_64 = hv_vtl_wakeup_secondary_cpu; + apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu); return 0; } --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -417,8 +417,6 @@ static inline bool apic_id_valid(u32 api return apic_id <= apic->max_apic_id; } -extern void __init apic_set_eoi_cb(void (*eoi)(void)); - #else /* CONFIG_X86_LOCAL_APIC */ static inline u32 apic_read(u32 reg) { return 0; } @@ -478,7 +476,6 @@ static inline unsigned int read_apic_id( #ifdef CONFIG_X86_64 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); -extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); extern int default_acpi_madt_oem_check(char *, char *); extern void x86_64_probe_apic(void); #else --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -1174,7 +1174,7 @@ static int __init acpi_parse_mp_wake(uni acpi_mp_wake_mailbox_paddr = mp_wake->base_address; - acpi_wake_cpu_handler_update(acpi_wakeup_cpu); + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); return 0; } --- a/arch/x86/kernel/apic/init.c +++ b/arch/x86/kernel/apic/init.c @@ -55,30 +55,3 @@ void __init apic_install_driver(struct a pr_info("Switched APIC routing to: %s\n", driver->name); } - -#ifdef CONFIG_X86_64 -void __init acpi_wake_cpu_handler_update(wakeup_cpu_handler handler) -{ - struct apic **drv; - - for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) - (*drv)->wakeup_secondary_cpu_64 = handler; -} -#endif - -/* - * Override the generic EOI implementation with an optimized version. - * Only called during early boot when only one CPU is active and with - * interrupts disabled, so we know this does not race with actual APIC driver - * use. - */ -void __init apic_set_eoi_cb(void (*eoi)(void)) -{ - struct apic **drv; - - for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { - /* Should happen once for each apic */ - WARN_ON((*drv)->eoi == eoi); - (*drv)->eoi = eoi; - } -} --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -332,7 +332,7 @@ static void kvm_register_steal_time(void static DEFINE_PER_CPU_DECRYPTED(unsigned long, kvm_apic_eoi) = KVM_PV_EOI_DISABLED; -static notrace void kvm_guest_apic_eoi_write(void) +static notrace __maybe_unused void kvm_guest_apic_eoi_write(void) { /** * This relies on __test_and_clear_bit to modify the memory @@ -825,7 +825,7 @@ static void __init kvm_guest_init(void) } if (kvm_para_has_feature(KVM_FEATURE_PV_EOI)) - apic_set_eoi_cb(kvm_guest_apic_eoi_write); + apic_update_callback(eoi, kvm_guest_apic_eoi_write); if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF_INT) && kvmapf) { static_branch_enable(&kvm_async_pf_enabled); From patchwork Tue Aug 1 10:47:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129194 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2595658vqg; Tue, 1 Aug 2023 04:17:30 -0700 (PDT) X-Google-Smtp-Source: APBJJlGImMOMmltQXzQ7J9K8ktsHAHVWxfEfJsLnZRkBsU4+RSUi4rn8Y7QzrJVapRprt2Etm8eu X-Received: by 2002:a05:6a20:938a:b0:133:8784:15f7 with SMTP id x10-20020a056a20938a00b00133878415f7mr13965979pzh.14.1690888650076; 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Mark snp_set_wakeup_secondary_cpu() and kvm_setup_pv_ipi() __init, as they are only invoked from init code and otherwise trigger a section mismatch as they are now invoking a __init function. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- V2: Mark snp_set_wakeup_secondary_cpu() and kvm_setup_pv_ipi() __init. --- arch/x86/hyperv/hv_apic.c | 20 ++++++++++---------- arch/x86/kernel/kvm.c | 6 +++--- arch/x86/kernel/sev.c | 4 ++-- 3 files changed, 15 insertions(+), 15 deletions(-) --- a/arch/x86/hyperv/hv_apic.c +++ b/arch/x86/hyperv/hv_apic.c @@ -288,12 +288,12 @@ void __init hv_apic_init(void) */ orig_apic = *apic; - apic->send_IPI = hv_send_ipi; - apic->send_IPI_mask = hv_send_ipi_mask; - apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself; - apic->send_IPI_allbutself = hv_send_ipi_allbutself; - apic->send_IPI_all = hv_send_ipi_all; - apic->send_IPI_self = hv_send_ipi_self; + apic_update_callback(send_IPI, hv_send_ipi); + apic_update_callback(send_IPI_mask, hv_send_ipi_mask); + apic_update_callback(send_IPI_mask_allbutself, hv_send_ipi_mask_allbutself); + apic_update_callback(send_IPI_allbutself, hv_send_ipi_allbutself); + apic_update_callback(send_IPI_all, hv_send_ipi_all); + apic_update_callback(send_IPI_self, hv_send_ipi_self); } if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) { @@ -312,10 +312,10 @@ void __init hv_apic_init(void) */ apic_update_callback(eoi, hv_apic_eoi_write); if (!x2apic_enabled()) { - apic->read = hv_apic_read; - apic->write = hv_apic_write; - apic->icr_write = hv_apic_icr_write; - apic->icr_read = hv_apic_icr_read; + apic_update_callback(read, hv_apic_read); + apic_update_callback(write, hv_apic_write); + apic_update_callback(icr_write, hv_apic_icr_write); + apic_update_callback(icr_read, hv_apic_icr_read); } } } --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -622,10 +622,10 @@ late_initcall(setup_efi_kvm_sev_migratio /* * Set the IPI entry points */ -static void kvm_setup_pv_ipi(void) +static __init void kvm_setup_pv_ipi(void) { - apic->send_IPI_mask = kvm_send_ipi_mask; - apic->send_IPI_mask_allbutself = kvm_send_ipi_mask_allbutself; + apic_update_callback(send_IPI_mask, kvm_send_ipi_mask); + apic_update_callback(send_IPI_mask_allbutself, kvm_send_ipi_mask_allbutself); pr_info("setup PV IPIs\n"); } --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1089,7 +1089,7 @@ static int wakeup_cpu_via_vmgexit(int ap return ret; } -void snp_set_wakeup_secondary_cpu(void) +void __init snp_set_wakeup_secondary_cpu(void) { if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) return; @@ -1099,7 +1099,7 @@ void snp_set_wakeup_secondary_cpu(void) * required method to start APs under SNP. If the hypervisor does * not support AP creation, then no APs will be started. */ - apic->wakeup_secondary_cpu = wakeup_cpu_via_vmgexit; + apic_update_callback(wakeup_secondary_cpu, wakeup_cpu_via_vmgexit); } int __init sev_es_setup_ap_jump_table(struct real_mode_header *rmh) From patchwork Tue Aug 1 10:47:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129192 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2595226vqg; Tue, 1 Aug 2023 04:16:38 -0700 (PDT) X-Google-Smtp-Source: APBJJlG6wqOEpetu1UcNpN1JyN43SXAaL+F3uVMU741Y3IdJoN5/WiH210j7x7Ht0b9Iof8zBKq7 X-Received: by 2002:a17:90a:9bc4:b0:268:d1a4:9092 with SMTP id b4-20020a17090a9bc400b00268d1a49092mr3582952pjw.28.1690888597604; Tue, 01 Aug 2023 04:16:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690888597; cv=none; d=google.com; s=arc-20160816; b=AXH6OwzkDij7hE26r76wDXkvB6ifn04KM8AVfrVe5rAL9Tb994txl1NjwfzeU4YoBb 1Yyly9UowRoueYVeW9f3qeIjTDZBUEaTsMkUjkcOoE0oBzMP6vD8NbvsNAfs8tXldw/v T2QxzPACgk9HzOMuzKRh30mOhorjYlv/XUWbqd0mMiw9buDHOUdv2qaPuzyLYBkG4rcC UTmCiHpDN5QVM7oY/+GMRpFiwYZqDFylJyLoemxq5jGUkttn+0eHtJedD62i8lc8VNTM kVJX40Z2o7vBxHzCr46ECwNa/BNA5sB+gy9PL1Cism9khT5iuiH0ZoWWXA9GjaFALMcX eo0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=rpTRjlnnjgf8oYcfpsFvRp74BGzYvWPgVxB1Kwz9Sb8=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=LW6h/ejPBMpBn/C63Y6SSWdZU+iBgOugrSXX8u0J8wFhCk9JQC2Mou2QlnQLpl4TdZ 2OPP9CfU6cbeH7Bqyo/DSi6bHDbXGdsgqpEwjazzpgX4HGL9amziskCsVGL2kcKP31sf Wh4DnnqxF2M+w152SqcbdPzAzt6ON89z40V2zhsgN3IyYBqWPRgv9EI3IJzmee+M/xF+ MO4ue8zoIMtbchSrl4r0nIvOICN3ChHDVOxAzjbcRqYEhCg91XtAVNiRxRDA/mDWjVJB SUpKrpu+JtAz2n6yq4ttTBxK04MU/8Fpb17Drj+2Z91srAiBMzizzlYeVmc8/PrHYthg Rs4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=b6UmIyWp; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=r+PBtLoZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id oc17-20020a17090b1c1100b0025be132d177si10829138pjb.60.2023.08.01.04.16.24; Tue, 01 Aug 2023 04:16:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=b6UmIyWp; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=r+PBtLoZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234240AbjHAKwW (ORCPT + 99 others); Tue, 1 Aug 2023 06:52:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230026AbjHAKva (ORCPT ); Tue, 1 Aug 2023 06:51:30 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5383E2D42 for ; Tue, 1 Aug 2023 03:49:04 -0700 (PDT) Message-ID: <20230801103818.214469342@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886870; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rpTRjlnnjgf8oYcfpsFvRp74BGzYvWPgVxB1Kwz9Sb8=; b=b6UmIyWp7JRa3iyD8EaaXENlR2Wrt6psOarGkTEb2TK22UeAXMgwQwcq8h8t03fv0I2C+D IoeacXSH2ZVimObm/LrTcjzdNwhvetGBcpX9cyQEY5sYYGlGjnl6yqbPqlCeVwSYoP9X/l iGOlvDzc31DPS6LEonkItVK6TLlPJSFD0MUOeTWjxN2xozgZeGWrtP/lOp4NnwjYMeJk66 xRIL6jRFy4cAvIdRvgrBeBp2tVlBuqW8tM9teQiCrKQ01E0hJGQVLEx7Gtmu7mZzhZkP/y cG1O4LK+x2u/mkgD3YSVOC0TEhjllRbm21/nUDf8HCAjL8WIF4HujNFr/D4BAg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886870; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rpTRjlnnjgf8oYcfpsFvRp74BGzYvWPgVxB1Kwz9Sb8=; b=r+PBtLoZFsOTPQkwISDyGcQeGOmDZpoFit4aBnN7GTjjPPz2dGJwRJq1bortUs+c+AZaN0 EP5lDTGhc8PU2VCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 56/60] x86/xen/apic: Mark apic __ro_after_init References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:50 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773025202321742836 X-GMAIL-MSGID: 1773025202321742836 Nothing can change it post init. Remove the 32bit callbacks and comments as XENPV is strictly 64bit. While at it mop up the whitespace damage which causes eyebleed due to an editor which is highlighting it. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) Cc: Juergen Gross --- arch/x86/xen/apic.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -123,43 +123,41 @@ static int xen_cpu_present_to_apicid(int return BAD_APICID; } -static struct apic xen_pv_apic = { - .name = "Xen PV", - .probe = xen_apic_probe_pv, +static struct apic xen_pv_apic __ro_after_init = { + .name = "Xen PV", + .probe = xen_apic_probe_pv, .acpi_madt_oem_check = xen_madt_oem_check, /* .delivery_mode and .dest_mode_logical not used by XENPV */ .disable_esr = 0, - .check_apicid_used = default_check_apicid_used, /* Used on 32-bit */ - .ioapic_phys_id_map = default_ioapic_phys_id_map, /* Used on 32-bit */ .cpu_present_to_apicid = xen_cpu_present_to_apicid, .phys_pkg_id = xen_phys_pkg_id, /* detect_ht */ .max_apic_id = UINT_MAX, - .get_apic_id = xen_get_apic_id, - .set_apic_id = xen_set_apic_id, /* Can be NULL on 32-bit. */ + .get_apic_id = xen_get_apic_id, + .set_apic_id = xen_set_apic_id, .calc_dest_apicid = apic_flat_calc_apicid, #ifdef CONFIG_SMP - .send_IPI_mask = xen_send_IPI_mask, - .send_IPI_mask_allbutself = xen_send_IPI_mask_allbutself, - .send_IPI_allbutself = xen_send_IPI_allbutself, - .send_IPI_all = xen_send_IPI_all, - .send_IPI_self = xen_send_IPI_self, + .send_IPI_mask = xen_send_IPI_mask, + .send_IPI_mask_allbutself = xen_send_IPI_mask_allbutself, + .send_IPI_allbutself = xen_send_IPI_allbutself, + .send_IPI_all = xen_send_IPI_all, + .send_IPI_self = xen_send_IPI_self, #endif .read = xen_apic_read, .write = xen_apic_write, .eoi = xen_apic_eoi, - .icr_read = xen_apic_icr_read, - .icr_write = xen_apic_icr_write, + .icr_read = xen_apic_icr_read, + .icr_write = xen_apic_icr_write, }; +apic_driver(xen_pv_apic); void __init xen_init_apic(void) { x86_apic_ops.io_apic_read = xen_io_apic_read; } -apic_driver(xen_pv_apic); From patchwork Tue Aug 1 10:47:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129229 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2611863vqg; Tue, 1 Aug 2023 04:52:21 -0700 (PDT) X-Google-Smtp-Source: APBJJlHD7PzoQ0HcpZj+2VrXh5As0gXbrIOByK/2AgNyz5MXH5ia0fraS19Vm3jj1lWamTTxxJIS X-Received: by 2002:a05:6512:32a9:b0:4f9:5781:8628 with SMTP id q9-20020a05651232a900b004f957818628mr1862839lfe.24.1690890740886; Tue, 01 Aug 2023 04:52:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690890740; cv=none; d=google.com; s=arc-20160816; b=uy1yl6lNvubcJO43xrxAj1o0oIbheevmHo2lkUOAzZ9Hx1DpFtmVUmJUWf+1wH/dUb qpD/n4BuZKfUcBgtiwiPGcFpRImBgsBMJs8TnVSTHKsYV50TkY/TC6yz5MV74mAGY0Uw DBCgKxqHFzo6GkVNQzlDEBj5cxgUxK78MHNDlnFBLrynUsxZEdRfNzNueyeOrv7zs2Nq sQxm7x0MLK+z+Oc7f+ECkGy9DkaV6fZZgKtETk5Z2cL5qOgX82MfyuFMobqaQgKCRy5w jNajtMrAuvTrxCltLuPgDcPgu77q3APyzBOU4amhcrIQItlYPE3bqGdOSfWhweIcpFL7 UVyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=ughx6myInj7tBGUgtVNaK0CKBD3pdVmOGF8WRhhzTa4=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=yKBLXPWgvwAxH1U6C4kOx9OCMsdhk/51MN1/QMYsihc1BadqVft0X5j8jWoXpnz/Bz OUR+FDLee1yjjq4Gs9SPx0Ynb1UfcMJ1CQwMgmEzmePeRPPyGxaEc2vA1N5Up6sJcsE3 MkHOT7SMcHUG8xh/jZBNEq6eUJKGZ7GyIbe/3yKVgTL3Xc/tnSiidSEpFNFsT3gJv3uU NAisoRhGLOnIcFntBhDjoK5jA4/AyxVnWni25C63XxxJamp81EUwniLO5cflSWfHm8ZN pYaH68jGGcQd07ns9VHd1fZ7ug+cc4R/zk7UyyLFmvVsTk/RHSq7eG848yu5w2Fr8xlI KQ/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=rHSLn+ir; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o7-20020a056402038700b0052228a17401si7885335edv.381.2023.08.01.04.51.57; Tue, 01 Aug 2023 04:52:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=rHSLn+ir; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233956AbjHAKwr (ORCPT + 99 others); Tue, 1 Aug 2023 06:52:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234234AbjHAKwB (ORCPT ); Tue, 1 Aug 2023 06:52:01 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B000A30D5 for ; Tue, 1 Aug 2023 03:49:21 -0700 (PDT) Message-ID: <20230801103818.269222348@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690886871; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ughx6myInj7tBGUgtVNaK0CKBD3pdVmOGF8WRhhzTa4=; b=rHSLn+iroDKBNUKXtw9pPhYsqrmzkwUqLvllzlu3roeIo8eKUELgVIyowKOgpjhQ5ahzU2 SiqULSqtGRWtA+NsHCojvMHt+mQR8qArElm+gcZJwEe326cPQs4vmEtPw/+E2D9ulakNln Erkfx1ebufHlpLZAwbZN4bZ4SbRpOL3KGen8flRCVefaPZqk9xDqHAeaP2vS7TuSydjGfH W7oMsCHJW9MaMihU4w5P/dpRy1BdvIZC2rLroPZ2ZFGJCSHyl1+/Crl1T5V6oZFixlLTNP S9nzhXY9qE4d+rYbycur740ZJ19zyugcho4QPp59BJSg5EUy9Aiqq6iiuewRtA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690886871; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ughx6myInj7tBGUgtVNaK0CKBD3pdVmOGF8WRhhzTa4=; b=QNQIcXi9BMi/myoVMoi004UXU0lGKYIRwNMIv8DSbTRhMtYL/aANXjaSlmBbiyCf6XA2bN 1GbnopHshC91y3AQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V3 57/60] x86/apic: Mark all hotpath APIC callback wrappers __always_inline References: <20230801103042.936020332@linutronix.de> MIME-Version: 1.0 Date: Tue, 1 Aug 2023 12:47:51 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773027449637945688 X-GMAIL-MSGID: 1773027449637945688 There is no value for instrumentation to look at those wrappers and with the upcoming conversion to static calls even less so. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -371,48 +371,48 @@ void __init apic_install_driver(struct a pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \ } -static inline u32 apic_read(u32 reg) +static __always_inline u32 apic_read(u32 reg) { return apic->read(reg); } -static inline void apic_write(u32 reg, u32 val) +static __always_inline void apic_write(u32 reg, u32 val) { apic->write(reg, val); } -static inline void apic_eoi(void) +static __always_inline void apic_eoi(void) { apic->eoi(); } -static inline void apic_native_eoi(void) +static __always_inline void apic_native_eoi(void) { apic->native_eoi(); } -static inline u64 apic_icr_read(void) +static __always_inline u64 apic_icr_read(void) { return apic->icr_read(); } -static inline void apic_icr_write(u32 low, u32 high) +static __always_inline void apic_icr_write(u32 low, u32 high) { apic->icr_write(low, high); } -static inline void apic_wait_icr_idle(void) +static __always_inline void apic_wait_icr_idle(void) { if (apic->wait_icr_idle) apic->wait_icr_idle(); } -static inline u32 safe_apic_wait_icr_idle(void) +static __always_inline u32 safe_apic_wait_icr_idle(void) { return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; } -static inline bool apic_id_valid(u32 apic_id) +static __always_inline bool apic_id_valid(u32 apic_id) { return apic_id <= apic->max_apic_id; } From patchwork Tue Aug 1 10:47:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129260 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2635104vqg; Tue, 1 Aug 2023 05:32:37 -0700 (PDT) X-Google-Smtp-Source: APBJJlGdpp1y0v2ShAv4d0DTXsw2DFhyTmOnnwUJAhJSbTuECrHzmlDDq4t7rNMgQcpxDMx/L1VD X-Received: by 2002:a17:907:1dce:b0:99b:bbe:e232 with SMTP id og14-20020a1709071dce00b0099b0bbee232mr2492950ejc.68.1690893156738; Tue, 01 Aug 2023 05:32:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893156; cv=none; d=google.com; s=arc-20160816; b=XbEIHL4i33cVOLSjSSqJJPQKm64cCkaHtG6PygTCTQBy6Zqh0QMs1ZmnbdgTAWgXWM Vx+Pla4n4KSOhHqvJCKa3Wudiv2Q8tAYpHWV/CenCetMJc5qtFbAMIiZqjPMPirngcNw W7nJpCsoLmjsykb+JbhRbHjBpuCDLA8hEAqSZHG6pu7ClIUL7b9kNZ7wixFhSvC1/PB7 IPwEI/WNLnRPJdLk2efqILP649SWShZ2+YnwdbSkkb5LjH7AvOw6b1258q+Y6OEcwkyv b4X51fdfwCU4ahVO7eiHs4XbrJJEQhkYUY0Pgh0rcZfFkMzYx72IMr9VtddohNPgcUFn Izcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=MV6Y606SVssEQVKgDvP1PL7mW4j5AtallYXi4hZ7gRY=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=BsZlXgo7n5YiBZoWxHbQPf0TdX0WgV401mgc3NyAb3dsBfcCMu4vbbjjBi9sOX8ykY f+xLif+Gx8Y5KNKPq68SKyqyUVX3PEIucWTttHvtC5En6Dvt6TjAgQNx9BfRZIGwIr99 73bXzMFaCPCpmQ/ldqk0kRqdxPxHLwy3HlhmVbkmLGEGjfRHyj9Yh+3sDuskJ1qPY/od 5ZY9TD6ESaiEdW2lKyA/Uh9eIQzgKerTjkKXR5DWvefbdSIXiyVjfplJQOSl5pENhbrT O6aBQsilTyOSMIoohNQVfdeKhw+rgJIx/VLYw2WO5Sy0Bu+K+eSngfdPmyZW/P6BC/ku kv2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=DJ8JAggR; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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No functional change. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/hyperv/hv_spinlock.c | 2 +- arch/x86/include/asm/apic.h | 30 ++++++++++++++++++++++++++++++ arch/x86/kernel/apic/apic.c | 2 +- arch/x86/kernel/apic/hw_nmi.c | 4 +++- arch/x86/kernel/apic/ipi.c | 16 ++++++++-------- arch/x86/kernel/apic/vector.c | 6 +++--- arch/x86/kernel/cpu/mce/inject.c | 3 +-- arch/x86/kernel/irq_work.c | 2 +- arch/x86/kernel/nmi_selftest.c | 2 +- arch/x86/kernel/smp.c | 2 +- arch/x86/kvm/vmx/posted_intr.c | 2 +- arch/x86/kvm/vmx/vmx.c | 2 +- arch/x86/platform/uv/uv_nmi.c | 2 +- 13 files changed, 53 insertions(+), 22 deletions(-) --- a/arch/x86/hyperv/hv_spinlock.c +++ b/arch/x86/hyperv/hv_spinlock.c @@ -20,7 +20,7 @@ static bool __initdata hv_pvspin = true; static void hv_qlock_kick(int cpu) { - apic->send_IPI(cpu, X86_PLATFORM_IPI_VECTOR); + __apic_send_IPI(cpu, X86_PLATFORM_IPI_VECTOR); } static void hv_qlock_wait(u8 *byte, u8 val) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -401,6 +401,36 @@ static __always_inline void apic_icr_wri apic->icr_write(low, high); } +static __always_inline void __apic_send_IPI(int cpu, int vector) +{ + apic->send_IPI(cpu, vector); +} + +static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector) +{ + apic->send_IPI_mask(mask, vector); +} + +static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) +{ + apic->send_IPI_mask_allbutself(mask, vector); +} + +static __always_inline void __apic_send_IPI_allbutself(int vector) +{ + apic->send_IPI_allbutself(vector); +} + +static __always_inline void __apic_send_IPI_all(int vector) +{ + apic->send_IPI_all(vector); +} + +static __always_inline void __apic_send_IPI_self(int vector) +{ + apic->send_IPI_self(vector); +} + static __always_inline void apic_wait_icr_idle(void) { if (apic->wait_icr_idle) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -502,7 +502,7 @@ static int lapic_timer_set_oneshot(struc static void lapic_timer_broadcast(const struct cpumask *mask) { #ifdef CONFIG_SMP - apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); + __apic_send_IPI_mask(mask, LOCAL_TIMER_VECTOR); #endif } --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -21,6 +21,8 @@ #include #include +#include "local.h" + #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF u64 hw_nmi_get_sample_period(int watchdog_thresh) { @@ -31,7 +33,7 @@ u64 hw_nmi_get_sample_period(int watchdo #ifdef arch_trigger_cpumask_backtrace static void nmi_raise_cpu_backtrace(cpumask_t *mask) { - apic->send_IPI_mask(mask, NMI_VECTOR); + __apic_send_IPI_mask(mask, NMI_VECTOR); } void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -54,9 +54,9 @@ void apic_send_IPI_allbutself(unsigned i return; if (static_branch_likely(&apic_use_ipi_shorthand)) - apic->send_IPI_allbutself(vector); + __apic_send_IPI_allbutself(vector); else - apic->send_IPI_mask_allbutself(cpu_online_mask, vector); + __apic_send_IPI_mask_allbutself(cpu_online_mask, vector); } /* @@ -70,12 +70,12 @@ void native_smp_send_reschedule(int cpu) WARN(1, "sched: Unexpected reschedule of offline CPU#%d!\n", cpu); return; } - apic->send_IPI(cpu, RESCHEDULE_VECTOR); + __apic_send_IPI(cpu, RESCHEDULE_VECTOR); } void native_send_call_func_single_ipi(int cpu) { - apic->send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR); + __apic_send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR); } void native_send_call_func_ipi(const struct cpumask *mask) @@ -87,14 +87,14 @@ void native_send_call_func_ipi(const str goto sendmask; if (cpumask_test_cpu(cpu, mask)) - apic->send_IPI_all(CALL_FUNCTION_VECTOR); + __apic_send_IPI_all(CALL_FUNCTION_VECTOR); else if (num_online_cpus() > 1) - apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR); + __apic_send_IPI_allbutself(CALL_FUNCTION_VECTOR); return; } sendmask: - apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); + __apic_send_IPI_mask(mask, CALL_FUNCTION_VECTOR); } #endif /* CONFIG_SMP */ @@ -221,7 +221,7 @@ void default_send_IPI_mask_allbutself_ph */ void default_send_IPI_single(int cpu, int vector) { - apic->send_IPI_mask(cpumask_of(cpu), vector); + __apic_send_IPI_mask(cpumask_of(cpu), vector); } void default_send_IPI_allbutself(int vector) --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -876,7 +876,7 @@ static int apic_retrigger_irq(struct irq unsigned long flags; raw_spin_lock_irqsave(&vector_lock, flags); - apic->send_IPI(apicd->cpu, apicd->vector); + __apic_send_IPI(apicd->cpu, apicd->vector); raw_spin_unlock_irqrestore(&vector_lock, flags); return 1; @@ -958,7 +958,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_irq_move_c */ irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); if (irr & (1U << (vector % 32))) { - apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); + __apic_send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); continue; } free_moved_vector(apicd); @@ -976,7 +976,7 @@ static void __send_cleanup_vector(struct cpu = apicd->prev_cpu; if (cpu_online(cpu)) { hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); - apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); + __apic_send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); } else { apicd->prev_vector = 0; } --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -270,8 +270,7 @@ static void __maybe_unused raise_mce(str mce_irq_ipi, NULL, 0); preempt_enable(); } else if (m->inject_flags & MCJ_NMI_BROADCAST) - apic->send_IPI_mask(mce_inject_cpumask, - NMI_VECTOR); + __apic_send_IPI_mask(mce_inject_cpumask, NMI_VECTOR); } start = jiffies; while (!cpumask_empty(mce_inject_cpumask)) { --- a/arch/x86/kernel/irq_work.c +++ b/arch/x86/kernel/irq_work.c @@ -28,7 +28,7 @@ void arch_irq_work_raise(void) if (!arch_irq_work_has_interrupt()) return; - apic->send_IPI_self(IRQ_WORK_VECTOR); + __apic_send_IPI_self(IRQ_WORK_VECTOR); apic_wait_icr_idle(); } #endif --- a/arch/x86/kernel/nmi_selftest.c +++ b/arch/x86/kernel/nmi_selftest.c @@ -75,7 +75,7 @@ static void __init test_nmi_ipi(struct c /* sync above data before sending NMI */ wmb(); - apic->send_IPI_mask(mask, NMI_VECTOR); + __apic_send_IPI_mask(mask, NMI_VECTOR); /* Don't wait longer than a second */ timeout = USEC_PER_SEC; --- a/arch/x86/kernel/smp.c +++ b/arch/x86/kernel/smp.c @@ -237,7 +237,7 @@ static void native_stop_other_cpus(int w pr_emerg("Shutting down cpus with NMI\n"); for_each_cpu(cpu, &cpus_stop_mask) - apic->send_IPI(cpu, NMI_VECTOR); + __apic_send_IPI(cpu, NMI_VECTOR); } /* * Don't wait longer than 10 ms if the caller didn't --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -175,7 +175,7 @@ static void pi_enable_wakeup_handler(str * scheduled out). */ if (pi_test_on(&new)) - apic->send_IPI_self(POSTED_INTR_WAKEUP_VECTOR); + __apic_send_IPI_self(POSTED_INTR_WAKEUP_VECTOR); local_irq_restore(flags); } --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4144,7 +4144,7 @@ static inline void kvm_vcpu_trigger_post */ if (vcpu != kvm_get_running_vcpu()) - apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); + __apic_send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); return; } #endif --- a/arch/x86/platform/uv/uv_nmi.c +++ b/arch/x86/platform/uv/uv_nmi.c @@ -601,7 +601,7 @@ static void uv_nmi_nr_cpus_ping(void) for_each_cpu(cpu, uv_nmi_cpu_mask) uv_cpu_nmi_per(cpu).pinging = 1; - apic->send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI); + __apic_send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI); } /* Clean up flags for CPU's that ignored both NMI and ping */ From patchwork Tue Aug 1 10:47:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129223 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2609049vqg; Tue, 1 Aug 2023 04:46:04 -0700 (PDT) X-Google-Smtp-Source: APBJJlENfAQSJYyrlmQomXe1jCXFjyzSQzuEAi4LK66b9rBrI5mRS9n0WJmXFdtmEDlfgitW6ZJJ X-Received: by 2002:a17:906:53d3:b0:99b:f534:9bb6 with SMTP id p19-20020a17090653d300b0099bf5349bb6mr2422996ejo.9.1690890364218; Tue, 01 Aug 2023 04:46:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690890364; cv=none; d=google.com; s=arc-20160816; b=OKWWTBQZnlZleRwJP3GDJV6lVy7TDx+Fhem0nHzlhieuOEiETOc/C2TZSFr3VPVPdS ruxsno8NvkVR+Emrt7wyScLgFA3rpGmXOAhyKfI5uTq6cO3TpzpzqRtj4jLwb+I6wcyR 2YllvFVAuuuWcw/QMF/elT5LgDNrNRDmQ7aDrgfm5qNVQPyf6T/0olzrVp70oIAMv3ll TKMw8BW82kS3TBiVu/IHkhs10SZioy/GOrxZDJNFvzxrrucxTXMJx5AmFZwoMzLPSMG6 S+3YvMQ/pbGcgpqXQYmsQ3gyJ9z3UIpgGtBVdTjQ/QeccpYk34UvzBWjWCaeImRWCoeh UpyQ== ARC-Message-Signature: i=1; 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Note this deliberately uses STATIC_CALL_NULL() because otherwise it would be required to have the definitions in the 32bit and the 64bit default APIC implementations and it's hard to keep the calls in sync. The other option would be to have stub functions for each callback type. Not pretty either So the NULL capable calls are used and filled in during early boot after the static key infrastructure has been initialized. The calls will be static_call() except for the wait_irc_idle() callback which is valid to be NULL for X2APIC systems. Update the calls when a new APIC driver is installed and when a callback override is invoked. Export the trampolines for the two calls which are used in KVM and MCE error inject modules. Test the setup and let the next step convert the inline wrappers to make it effective. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 21 +++++++++++++++++ arch/x86/kernel/apic/init.c | 53 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -3,6 +3,7 @@ #define _ASM_X86_APIC_H #include +#include #include #include @@ -368,9 +369,29 @@ void __init apic_install_driver(struct a #define apic_update_callback(_callback, _fn) { \ __x86_apic_override._callback = _fn; \ apic->_callback = _fn; \ + static_call_update(apic_call_##_callback, _fn); \ pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \ } +#define DECLARE_APIC_CALL(__cb) \ + DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb) + +DECLARE_APIC_CALL(eoi); +DECLARE_APIC_CALL(native_eoi); +DECLARE_APIC_CALL(icr_read); +DECLARE_APIC_CALL(icr_write); +DECLARE_APIC_CALL(read); +DECLARE_APIC_CALL(send_IPI); +DECLARE_APIC_CALL(send_IPI_mask); +DECLARE_APIC_CALL(send_IPI_mask_allbutself); +DECLARE_APIC_CALL(send_IPI_allbutself); +DECLARE_APIC_CALL(send_IPI_all); +DECLARE_APIC_CALL(send_IPI_self); +DECLARE_APIC_CALL(wait_icr_idle); +DECLARE_APIC_CALL(wakeup_secondary_cpu); +DECLARE_APIC_CALL(wakeup_secondary_cpu_64); +DECLARE_APIC_CALL(write); + static __always_inline u32 apic_read(u32 reg) { return apic->read(reg); --- a/arch/x86/kernel/apic/init.c +++ b/arch/x86/kernel/apic/init.c @@ -5,6 +5,34 @@ #include "local.h" +/* + * Use DEFINE_STATIC_CALL_NULL() to avoid having to provide stub functions + * for each callback. The callbacks are setup during boot and all except + * wait_icr_idle() must be initialized before usage. The IPI wrappers + * use static_call() and not static_call_cond() to catch any fails. + */ +#define DEFINE_APIC_CALL(__cb) \ + DEFINE_STATIC_CALL_NULL(apic_call_##__cb, *apic->__cb) + +DEFINE_APIC_CALL(eoi); +DEFINE_APIC_CALL(native_eoi); +DEFINE_APIC_CALL(icr_read); +DEFINE_APIC_CALL(icr_write); +DEFINE_APIC_CALL(read); +DEFINE_APIC_CALL(send_IPI); +DEFINE_APIC_CALL(send_IPI_mask); +DEFINE_APIC_CALL(send_IPI_mask_allbutself); +DEFINE_APIC_CALL(send_IPI_allbutself); +DEFINE_APIC_CALL(send_IPI_all); +DEFINE_APIC_CALL(send_IPI_self); +DEFINE_APIC_CALL(wait_icr_idle); +DEFINE_APIC_CALL(wakeup_secondary_cpu); +DEFINE_APIC_CALL(wakeup_secondary_cpu_64); +DEFINE_APIC_CALL(write); + +EXPORT_STATIC_CALL_TRAMP_GPL(apic_call_send_IPI_mask); +EXPORT_STATIC_CALL_TRAMP_GPL(apic_call_send_IPI_self); + /* The container for function call overrides */ struct apic_override __x86_apic_override __initdata; @@ -30,10 +58,34 @@ static __init void restore_override_call apply_override(wakeup_secondary_cpu_64); } +#define update_call(__cb) \ + static_call_update(apic_call_##__cb, *apic->__cb) + +static __init void update_static_calls(void) +{ + update_call(eoi); + update_call(native_eoi); + update_call(write); + update_call(read); + update_call(send_IPI); + update_call(send_IPI_mask); + update_call(send_IPI_mask_allbutself); + update_call(send_IPI_allbutself); + update_call(send_IPI_all); + update_call(send_IPI_self); + update_call(icr_read); + update_call(icr_write); + update_call(wait_icr_idle); + update_call(wakeup_secondary_cpu); + update_call(wakeup_secondary_cpu_64); +} + void __init apic_setup_apic_calls(void) { /* Ensure that the default APIC has native_eoi populated */ apic->native_eoi = apic->eoi; + update_static_calls(); + pr_info("Static calls initialized\n"); } void __init apic_install_driver(struct apic *driver) @@ -52,6 +104,7 @@ void __init apic_install_driver(struct a /* Apply any already installed callback overrides */ restore_override_callbacks(); + update_static_calls(); pr_info("Switched APIC routing to: %s\n", driver->name); } From patchwork Tue Aug 1 10:47:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 129248 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2623139vqg; Tue, 1 Aug 2023 05:11:14 -0700 (PDT) X-Google-Smtp-Source: APBJJlHLuDMrIPSL4W8/PSmsbsWLgSxoVzQ6f9DEadoIZh3fY2aEv4DPWKi6svxon4RgLPMViLbI X-Received: by 2002:a05:6512:214a:b0:4f8:631b:bf77 with SMTP id s10-20020a056512214a00b004f8631bbf77mr2055717lfr.22.1690891874342; Tue, 01 Aug 2023 05:11:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690891874; cv=none; d=google.com; s=arc-20160816; b=dZMLZ4rr7vs2LA+KPSPsAPEcB/DHl6qxLdBewYVxe9jFtjk3N6QcxMkXlaYSEkRGob iqWINPnghZmcpEYiB9P5PRRM3drhUF+qy2fyvSCAO7uQiIyfByg7UuOGQtVIFK8U2b6U EhT+tz4WXE7ZsH/N+17CqXPswnApkK7eK7+1/22biPB1+8FjHI95kBid+TEsfxAdIBm0 Tl2aT64b7ilqXBZqdbMLKHvsweYnq/S9F9aDU71lkLuTkDcUZa5knXgjfxqsRaaPlhS9 VXArqDzx89j/ZWgsi99pQy04QzNaSkv4QYuhak0XdogBD5TzHuJ72AMA0XJx4pqC/irU A5vQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=4thjqk06PAC51pOMOTPF8ETngeGfrVOo3TNMYdEenIA=; fh=mE3iieUIZLcDfOLIULj9X6/p0bMDPZGFSVRsnyRUnTc=; b=JJWOsl9bLp2cJUQZPlJPVmEPE3A4aHzgkbzSwZmDDVvhKNbpa1COg+etCS8w63OYfp 6MJslD4pZdiCctQVc4rkQRWgI2eEHw9Vi4EH4GjlHH2RDLKa7e56JqgQ1P1BakDZY1Zo b0retS2BV5nIBjtWsINabT/Q89ucaCxGzoeh9GzDJt6mcXwJlRSQ9Bs9NncM1Sh0+MZT vbvmsiCvCdFVSOzymsEc4A8UxaQF6FOvxWyRjTYMLHpCXQnworRSE52M+Zx4j/YjrDHr 4oWhmNgj1y8gozZ1q/j/Ax0Vcs8PeOPHEwwXsYDclLjdjdZZIocTl1t7yNS9Oq8lbtP2 WxYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=hYq2NTJt; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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That really can do the conditional callback. The regular wait_icr_idle() matters as it is used in irq_work_raise(), so X2APIC machines spare the conditional. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -394,68 +394,67 @@ DECLARE_APIC_CALL(write); static __always_inline u32 apic_read(u32 reg) { - return apic->read(reg); + return static_call(apic_call_read)(reg); } static __always_inline void apic_write(u32 reg, u32 val) { - apic->write(reg, val); + static_call(apic_call_write)(reg, val); } static __always_inline void apic_eoi(void) { - apic->eoi(); + static_call(apic_call_eoi)(); } static __always_inline void apic_native_eoi(void) { - apic->native_eoi(); + static_call(apic_call_native_eoi)(); } static __always_inline u64 apic_icr_read(void) { - return apic->icr_read(); + return static_call(apic_call_icr_read)(); } static __always_inline void apic_icr_write(u32 low, u32 high) { - apic->icr_write(low, high); + static_call(apic_call_icr_write)(low, high); } static __always_inline void __apic_send_IPI(int cpu, int vector) { - apic->send_IPI(cpu, vector); + static_call(apic_call_send_IPI)(cpu, vector); } static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector) { - apic->send_IPI_mask(mask, vector); + static_call_mod(apic_call_send_IPI_mask)(mask, vector); } static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) { - apic->send_IPI_mask_allbutself(mask, vector); + static_call(apic_call_send_IPI_mask_allbutself)(mask, vector); } static __always_inline void __apic_send_IPI_allbutself(int vector) { - apic->send_IPI_allbutself(vector); + static_call(apic_call_send_IPI_allbutself)(vector); } static __always_inline void __apic_send_IPI_all(int vector) { - apic->send_IPI_all(vector); + static_call(apic_call_send_IPI_all)(vector); } static __always_inline void __apic_send_IPI_self(int vector) { - apic->send_IPI_self(vector); + static_call_mod(apic_call_send_IPI_self)(vector); } static __always_inline void apic_wait_icr_idle(void) { - if (apic->wait_icr_idle) - apic->wait_icr_idle(); + static_call_cond(apic_call_wait_icr_idle)(); } static __always_inline u32 safe_apic_wait_icr_idle(void)