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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ay21-20020a170906d29500b0099bca8453f0si8240167ejb.764.2023.07.31.23.49.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 23:49:53 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=KSLdTVJ5; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6C98C3857352 for ; Tue, 1 Aug 2023 06:49:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6C98C3857352 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690872570; bh=hkFxpF8PAspg9SM0ZdiPOY3YMe7573KBcCsbeeDeYQ8=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=KSLdTVJ5IyXPaihgF83ZcKQ96iMwbuAkIB7slKSoRCk80Z+GNFWb8OABpeQPxWN9V oDhBXJXO3xBCQ5Bugohjkof42WKL3wMuP6ENgRbjRmsiuSwbInPLVLKdtHVfqwbjU8 m15S1M8x0bAiXLsrKJQZgrQ7Vxd96Y1BmPqhjAtQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (unknown [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id DD09338582BC for ; Tue, 1 Aug 2023 06:48:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DD09338582BC X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="400163370" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="400163370" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2023 23:48:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="1059274291" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="1059274291" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga005.fm.intel.com with ESMTP; 31 Jul 2023 23:48:33 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1CD7F100514A; Tue, 1 Aug 2023 14:48:33 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFSUB and VFRSUB rounding mode intrinsic API Date: Tue, 1 Aug 2023 14:48:31 +0800 Message-Id: <20230801064831.3261727-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773008420531937804 X-GMAIL-MSGID: 1773008420531937804 From: Pan Li This patch would like to support the rounding mode API for both the VFSUB and VFRSUB as below samples. * __riscv_vfsub_vv_f32m1_rm * __riscv_vfsub_vv_f32m1_rm_m * __riscv_vfsub_vf_f32m1_rm * __riscv_vfsub_vf_f32m1_rm_m * __riscv_vfrsub_vf_f32m1_rm * __riscv_vfrsub_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class reverse_binop_frm): Add new template for reversed frm. (vfsub_frm_obj): New obj. (vfrsub_frm_obj): Likewise. * config/riscv/riscv-vector-builtins-bases.h: (vfsub_frm): New declaration. (vfrsub_frm): Likewise. * config/riscv/riscv-vector-builtins-functions.def (vfsub_frm): New function define. (vfrsub_frm): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-rsub.c: New test. * gcc.target/riscv/rvv/base/float-point-single-sub.c: New test. Signed-off-by: Pan Li --- .../riscv/riscv-vector-builtins-bases.cc | 21 +++++++++++++ .../riscv/riscv-vector-builtins-bases.h | 2 ++ .../riscv/riscv-vector-builtins-functions.def | 3 ++ .../riscv/rvv/base/float-point-single-rsub.c | 19 ++++++++++++ .../riscv/rvv/base/float-point-single-sub.c | 30 +++++++++++++++++++ 5 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 316b35b57c8..035cafc43b3 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -298,6 +298,23 @@ public: } }; +/* Implements below instructions for frm + - vfrsub +*/ +template +class reverse_binop_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + +public: + rtx expand (function_expander &e) const override + { + return e.use_exact_insn ( + code_for_pred_reverse_scalar (CODE, e.vector_mode ())); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2042,7 +2059,9 @@ static CONSTEXPR const vid vid_obj; static CONSTEXPR const binop vfadd_obj; static CONSTEXPR const binop vfsub_obj; static CONSTEXPR const binop_frm vfadd_frm_obj; +static CONSTEXPR const binop_frm vfsub_frm_obj; static CONSTEXPR const reverse_binop vfrsub_obj; +static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj; static CONSTEXPR const widen_binop vfwadd_obj; static CONSTEXPR const widen_binop vfwsub_obj; static CONSTEXPR const binop vfmul_obj; @@ -2269,7 +2288,9 @@ BASE (vid) BASE (vfadd) BASE (vfadd_frm) BASE (vfsub) +BASE (vfsub_frm) BASE (vfrsub) +BASE (vfrsub_frm) BASE (vfwadd) BASE (vfwsub) BASE (vfmul) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index e771a36adc8..5c6b239c274 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -144,7 +144,9 @@ extern const function_base *const vid; extern const function_base *const vfadd; extern const function_base *const vfadd_frm; extern const function_base *const vfsub; +extern const function_base *const vfsub_frm; extern const function_base *const vfrsub; +extern const function_base *const vfrsub_frm; extern const function_base *const vfwadd; extern const function_base *const vfwsub; extern const function_base *const vfmul; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 035c9e4252f..fa1c2cef970 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -291,6 +291,9 @@ DEF_RVV_FUNCTION (vfsub, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfrsub, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvv_ops) DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvf_ops) +DEF_RVV_FUNCTION (vfsub_frm, alu_frm, full_preds, f_vvv_ops) +DEF_RVV_FUNCTION (vfsub_frm, alu_frm, full_preds, f_vvf_ops) +DEF_RVV_FUNCTION (vfrsub_frm, alu_frm, full_preds, f_vvf_ops) // 13.3. Vector Widening Floating-Point Add/Subtract Instructions DEF_RVV_FUNCTION (vfwadd, widen_alu, full_preds, f_wvv_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c new file mode 100644 index 00000000000..1d770adc32c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_vfrsub_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfrsub_vf_f32m1_rm (op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfrsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfrsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl); +} + +/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c new file mode 100644 index 00000000000..34ed03a31d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfsub_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfsub_vv_f32m1_rm (op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfsub_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfsub_vv_f32m1_rm_m (mask, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfsub_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfsub_vf_f32m1_rm (op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl); +} + +/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */