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[83.9.30.53]) by smtp.gmail.com with ESMTPSA id ep28-20020a056512485c00b004fe1bac4080sm2024882lfb.222.2023.07.31.12.21.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 12:21:37 -0700 (PDT) From: Konrad Dybcio Date: Mon, 31 Jul 2023 21:21:32 +0200 Subject: [PATCH v2 1/2] dt-bindings: clock: qcom,sm8350-videocc: Add SC8280XP MIME-Version: 1.0 Message-Id: <20230703-topic-8280_videocc-v2-1-c88269806269@linaro.org> References: <20230703-topic-8280_videocc-v2-0-c88269806269@linaro.org> In-Reply-To: <20230703-topic-8280_videocc-v2-0-c88269806269@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690831295; l=908; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=09vaheOwPFgSKvoFFPC1+TxzhpnRaLHei7up05bRFww=; b=eWW9amWrxG5uiuQwj6XKg0uo9aY6AR9mGVP8x/iG039uc295/S37S4cgVj1KL+C4d8j5Brp+s lnKXQA4nY58CcHkmht1o3PFfQN9ew+5aVVk6FoC6zVfQz7iqv4hjrdI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772967546238505564 X-GMAIL-MSGID: 1772967546238505564 SC8280XP reuses the SM8350 video clock controller block, changing just a couple tunables. Docuemnt it. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml index 23505c8c3dbd..2114664978e1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml @@ -19,7 +19,9 @@ description: | properties: compatible: - const: qcom,sm8350-videocc + enum: + - qcom,sc8280xp-videocc + - qcom,sm8350-videocc clocks: items: From patchwork Mon Jul 31 19:21:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 128862 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2252667vqg; Mon, 31 Jul 2023 13:36:20 -0700 (PDT) X-Google-Smtp-Source: APBJJlG84XpRqXvaVqXqsl5DD7Wwr+QAJGgpzPH0A1sOkADQtSKfOekSClG86lxkODcCZ9NvzT46 X-Received: by 2002:a05:6402:6cf:b0:522:acfc:3138 with SMTP id n15-20020a05640206cf00b00522acfc3138mr784760edy.36.1690835780016; Mon, 31 Jul 2023 13:36:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690835780; cv=none; d=google.com; s=arc-20160816; b=n4A2vYvXCZjSwRPum91nh3vwH0M/PJXu3hURQayENrTXHlffm1CaDzmpGDF4zKwxN5 2xPyIS+iOAwaju5/lRhS9mdDRfVVOLdc2tzSaAAyPxKSkKCN++QndXfryB3JG4itEzfR +4tyNsw4L23qWjx6XC8nSxrsoQ3AixarmFhLiQ8MhN/PB9oyv5Td2ZC44AAtcDJ86jZZ JNy5L6ZYcoXRRfAwU4Nk8LTICHW77QAUajPmpJKfSQDjmScte3nfLfsSw6AG46LquE3H 9Rbo+jSsVsOTTBbnsd3e/iy1KynJwnpcJmP3bsQX+yWyOEfzuMveS9ykMRhY9Fbt7/M3 V7gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=PH18c6fQCGlXIcWcVtPWcBFP7H4EemWa9GS7wznpGb8=; fh=n1cAvN1YDzWaFO2fnTgJCG6/VjPvD1W5uX40hpWOwo4=; b=OPn3APYx+wG8a28pZnYZzAh6gmLhowPkXpdpJnAMcu6y7X8nc8GZQkJcfqkprRUKob YSHIrBxvNlSNS9/j892p9uD/i1rpuhu0t//i7/GFTFz/b93t6JIN6wzLBb8D6Qaa6RAP +4nlPTtSyDNSt5ajP30QqazFMTXun12BSNNRkxpzJqCI9QrDrnpBS31MKk4fsuchUAFo 4VR5r5SBnYmPTMAZpoxsdgjy/wCmEgYbmXFQ2NaUuUlCsrqRxGsmCFrcaS66aghHk4nj MZe0SQSTclC2/CxK9TPC0tO9uflDdCfjshJgka7zbmQqjXhgmDNk700U3fs4VZD3M2gW Jbng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UXRqATWl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.30.53]) by smtp.gmail.com with ESMTPSA id ep28-20020a056512485c00b004fe1bac4080sm2024882lfb.222.2023.07.31.12.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 12:21:38 -0700 (PDT) From: Konrad Dybcio Date: Mon, 31 Jul 2023 21:21:33 +0200 Subject: [PATCH v2 2/2] clk: qcom: videocc-sm8350: Add SC8280XP support MIME-Version: 1.0 Message-Id: <20230703-topic-8280_videocc-v2-2-c88269806269@linaro.org> References: <20230703-topic-8280_videocc-v2-0-c88269806269@linaro.org> In-Reply-To: <20230703-topic-8280_videocc-v2-0-c88269806269@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690831295; l=3984; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=o5bVSx2gpTMciO9+T8/74+UVoyE1JD3fP/a+IZWVKbg=; b=ZGbEbtkrYDpuq6H+9Oj/I0FpRhjvMeWlMmYt6iYbz989Pu2/4tIBrqVbdfNoqgOrlcN3n0E5R GpYndhxqGTAAsstEIWon11A/mBN5nw3FnYGKP6gRbJRfDik2GABlMFM X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772969818524045297 X-GMAIL-MSGID: 1772969818524045297 SC8280XP, being a partial derivative of SM8350, shares almost the exact same videocc block. Extend the 8350 driver to support the bigger brother. The only notable changes are higher possible frequencies on some clocks and some switcheroo within the XO/sleep registers (probably due to some different board crystal configuration). Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/videocc-sm8350.c | 42 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c index b148877fc73d..7246f3c99492 100644 --- a/drivers/clk/qcom/videocc-sm8350.c +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -41,6 +41,10 @@ static const struct pll_vco lucid_5lpe_vco[] = { { 249600000, 1750000000, 0 }, }; +static const struct pll_vco lucid_5lpe_vco_8280xp[] = { + { 249600000, 1800000000, 0 }, +}; + static const struct alpha_pll_config video_pll0_config = { .l = 0x25, .alpha = 0x8000, @@ -159,6 +163,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_8280xp[] = { + F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1599000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1680000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs0_clk_src = { .cmd_rcgr = 0xb94, .mnd_width = 0, @@ -181,6 +195,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_8280xp[] = { + F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1800000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs1_clk_src = { .cmd_rcgr = 0xbb4, .mnd_width = 0, @@ -499,6 +522,7 @@ static struct qcom_cc_desc video_cc_sm8350_desc = { static int video_cc_sm8350_probe(struct platform_device *pdev) { + u32 video_cc_xo_clk_cbcr = 0xeec; struct regmap *regmap; int ret; @@ -510,6 +534,21 @@ static int video_cc_sm8350_probe(struct platform_device *pdev) if (ret) return ret; + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8280xp-videocc")) { + video_cc_sleep_clk_src.cmd_rcgr = 0xf38; + video_cc_sleep_clk.halt_reg = 0xf58; + video_cc_sleep_clk.clkr.enable_reg = 0xf58; + video_cc_xo_clk_src.cmd_rcgr = 0xf14; + video_cc_xo_clk_cbcr = 0xf34; + + video_pll0.vco_table = video_pll1.vco_table = lucid_5lpe_vco_8280xp; + /* No change, but assign it for completeness */ + video_pll0.num_vco = video_pll1.num_vco = ARRAY_SIZE(lucid_5lpe_vco_8280xp); + + video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_8280xp; + video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_8280xp; + } + regmap = qcom_cc_map(pdev, &video_cc_sm8350_desc); if (IS_ERR(regmap)) { pm_runtime_put(&pdev->dev); @@ -525,7 +564,7 @@ static int video_cc_sm8350_probe(struct platform_device *pdev) * video_cc_xo_clk */ regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0)); ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); pm_runtime_put(&pdev->dev); @@ -534,6 +573,7 @@ static int video_cc_sm8350_probe(struct platform_device *pdev) } static const struct of_device_id video_cc_sm8350_match_table[] = { + { .compatible = "qcom,sc8280xp-videocc" }, { .compatible = "qcom,sm8350-videocc" }, { } };