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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id i20-20020a170906115400b0098e417a0c3bsi6761385eja.109.2023.07.31.05.22.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 05:22:06 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7C9913857BA4 for ; Mon, 31 Jul 2023 12:21:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id DCFA23858426 for ; Mon, 31 Jul 2023 12:20:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DCFA23858426 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp64t1690806029tzee3j5s Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 31 Jul 2023 20:20:28 +0800 (CST) X-QQ-SSF: 00400000000000G0V000000A0000000 X-QQ-FEAT: 8QSH/3AgdaqsOyuFCBzL48qUelqWL/O3LhKotfEyk6AnYOkYdl8ld4YOOZD0j NtUslbvshhEFFC9To04ZK/urOzOoNk6jPqaqqRMuv9UWcV0BH459k0MFYNBeJfDoSB1F7sG aBl1x+NEeFQuqfz49dUSmd60UufBmdm6xJT4cK8Fr3tFBO6TvGdxoqx0E/Jw3DM5VRMGVNG 4jfOfpjsgmQQzFxQEH7eFY0gMsxOp6RzBdK0NuQN7qTeiHxZPbeD6X34ecPXU1wKSp8WXbv DYf5bkNFId2N/VuTUwL9M8+QCd/o9xI4HCAw5d+348GicY440+kehcAR5gI7Lv6WQMSx/ER mPM4lkVI+SkRjaf0dLHJ/9FzNgUOoXwy2lb7xjHhOeKGkxYf2Xr2/ewyZYWNU9J+O8FaOyx D9ciqdv3xZ8vvmnMwC0nYQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12472991811075653052 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, macro@embecosm.com, pan2.li@intel.com, Juzhe-Zhong Subject: [committed] RISC-V: Fix bug of get_mask_mode Date: Mon, 31 Jul 2023 20:20:26 +0800 Message-Id: <20230731122026.966504-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772938724751825804 X-GMAIL-MSGID: 1772938724751825804 Fix bugs: ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc: In function ‘void riscv_vector::emit_vlmax_masked_fp_mu_insn(unsigned int, int, rtx_def**)’: ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:999:54: error: request for member ‘require’ in ‘riscv_vector::get_mask_mode(dest_mode)’, which is of non-class type ‘machine_mode’ machine_mode mask_mode = get_mask_mode (dest_mode).require (); ^~~~~~~ ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc: In function ‘void riscv_vector::emit_nonvlmax_tumu_insn(unsigned int, int, rtx_def**, rtx)’: ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:1057:54: error: request for member ‘require’ in ‘riscv_vector::get_mask_mode(dest_mode)’, which is of non-class type ‘machine_mode’ machine_mode mask_mode = get_mask_mode (dest_mode).require (); ^~~~~~~ ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc: In function ‘void riscv_vector::emit_nonvlmax_fp_tumu_insn(unsigned int, int, rtx_def**, rtx)’: ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:1076:54: error: request for member ‘require’ in ‘riscv_vector::get_mask_mode(dest_mode)’, which is of non-class type ‘machine_mode’ machine_mode mask_mode = get_mask_mode (dest_mode).require (); Obvious fix. Pushed. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_masked_fp_mu_insn): Fix bug. (emit_nonvlmax_tumu_insn): Ditto. (emit_nonvlmax_fp_tumu_insn): Ditto. (expand_vec_series): Ditto. (expand_vector_init_insert_elems): Ditto. --- gcc/config/riscv/riscv-v.cc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 76b437cc55e..40e4574dcc0 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -996,7 +996,7 @@ static void emit_vlmax_masked_fp_mu_insn (unsigned icode, int op_num, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ false, @@ -1054,7 +1054,7 @@ static void emit_nonvlmax_tumu_insn (unsigned icode, int op_num, rtx *ops, rtx avl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ false, @@ -1073,7 +1073,7 @@ static void emit_nonvlmax_fp_tumu_insn (unsigned icode, int op_num, rtx *ops, rtx avl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ false, @@ -1306,7 +1306,6 @@ void expand_vec_series (rtx dest, rtx base, rtx step) { machine_mode mode = GET_MODE (dest); - machine_mode mask_mode = get_mask_mode (mode); poly_int64 nunits_m1 = GET_MODE_NUNITS (mode) - 1; poly_int64 value; @@ -2375,7 +2374,6 @@ expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, int nelts_reqd) { machine_mode mode = GET_MODE (target); - machine_mode mask_mode = get_mask_mode (mode); rtx dup = expand_vector_broadcast (mode, builder.elt (0)); emit_move_insn (target, dup); int ndups = builder.count_dups (0, nelts_reqd - 1, 1);