From patchwork Mon Jul 31 10:48:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 128625 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp1968490vqg; Mon, 31 Jul 2023 05:09:25 -0700 (PDT) X-Google-Smtp-Source: APBJJlEHh9wAYndQule7YhDY/6tV/JyT7XDC4DC7mqilJPPnBNoBukRuybjMcfMLz9BRdNdIExBi X-Received: by 2002:a17:906:3294:b0:98e:2097:f23e with SMTP id 20-20020a170906329400b0098e2097f23emr6341315ejw.77.1690805364785; Mon, 31 Jul 2023 05:09:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690805364; cv=none; d=google.com; s=arc-20160816; b=GEwu9Y0ZdmaBkAGepDJOr0MVlzxSUx9sAUwSc11Sud2D4Adjj0eRPuVlu+o44ZPXiR g6Z6Ia8vMdlMn+48/HEhXKXvOfT2Cvm2NhOH7gpzUd2cFQft0Q81dhBwU1bpMu1Uhevv rRo3B+P+U6PBp+0+6OnpiaNToZBQlEg9VadxZ+ak6UishTq51liLyY3psrkYgDTlWvmr Cvi4dgkyLqn7xPNA9o62tR8AK+dnrEI/4vN8R5RG0xbqYXMWLtD2wxt9CMX5UwVXjG+S L/UZAX9hZvB6phBRsB+KZtlTmYjxQtf17Q/00i6CqM3+tGquFEUZHYGhimumFZqLNoe5 V8ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:dkim-signature; bh=MdBXH3uSphZ3S/DQlu6um4GHYkgyiIe3GudkFMqQ35I=; fh=51loh+OS6vr0QdvTi7t7xEP2VSRDvSfeMVfkb8abBBs=; b=FwMKJgUCz4G+J9vwIe/I5ZqoGTM1sk3cM3mMLmGVTre2q+5Uc9XR0wnnsYc2Iq7oSC EhDhLbFJ5GCnZrvPapt+6dA9XXjKcqqrEFBHmlCn0Ztd6USMR2MUrepfuOJPQIdr8CdI CNueLI8ot6Cz8dxZOgRPufZVJBJ4tG7c7baBmGSMld+v7NI2wEnd1tq9awnbCTKsC7by Od5b1tuIyQr7rWGn+Lrs215sFiI3OZ+UmSJ5eNmvmFB7lBBWymWscRwU4Rdy8Sbj/Bh0 hjjqk3U97Fg91cVHTk2ZTtfkWbH4uO4guiMTVSO+ls+yU46hJopWmtauGB0OZcr0UcgN d1LA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=jF5zUKWv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m17-20020a170906849100b0099bd73cbd7dsi6759957ejx.429.2023.07.31.05.08.55; Mon, 31 Jul 2023 05:09:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=jF5zUKWv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230517AbjGaKtF (ORCPT + 99 others); Mon, 31 Jul 2023 06:49:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230240AbjGaKst (ORCPT ); Mon, 31 Jul 2023 06:48:49 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46A51E7D for ; Mon, 31 Jul 2023 03:48:47 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5734d919156so38000427b3.3 for ; Mon, 31 Jul 2023 03:48:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800526; x=1691405326; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=MdBXH3uSphZ3S/DQlu6um4GHYkgyiIe3GudkFMqQ35I=; b=jF5zUKWv+JJPzLJPTCtcIQlx+mDLm7QD217GXBNIJTo0QEZk0MsX7gxdB0vFXrli/U HUK/JgAMF7obKygq2QjjRSbtRqSNCflkgUe5lqzRZrptwfxJmo9xA1zBIEPRa6E3eQiQ YjlDdyI3+WL5aTENdTYwTp/TIRy6frsM8MUnqy+fuJtpE13m4dzIjAMiwwb+CvkA//A8 RTVqcv2qCUqzi49yo/tCk57LukWelKjObQGsVpq2vJ6h/FDTMXqPvRrEjOVpdOpMAUTc c96dvk4lXTWXeYGERHC226xc+FwNYZk7vLSa5jsHAhquww4YHOy4RUdtXWZCz5e3tKOM F/JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800526; x=1691405326; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=MdBXH3uSphZ3S/DQlu6um4GHYkgyiIe3GudkFMqQ35I=; b=PPh0c9hMn2C0VSOwWUxJifCfxjMWmdrCVlbhYpEGFRjPoPOZ2wisM5kuFoWL12JUhQ hhMAfSdakQqu1969Yd8cH37qDK80PUPM4uhBoBvoS9dz4aMQfxkWjdw6sOop/W2W8V0O 89RqjjHYt8krBQxOsbeW3tbierwElOfh7OHQyMnEuj30cFhFVDe9o9JLjvYXBRPJgiZt BufvWORBcmf5PDJq3F04W5b4EMi/BMs9Xs6I+g5crRyrVQ8Rxs/KH0iYBeXjlAIQ1XZb dW98UYG8q5E6/xlASQtG4PChsqRUvucD3Cx2xewkUGETr7+jnfih+F0y6twVDKQycxF6 lT+w== X-Gm-Message-State: ABy/qLYfOFvdaKTudUS0c5YORw+brJ48SXS3Dfove94MT+JpWIsofBtK H2QYTT/aDMiqlGbtIfHkU5dnYFgU3fu8 X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a81:b623:0:b0:584:4158:7f86 with SMTP id u35-20020a81b623000000b0058441587f86mr64515ywh.1.1690800526554; Mon, 31 Jul 2023 03:48:46 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:11 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.1.I67ab103c18d882aedc8a08985af1fba70bca084e@changeid> Subject: [PATCH v2 1/8] iommu/arm-smmu-v3: Move ctx_desc out of s1_cfg From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772937926426624901 X-GMAIL-MSGID: 1772937926426624901 s1_cfg describes the CD table that is inserted into an SMMU's STEs. It's weird for s1_cfg to also own ctx_desc which describes a CD that is inserted into that table. It is more appropriate for arm_smmu_domain to own ctx_desc. Signed-off-by: Michael Shavit Reviewed-by: Jason Gunthorpe --- Changes in v2: - Undo over-reaching column alignment change .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23 ++++++++++--------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 +++-- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index a5a63b1c947eb..968559d625c40 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -62,7 +62,7 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) return cd; } - smmu_domain = container_of(cd, struct arm_smmu_domain, s1_cfg.cd); + smmu_domain = container_of(cd, struct arm_smmu_domain, cd); smmu = smmu_domain->smmu; ret = xa_alloc(&arm_smmu_asid_xa, &new_asid, cd, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 9b0dc35056019..bb277ff86f65f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1869,7 +1869,7 @@ static void arm_smmu_tlb_inv_context(void *cookie) * careful, 007. */ if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { - arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid); + arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); } else { cmd.opcode = CMDQ_OP_TLBI_S12_VMALL; cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; @@ -1957,7 +1957,7 @@ static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + cmd.tlbi.asid = smmu_domain->cd.asid; } else { cmd.opcode = CMDQ_OP_TLBI_S2_IPA; cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; @@ -2088,7 +2088,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) mutex_lock(&arm_smmu_asid_lock); if (cfg->cdcfg.cdtab) arm_smmu_free_cd_tables(smmu_domain); - arm_smmu_free_asid(&cfg->cd); + arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); } else { struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; @@ -2107,13 +2107,14 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, u32 asid; struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr; - refcount_set(&cfg->cd.refs, 1); + refcount_set(&cd->refs, 1); /* Prevent SVA from modifying the ASID until it is written to the CD */ mutex_lock(&arm_smmu_asid_lock); - ret = xa_alloc(&arm_smmu_asid_xa, &asid, &cfg->cd, + ret = xa_alloc(&arm_smmu_asid_xa, &asid, cd, XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); if (ret) goto out_unlock; @@ -2126,23 +2127,23 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, if (ret) goto out_free_asid; - cfg->cd.asid = (u16)asid; - cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; - cfg->cd.tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | + cd->asid = (u16)asid; + cd->ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; + cd->tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; - cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; + cd->mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; /* * Note that this will end up calling arm_smmu_sync_cd() before * the master has been added to the devices list for this domain. * This isn't an issue because the STE hasn't been installed yet. */ - ret = arm_smmu_write_ctx_desc(smmu_domain, 0, &cfg->cd); + ret = arm_smmu_write_ctx_desc(smmu_domain, 0, cd); if (ret) goto out_free_cd_tables; @@ -2152,7 +2153,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, out_free_cd_tables: arm_smmu_free_cd_tables(smmu_domain); out_free_asid: - arm_smmu_free_asid(&cfg->cd); + arm_smmu_free_asid(cd); out_unlock: mutex_unlock(&arm_smmu_asid_lock); return ret; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index dcab85698a4e2..f841383a55a35 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -599,7 +599,6 @@ struct arm_smmu_ctx_desc_cfg { struct arm_smmu_s1_cfg { struct arm_smmu_ctx_desc_cfg cdcfg; - struct arm_smmu_ctx_desc cd; u8 s1fmt; u8 s1cdmax; }; @@ -724,7 +723,10 @@ struct arm_smmu_domain { enum arm_smmu_domain_stage stage; union { - struct arm_smmu_s1_cfg s1_cfg; + struct { + struct arm_smmu_ctx_desc cd; + struct arm_smmu_s1_cfg s1_cfg; + }; struct arm_smmu_s2_cfg s2_cfg; }; From patchwork Mon Jul 31 10:48:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 128654 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp1991808vqg; Mon, 31 Jul 2023 05:52:26 -0700 (PDT) X-Google-Smtp-Source: APBJJlH9q7bjzOh1F4DFtlpGcOK21YWDjIKK+d9qik0J0uKnhzeqndlgmgo9ts9+e2/gHelwLfMj X-Received: by 2002:a17:906:7795:b0:999:26d3:b815 with SMTP id s21-20020a170906779500b0099926d3b815mr7720266ejm.64.1690807946106; Mon, 31 Jul 2023 05:52:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690807946; cv=none; d=google.com; s=arc-20160816; b=jOl+FEuiIWRTE/9VXw/ZdOoXIeEGtJep+ySP3xRgx6HGerjxdHwrhNbEIggWkkWZtD oRwQCrY7IdxZhWJepfofcwWQQGvN3Op+8tv2mymUDbM/MkXz+VaYoNsQLfJGZ/65TRnK lcHb2rWal0ip0njProewCya7b90GlN8VsSjScC+rLLgcS7nZdncauaRkTMP0PWwJ79DB HYnZjQsJlfR9S84USBqJzjAUCV29FLxivLdHkSoQS2KIQSBj154ppS4Hwy3zGjrgfVIu 5InrFTfOiAXekKA7aFll54FI/WEEsRnIwVq+5+T0hnF3aHZMj7vcVmjM0o+dDKa5rU/l CoMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:dkim-signature; bh=XpxDiPCFOm0sbFmMF9gdCcsfofnkpvd6AL0rLhPbViQ=; fh=51loh+OS6vr0QdvTi7t7xEP2VSRDvSfeMVfkb8abBBs=; b=h3WTuavOWuBOpJ/spO6+ouTOqqpVAVi+w4UGDmEzkmJ7BL9b5CNrxhbS/Osl5JKTNx yqQ/GZJLVlSC8SchcOlqTLqwud8GycG1CrOjH2uxJGc8qPfjrL+opb1a+9VN8c+AfoTz UB8Aen4ycLha1+88wpAx5yhICNYc6XdEMNZWiIx+TtwEGKEfPZFeS1XkSP3gAh0x2egh yFF2aWsVwMenPQn9vbompM1XRIBbDh9f4Kx977DaYowQhHyB8/K/v3ESlzWdm/61H+pj RQpmDXgv8WaOJbrzLnbTAj+bVDH1UHK5eqYbfDmQoe4vXGg8HHITtAP23Nh54N1AeiFt tu9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=CprqZcvZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y20-20020a17090629d400b00982818cbb54si7059818eje.593.2023.07.31.05.52.01; Mon, 31 Jul 2023 05:52:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=CprqZcvZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230399AbjGaKtI (ORCPT + 99 others); Mon, 31 Jul 2023 06:49:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230165AbjGaKsx (ORCPT ); Mon, 31 Jul 2023 06:48:53 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE0621A7 for ; Mon, 31 Jul 2023 03:48:51 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-56cf9a86277so57554687b3.3 for ; Mon, 31 Jul 2023 03:48:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800531; x=1691405331; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=XpxDiPCFOm0sbFmMF9gdCcsfofnkpvd6AL0rLhPbViQ=; b=CprqZcvZgWUASS/ghl9a0jTUcICzr0dBfO70oSWdJfBWyUAYLPGAJS9BuMs3dZ8YXn AqdNx95bDXgpWgiPE29Tz1iz6qujpe9IE+sgGgxAGilKICawmzbihG/ip2rFZZeolni7 ADDKck32yG7qiKiayt3KdzPEZYIWPp7w6m+ri9SGlUqpsrpzTkdq7tzbpC3bwuBv7ouI XL0j+2Km05HTCeuonvWxIIEbXxKFYNJOEP39NfUFNaNBD32G5Hfa1Ul5AcVV9SFBH/gB 7/pJxG9Pn4dSAp4ycfQSFSV7hynPP3THy08jCMX6g5c6Rq0SnG0a/br0+sDq1tXuWT+v DJng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800531; x=1691405331; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=XpxDiPCFOm0sbFmMF9gdCcsfofnkpvd6AL0rLhPbViQ=; b=UR0NAI99TBCeHhdRaMbjq89MhK6Ief/EvgAddqv72P6F8vGkD9sIMfxX4z6RkHLq5V EsP2i9xps/DPEwAY58Q3k/b9yoKskD9xq14sTy5LeV8gO04axij8jsQaakBQGPErwTUW TYajdU9/ZXpmkbbMfcyzlpsaOtEgn3VYoHVf2CwQt+K/qHv3co5TKdiJQeeiqf+0T6Qe haVKN5s4OV8EiqALYM9mhDa56YtUi0u3n2q4DDzPtw48jn0vREEFhpdivNN9zZAHt9LF Y7p6tb1BTiYX94nO7Kakwb7J+Jg/AqwhmN7BKpVG1y11+DG2qMUPLg5zKn2pc4txETVG gyvQ== X-Gm-Message-State: ABy/qLajC+Jt/1D0LTDwz6pL6YfaaOwthslW7aS+S//4DbSD1aSJrcP6 2gZDwRvPf4OUlhofL2H4LLGMEg/ivHnB X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a81:c609:0:b0:570:b1:ca37 with SMTP id l9-20020a81c609000000b0057000b1ca37mr69408ywi.5.1690800531032; Mon, 31 Jul 2023 03:48:51 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:12 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.2.I1ef1ed19d7786c8176a0d05820c869e650c8d68f@changeid> Subject: [PATCH v2 2/8] iommu/arm-smmu-v3: Replace s1_cfg with cdtab_cfg From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772940633030765381 X-GMAIL-MSGID: 1772940633030765381 arm_smmu_ctx_desc_cfg is renamed to arm_smmu_cdtab_cfg to make it more obvious that it represents a cd table. The max number of CDs that can be represented by the CD table is stored in this truct in its log2 form since it is more useful for users of the CD table, and replaces the s1cdmax field in s1_cfg. Instead of storing s1_cfg.s1fmt, it can also be trivially computed from the cdtab_cfg, and is therefore removed from s1_cfg. Signed-off-by: Michael Shavit --- Changes in v2: - Updated commit message drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 45 +++++++++++---------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 10 ++--- 2 files changed, 26 insertions(+), 29 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index bb277ff86f65f..8cf4987dd9ec7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1033,9 +1033,9 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_domain *smmu_domain, unsigned int idx; struct arm_smmu_l1_ctx_desc *l1_desc; struct arm_smmu_device *smmu = smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->s1_cfg.cdcfg; + struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; - if (smmu_domain->s1_cfg.s1fmt == STRTAB_STE_0_S1FMT_LINEAR) + if (!cdcfg->l1_desc) return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; idx = ssid >> CTXDESC_SPLIT; @@ -1071,7 +1071,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, bool cd_live; __le64 *cdptr; - if (WARN_ON(ssid >= (1 << smmu_domain->s1_cfg.s1cdmax))) + if (WARN_ON(ssid >= (1 << smmu_domain->cd_table.max_cds_bits))) return -E2BIG; cdptr = arm_smmu_get_cd_ptr(smmu_domain, ssid); @@ -1138,19 +1138,16 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) size_t l1size; size_t max_contexts; struct arm_smmu_device *smmu = smmu_domain->smmu; - struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; - struct arm_smmu_ctx_desc_cfg *cdcfg = &cfg->cdcfg; + struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; - max_contexts = 1 << cfg->s1cdmax; + max_contexts = 1 << cdcfg->max_cds_bits; if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || max_contexts <= CTXDESC_L2_ENTRIES) { - cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR; cdcfg->num_l1_ents = max_contexts; l1size = max_contexts * (CTXDESC_CD_DWORDS << 3); } else { - cfg->s1fmt = STRTAB_STE_0_S1FMT_64K_L2; cdcfg->num_l1_ents = DIV_ROUND_UP(max_contexts, CTXDESC_L2_ENTRIES); @@ -1186,7 +1183,7 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain) int i; size_t size, l1size; struct arm_smmu_device *smmu = smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->s1_cfg.cdcfg; + struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; if (cdcfg->l1_desc) { size = CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3); @@ -1276,7 +1273,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, u64 val = le64_to_cpu(dst[0]); bool ste_live = false; struct arm_smmu_device *smmu = NULL; - struct arm_smmu_s1_cfg *s1_cfg = NULL; + struct arm_smmu_ctx_desc_cfg *cd_table = NULL; struct arm_smmu_s2_cfg *s2_cfg = NULL; struct arm_smmu_domain *smmu_domain = NULL; struct arm_smmu_cmdq_ent prefetch_cmd = { @@ -1294,7 +1291,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, if (smmu_domain) { switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: - s1_cfg = &smmu_domain->s1_cfg; + cd_table = &smmu_domain->cd_table; break; case ARM_SMMU_DOMAIN_S2: case ARM_SMMU_DOMAIN_NESTED: @@ -1325,7 +1322,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, val = STRTAB_STE_0_V; /* Bypass/fault */ - if (!smmu_domain || !(s1_cfg || s2_cfg)) { + if (!smmu_domain || !(cd_table || s2_cfg)) { if (!smmu_domain && disable_bypass) val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else @@ -1344,7 +1341,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, return; } - if (s1_cfg) { + if (cd_table) { u64 strw = smmu->features & ARM_SMMU_FEAT_E2H ? STRTAB_STE_1_STRW_EL2 : STRTAB_STE_1_STRW_NSEL1; @@ -1360,10 +1357,14 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, !master->stall_enabled) dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); - val |= (s1_cfg->cdcfg.cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | - FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | - FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | - FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); + val |= (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | + FIELD_PREP(STRTAB_STE_0_S1CDMAX, + cd_table->max_cds_bits) | + FIELD_PREP(STRTAB_STE_0_S1FMT, + cd_table->l1_desc ? + STRTAB_STE_0_S1FMT_64K_L2 : + STRTAB_STE_0_S1FMT_LINEAR); } if (s2_cfg) { @@ -2082,11 +2083,11 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) /* Free the CD and ASID, if we allocated them */ if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { - struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; /* Prevent SVA from touching the CD while we're freeing it */ mutex_lock(&arm_smmu_asid_lock); - if (cfg->cdcfg.cdtab) + if (cdcfg->cdtab) arm_smmu_free_cd_tables(smmu_domain); arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); @@ -2106,7 +2107,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, int ret; u32 asid; struct arm_smmu_device *smmu = smmu_domain->smmu; - struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr; @@ -2119,7 +2120,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, if (ret) goto out_unlock; - cfg->s1cdmax = master->ssid_bits; + cdcfg->max_cds_bits = master->ssid_bits; smmu_domain->stall_enabled = master->stall_enabled; @@ -2457,7 +2458,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && - master->ssid_bits != smmu_domain->s1_cfg.s1cdmax) { + master->ssid_bits != smmu_domain->cd_table.max_cds_bits) { ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index f841383a55a35..35a93e8858872 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -595,12 +595,8 @@ struct arm_smmu_ctx_desc_cfg { dma_addr_t cdtab_dma; struct arm_smmu_l1_ctx_desc *l1_desc; unsigned int num_l1_ents; -}; - -struct arm_smmu_s1_cfg { - struct arm_smmu_ctx_desc_cfg cdcfg; - u8 s1fmt; - u8 s1cdmax; + /* log2 of the maximum number of CDs supported by this table */ + u8 max_cds_bits; }; struct arm_smmu_s2_cfg { @@ -725,7 +721,7 @@ struct arm_smmu_domain { union { struct { struct arm_smmu_ctx_desc cd; - struct arm_smmu_s1_cfg s1_cfg; + struct arm_smmu_ctx_desc_cfg cd_table; }; struct arm_smmu_s2_cfg s2_cfg; }; From patchwork Mon Jul 31 10:48:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 128623 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp1960521vqg; Mon, 31 Jul 2023 04:56:38 -0700 (PDT) X-Google-Smtp-Source: APBJJlFhSGWdA8rz9j9dgw/eM8Ruusha+twWECNXHMy/st6B+mp0D86C7Nurk5u1EM2DFTVnrMw3 X-Received: by 2002:a05:6a00:2293:b0:687:1f51:38ac with SMTP id f19-20020a056a00229300b006871f5138acmr7271531pfe.13.1690804598227; Mon, 31 Jul 2023 04:56:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690804598; cv=none; d=google.com; s=arc-20160816; b=GSFNVxk+ZZTgi3EKi+Q9LLmQ/ZnfuLzE6FcjTP6vaZsBBFa6dozTT2PFV8TFrXUR1z ZHHRTg+PJdKWrPIV2VXv4fSLHdRx7uarmFpjSISLkjDV+LCjWgDSr2yEZN29dw6oWrPv AksZWbwseG0llSuCnqnSP109bRh49GuTiJfuVXo/cn7BNjW0NYeFuLIKzvG7ypRCegZw MYIP7GRd8tIKClWyO9q38GIjsihqqTaJtk82tFhdM380bq1O6Om3INEF+NngJ8Knyxbj qMbryGSHHI1QhWLiiuLwAmJpftEhZKZh3oMZLiZvngaSFFHQrosEMPG7eEmzn1Bx/4pE cRzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:dkim-signature; bh=6LEwoPypxNg/0wwK9DSpnnqLrV8S3AoRDp+1fjKUE9c=; fh=51loh+OS6vr0QdvTi7t7xEP2VSRDvSfeMVfkb8abBBs=; b=CCFRI0bYl7YzLeO16rX70MRrCkSrT2C4hPenqYqLdVUMlko3NBRxJACQePNhC2O2GX BYBIDO6brthYm3TG7zuP7NO/ZwjXbZQ9cuJ/B/eAEr5fTOMZY8hYs8qRbMXRlqxfWROV lpsEnuDnjPv52pcBGOOrmWe7Ngauh2IVLzDh7s/GV3yKKGCF1C7DTaGdvvApVWnNXnto 73LviWsAFUf5in+orvTSV0Ru2/8iGZn/5QUO4EoBc/mk0ferZi3Y5BerJIGSlPNmyOci pcZ/jSKU4NY0L2Jx6hUXP1cdjUR5ezmWr0oJQbeaw9upGDq2iMf4LqLkarpAoEzm8Ro1 l/oA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=EEMFNUSX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a4-20020a056a000c8400b00681ad13f7cbsi7487924pfv.121.2023.07.31.04.56.26; Mon, 31 Jul 2023 04:56:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=EEMFNUSX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231202AbjGaKtM (ORCPT + 99 others); Mon, 31 Jul 2023 06:49:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230364AbjGaKs6 (ORCPT ); Mon, 31 Jul 2023 06:48:58 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E27D10C7 for ; Mon, 31 Jul 2023 03:48:56 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-583f048985bso58230667b3.2 for ; Mon, 31 Jul 2023 03:48:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800535; x=1691405335; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=6LEwoPypxNg/0wwK9DSpnnqLrV8S3AoRDp+1fjKUE9c=; b=EEMFNUSXVHTC6HAOa38cmSdOEiaoD2jrNpOHT4VveZGabJGsF8dATyht8Xu/hVKbF6 yF/iFDQeMQ7/gWSYJLsfl+7c5oWtTZh4CfBNMmT/WxVunxHXK3tDqFjxNbgpcGTWmW+6 cCaTaHWSlh3Tx2Qr1H7elgc4IPaOX0m36Jh/tnctw8a3UvBC18Lue9/rCCUw7agpoWnn jucQMcbNR9YDAU9QQomc+FfMt3++7DCVfUkBTYzM86OAzAZaPJea2J7EHFIApn8iEbL9 HLW1iV8Q8HojjNdueabZhuwjVbL6Bl/q/sGb/wFWCKz7nO2mFW0tD5gwBxK+TJ1ofVJO fIKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800535; x=1691405335; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=6LEwoPypxNg/0wwK9DSpnnqLrV8S3AoRDp+1fjKUE9c=; b=fJs6X6W4VBzruArmPfFGcP6NCS+3e38f87vFGiuMNizhAR0LaaTCda+R2mpllBqgDa 1kURdqq1JBjkS6Wal6ldWJ2icOtroi85ZsjWcFvXUQCpkUcih90teOOq2Gz58nPL2vOS 2nCZB1TpAJQAJadzdTiSva3LI0LN7TSpYrBRY2WgZheJ2z/G+6ahe289j7pjb2fqVOBJ zQgZNJxVPGL7ASRBC2PB+XZa8ouY0sT/qeTIyFgBmzcb9qRn8Fn+UtnzjL7CURzH8mCA YIUNr0wcjd/ZJmd2N8e1FBkEZF2ViW+XeIDs0kIMjIppCjSN6CdyqnrUfeb42xCUimta knfA== X-Gm-Message-State: ABy/qLYEzD9T8CkiS5YHoDq625DqEMpBPHCkv70/WMzgml5YczDyAyTc vj/IgS3XnGqAb0Q0JQbwyyouJ7ecR75o X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a81:b703:0:b0:584:41a6:6cd8 with SMTP id v3-20020a81b703000000b0058441a66cd8mr66785ywh.8.1690800535642; Mon, 31 Jul 2023 03:48:55 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:13 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.3.I875254464d044a8ce8b3a2ad6beb655a4a006456@changeid> Subject: [PATCH v2 3/8] iommu/arm-smmu-v3: Encapsulate ctx_desc_cfg init in alloc_cd_tables From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772937122115104156 X-GMAIL-MSGID: 1772937122115104156 This is slighlty cleaner: arm_smmu_ctx_desc_cfg is initialized in a single function instead of having pieces set ahead-of time by its caller. Signed-off-by: Michael Shavit Reviewed-by: Jason Gunthorpe --- (no changes since v1) drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 8cf4987dd9ec7..8a286e3838d70 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1132,7 +1132,8 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, return 0; } -static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) +static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_master *master) { int ret; size_t l1size; @@ -1140,6 +1141,7 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; + cdcfg->max_cds_bits = master->ssid_bits; max_contexts = 1 << cdcfg->max_cds_bits; if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || @@ -2107,7 +2109,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, int ret; u32 asid; struct arm_smmu_device *smmu = smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr; @@ -2120,11 +2121,9 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, if (ret) goto out_unlock; - cdcfg->max_cds_bits = master->ssid_bits; - smmu_domain->stall_enabled = master->stall_enabled; - ret = arm_smmu_alloc_cd_tables(smmu_domain); + ret = arm_smmu_alloc_cd_tables(smmu_domain, master); if (ret) goto out_free_asid; From patchwork Mon Jul 31 10:48:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 128587 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp1934896vqg; Mon, 31 Jul 2023 04:04:16 -0700 (PDT) X-Google-Smtp-Source: APBJJlF0CZvTrBMp8Dw030kll8YPwtobICrBfF+2GXlOsl4LvrNaIxD+ABOQ5aC/aR+hVrSxtMxW X-Received: by 2002:a05:6512:3d88:b0:4fb:78b1:1cd4 with SMTP id k8-20020a0565123d8800b004fb78b11cd4mr7246399lfv.49.1690801455766; Mon, 31 Jul 2023 04:04:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690801455; cv=none; d=google.com; s=arc-20160816; b=VboNx1u3IlKWj3YweTuJvc9+2mBuFuxPxIOup5gspaixJQTAkY2+GLqwML68KM6SyF 2tFCoAnpgn06FvDcb8O1PUDwGjr/X/OIh9lFuV3cDVxcsUjj4aFMgu91gVORX++2aZqt n6V/iC8vY7xXMUJ7Y+6iyymNKg8QH3nXTfPMRbtoR7QTbBQPybkYGD6GyTsh8ylKKEl1 iqtuOiiNIrPhT1sdj//5DBT+oM0I2NJHvdhUUOhwhBBMs6KdhEXmvigqL69gMRqTw77J RfM4MzDzLheo8gGsOaSAKa1zW9FjYnDue60GiswhgCA6n0w7jGt7BtP0N39Qy7lef6Qj iVow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:dkim-signature; bh=5wCGxdM3vMHiwD5Hqt1d7Th7Pi/IDzxiPCnlsNf6ST4=; fh=51loh+OS6vr0QdvTi7t7xEP2VSRDvSfeMVfkb8abBBs=; b=UmWcnbrWOPukjNYMNyCHc0/wjMjETzjkYkJ1C3MSBnf9qbG9ioihOKCVv5liZlwx0r SmS4a2XL7VCGEPmchtSU8bzO+hNw4NX9l85/lwFvy0DwBstUHxcuCKNpfJDddCvONQRz QZ7yPHkLVaB8pmb1Rd1eL64lK0PdudR93nVO4lIAkGrqN/FyDLlM4Clhv3b/odfh58aS bYeaXVYns/oNz7G41pCCjYR62TA6Xaq9T0dAA1ZNqpWxgGqCIaI7/+RZXjwR3rRjR0H/ hVQr8PnIBRe7TRMHP4o0YK+7r2Slt2pJxtsXW9N/SwlEcaG5udV2v7+OtpgTc/PtC11U NqUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=wvipL4WY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h24-20020aa7c618000000b00522cf0ca3d6si601563edq.217.2023.07.31.04.03.48; Mon, 31 Jul 2023 04:04:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=wvipL4WY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230465AbjGaKtT (ORCPT + 99 others); Mon, 31 Jul 2023 06:49:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230425AbjGaKtC (ORCPT ); Mon, 31 Jul 2023 06:49:02 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20231E7A for ; Mon, 31 Jul 2023 03:49:01 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-d1851c52f3dso4468680276.1 for ; Mon, 31 Jul 2023 03:49:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800540; x=1691405340; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=5wCGxdM3vMHiwD5Hqt1d7Th7Pi/IDzxiPCnlsNf6ST4=; b=wvipL4WYLuG06Yh5YopeGwe+XP+zY71R/EbIkI2asNYrYY+npiquOLOKtTV2H4wE2V EaHCyurHW1OnBNBicb3akuqlgF4MJPoQognV8Zlk2nlY3F68isgainEajrK0YmO8BFKX v9uxGx2aUalsMGIWmLEXx77Qt9MTtXIWfIaXsQN9QhUdFKcBkreF2WgktcFBR6IE/uoH 55LrshvxNW8mBQlz05AGY0+XgdTfXjNZFqKztaF2CceW22NfA18nxf+yKVrkIKH/GwA+ awt3aG+Mo/+5YJJba+ZkC4K6v8Jqe+YiictB/4pRzc9kXU9nN1RKGk/pvbOiCaLhUeE+ mn5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800540; x=1691405340; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5wCGxdM3vMHiwD5Hqt1d7Th7Pi/IDzxiPCnlsNf6ST4=; b=FaqKoN20ya2CJHnuZpVPzCy6fHoo3H50avWVf/eTGtiKzlclo2JMbuUWfTEeAmW5yB A0djZlOjnhYDqFPqEh/HV405le98JUAy18WtnEUMxKG9TgLpU2A1QKaEu4truVHOiqWB sSELAziqqg/pFD+7+n0PxYBPlnuFsLW7h4B5Wu1L7OJTExfyu67mRyVqAG4OxO7RAPSu NizqIOcu4PHwjJkRdR0g3ziLHl3DiOwIlttRQ4Lar4JsrzjeiAnq12xpHBaR170jiEv6 fWjY6z+ywel8UsH55aLyT35JANqZKj7rCeIGOwF714Y2iy+PwejAWmswuFF7AbdKY2ek 8qkw== X-Gm-Message-State: ABy/qLb9xzKy6w2N8QMb+XTQQZ2BDM9/2W3ksBkfleLeargX9vVtgSWE 44E7qBk0D+21anItGw+63ho6FljTqBci X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a25:7341:0:b0:d0b:ca14:33fd with SMTP id o62-20020a257341000000b00d0bca1433fdmr49423ybc.8.1690800540379; Mon, 31 Jul 2023 03:49:00 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:14 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.4.I5aa89c849228794a64146cfe86df21fb71629384@changeid> Subject: [PATCH v2 4/8] iommu/arm-smmu-v3: move stall_enabled to the cd table From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772933827384915997 X-GMAIL-MSGID: 1772933827384915997 This controls whether CD entries will have the stall bit set when writing entries into the table. Signed-off-by: Michael Shavit Reviewed-by: Jason Gunthorpe --- Changes in v2: - Use a bitfield instead of a bool for stall_enabled drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++---- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 ++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 8a286e3838d70..654acf6002bf3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1114,7 +1114,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) | CTXDESC_CD_0_V; - if (smmu_domain->stall_enabled) + if (smmu_domain->cd_table.stall_enabled) val |= CTXDESC_CD_0_S; } @@ -1141,6 +1141,7 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; + cdcfg->stall_enabled = master->stall_enabled; cdcfg->max_cds_bits = master->ssid_bits; max_contexts = 1 << cdcfg->max_cds_bits; @@ -2121,8 +2122,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, if (ret) goto out_unlock; - smmu_domain->stall_enabled = master->stall_enabled; - ret = arm_smmu_alloc_cd_tables(smmu_domain, master); if (ret) goto out_free_asid; @@ -2461,7 +2460,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && - smmu_domain->stall_enabled != master->stall_enabled) { + smmu_domain->cd_table.stall_enabled != + master->stall_enabled) { ret = -EINVAL; goto out_unlock; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 35a93e8858872..05b1f0ee60808 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -597,6 +597,8 @@ struct arm_smmu_ctx_desc_cfg { unsigned int num_l1_ents; /* log2 of the maximum number of CDs supported by this table */ u8 max_cds_bits; + /* Whether CD entries in this table have the stall bit set. */ + u8 stall_enabled:1; }; struct arm_smmu_s2_cfg { @@ -714,7 +716,6 @@ struct arm_smmu_domain { struct mutex init_mutex; /* Protects smmu pointer */ struct io_pgtable_ops *pgtbl_ops; - bool stall_enabled; atomic_t nr_ats_masters; enum arm_smmu_domain_stage stage; From patchwork Mon Jul 31 10:48:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 128610 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp1950406vqg; Mon, 31 Jul 2023 04:34:07 -0700 (PDT) X-Google-Smtp-Source: APBJJlFoCME3K4fbLmL26m91OTu9KQkP5vNA6+fyld0+A2uWPEwrzn1uQYYBElArsFAX0h8j0sKc X-Received: by 2002:a17:903:1112:b0:1b8:4baa:52ff with SMTP id n18-20020a170903111200b001b84baa52ffmr11231246plh.47.1690803247503; Mon, 31 Jul 2023 04:34:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690803247; cv=none; d=google.com; s=arc-20160816; b=C65eTWXTpiV11ITgpSPM/7sqSW9QQEOT4grnFo+GswHhZp7enKeFR6238cT11GsNPI n/13P667enbjG6rVWdilMWFfIV1sZcAwdBBazfIac+/CjR5xULB3I7/FToLwtq6g913o 5xftGD5iyQUSTl61SpDoHDRbx0wy4XCD8m1QH8Jd6YF94p7wrDOi1Ecst93rZdQRIXA7 GhKPdKI2+3PCihaUFk5n+hH4SdkkU+5/akCqBEvo5IcuzoiE07qDNYo1MA4zBGtazCph G0N7nn04jeHa3/KVKvy81cLVqSJXteUNj3L79/gC8LgG773TuJz6GuMp2RiL27hWrv25 J9RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:dkim-signature; bh=TOLHkJaT+7H0fEwKCF1U6y0LUywm6xuO1oN6Y683ukY=; fh=51loh+OS6vr0QdvTi7t7xEP2VSRDvSfeMVfkb8abBBs=; b=o9SFy+MXlAb7vXDS1KjAyasIWT+2hy90cJej3urCFVNAWxj782jzYxg0XffN69Avo2 zHzwoRVuOw41fEqteVT/Es4Fbz9svgdSYl1agbqprIS0OfxNhjRijRqA9Pw57UVgSCMX Jgjth9C5pbubhMkiMIeJmjyCpnRCgBKu7MrxH509sg80FvhBnnmP5MiuvAsKzBwqp602 ZiosdCJiwEIYa//N1Ia//Y9RVpXQM6sq505roP+DauWWGtwWdCTIm+Cn7hkbmeapE0U1 hc9wT0tGdsOu4xpsklSkbn+77lMpIpikacZ5KIDBN200mvmJ10gwSf0/eT+jCFA73gXC vaWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=wpLAsENI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f10-20020a170902ce8a00b001b3c63eba76si7350469plg.492.2023.07.31.04.33.54; Mon, 31 Jul 2023 04:34:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=wpLAsENI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230200AbjGaKt2 (ORCPT + 99 others); Mon, 31 Jul 2023 06:49:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231278AbjGaKtQ (ORCPT ); Mon, 31 Jul 2023 06:49:16 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6558F10EB for ; Mon, 31 Jul 2023 03:49:05 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-583c49018c6so51274027b3.0 for ; Mon, 31 Jul 2023 03:49:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800544; x=1691405344; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=TOLHkJaT+7H0fEwKCF1U6y0LUywm6xuO1oN6Y683ukY=; b=wpLAsENIWJ8wPIvQXtzKrwlZ6cmns5IxNkosywEnU8vIi2VRqkKXyg7IgNJLtU2yYM pA798G7cy5i8aGBzkQfk7TMF+3OzVxxf4KXgsLYfYtzN983zooa0XPtIvRQJBZPPTnzb gNIlPXfmoBL6gRtQAKXVw0vyIz3ZVrSzxEV47z7ZCPvWlAWJ43TH/sqJxrU60QmCutYJ unlLPnHUz52Mf7NRqdcrEWLGxS1xK9S1Bgic8ph8D7Kreo16nJyjyyR0MD+usfE8nmr6 S6sFMIovzFLeTmgEVZxrwwFn0cAC2vkGgj9Pkvtb6nNvjIpZU23gEXufrm8bnoRuB2Uz bMJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800544; x=1691405344; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=TOLHkJaT+7H0fEwKCF1U6y0LUywm6xuO1oN6Y683ukY=; b=iIdsTTUV+Buoqmgi3S0S7styvwdyWQsqeNPR7iXR7kpmePkmYy/ZFZ/dCv/jDiTyvD MpMQo/oQJX6FwYZaKMD+pD0AjJTea7t7xhJvfsyW3OFUNHEYGyNoneoEHviUq3z5Nmmw 6n/1v+wpPDiXDdF+sDPVf/3VU/dVt6y/W9lWGDI3Aj8rW7QmjlVvMt8JBlB8dozPGRJG SlR+5WyHWDvM+txf3yvtCN98TNNeisk6Pwif5vCiTVn3Ce37pA5JJrzAVzZmTHlDGuKN ueSPcJFd+xpOoSyHaYiYuRqwfdDj+SUQmkT6xQGvpRO82eZ6t24ZYE80wmt1GLtLLd04 UKpg== X-Gm-Message-State: ABy/qLbS/aE472aMYWTwqLSc3+gCRrUZebcv/xczm1E3uv3MajWLi7UH v87zcS/6duK8mnspl98HLOU6JoVavU9X X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a81:ec0f:0:b0:576:6e4e:b87f with SMTP id j15-20020a81ec0f000000b005766e4eb87fmr72197ywm.10.1690800544479; Mon, 31 Jul 2023 03:49:04 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:15 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.5.Idedc0f496231e2faab3df057219c5e2d937bbfe4@changeid> Subject: [PATCH v2 5/8] iommu/arm-smmu-v3: Skip cd sync if CD table isn't active From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772935705820565357 X-GMAIL-MSGID: 1772935705820565357 This commit explicitly keeps track of whether a CD table is installed in an STE so that arm_smmu_sync_cd can skip the sync when unnecessary. This was previously achieved through the domain->devices list, but we are moving to a model where arm_smmu_sync_cd directly operates on a master and the master's CD table instead of a domain. Signed-off-by: Michael Shavit Reviewed-by: Jason Gunthorpe --- Changes in v2: - Store field as a bit instead of a bool. Fix comment about STE being live before the sync in write_ctx_desc(). drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 654acf6002bf3..4f7fe19d88fda 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -987,6 +987,9 @@ static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain, }, }; + if (!smmu_domain->cd_table.installed) + return; + cmds.num = 0; spin_lock_irqsave(&smmu_domain->devices_lock, flags); @@ -1098,7 +1101,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, cdptr[3] = cpu_to_le64(cd->mair); /* - * STE is live, and the SMMU might read dwords of this CD in any + * STE may be live, and the SMMU might read dwords of this CD in any * order. Ensure that it observes valid values before reading * V=1. */ @@ -1368,6 +1371,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, cd_table->l1_desc ? STRTAB_STE_0_S1FMT_64K_L2 : STRTAB_STE_0_S1FMT_LINEAR); + cd_table->installed = true; } if (s2_cfg) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 05b1f0ee60808..3a56987a5fd0b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -599,6 +599,8 @@ struct arm_smmu_ctx_desc_cfg { u8 max_cds_bits; /* Whether CD entries in this table have the stall bit set. */ u8 stall_enabled:1; + /* Whether this CD table is installed in any STE */ + u8 installed:1; }; struct arm_smmu_s2_cfg { From patchwork Mon Jul 31 10:48:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 128694 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2025956vqg; Mon, 31 Jul 2023 06:48:00 -0700 (PDT) X-Google-Smtp-Source: APBJJlE3t4o48TXdJfh8f8Ghe8xmE8vxYZVartvLmfc5dN6aDdL7DvmLzDLCmmedPNFhJ+qnFq84 X-Received: by 2002:a2e:8748:0:b0:2b6:a7dd:e22 with SMTP id q8-20020a2e8748000000b002b6a7dd0e22mr6850865ljj.48.1690811279943; Mon, 31 Jul 2023 06:47:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690811279; cv=none; d=google.com; s=arc-20160816; b=z7v7EDjQkPcb89hAueOnIYX1RlZNkVmEtMDEbDNK0v5ooGQHxQGTniiF4ZAu4ed1YD xnnH7QXiSsa7hyaoxrIjPd2QgmNh3WRY1P3Nh0Np/BTg0fn8O/wjoi8cOTQz3JOjsGf3 ZGYor5TDMKNOrOI08xG1x0LxnfnYaywK7zdGu89snbCOrZQshU+QeMWgaonSdTh5Y8qn TpK04IvOYLFkPYfBcxQk9tPqKlCUoX/nkYL+QVqtIdLrw6KhkHIiuY6tkEjPizEOctj8 2wQKn+xrDFx4PLsyQ5l/4i1C9SI+j3aUv1izkfvQWa5zHc+l3izdwrHgnL2aUkm4mJmh k21Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:dkim-signature; bh=YBnr3ePqGRSHGL39Ok/yCt1mWN8mbG/Gp+AtUdQxaUU=; fh=51loh+OS6vr0QdvTi7t7xEP2VSRDvSfeMVfkb8abBBs=; b=wg4X7hRb80NXfsJStawir66aYDdSJ9T31sOt6wmPdY4J88g7g37uRfFaE//eWfBdM+ ztSlVabZ8mf1rR9VPNcuDwNADiS6v9C1ejjrp/uwgf61YrEdjbWKrF4z56VJWBQ89VA0 IHnz0ql5OtNcHKcOQ8daEpC1H2hoIjBQcm4F1Br04DcUu4ZVRVWMWU80td029nhLkjVW Ap6yP7cT9/0Dy3zH1N+mVVjRD8eSMXwphCL3fwbfYuEPEQTppg326UyhFuFWahfIGDQN K/Khr1XBJrr1TOVAlFO/D1DbbQNrk4ctSTxZK1dAXcNUmk5OOqJNDa38tlJcZPgIypua 0d/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=LYRxRKjh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gz21-20020a170906f2d500b0099027b40d82si2648055ejb.243.2023.07.31.06.47.35; Mon, 31 Jul 2023 06:47:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=LYRxRKjh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231461AbjGaKtf (ORCPT + 99 others); Mon, 31 Jul 2023 06:49:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231439AbjGaKtW (ORCPT ); Mon, 31 Jul 2023 06:49:22 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A8561721 for ; Mon, 31 Jul 2023 03:49:09 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-56942442eb0so54515817b3.1 for ; Mon, 31 Jul 2023 03:49:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800549; x=1691405349; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=YBnr3ePqGRSHGL39Ok/yCt1mWN8mbG/Gp+AtUdQxaUU=; b=LYRxRKjhcjiEFyRGbuA+d1Htgawgo/mKs784rG+yG74V+0fqyVm0Ry2Hrugx5xM0Mb f+95tqZfWPpiQRd9XIJKCF8aL1+sSWUWh7xWkWKxeylOfQotrpey7e4Qb/uBcWUIvRad UepvQdRCnE6DbhEU2QCoTsO3qOlmthhnQsYmgTOuH8ADFKp8NN5baiPeenqOLF+60zDv mLo4wS02dl4CdyZ4Rx4I8pK2cVAJsDlkIvpSgJG8n+T62SLTXTSnjtGBepLgTupMWT8G a4oo9VLx3G3K/+6o6aqP9kDekhq8jOGqMwLLON42QcuTNV+jYNhstOXAUL8aDBv4T0sJ 4N4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800549; x=1691405349; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YBnr3ePqGRSHGL39Ok/yCt1mWN8mbG/Gp+AtUdQxaUU=; b=l62UFMEQXmcJCpPC4jWNwYibcS5GKwvV6ZFCL2yon9W2KhtKdccyO9op92Xt0RXFDX qlw6l9lKXn5sNUSArOkSV2HiiP4GyLfCSX4UR5b9OT55KoXyiklolg9GvHd57JreWiir e9Hq+o/cFxXUWmZHF3K4WQD/eduLtP5jGshOvw3dWOYzuwzGHKTYiKNxquW8wwJT+PhV 5/vrNRlvNC2xxlf1tq4M24+v4ExJkHSnT7VDNNDmKHmHV1dBFM60m26KFc5NgHa6yTqX NiOjBHkB0Nkpn4wtdqj9bcrlU7osd8fcDdWZy6OyRIo6ExNvCOn+B+8+MBfkFzSFjVND 4xKA== X-Gm-Message-State: ABy/qLZe4FK9VbwZYFgafCLpw2j8YbJWh8yuL0K3ByOw4Qn2wf+YAoLR bHOx2Vi2/54/WbYYSqfsbrdllMun77+1 X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a05:6902:160e:b0:d09:6ba9:69ec with SMTP id bw14-20020a056902160e00b00d096ba969ecmr55603ybb.4.1690800549003; Mon, 31 Jul 2023 03:49:09 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:16 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.6.I219054a6cf538df5bb22f4ada2d9933155d6058c@changeid> Subject: [PATCH v2 6/8] iommu/arm-smmu-v3: Refactor write_ctx_desc From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772944128735890296 X-GMAIL-MSGID: 1772944128735890296 Update arm_smmu_write_ctx_desc and downstream functions to operate on a master instead of an smmu domain. We expect arm_smmu_write_ctx_desc() to only be called to write a CD entry into a CD table owned by the master. Under the hood, arm_smmu_write_ctx_desc still fetches the CD table from the domain that is attached to the master, but a subsequent commit will move that table's ownership to the master. Note that this change isn't a nop refactor since SVA will call arm_smmu_write_ctx_desc in a loop for every master the domain is attached to despite the fact that they all share the same CD table. This loop may look weird but becomes necessary when the CD table becomes per-master in a subsequent commit. Signed-off-by: Michael Shavit --- Changes in v2: - minor style fixes Changes in v1: - arm_smmu_write_ctx_desc now get's the CD table to write to from the master parameter instead of a distinct parameter. This works well because the CD table being written to should always be owned by the master by the end of this series. This version no longer allows master to be NULL. .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 33 +++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 59 ++++++++----------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- 3 files changed, 53 insertions(+), 41 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 968559d625c40..8242ee3405f2d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -45,9 +45,11 @@ static struct arm_smmu_ctx_desc * arm_smmu_share_asid(struct mm_struct *mm, u16 asid) { int ret; + unsigned long flags; u32 new_asid; struct arm_smmu_ctx_desc *cd; struct arm_smmu_device *smmu; + struct arm_smmu_master *master; struct arm_smmu_domain *smmu_domain; cd = xa_load(&arm_smmu_asid_xa, asid); @@ -80,7 +82,11 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) * be some overlap between use of both ASIDs, until we invalidate the * TLB. */ - arm_smmu_write_ctx_desc(smmu_domain, 0, cd); + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + arm_smmu_write_ctx_desc(master, 0, cd); + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); /* Invalidate TLB entries previously associated with that context */ arm_smmu_tlb_inv_asid(smmu, asid); @@ -211,6 +217,8 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) { struct arm_smmu_mmu_notifier *smmu_mn = mn_to_smmu(mn); struct arm_smmu_domain *smmu_domain = smmu_mn->domain; + struct arm_smmu_master *master; + unsigned long flags; mutex_lock(&sva_lock); if (smmu_mn->cleared) { @@ -222,7 +230,11 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) * DMA may still be running. Keep the cd valid to avoid C_BAD_CD events, * but disable translation. */ - arm_smmu_write_ctx_desc(smmu_domain, mm->pasid, &quiet_cd); + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + arm_smmu_write_ctx_desc(master, mm->pasid, &quiet_cd); + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_mn->cd->asid); arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, 0, 0); @@ -248,7 +260,9 @@ arm_smmu_mmu_notifier_get(struct arm_smmu_domain *smmu_domain, struct mm_struct *mm) { int ret; + unsigned long flags; struct arm_smmu_ctx_desc *cd; + struct arm_smmu_master *master; struct arm_smmu_mmu_notifier *smmu_mn; list_for_each_entry(smmu_mn, &smmu_domain->mmu_notifiers, list) { @@ -279,7 +293,11 @@ arm_smmu_mmu_notifier_get(struct arm_smmu_domain *smmu_domain, goto err_free_cd; } - ret = arm_smmu_write_ctx_desc(smmu_domain, mm->pasid, cd); + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + ret = arm_smmu_write_ctx_desc(master, mm->pasid, cd); + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); if (ret) goto err_put_notifier; @@ -296,6 +314,8 @@ arm_smmu_mmu_notifier_get(struct arm_smmu_domain *smmu_domain, static void arm_smmu_mmu_notifier_put(struct arm_smmu_mmu_notifier *smmu_mn) { + unsigned long flags; + struct arm_smmu_master *master; struct mm_struct *mm = smmu_mn->mn.mm; struct arm_smmu_ctx_desc *cd = smmu_mn->cd; struct arm_smmu_domain *smmu_domain = smmu_mn->domain; @@ -304,7 +324,12 @@ static void arm_smmu_mmu_notifier_put(struct arm_smmu_mmu_notifier *smmu_mn) return; list_del(&smmu_mn->list); - arm_smmu_write_ctx_desc(smmu_domain, mm->pasid, NULL); + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + arm_smmu_write_ctx_desc(master, mm->pasid, NULL); + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); /* * If we went through clear(), we've already invalidated, and no diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 4f7fe19d88fda..f1d480a391511 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -971,14 +971,12 @@ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); } -static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain, +static void arm_smmu_sync_cd(struct arm_smmu_master *master, int ssid, bool leaf) { size_t i; - unsigned long flags; - struct arm_smmu_master *master; struct arm_smmu_cmdq_batch cmds; - struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_device *smmu = master->smmu; struct arm_smmu_cmdq_ent cmd = { .opcode = CMDQ_OP_CFGI_CD, .cfgi = { @@ -987,19 +985,14 @@ static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain, }, }; - if (!smmu_domain->cd_table.installed) + if (!master->domain->cd_table.installed) return; cmds.num = 0; - - spin_lock_irqsave(&smmu_domain->devices_lock, flags); - list_for_each_entry(master, &smmu_domain->devices, domain_head) { - for (i = 0; i < master->num_streams; i++) { - cmd.cfgi.sid = master->streams[i].id; - arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); - } + for (i = 0; i < master->num_streams; i++) { + cmd.cfgi.sid = master->streams[i].id; + arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); } - spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); arm_smmu_cmdq_batch_submit(smmu, &cmds); } @@ -1029,14 +1022,13 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, WRITE_ONCE(*dst, cpu_to_le64(val)); } -static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_domain *smmu_domain, - u32 ssid) +static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) { __le64 *l1ptr; unsigned int idx; struct arm_smmu_l1_ctx_desc *l1_desc; - struct arm_smmu_device *smmu = smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; + struct arm_smmu_device *smmu = master->smmu; + struct arm_smmu_ctx_desc_cfg *cdcfg = &master->domain->cd_table; if (!cdcfg->l1_desc) return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; @@ -1050,13 +1042,13 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_domain *smmu_domain, l1ptr = cdcfg->cdtab + idx * CTXDESC_L1_DESC_DWORDS; arm_smmu_write_cd_l1_desc(l1ptr, l1_desc); /* An invalid L1CD can be cached */ - arm_smmu_sync_cd(smmu_domain, ssid, false); + arm_smmu_sync_cd(master, ssid, false); } idx = ssid & (CTXDESC_L2_ENTRIES - 1); return l1_desc->l2ptr + idx * CTXDESC_CD_DWORDS; } -int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, +int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, struct arm_smmu_ctx_desc *cd) { /* @@ -1073,11 +1065,12 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, u64 val; bool cd_live; __le64 *cdptr; + struct arm_smmu_ctx_desc_cfg *cd_table = &master->domain->cd_table; - if (WARN_ON(ssid >= (1 << smmu_domain->cd_table.max_cds_bits))) + if (WARN_ON(ssid >= (1 << cd_table->max_cds_bits))) return -E2BIG; - cdptr = arm_smmu_get_cd_ptr(smmu_domain, ssid); + cdptr = arm_smmu_get_cd_ptr(master, ssid); if (!cdptr) return -ENOMEM; @@ -1101,11 +1094,11 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, cdptr[3] = cpu_to_le64(cd->mair); /* - * STE may be live, and the SMMU might read dwords of this CD in any - * order. Ensure that it observes valid values before reading - * V=1. + * STE may be live, and the SMMU might read dwords of this CD + * in any order. Ensure that it observes valid values before + * reading V=1. */ - arm_smmu_sync_cd(smmu_domain, ssid, true); + arm_smmu_sync_cd(master, ssid, true); val = cd->tcr | #ifdef __BIG_ENDIAN @@ -1117,7 +1110,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) | CTXDESC_CD_0_V; - if (smmu_domain->cd_table.stall_enabled) + if (cd_table->stall_enabled) val |= CTXDESC_CD_0_S; } @@ -1131,7 +1124,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, * without first making the structure invalid. */ WRITE_ONCE(cdptr[0], cpu_to_le64(val)); - arm_smmu_sync_cd(smmu_domain, ssid, true); + arm_smmu_sync_cd(master, ssid, true); return 0; } @@ -1141,7 +1134,7 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, int ret; size_t l1size; size_t max_contexts; - struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_device *smmu = master->smmu; struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; cdcfg->stall_enabled = master->stall_enabled; @@ -2141,12 +2134,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; cd->mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; - /* - * Note that this will end up calling arm_smmu_sync_cd() before - * the master has been added to the devices list for this domain. - * This isn't an issue because the STE hasn't been installed yet. - */ - ret = arm_smmu_write_ctx_desc(smmu_domain, 0, cd); + ret = arm_smmu_write_ctx_desc(master, 0, cd); if (ret) goto out_free_cd_tables; @@ -2464,8 +2452,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && - smmu_domain->cd_table.stall_enabled != - master->stall_enabled) { + smmu_domain->cd_table.stall_enabled != master->stall_enabled) { ret = -EINVAL; goto out_unlock; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 3a56987a5fd0b..c7e8684fd887d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -746,7 +746,7 @@ extern struct xarray arm_smmu_asid_xa; extern struct mutex arm_smmu_asid_lock; extern struct arm_smmu_ctx_desc quiet_cd; -int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, +int arm_smmu_write_ctx_desc(struct arm_smmu_master *smmu_master, int ssid, struct arm_smmu_ctx_desc *cd); void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid); void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, From patchwork Mon Jul 31 10:48:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 128588 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp1936330vqg; Mon, 31 Jul 2023 04:06:56 -0700 (PDT) X-Google-Smtp-Source: APBJJlG3Av0YDqYSbbhnQrXxPJVdsDWs1YexNKCRMZiAFGoL/GIxa9aQFXZn7EGpMwQbRhitWtcX X-Received: by 2002:a17:906:7788:b0:987:498a:87f6 with SMTP id s8-20020a170906778800b00987498a87f6mr5974730ejm.34.1690801616033; Mon, 31 Jul 2023 04:06:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690801616; cv=none; d=google.com; s=arc-20160816; b=E7vMoWmCRQBWOC1HfTacyahl1P9bWx5xydawJ1noh4jwkw1suRgPSpWpk01pjqBo1R ZhOoveqJTaINOGOq55v23imhGZ0zrH3IlWNYivE17xq1mGu60Ac3FBoSZ8sboKHlsrXN 949jtOuS6JB5z2+8lkPB7+X11wP9b1LLKCCQE5FxiGFToetSa5dJiLvT8U6oTL6PvhRs 4x3sjElUJFBHsgrQPAmrqTq4HwyT0MxgTW+UIsgv6T7gQUKsMR3b3ekvfrtonrsnGLIp quhZIq7iTrBBoTvrIuv9yaJaBxK1rveg4OwThr/MOxS2MQ6MZV7iWf4V4jMbd5QIcqWx iJ9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:dkim-signature; bh=ZelAiweKReDmZ+3ilWf0JDqwAE1IZFSEFfM52cq7NZw=; fh=51loh+OS6vr0QdvTi7t7xEP2VSRDvSfeMVfkb8abBBs=; b=CV/eysj9VGATc+KIHMjcxFXLcNiRUFC1ylPdQ4IyTKtKwQKXc2nlMOJ1yQQ2ckUVF3 8jOCM5bxbbfu3pvv0UhaWrJ5iIdDUQr5tfKgrIQKodPJp9he3aGUTDGrJpnmD0oxCQfr FtX3i7y3kV2a+11Kr9BPTDUZS6dq5KohkD39AjTqSHFrK3oluswajZNQBHI34cCB5WxP kS/y0XxZshJ+tk2YSWiRj0yKM5Issf7Sd4cCp3KMwRPKN7/FdqEEB5W+VvQE7w6/y3T7 otXQ4VcZ/JimqBl0ezo0UhS/x5j2VWqP+xqmg8gTn10DcDwV0OyzGEddCxQNOx7Aqtgj M+Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=vUHur2ZU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j13-20020a17090686cd00b0099bd4f6106esi6486882ejy.105.2023.07.31.04.06.31; Mon, 31 Jul 2023 04:06:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=vUHur2ZU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231352AbjGaKu3 (ORCPT + 99 others); Mon, 31 Jul 2023 06:50:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231338AbjGaKtv (ORCPT ); Mon, 31 Jul 2023 06:49:51 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9869719A5 for ; Mon, 31 Jul 2023 03:49:14 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-584139b6b03so51160867b3.3 for ; Mon, 31 Jul 2023 03:49:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800553; x=1691405353; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=ZelAiweKReDmZ+3ilWf0JDqwAE1IZFSEFfM52cq7NZw=; b=vUHur2ZUeGbn36wju3MyWP3BjmNmzXpPoRYPra0Fl2aCHoclVCDB2JsQjjaNf2fV4K BsTNJS4JCxVmpQhLz/qz6kJmRbc8A6hiJSZczZBn+0ef1qoee+I3FY7VEAc0j4c8L8I2 QCPqIwuscv1FbyUbZLTaaSB56oXwMOJmzKTKUDCFxMxYgDMGw5saOnFiUNG9ejNtttnG gnjkLkfAVc43dc0lDoEEeMP6o/HjgVcSCtedF3INApdnkmNfocK4AdEWgXnHWLt3LJec dMGOjH7arCZgm8ay2638PewXNbHOUp9eTgL7fs+qIMAPSm5xWY1A55FUfm5AuWvirraM 5HLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800553; x=1691405353; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ZelAiweKReDmZ+3ilWf0JDqwAE1IZFSEFfM52cq7NZw=; b=gRPUisZL+CwOLk0R3Z+7yWw+C2hY50nBFdEDFmqu0B0/SpXcZfRzIZWySO0mSZL7Xv h5KF33SQIPLcQvPJPD4q/AIqPGkNHZ9B12nvkup0ukN71dac60t2sxvozmS6CVrNUtn4 umf8U1mnufZluX7ZC91bcF2ZmtvHNNl1AF32weFajzDMk38/N8N+FhAq6qNmK8blAdEo pMhsZYka8fRhZBHtieNcg994t3twW/+T2ych+G7gbkOoDm9TxpmL//ZmYLusg3x2gCn4 wGXiyb++Jn/Q0gkqdp5ulk88TmLrYlt3A/4tNni4fzWOa5lOxn+SavA+IlVySHRlWW+t twAg== X-Gm-Message-State: ABy/qLZSl9XuN0oaYMVtJzDPvAIkf/5Cx+1ZeXnxcaoZY66YiSXWV8p1 4uo7tUTtTfcH6hyXk+ykqXnflCi6YdYq X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a05:6902:100f:b0:cf9:3564:33cc with SMTP id w15-20020a056902100f00b00cf9356433ccmr61438ybt.13.1690800553122; Mon, 31 Jul 2023 03:49:13 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:17 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.7.Ice063dcf87d1b777a72e008d9e3406d2bcf6d876@changeid> Subject: [PATCH v2 7/8] iommu/arm-smmu-v3: Move CD table to arm_smmu_master From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772933995638519222 X-GMAIL-MSGID: 1772933995638519222 With this change, each master will now own its own CD table instead of sharing one with other masters attached to the same domain. Attaching a stage 1 domain installs CD entries into the master's CD table. SVA writes its CD entries into each master's CD table if the domain is shared across masters. Signed-off-by: Michael Shavit Reviewed-by: Jason Gunthorpe --- Changes in v2: - Allocate CD table when it's first needed instead of on probe. Changes in v1: - The master's CD table allocation was previously split to a different commit. This change now atomically allocates the new CD table, uses it, and removes the old one. drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 67 +++++++++------------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 +- 2 files changed, 32 insertions(+), 41 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f1d480a391511..2949e1ad3914a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -985,7 +985,7 @@ static void arm_smmu_sync_cd(struct arm_smmu_master *master, }, }; - if (!master->domain->cd_table.installed) + if (!master->cd_table.installed) return; cmds.num = 0; @@ -1028,7 +1028,7 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) unsigned int idx; struct arm_smmu_l1_ctx_desc *l1_desc; struct arm_smmu_device *smmu = master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg = &master->domain->cd_table; + struct arm_smmu_ctx_desc_cfg *cdcfg = &master->cd_table; if (!cdcfg->l1_desc) return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; @@ -1065,7 +1065,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, u64 val; bool cd_live; __le64 *cdptr; - struct arm_smmu_ctx_desc_cfg *cd_table = &master->domain->cd_table; + struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; if (WARN_ON(ssid >= (1 << cd_table->max_cds_bits))) return -E2BIG; @@ -1128,14 +1128,13 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, return 0; } -static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, - struct arm_smmu_master *master) +static int arm_smmu_alloc_cd_tables(struct arm_smmu_master *master) { int ret; size_t l1size; size_t max_contexts; struct arm_smmu_device *smmu = master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; + struct arm_smmu_ctx_desc_cfg *cdcfg = &master->cd_table; cdcfg->stall_enabled = master->stall_enabled; cdcfg->max_cds_bits = master->ssid_bits; @@ -1177,12 +1176,12 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, return ret; } -static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain) +static void arm_smmu_free_cd_tables(struct arm_smmu_master *master) { int i; size_t size, l1size; - struct arm_smmu_device *smmu = smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; + struct arm_smmu_device *smmu = master->smmu; + struct arm_smmu_ctx_desc_cfg *cdcfg = &master->cd_table; if (cdcfg->l1_desc) { size = CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3); @@ -1290,7 +1289,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, if (smmu_domain) { switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: - cd_table = &smmu_domain->cd_table; + cd_table = &master->cd_table; break; case ARM_SMMU_DOMAIN_S2: case ARM_SMMU_DOMAIN_NESTED: @@ -2081,14 +2080,10 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) free_io_pgtable_ops(smmu_domain->pgtbl_ops); - /* Free the CD and ASID, if we allocated them */ + /* Free the ASID or VMID */ if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { - struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; - /* Prevent SVA from touching the CD while we're freeing it */ mutex_lock(&arm_smmu_asid_lock); - if (cdcfg->cdtab) - arm_smmu_free_cd_tables(smmu_domain); arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); } else { @@ -2100,7 +2095,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) kfree(smmu_domain); } -static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, +static int arm_smmu_domain_finalise_cd(struct arm_smmu_domain *smmu_domain, struct arm_smmu_master *master, struct io_pgtable_cfg *pgtbl_cfg) { @@ -2119,10 +2114,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, if (ret) goto out_unlock; - ret = arm_smmu_alloc_cd_tables(smmu_domain, master); - if (ret) - goto out_free_asid; - cd->asid = (u16)asid; cd->ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; cd->tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | @@ -2134,17 +2125,9 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; cd->mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; - ret = arm_smmu_write_ctx_desc(master, 0, cd); - if (ret) - goto out_free_cd_tables; - mutex_unlock(&arm_smmu_asid_lock); return 0; -out_free_cd_tables: - arm_smmu_free_cd_tables(smmu_domain); -out_free_asid: - arm_smmu_free_asid(cd); out_unlock: mutex_unlock(&arm_smmu_asid_lock); return ret; @@ -2207,7 +2190,7 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, ias = min_t(unsigned long, ias, VA_BITS); oas = smmu->ias; fmt = ARM_64_LPAE_S1; - finalise_stage_fn = arm_smmu_domain_finalise_s1; + finalise_stage_fn = arm_smmu_domain_finalise_cd; break; case ARM_SMMU_DOMAIN_NESTED: case ARM_SMMU_DOMAIN_S2: @@ -2447,14 +2430,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) } else if (smmu_domain->smmu != smmu) { ret = -EINVAL; goto out_unlock; - } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && - master->ssid_bits != smmu_domain->cd_table.max_cds_bits) { - ret = -EINVAL; - goto out_unlock; - } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && - smmu_domain->cd_table.stall_enabled != master->stall_enabled) { - ret = -EINVAL; - goto out_unlock; } master->domain = smmu_domain; @@ -2469,6 +2444,22 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) if (smmu_domain->stage != ARM_SMMU_DOMAIN_BYPASS) master->ats_enabled = arm_smmu_ats_supported(master); + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + if (!master->cd_table.cdtab) { + ret = arm_smmu_alloc_cd_tables(master); + if (ret) { + master->domain = NULL; + goto out_unlock; + } + } + + ret = arm_smmu_write_ctx_desc(master, 0, &smmu_domain->cd); + if (ret) { + master->domain = NULL; + goto out_unlock; + } + } + arm_smmu_install_ste_for_dev(master); spin_lock_irqsave(&smmu_domain->devices_lock, flags); @@ -2723,6 +2714,8 @@ static void arm_smmu_release_device(struct device *dev) arm_smmu_detach_dev(master); arm_smmu_disable_pasid(master); arm_smmu_remove_master(master); + if (master->cd_table.cdtab_dma) + arm_smmu_free_cd_tables(master); kfree(master); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index c7e8684fd887d..0ee3dc7291a15 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -696,6 +696,7 @@ struct arm_smmu_master { struct arm_smmu_domain *domain; struct list_head domain_head; struct arm_smmu_stream *streams; + struct arm_smmu_ctx_desc_cfg cd_table; unsigned int num_streams; bool ats_enabled; bool stall_enabled; @@ -722,11 +723,8 @@ struct arm_smmu_domain { enum arm_smmu_domain_stage stage; union { - struct { struct arm_smmu_ctx_desc cd; - struct arm_smmu_ctx_desc_cfg cd_table; - }; - struct arm_smmu_s2_cfg s2_cfg; + struct arm_smmu_s2_cfg s2_cfg; }; struct iommu_domain domain; From patchwork Mon Jul 31 10:48:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 128605 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp1948721vqg; Mon, 31 Jul 2023 04:30:55 -0700 (PDT) X-Google-Smtp-Source: APBJJlH7q/obD9y+Z/EyEsAeCKvuzmW5FrQjku4w0O6sIUHzxO5uxtD7Z2O8vPvBKiJJtprt/aEz X-Received: by 2002:a05:6402:27d2:b0:522:b723:11bd with SMTP id c18-20020a05640227d200b00522b72311bdmr7098189ede.4.1690803055673; Mon, 31 Jul 2023 04:30:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690803055; cv=none; d=google.com; s=arc-20160816; b=nbfCBV1De+HY3zDC+ieZKmLyVnydx8Z0D7NMTIwnkxXZYFaZtzo1O4JZJLqiRiNPpl Io5wBpcVnPUz4emFMcp0nWyNoSTI8H/68c1e4YL0qUIAErml+35rgNs0LfdkWPCOXGPE PJK3g50R4lDL2fuLES+kLAUFOq/5RSlx5fSligAKzyHK8fq15xwXORLBoLX2Cv4oegow yKDazkra3zsypmyV6C2i6yp2KjkqDOYQqbX+4W1P2YkBkPGgXHKdGATXNYBJrnFs4nQ4 6iqK4MckPlOcw8gOB523vcOREjg35fntAX5BIS6Uv/5RnsO9M4IUfqZlpGTlJh7UAaBY NP4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:dkim-signature; bh=YJP5V5vq+SKeEm3Hg6wbMxauuZX6cc204/bKb76wukw=; fh=51loh+OS6vr0QdvTi7t7xEP2VSRDvSfeMVfkb8abBBs=; b=cSSdu9VD+Qk9sKKh8tl6QS0wPrxz3C/0iQV3sKjJcSgn8DPRZHtM19ZHdBP3qaL8rz whQC6fSYFCoDpMzD6mH/CbjBKMr0W43jOQuLiktaXHO4yc2iHrIdR9zF4LJhyk1PKFZE UaPA7VOmO/EaILFCCYKq6rUrqoigs9xlWEk6MshLSZo4BicnpfIE1WUCn6OzRDROEHrC 1gEzSacUQgo2gi6dRFwpBSoYFuY+6SqU/Tdaxb/pDBe8jcyqVm4tFnuvNSykOQtnGhEe 29FmJojsNxag35LHhouP/wwhnkj9lEagrv2wMt1GRL1BGFA1wtABxXMA5zp/czM0I2JW tzCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=kq+q2jNz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g7-20020aa7d1c7000000b005223abb31ccsi6577559edp.354.2023.07.31.04.30.31; Mon, 31 Jul 2023 04:30:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=kq+q2jNz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231533AbjGaKuA (ORCPT + 99 others); Mon, 31 Jul 2023 06:50:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231823AbjGaKtf (ORCPT ); Mon, 31 Jul 2023 06:49:35 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD4DD1BD2 for ; Mon, 31 Jul 2023 03:49:18 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-58456435437so52986397b3.0 for ; Mon, 31 Jul 2023 03:49:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800557; x=1691405357; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=YJP5V5vq+SKeEm3Hg6wbMxauuZX6cc204/bKb76wukw=; b=kq+q2jNzWK9y2fTrKQKudw+D1sNOrIVWQZ433hIGaziSm+xkYYQUEaHicxjLKL+vXr Y60Z/C+zPA1NJHn5J+uYrYdgYnnYXEB4MOc3VyvA80v8WCDt0hqYT8HqIX/lZIpHv0Fi knSZro52XgdVS+IX0sGzvA+FLf0XSvfxp6ZK0pE92iSym9jLJIIYYfNidymeo90TPfqq ZwtlEms+je4ryDy1fPVy5cfyoIHlN0JwAC89gVcQLE9WuTDTnuDKG1E3ebIjUGdZ2fAQ z39MYenrRrTEBHmmxEaeoMU9R1p9+TyXTkN35woawfCMlGfvdmpXnnSOnuM8B7lDrJIk Rbkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800557; x=1691405357; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YJP5V5vq+SKeEm3Hg6wbMxauuZX6cc204/bKb76wukw=; b=ZHVjmkkdV45VKrdBTAz2hdDzjXjG6w6txlwmeyhfIHsIOsVamj3EkiJkTm/7UqecXS 6au7d89LYKYQLSoLb7Ad0pV0dU60E/68JzH5vTX2yBJ9E8QtYe6ooB7rydFR38P3o8TF 18mZncWrPnaCDZ3OzNLoBOZQBUFoz55D9OYpDF7h/n7AGLWXeaCG1MvAwr+vFovoGqNQ WhykC8cjZfzN8etJEOannYMU02q++lXQ5GP+ZPhKZC64XHdsp6qSjBMGxVmhszXM0tLF Brhf+NfGHXZvl7hPK/000xe0KD2RAX7tw5CTmU7BUv1IJDJicc7AN3wDfGMztEIU+eU3 7Veg== X-Gm-Message-State: ABy/qLZ9rNn6KAHfX+fEo5U89FzknHmqM997oEuPXzDF5e7Rtq0C8AXr nejuguf+lz3R7El+NI0ZnooHulcFbonw X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a25:e743:0:b0:d10:5b67:843c with SMTP id e64-20020a25e743000000b00d105b67843cmr50706ybh.4.1690800557330; Mon, 31 Jul 2023 03:49:17 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:18 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.8.I5ee79793b444ddb933e8bc1eb7b77e728d7f8350@changeid> Subject: [PATCH v2 8/8] iommu/arm-smmu-v3: Rename cdcfg to cd_table From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772935505316627802 X-GMAIL-MSGID: 1772935505316627802 since cdcfg sounds like it represents a CD entry when it's in fact a CD table. Signed-off-by: Michael Shavit Reviewed-by: Jason Gunthorpe --- Changes in v2: - New commit drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 66 ++++++++++----------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 2949e1ad3914a..b8e6f056bf36d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1028,18 +1028,18 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) unsigned int idx; struct arm_smmu_l1_ctx_desc *l1_desc; struct arm_smmu_device *smmu = master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg = &master->cd_table; + struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; - if (!cdcfg->l1_desc) - return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; + if (!cd_table->l1_desc) + return cd_table->cdtab + ssid * CTXDESC_CD_DWORDS; idx = ssid >> CTXDESC_SPLIT; - l1_desc = &cdcfg->l1_desc[idx]; + l1_desc = &cd_table->l1_desc[idx]; if (!l1_desc->l2ptr) { if (arm_smmu_alloc_cd_leaf_table(smmu, l1_desc)) return NULL; - l1ptr = cdcfg->cdtab + idx * CTXDESC_L1_DESC_DWORDS; + l1ptr = cd_table->cdtab + idx * CTXDESC_L1_DESC_DWORDS; arm_smmu_write_cd_l1_desc(l1ptr, l1_desc); /* An invalid L1CD can be cached */ arm_smmu_sync_cd(master, ssid, false); @@ -1134,33 +1134,33 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_master *master) size_t l1size; size_t max_contexts; struct arm_smmu_device *smmu = master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg = &master->cd_table; + struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; - cdcfg->stall_enabled = master->stall_enabled; - cdcfg->max_cds_bits = master->ssid_bits; - max_contexts = 1 << cdcfg->max_cds_bits; + cd_table->stall_enabled = master->stall_enabled; + cd_table->max_cds_bits = master->ssid_bits; + max_contexts = 1 << cd_table->max_cds_bits; if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || max_contexts <= CTXDESC_L2_ENTRIES) { - cdcfg->num_l1_ents = max_contexts; + cd_table->num_l1_ents = max_contexts; l1size = max_contexts * (CTXDESC_CD_DWORDS << 3); } else { - cdcfg->num_l1_ents = DIV_ROUND_UP(max_contexts, + cd_table->num_l1_ents = DIV_ROUND_UP(max_contexts, CTXDESC_L2_ENTRIES); - cdcfg->l1_desc = devm_kcalloc(smmu->dev, cdcfg->num_l1_ents, - sizeof(*cdcfg->l1_desc), + cd_table->l1_desc = devm_kcalloc(smmu->dev, cd_table->num_l1_ents, + sizeof(*cd_table->l1_desc), GFP_KERNEL); - if (!cdcfg->l1_desc) + if (!cd_table->l1_desc) return -ENOMEM; - l1size = cdcfg->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3); + l1size = cd_table->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3); } - cdcfg->cdtab = dmam_alloc_coherent(smmu->dev, l1size, &cdcfg->cdtab_dma, + cd_table->cdtab = dmam_alloc_coherent(smmu->dev, l1size, &cd_table->cdtab_dma, GFP_KERNEL); - if (!cdcfg->cdtab) { + if (!cd_table->cdtab) { dev_warn(smmu->dev, "failed to allocate context descriptor\n"); ret = -ENOMEM; goto err_free_l1; @@ -1169,9 +1169,9 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_master *master) return 0; err_free_l1: - if (cdcfg->l1_desc) { - devm_kfree(smmu->dev, cdcfg->l1_desc); - cdcfg->l1_desc = NULL; + if (cd_table->l1_desc) { + devm_kfree(smmu->dev, cd_table->l1_desc); + cd_table->l1_desc = NULL; } return ret; } @@ -1181,30 +1181,30 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_master *master) int i; size_t size, l1size; struct arm_smmu_device *smmu = master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg = &master->cd_table; + struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; - if (cdcfg->l1_desc) { + if (cd_table->l1_desc) { size = CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3); - for (i = 0; i < cdcfg->num_l1_ents; i++) { - if (!cdcfg->l1_desc[i].l2ptr) + for (i = 0; i < cd_table->num_l1_ents; i++) { + if (!cd_table->l1_desc[i].l2ptr) continue; dmam_free_coherent(smmu->dev, size, - cdcfg->l1_desc[i].l2ptr, - cdcfg->l1_desc[i].l2ptr_dma); + cd_table->l1_desc[i].l2ptr, + cd_table->l1_desc[i].l2ptr_dma); } - devm_kfree(smmu->dev, cdcfg->l1_desc); - cdcfg->l1_desc = NULL; + devm_kfree(smmu->dev, cd_table->l1_desc); + cd_table->l1_desc = NULL; - l1size = cdcfg->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3); + l1size = cd_table->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3); } else { - l1size = cdcfg->num_l1_ents * (CTXDESC_CD_DWORDS << 3); + l1size = cd_table->num_l1_ents * (CTXDESC_CD_DWORDS << 3); } - dmam_free_coherent(smmu->dev, l1size, cdcfg->cdtab, cdcfg->cdtab_dma); - cdcfg->cdtab_dma = 0; - cdcfg->cdtab = NULL; + dmam_free_coherent(smmu->dev, l1size, cd_table->cdtab, cd_table->cdtab_dma); + cd_table->cdtab_dma = 0; + cd_table->cdtab = NULL; } bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd)