From patchwork Mon Jul 31 01:17:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 128307 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp1740989vqg; Sun, 30 Jul 2023 18:28:11 -0700 (PDT) X-Google-Smtp-Source: APBJJlEtexdQJTc7PL/SVRxjRcHhH6rQWvAdnFCPu4yZAXpq8sweiKbYbTPezSqMKlsotrLITEWH X-Received: by 2002:a17:907:78d3:b0:991:e7c2:d0be with SMTP id kv19-20020a17090778d300b00991e7c2d0bemr6892264ejc.63.1690766891257; Sun, 30 Jul 2023 18:28:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690766891; cv=none; d=google.com; s=arc-20160816; b=MJ7iB+Pj32TyhZoY59ontuNLJvaPXxoj9gzItNi/CCZGA0O5wEOakDehmSnWoBiZkM f/8w63dv4tcTssH35Z/tjUOnvuds1IH0wR0qaYnCXW7X7MJQaUgXJQKIsCyRBHBqxOaU +Cn8kiJ6fhVDDpv+0bwUt78gR0kxHejDR16HKwSBEwdhDyWsMeY9Lj9R5yXYy4+GO9Jq oQkksBjFioVaHj4ualCiztKvmwnvHHCWZzzU+FuHJ4ToH/f/X6hEdEg5oRoU2vv8wsRs 5pCw1ddDudu+DQhSZonlByWYMKU0XlfJEuOAdPsFAdXD5vuVdTBYJyTPHV0XWRJE9mJu Weag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=S2PytuSo5CQRrq/+99o3+o10cXF0ea3Zz2xuFEIV7Yk=; fh=nvt2fN7UnqEO9kn1OY1RExFwWKEspZcEqiYnO1gdBwU=; b=JGaMAHyq4ewkrGuAny/f/ThkUTASUVx9tvDpWJuGalidYKnkTMAytzFm/lR8uUGRfR SZVUMtRuEhiJEftjNHbN8e3ZautOGLCtPJpHwmlASvAqbjeV+tLCkVQp6bVGle5rv7cQ N2F/WRWJF68wZYZuy6nSXEEOA+WC10Ex382nm3acMnBuKteIVFj3m1ImKZm9ryJGy0EW e6O2z9MHuMQp74Tqof7w93pvcCpmbC02yapmXwPGleLx8UbJs/12r0Ot5ux8o3K+7iS1 +h6Ic47zfLSJFJC8WOn+60aQo8gLAmmlR1DiTMfgaYe08tfHNHXh3XKdqujcl3XDjNv6 LPXw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l19-20020a170906079300b0099279b2cdd8si6045036ejc.831.2023.07.30.18.27.47; Sun, 30 Jul 2023 18:28:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229742AbjGaBS3 (ORCPT + 99 others); Sun, 30 Jul 2023 21:18:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229600AbjGaBSZ (ORCPT ); Sun, 30 Jul 2023 21:18:25 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C9DDA1A4; Sun, 30 Jul 2023 18:18:23 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F3080168F; Sun, 30 Jul 2023 18:19:06 -0700 (PDT) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BDD283F5A1; Sun, 30 Jul 2023 18:18:21 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT Date: Mon, 31 Jul 2023 02:17:23 +0100 Message-Id: <20230731011725.7228-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230731011725.7228-1-andre.przywara@arm.com> References: <20230731011725.7228-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772897583764341267 X-GMAIL-MSGID: 1772897583764341267 The Orange Pi Zero 2 got a successor (Zero 3), which shares quite some DT nodes with the Zero 2, but comes with a different PMIC. Move the common parts (except the PMIC) into a new shared file, and include that from the existing board .dts file. No functional change, the generated DTB is the same, except some phandle numbering differences. Signed-off-by: Andre Przywara --- .../allwinner/sun50i-h616-orangepi-zero2.dts | 119 +--------------- .../allwinner/sun50i-h616-orangepi-zerox.dtsi | 131 ++++++++++++++++++ 2 files changed, 132 insertions(+), 118 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zerox.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts index cb8600d0ea1ef..c786b170fb9a8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -5,95 +5,19 @@ /dts-v1/; -#include "sun50i-h616.dtsi" - -#include -#include -#include +#include "sun50i-h616-orangepi-zerox.dtsi" / { model = "OrangePi Zero2"; compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; - - aliases { - ethernet0 = &emac0; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = ; - gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ - default-state = "on"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_vcc5v>; - enable-active-high; - gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ - }; }; -&ehci1 { - status = "okay"; -}; - -/* USB 2 & 3 are on headers only. */ - &emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; phy-supply = <®_dcdce>; - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; - status = "okay"; -}; - -&mdio0 { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; }; &mmc0 { vmmc-supply = <®_dcdce>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; }; &r_rsb { @@ -211,44 +135,3 @@ &pio { vcc-ph-supply = <®_aldo1>; vcc-pi-supply = <®_aldo1>; }; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zerox.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zerox.dtsi new file mode 100644 index 0000000000000..56c7e1d87bd95 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zerox.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + */ + +#include "sun50i-h616.dtsi" + +#include +#include +#include + +/ { + aliases { + ethernet0 = &emac0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + }; +}; + +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; From patchwork Mon Jul 31 01:17:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 128309 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp1742505vqg; Sun, 30 Jul 2023 18:33:33 -0700 (PDT) X-Google-Smtp-Source: APBJJlGkFpS/sV7Tq47/k5Zm78dp2y+qXdZe8aDj9JcDMuxZQOz8SNDxBo94OjMnw/6faCZy8Kh8 X-Received: by 2002:a17:90a:bb81:b0:268:5f1a:ede1 with SMTP id v1-20020a17090abb8100b002685f1aede1mr7517544pjr.36.1690767212753; Sun, 30 Jul 2023 18:33:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690767212; cv=none; d=google.com; s=arc-20160816; b=osp2omzH833960yq6ib5ZVs/t5QMe9aVXEt9yOaUH/bdlEPU7g5+hGVaFUmN7YVW3I 9qL5o7xTsf2Dm3BonxnCAd1F64znumVldEyu+mvBa2jgAebKA0KbE4cq1wC2zHdUIhPN 9SMZTEho0EGcVb5d7kan/ZwSyeHifhjO0IKLqq3Q5FedBI4KxsmOV+RPMiBkNADNnBBA MWH/ze4dSH7J/oPV/s8r7iKisq5YgQrspknbz+UFEjDnaPbyYMb2NkNDmJc0Fh9mPWOa NzY3X7witllYd0wvCOJJu7R33nIRKTEc22cuHJfgx6KPZIda+Y9BBrP8vNOljHkYXTT6 1/bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=JF4pG+APAtBzRkwQ73bO0OImBolre6ewdZZf/WJPV1I=; fh=nvt2fN7UnqEO9kn1OY1RExFwWKEspZcEqiYnO1gdBwU=; b=DFlrU6lMobnMzSYzBcmOx+SnG7gIzm3dmv6oUgACKU/rc42aYIVuy9ffkAfdz7hdoO iamCbUJkrYbfXLIa34JlxWLqVG6jwFJMNC+oNmoJenVuSwxms7HehYG9Q9NYW4LGGLUO Ue/IVtvjH4b3z3dXpH5sKiRYJMcJc7UpPo0QAT5fLtGaZpw2UVyL8n1LeVKb4HJh696A GpLM3F66EXelpbK+Jhet+Qm8CAU68H3/SM3VOlEi2WQpfvh22QMCAqVhi6TIeYRcV67i RM8AoksPTu9tzvhjIEWyoRRf3MJ74Q/Tx/tn3yEKzM9XpDvg1t1zX4i0wShCKIHBSgqh 3ALA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v24-20020a17090abb9800b0026306b94ee0si6604222pjr.135.2023.07.30.18.33.20; Sun, 30 Jul 2023 18:33:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229752AbjGaBSb (ORCPT + 99 others); Sun, 30 Jul 2023 21:18:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229726AbjGaBS0 (ORCPT ); Sun, 30 Jul 2023 21:18:26 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AA99E1A2; Sun, 30 Jul 2023 18:18:25 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D634E1691; Sun, 30 Jul 2023 18:19:08 -0700 (PDT) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C714D3F5A1; Sun, 30 Jul 2023 18:18:23 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] dt-bindings: arm: sunxi: document Orange Pi Zero 3 board name Date: Mon, 31 Jul 2023 02:17:24 +0100 Message-Id: <20230731011725.7228-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230731011725.7228-1-andre.przywara@arm.com> References: <20230731011725.7228-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772897920894557618 X-GMAIL-MSGID: 1772897920894557618 The Orange Pi Zero 3 board is an updated version of the Zero 2 board. It uses a SoC called H618, which just seems to be an H616 with more L2 cache. Add the board/SoC compatible string pair to the list of known boards. Signed-off-by: Andre Przywara Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ee8fdd2da869a..58f322b9585f2 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -997,4 +997,9 @@ properties: - const: xunlong,orangepi-zero2 - const: allwinner,sun50i-h616 + - description: Xunlong OrangePi Zero 3 + items: + - const: xunlong,orangepi-zero3 + - const: allwinner,sun50i-h618 + additionalProperties: true From patchwork Mon Jul 31 01:17:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 128312 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp1750218vqg; Sun, 30 Jul 2023 19:02:07 -0700 (PDT) X-Google-Smtp-Source: APBJJlHPTEelGfeZWEsw6yRvcjysEtXWWks36lwi1y6YV/bssNfbW3mLWKtN3LK0qUGiDqaULae+ X-Received: by 2002:a17:907:2cea:b0:993:e860:f20 with SMTP id hz10-20020a1709072cea00b00993e8600f20mr5691773ejc.19.1690768927414; Sun, 30 Jul 2023 19:02:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690768927; cv=none; d=google.com; s=arc-20160816; b=CKMheUdZg573JGYpisjLf8+gcSdRLsKeuZkb9zpOKZ2mt+9juZg9KWVKJF4w5RW1TI jbpPg2nWCV7HSF6SDsaz7kangrjePtieJOuMaK72G5/Xto+usr9rjPbvEutMQBuG4ULa vwCWy3nVM/en2d7eIPiAx9/shnn127tcvPF75n6yF72mqF3skGU0DCvbPWpUffU94Kvb jsUQywgM8pzTu5uap/WrXAVZ6H2837CL1zo/5Fv8S7U8bEmjIX9tAn5QiCegePTVhndC RLS2YNFKZXmHPhW+R4Fu8j56mTClnjcSayRUc2ghr4aT/rY8pEwHqMj8Bl8rpYkim1ua v8mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=F2OMWLZDjUokTn7gTkusls4zqoDj/cE0gZ7oKKF6ajo=; fh=nvt2fN7UnqEO9kn1OY1RExFwWKEspZcEqiYnO1gdBwU=; b=ljxZzf8OAwEmHK3CAU4JlH4mMIZAtm5Oa9D7XfN0vPN/hPqZXUFl3k7Vhi7jvF3Rjg k2jP7rCoMJZS+CIJ2flEmK5JmK3EAwBTHj17I0XXmR531/4kF/AdBlSOCv0SUg68ME5r xc0ArwepsYrJ2e5JyxD1ZwXLtMVhWbN3bq/nTpyHZOrng5MX/CtvzPKjBo21I2XSdSns zaxG6Kgk0D55VkNwjOoB2LKb3rs+NPqCasZNnckb8meQibkVbOATaH7fiNQUbPogwwea R404eSfg8RqMmKa+XrvibLWk5AUxyhvUGVIl5MmGa12xhxLr4J4D5gg2iN7giaI5XLOT jpSw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id lu20-20020a170906fad400b0099309c64f17si1111441ejb.146.2023.07.30.19.01.43; Sun, 30 Jul 2023 19:02:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229826AbjGaBSo (ORCPT + 99 others); Sun, 30 Jul 2023 21:18:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229739AbjGaBS3 (ORCPT ); Sun, 30 Jul 2023 21:18:29 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 980921A2; Sun, 30 Jul 2023 18:18:27 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BA00D1692; Sun, 30 Jul 2023 18:19:10 -0700 (PDT) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AACFC3F5A1; Sun, 30 Jul 2023 18:18:25 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: allwinner: h616: Add OrangePi Zero 3 board support Date: Mon, 31 Jul 2023 02:17:25 +0100 Message-Id: <20230731011725.7228-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230731011725.7228-1-andre.przywara@arm.com> References: <20230731011725.7228-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772899719004036198 X-GMAIL-MSGID: 1772899719004036198 The OrangePi Zero 3 is a development board based on the Allwinner H618 SoC, which seems to be just an H616 with more L2 cache. The board itself is a slightly updated version of the Orange Pi Zero 2. It features: - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU - 1/1.5/2/4 GiB LPDDR4 DRAM SKUs (only up to 1GB on the Zero2) - AXP313a PMIC (more capable AXP305 on the Zero2) - Raspberry-Pi-1 compatible GPIO header - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports - 1 USB 2.0 host port - 1 USB 2.0 type C port (power supply + OTG) - MicroSD slot - on-board 16MiB bootable SPI NOR flash (only 2MB on the Zero2) - 1Gbps Ethernet port (via Motorcomm YT8531 PHY) (RTL8211 on the Zero2) - micro-HDMI port - (yet) unsupported Allwinner WiFi/BT chip Add the devicetree file describing the currently supported features, namely LEDs, SD card, PMIC, SPI flash, Ethernet, USB. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun50i-h618-orangepi-zero3.dts | 86 +++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 6a96494a2e0a3..3b0ad54062381 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts new file mode 100644 index 0000000000000..1964e27b7b187 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2023 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616-orangepi-zerox.dtsi" + +/ { + model = "OrangePi Zero3"; + compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; +}; + +&emac0 { + phy-supply = <®_dldo1>; +}; + +&mmc0 { + vmmc-supply = <®_dldo1>; + broken-cd; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + interrupt-parent = <&pio>; + interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x36>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL, so needs to be always on. */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +};