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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s1-20020a63dc01000000b00563de9f0f05si2936116pgg.42.2023.07.28.04.26.54; Fri, 28 Jul 2023 04:27:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=GuLxLrg+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235781AbjG1KXc (ORCPT + 99 others); Fri, 28 Jul 2023 06:23:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235911AbjG1KXT (ORCPT ); Fri, 28 Jul 2023 06:23:19 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAD551FDA; Fri, 28 Jul 2023 03:23:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1690539798; x=1722075798; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=z8bPrfHdyCe3PLAOc0IGM9zltBj6HhwNodkZl406Bo8=; b=GuLxLrg+NkPep3zrf8WUlsFt7J7y+K7ybUxd5tYZbkQA/wf6LOFiGxmw xRDCb6P7z1tLpclRhE2m4NgQAbNTynIk0dzMqf8Tes3uG5wwT2zkB5aGc kL7p4iOnIaDqXuDUIhZSsscigAsTofkBaYY/6d63lXDm9LUxE6MdrBHmt 0exzDSl812EaDEZsdwf2DeCtTXdxDv9wS9o+Pjiz9vICCtOOq1QTXXlfy EMPQx83x5+ym0JBp/H3sQl25p8QCJCS1gWblhDi3UMoOW02EMIvykB/x7 uD63/YNxuOZrjPQSLz7qzI07ecGJZGgjCPPSCHnPLwCYYBbaBIIKZdig9 g==; X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="225812856" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jul 2023 03:23:18 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 28 Jul 2023 03:23:17 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 28 Jul 2023 03:23:12 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , Subject: [PATCH v3 01/50] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60, sam9x7 compatible Date: Fri, 28 Jul 2023 15:52:56 +0530 Message-ID: <20230728102256.265291-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772663477043515416 X-GMAIL-MSGID: 1772663477043515416 Add sam9x60, sam9x7 compatible string support in the schema file. Signed-off-by: Varshini Rajendran --- .../soc/microchip/atmel,at91rm9200-tcb.yaml | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml index a46411149571..912aea5abcf0 100644 --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml @@ -15,13 +15,20 @@ description: | properties: compatible: - items: - - enum: - - atmel,at91rm9200-tcb - - atmel,at91sam9x5-tcb - - atmel,sama5d2-tcb - - const: simple-mfd - - const: syscon + oneOf: + - items: + - enum: + - atmel,at91rm9200-tcb + - atmel,at91sam9x5-tcb + - atmel,sama5d2-tcb + - microchip,sam9x60-tcb + - const: simple-mfd + - const: syscon + - items: + - const: microchip,sam9x7-tcb + - const: atmel,sama5d2-tcb + - const: simple-mfd + - const: syscon reg: maxItems: 1 From patchwork Fri Jul 28 10:23:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127573 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp385676vqg; Fri, 28 Jul 2023 05:07:58 -0700 (PDT) X-Google-Smtp-Source: APBJJlHue4SJmiz+zrLcJbBxKpr7m/9YpS0DWVwlzftJ2KNdJsbZUUAZEMVjqGaR0qQkqXE3inHF X-Received: by 2002:a17:907:2cd5:b0:99b:d440:bf0c with SMTP id hg21-20020a1709072cd500b0099bd440bf0cmr1611029ejc.57.1690546077885; Fri, 28 Jul 2023 05:07:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690546077; cv=none; d=google.com; s=arc-20160816; b=s/BGR6knvbdt+XyD8RfKTLOS9YZ5cqfWtaxyB5DWBApOwSyQyslPmCIdFLD+Bsuiic Bnnyga0yrCiCMas/TxrmLN9zqgvxZlFjUngpwItraOWxaeqnAd3bgSfGJU/ejQZMMDGd mpyVQaBRLJkhbXfdWQGL9TB8+OaAPXT1A0VQ90qKb2WagOJg5tMijbKor33Hml49IM+y CKToSXNHVER+G0eme/Xk3BacwjmLWUMTk65KzHjRGmtYNH9SMFyYHKzko8n22OAkr3RC rNx2uaP5cMSffecbuGjvocIxE71O+mlyLun8iVAB7aDPpiAUhF/kMjVUxhBCeTAhFlUr hOKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=0UpIonN1fiunqHAu2LV7hR0H/Kl/Z969YOANJ7ffE+E=; fh=lXnJlBVwch+MAMreFfDaycJtijm9c1jwNh5wvdY61HY=; b=Mg0eP6tNlWUW6+IEgj7ZVlWlKOyumIJsSfJ6/OtvKSK1PRn7rSGYV2U0koJARG1nMV 8iMjSoxFSMyQnNBvz1qqvqY1FmiF7+cShFDfF1XSNyuFnwaBtDjz4lrOCUqzQMqRvtYs T1S/0ELr1FtlPlOdXEskt51AhFlzBAeGQVOn5U1lc6yV0vwzKTtg53zuRQVD7GeAPtvk +KwqFQZrspkxtvtr0WA/rrK+r1Fhu/CQmt1CjZM5lHiXPmPksEydPlS5ItcvHkmIhpZx u7lhLuj3fJmBhXLDfd6okBUue3P2eDm2Eu1niCRZRZ6aEsRtcXiuDnOOKZnxpECDmRe5 20Rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=e7OODQby; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Rob Herring --- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml index b956bb5fada7..e5c8f4e085de 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -67,6 +67,7 @@ properties: - const: generic-ehci - items: - enum: + - atmel,at91sam9g45-ehci - cavium,octeon-6335-ehci - ibm,usb-ehci-440epx - ibm,usb-ehci-460ex From patchwork Fri Jul 28 10:23:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127547 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp373541vqg; Fri, 28 Jul 2023 04:46:45 -0700 (PDT) X-Google-Smtp-Source: APBJJlHZoBwIydEst9p0Jj6K+DLQ7AaWZg590/4n1mBz1dzovlXeOi4GXyJqkcL6O14r/jvQW3l5 X-Received: by 2002:a17:906:3142:b0:99b:5445:10ca with SMTP id e2-20020a170906314200b0099b544510camr1928879eje.58.1690544805256; Fri, 28 Jul 2023 04:46:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690544805; cv=none; d=google.com; s=arc-20160816; b=s4SeJ0rkQoRXCX726MBMY4eFd77iWENVT8LTDmz/xUpuOo3DTiTl6kDM/OPduTQBjS QWH6dx0FnbrqlQRJhZaaQMJP6DIBt50PZ4L4p612k/18sUZJjoe8IHbmqzDI/3l8S39p hK/4jnVds5rcqR0bFKwtHHAHL7AjFvPPg+y2k92Q4qon3GakSEfHXHKvTSpj95aZ7luw qvKTdCH2BJ9Z/7U8dV+yAvLLx+d8VtUUIL3g0jzgl73emQoGJEUbQiKitj28gpdMd9+q xnl80AvtEVBkXUIHWPzR3iLA+bAmVn9sVVJXdeUwr2g9GGv8dCFS7AQSbrs4q5ZJww7U 2umA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=OesRZBcJO9pSDxUsADv5yskI36fu1oxSnpdOa0pBYsA=; fh=phIqN6dd83M7FeSaNy2FXqVJ7YUTJNogZmGQWK30o2M=; b=02/hRZEzvh1Jx/6RXH2kP3I+7VKfceX+QxEuJiDfedVMrQ+1K3vxQRy883IF80Aux4 Fc0EvLokeNy6TGAdBSeRzPb6mPcQkUxGS6B3lAvvHWIQZL7hKE9aeO2rIuoj0Sfx366y NnCFxe7UISr43ctQpe47MbWPYClbaIZUL5x27OrD8MiIzHBtJnwbJzgoKBdYWRALs1EH 9gXJNIaPVWsmXF2R4O+vSST2AGWY3RIg7ZP92fcRvQujB1uM2w77m3lW3ERdRA0iWhdm foYIvtf+ZUrA9LHGb8BL7JrRDBXLindXFQj7E7q/kUrzONsoD10nc1WAo485DvbzDmuR WBDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=kZnEtXVi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Rob Herring --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index bf8894a0257e..c9840a284322 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -59,6 +59,12 @@ properties: - cdns,gem # Generic - cdns,macb # Generic + - items: + - enum: + - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface + - enum: + - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface + reg: minItems: 1 items: From patchwork Fri Jul 28 10:23:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127519 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp355569vqg; Fri, 28 Jul 2023 04:10:19 -0700 (PDT) X-Google-Smtp-Source: APBJJlHQ1ctpFbzF61Yh2EBhk9Byi9frs9poMpqgT+PTmCuuNS/9lREcrQjP8zJ7W64MSA6pBeCM X-Received: by 2002:a2e:9d0a:0:b0:2b6:cf0f:1fbf with SMTP id t10-20020a2e9d0a000000b002b6cf0f1fbfmr1384049lji.42.1690542619188; Fri, 28 Jul 2023 04:10:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690542619; cv=none; d=google.com; s=arc-20160816; b=oaJ9Tcgbada3Kc6CbJvx6uahVV75tmOn0N7JGWQBcz4J1jh5IyxTwZSp+97uDGSN6j 8fZiOkvZfeRfl0yuWqYgs4gWsL0hMOrKdilj0tvG/RMIIJ2tG+XqH7vv9hMeAcciMrxd LWqH0DkbZPCBXF9i7Yy80HSQITdJDlH7XtJRQfc5sT7F+KxdKd+2ODaNyyYuKdrKr6nf /VX6wDuZdmZrJEbwLvntnrYXEe6MWHkC+yteFDQefRBoZwYfgBnmGzZP9iksV0Wmm/LO MEKV7T3KioVyDXdZ+OKejaldunq7XAe513CEtTbvMX20egZGfEaE2NZk7Lma+Rq/bAd/ KTjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=UGRlLcfzLGIzEYb//UML+uC3G4MFAtu/lzpvSwa3nDc=; fh=3yUsdBA08SvQyLq/lzyuv0s1mWQPLtG9JMoDnSLp7mw=; b=rMZOEuESrXHM9M1w9RpctzBqTZ9pBsZJAX6f0oXAosP6v2luF/1DCFTXCxtaVPp2nX TZ+fSnEX0IVVAP4mRmmnliKuas0SsaTEMaLw3bOQVTuz9Kld+SGnuQsgWylpNzu1lio+ Xv+HDDxuOep9M6KZ5JTzYqJdAlt8uPLFXyLHbRHDQMQIT1W5Oz1otko8F1BdD3z2Bi6X TlMv2zkALzsArEazf53M62mH8VyWiQ3b0vp1TbPEbsbhd65vwf0bG/Qtywc2q3DBMhQf r3N2zZxdeGqU4r9QG7VNeIiAyD7KG0sz3tpXqR3CUdTEPnVWIh8Qe4YQZ63SS6w31+jj adbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=pKbMnWEr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml index 7be29877e6d2..94b83047c3cf 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml @@ -20,6 +20,9 @@ properties: - items: - const: microchip,sama7g5-sckc - const: microchip,sam9x60-sckc + - items: + - const: microchip,sam9x7-sckc + - const: microchip,sam9x60-sckc reg: maxItems: 1 From patchwork Fri Jul 28 10:23:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127516 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp342841vqg; Fri, 28 Jul 2023 03:46:34 -0700 (PDT) X-Google-Smtp-Source: APBJJlGpZHF6weJaUajXu5Hbf5yk+tB9+G+X51faL82wCJP6ili8DtxXotH03cd0pGfenlri+BeR X-Received: by 2002:a05:6a20:1606:b0:13b:7848:9515 with SMTP id l6-20020a056a20160600b0013b78489515mr1823920pzj.13.1690541193947; Fri, 28 Jul 2023 03:46:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690541193; cv=none; d=google.com; s=arc-20160816; b=sHlylc8yRfJ2k6GJBcI7blK40+Aqi5LFAP6NhUwZJxaR8HAvpm31jdhM94aNyXA0P7 f+wYHJtyzyG0n7VPOJqRtLzGgLrHvNUY3TJcP1HW7TPRd7yhw8tB+jO4WdFl371nZ89s X5QdpJzaycSrQg6Rq7McI9+DnXbHqfvD8DH7hxm+HsUZ01aAY1DM+5ObIVRETwOzraBZ dMKRXHCNc7iR2C+gcT176AklcA9Pakc6Plq2rj0XGW9uw+Q+zQ0SrAmHjz1s25CR3dN0 bdN48H/Whf7ZfL+fGRoDS/ZhRbPyYnSbAP9W6rENcN+W9dV+RHEqhIeBOm0Kbh+b9raX yq2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=8IYqJZ9pXGc18AMCTe+r7a+VCTtZFTNcX6EeogaiaXk=; fh=3yUsdBA08SvQyLq/lzyuv0s1mWQPLtG9JMoDnSLp7mw=; b=Bi7a/N/D+Zx3K7G8Arq5eq4IJ/fFvv2oBkN3QeX2gxzjwQwBTOpv/w2ztlMWXVE/xs TLwfXkC6RCJVmPJvPEIdjrEo5jzDoLm/QpeCT954HmPuVrLX64rU4ySvt5v6KTiVHmJW cYSk+tHE2ACyfGn0dk80qbLFqZa1WQQyUH1195TvkbAm6Kcnu64l/Fm7oQNO/niO4e2w R9emLpJzCXHURk0nfLANkZLqoIYIYv70m8JlQQ/oXPEJvi/yM2HjcL4M7447tdY0h5sG XPtBW6xfuNGu2Vt/JkTmlNWbaboNBp+5oaJ0OticuTmuCnE7JdcxauA7UQt/mP4/48kc Yqwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=BiWR3Muc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml index c1bdcd9058ed..ce0d99503645 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml @@ -43,6 +43,7 @@ properties: - atmel,sama5d4-pmc - microchip,sam9x60-pmc - microchip,sama7g5-pmc + - microchip,sam9x7-pmc - const: syscon reg: From patchwork Fri Jul 28 10:23:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127560 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp382036vqg; Fri, 28 Jul 2023 05:03:10 -0700 (PDT) X-Google-Smtp-Source: APBJJlFm2weYPL0x5erkN0LHbkOXxhkiqNwYG0kOU2lROm44CRZ7bYx0h7WfrKlslX59uAaeB7iB X-Received: by 2002:a17:906:5308:b0:997:e959:be3e with SMTP id h8-20020a170906530800b00997e959be3emr1835932ejo.76.1690545789936; Fri, 28 Jul 2023 05:03:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690545789; cv=none; d=google.com; s=arc-20160816; b=uZlHKPIyxxdVGvx3c2zYyF6BY2E7u7CZjqho7s9FhlK1aTNOK9rpuoUZLVv/k2Tui6 HXk6iZgYK6Ss3KvuGSda10iJHjD+3kWrXQGNViO5DoHtMIHRc3fmS3vanXZS69uXN8U0 cDEagzJGk9iel8J2RVVPPJAqy5r7SYb5lRu8JJgN5cwP6OlWcHMloMZP+UoSAD78wUJf ztfpsufru2Ci1utyONRV+fpSigL5U4+zZ3Q+jEA9Rc7V8WvQ5OhwAVfd9sg5okxKnyVI aKpkGrb5UHRoK2BnCKzVCRbbg0kbfVnP79uagBr3Ovc5wC5BOQ2XsFUFFxweBDoxU7Fe 2tSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=8mUmZInRHst5T/0oFrMJEd+h+Ip6I8aAAxYimI4rIQE=; fh=XQuyUOz+gIvBFQp9egkFH4SqpLLDHZoaa3ZxtNVn0Tk=; b=zMbB+/c845lfwWJ8+lZXzmKaJLb9PFCaMoyz85DuqH6T+qEU4v5u4jXlBvF4ccE5L1 ruZCJQYQeDZtUQrThT5TzHrHr5XdtnNlG5Ht3JtHfXxHbY7Iwka2HPuk3J+tVitLrvYV fOLDOBKzsvVOqGbAfSx+lgwbl8+6P9IOQ5fH9W70Xsonr5Ai4kk5ekfWtRJXwOIMblEk qkRrR5TAOQk9RCsCVemQHcWf/YvYsWB8iYm9vOlXN9ThtHefDYncvps5TBsWdogreFJG NyPBl5AOszn8U4WyPwvCqQ/Qk5S4aWYAFx1YoXWKfIupk6/m5cuHsd0HssawUE/a9Hwt yWNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=vJauf+Rk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Philipp Zabel --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 98465d26949e..c3b33bbc7319 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -26,6 +26,10 @@ properties: - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc + - items: + - enum: + - microchip,sam9x7-rstc + - const: microchip,sam9x60-rstc reg: minItems: 1 From patchwork Fri Jul 28 10:24:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127538 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp366387vqg; Fri, 28 Jul 2023 04:31:57 -0700 (PDT) X-Google-Smtp-Source: APBJJlF8hYkclowExjJUBgXjZnZ8Jqo5ME94gS004lHFOBQNBSpXdup/dcoBmzksQlFlWB3uPX65 X-Received: by 2002:a05:6871:1c6:b0:1ba:53ed:18c9 with SMTP id q6-20020a05687101c600b001ba53ed18c9mr3129008oad.37.1690543917631; Fri, 28 Jul 2023 04:31:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543917; cv=none; d=google.com; s=arc-20160816; b=ccC0KbRf68pCNsUKbMM+WmD7baMJJ0qWHh2cxJF0q30/8gcpFNK0fn5n1SzOwzWfcB 12CYIZxOTHq/bsfZOs9GbNdwP4el/hdwHzE0mzU9QYMb4UUGKk8Y9Vv6k+PBlbXVnJgT 31by0u5OJ/OtQ2PF1R+qpIFHen8HMmr7cCkc54R9DJ8SzQ2X9zIbtgC9mEIjZPVJw5Q0 t1jIg8vQKtQShOwHFM3rwAAMwMtD2xRpaXTpCDcTqziTpIzNq0mOcVxjX6rO9cLXS+65 uPvnOxq6MYM59iwDJXr7YGAYkMuSOiQksWsQYt+9LXeyBJ8h+SyDcOJuOi2CCrHUX9O5 afxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=v2cQjkMOMfFAqE79EExT8HROU0y/RFpUcp2R30fZV6A=; fh=ang+onfRNDXN2zgpcF8x1iRxuCYcOPlpQqNoYAm5rpo=; b=k2I/kfEQqm1rSqJlC+M05+kQjT6TBSFY/d4+BKJN1izUVDLcZipz94QDuZJBxtRqHT lvt1paHhM5EitZJRaGpZkyeJAQxK0Hb5le3ZA0T7ewMxvr3d25qIom2e/PEaq6f+fXN+ XIjo5A+ut6QSQKK7FL4xXVW71TeEqNw03fwKU74IzFdku2SYJTfEn63OrWZVjBvVdEXa QwiQdaDh4OQsV/J9GEDu8jZgQF3n5+ilL6yHi32IupjEjzJ2pH3BTmb6X2YGgUiCfoYY ycYSwDBVpi67XDwDgiyns7DTTSiH7YTrTbWwrtn86cYLrlDvs/XQe1Giq4QccwKO6E8v 4d7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=SZ5rl0+x; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Sebastian Reichel --- .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml index 8c58e12cdb60..0735ceb7c103 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -22,6 +22,9 @@ properties: - enum: - atmel,sama5d2-shdwc - microchip,sam9x60-shdwc + - items: + - const: microchip,sam9x7-shdwc + - const: microchip,sam9x60-shdwc reg: maxItems: 1 From patchwork Fri Jul 28 10:24:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127563 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp382826vqg; Fri, 28 Jul 2023 05:04:11 -0700 (PDT) X-Google-Smtp-Source: APBJJlE730UgNlANboepTJmfpLxxPBXuKPGJpdpF/4+Hcybi7Egp9W/ffmFuF6ae5XkUA1q/h/Ld X-Received: by 2002:a05:6a00:2287:b0:663:18c:a176 with SMTP id f7-20020a056a00228700b00663018ca176mr1371822pfe.32.1690545850985; Fri, 28 Jul 2023 05:04:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690545850; cv=none; d=google.com; s=arc-20160816; b=L92l/Z5Qw3jWev+Om88JydI6CHU0ynziqxDfIx+HejJTHsYxn3b3PL6b16uiG4IrmR kk+owte9KI+FjeidKFKmZKJlrOV2xoGFPmDiZHJntNJaq9+26mko3AUYfsKiyp/8y/1C SJrGVZaxK8oYYA0s0jeB2g9WE10Kb/SNMtoKaN4zdNxmTfOFGKptprqB5v/VBQcGHhZb 1Tg7BOcQkE/7hgIY3euAdzENoFuX04ftsI6UWI5/DmVARtdcPTac4Y1EH9sOBu+/0ssz BodmR3PAO61zKsRZYKmZW2XCRBdtB0Ew2xDW66GPLaIkgT3BAtcBEk3EZ+PJmjTxf5Vv 7HUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:to:from:dkim-signature; bh=kHl9hnxEiY8EvCxtUIqEbCHfBFBauDvLqGt+hB/eqQI=; fh=vGT8YAENzLLPXO/TJlWpvNCUgefPazFAaBAVPZGWGOU=; b=QBEjV2MFpfOta4kAPxgFggqXVTCHbAN5LUJqBDjepkoI/W7IJ1O7PbUWPM1cH77ydZ XxirlmO18w09jBnKd/GRU6Wk6C9jD4pP8h/X6fRsObO+qdkvigrVa4m9rAJ4CwjP2q4U b5RAIqi8t6nGQtRZh3HqjRIrM328b8l2XW3LrJcV6bi+XMHU0aznJpMdMrRcJixzeuKz PBIZKSE7gpkN+vwK1sK71s0T5Nk7pjiWFSkm+pyx9cZo2Vw/1q047qd8+sOjju/+DaMV oPVSwgHxu/k9WhlU2m/Rnh1DZBshp33sDhS+KDp5M1Pxdz3+VyTEb8krtkiDZPrSdlhf TkYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=EWo0AN8h; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 67a66bf74895..1339298203c6 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -11,7 +11,8 @@ PIT Timer required properties: shared across all System Controller members. PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" +- compatible: Should be "microchip,sam9x60-pit64b" or + "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b" - reg: Should contain registers location and length - interrupts: Should contain interrupt for PIT64B timer - clocks: Should contain the available clock sources for PIT64B timer. @@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties: "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", "microchip,sam9x60-ddramc", - "microchip,sama7g5-uddrc" + "microchip,sama7g5-uddrc", + "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc". - reg: Should contain registers location and length Examples: @@ -63,6 +65,7 @@ required properties: "atmel,-sfrbu", "syscon" can be "sama5d3", "sama5d4" or "sama5d2". It also can be "microchip,sam9x60-sfr", "syscon". + It also can be "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon". - reg: Should contain registers location and length sfr@f0038000 { From patchwork Fri Jul 28 10:24:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127531 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp364770vqg; Fri, 28 Jul 2023 04:29:12 -0700 (PDT) X-Google-Smtp-Source: APBJJlGTCQIBofMyusPt60KLbwrayCoMfEKEXsVJB1y5155iZWEzCrCz+6iAVE78wrM2JPSZzEaT X-Received: by 2002:a05:6a20:415:b0:137:2213:9495 with SMTP id a21-20020a056a20041500b0013722139495mr1068624pza.58.1690543751884; Fri, 28 Jul 2023 04:29:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543751; cv=none; d=google.com; s=arc-20160816; b=ZMko+NDIs/C3XHzqYulS0pcUg3EPeTkdemRBrtofkwKNIdb+EZUyiRnddQg3LXNayB PU3reK+85ub/p6vBa/BRjgn0eh5VyVL94K1NjOJv3b+JxAgz5rsPOjc9jkpLlgTXahD3 FnIqFLd3fzm77Fr/Z/t+VgQAwcazvfbGmLBOPJlWtU/1hL8OkEKfgjohPntc1HKUcydm UgXsiRK+LYg/OZdYI53TzIPCNUi6tq4O9fmsH1P0dApHqVG8DJcOwM9PxFk1JjvljT5c FehDczMY1WQWfZItGiMp1FuNYQMDRwu6v3jkmOgDemkFUAbGfgkjlA43yibJq5bSqV0U O9Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=Z2EbGAaxlRpcpGTfA6NLFlIYs/QDPTcymM7TcBVot1c=; fh=gGBmVXeutx2kZj2q+WZdevoLOb9he9G4xNwKP/Ul4Jo=; b=edowGDTZRLb8vRsyhbmDeB/Gz5dpLiOv7sCvD4cQBVyJ8+7jNxU0DvcWxQOokzXayi ZgH1l4rcEf1EsuBj1WqQbqLRKntqSsHsxPLJQYLfvOealjN9tvZuSyYrCOh99RQsq61E rDBHzAaY+cOOUbPV9YPpBt2uHcCLKzqGRunxoLEkKkxWiZDmM5MStoAWQB43hRz7AmcQ iLpJL/BdQtglwANQKg7oBkC/Rign+Riy8Lvh/NOY3k3fcw/oePlGjXegyKuq6JcuVZqy 5ReGlkPXX5E/Xc9Cxq94xUlw9OhmYJ1rjasOBXogiROdku/yuiTv3GIkHjkrlUUHgKsJ s17A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=qCEWUn25; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Rob Herring --- .../devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml index 0b7383b3106b..7dc0748444fd 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml @@ -12,7 +12,11 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-aes + oneOf: + - const: atmel,at91sam9g46-aes + - items: + - const: microchip,sam9x7-aes + - const: atmel,at91sam9g46-aes reg: maxItems: 1 From patchwork Fri Jul 28 10:24:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127525 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp359788vqg; Fri, 28 Jul 2023 04:18:17 -0700 (PDT) X-Google-Smtp-Source: APBJJlGI9cF5OxsipK0KwRwYPYQfAav9Jhb20VDJ+1S4h86RP2pi/c1eHQZO4Is10YvhZP+yZurt X-Received: by 2002:a17:903:2289:b0:1b2:2c0c:d400 with SMTP id b9-20020a170903228900b001b22c0cd400mr1144438plh.52.1690543096713; Fri, 28 Jul 2023 04:18:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543096; cv=none; d=google.com; s=arc-20160816; b=AjAs1Cg8pTzW52Nbhfv6hY457FDIaaaPVH5UaEVnXGi2tyWhFNjQhDd2rbLvyQBmpS sM91WlEoAv9wMkTja0BtmVDHy+6LaHgAs8h4e42U8WxXRm5VXKuriXZ5jlNadI/VJ8r8 xC6a8cyJ/NQgKDxLNrC391N2t+5mDyE9jKVPjBijzYf/XxR+jmTQuSkYZ5RqnnZGtLvu GO05V+33ocNuAk/tBDg72j+6Ddy0szj/TNAMABcy5BHmgsEEGwDM3ksVi2rQaARK5//r xAJr97zuiiCPOMYGC5/JJ18S5h3fks8Kb7sTRXf+uPSBNKi3SAL6nvZEJfo29jCzY16Q caig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=xJA1WBIT0aK+94ZRN67M3owib7FIP43QmyaeO6KBh0I=; fh=gGBmVXeutx2kZj2q+WZdevoLOb9he9G4xNwKP/Ul4Jo=; b=EPz2qJPo0xmqu96IfoOQk4awbvhyXh1jMrnfYVKWKlmkdQb9ktS5mgwthc0L8VaRO5 y1uQEdPd8ibmDugAMzfn4rJ+02AEOK2Zww0pEXZs+Gm3AtwPgcljLdKYQr4wW0BnEsm0 JKnc+MZebxu272xHyg8OyZp/FKt+0MFqD6AOLVVrE/1rJxJ0+AML+HwUfnd2BANh/E3z 2dp3VXyYORR28Z6MrbAAT/y1YYJBJlBxusEHXOmdetRh+qNcmnm6DpOw+6KLK2yGo1A+ nkGLJcKB7a8tNdi68BeEZOPKUniJRQF+PYcCzChkOAEy9pIY1rtS5yma6j/kg8mpqZWU uyqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Qt3wI1lM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Rob Herring --- .../devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml index ee2ffb034325..d378c53314dd 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml @@ -12,7 +12,11 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-sha + oneOf: + - const: atmel,at91sam9g46-sha + - items: + - const: microchip,sam9x7-sha + - const: atmel,at91sam9g46-sha reg: maxItems: 1 From patchwork Fri Jul 28 10:24:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127644 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp434288vqg; Fri, 28 Jul 2023 06:27:53 -0700 (PDT) X-Google-Smtp-Source: APBJJlHWsui9+Xwy6gXK/YHUYy2GmRzBV97Q3a5R+43ajpNmgFHqPjjctAII8CJPNaQj92zVlcgu X-Received: by 2002:a05:6a00:22c7:b0:64c:c5f9:1533 with SMTP id f7-20020a056a0022c700b0064cc5f91533mr2044118pfj.33.1690550873050; Fri, 28 Jul 2023 06:27:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690550873; cv=none; d=google.com; s=arc-20160816; b=sUvmdSoz8AkwOy0mKufzbcgeWyHINDy9WwzXBBJe4l0RLXeiCdyzgRR80qpoRhHU28 2Q6eyd+KKjkBcyNft8BFPcfDLhaQZizSn7OdYWWn5waHv+9GUr+cxueUQieWPoed6pph GV4DWGu22jPLPcLqYLKHr8/ASzDtkOdpQE80evqmzIqRplyOzyjnIh0JnO0RSHupkaJ+ aHd3cYpmUTT8n6vFb4LB+iRDsZ8uj9Ijb62WXw0UVhLivzgJbG/ps7tbj5TlB1D1+rJT x5r/AkJwDZE8zkmFja+MQNBgDZYMx689ntWWGerRjAt+4efF4AQI2P+rDqXXiV7GhEFX tvhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=kUdMdzPoWRWHMq94rUSKENF3sy6HV2bOYZT8Baa8S+A=; fh=gGBmVXeutx2kZj2q+WZdevoLOb9he9G4xNwKP/Ul4Jo=; b=izsyMmALzqIgtl2UeMoX77K08j2E6GXD6qn0A1rxRsB4WmenoB4wg7bjBRsz/HT3HF 2dbLWigcu1IcBkgh4tnb6n+mzYllZ9jvDJns/WeOd3oomwvVkieFPaK38OUUiG0MdX7u Ykm3HlLY1FNdlRu3j2GRhPlpJOkD4lGzvd3GPQ0ob6jcpc34/xYrWJDFDXOGE6HDAlOc flz2cwmanEBgpGuk2AR8Qxg7EKZF+UNtlffTlkJOXuF/w4xl0Ey4Pp1hag+rxQHnNrSz 6ft13AWSd2Pv2ppwjlWxKoPPX7mitnT8Ax00v+AF8KIEW4rx2oRmDHWJZB0QuhZbzncN I1yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="GfsbQC/r"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml index 3d6ed24b1b00..6a441f79efea 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml @@ -12,7 +12,11 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-tdes + oneOf: + - const: atmel,at91sam9g46-tdes + - items: + - const: microchip,sam9x7-tdes + - const: atmel,at91sam9g46-tdes reg: maxItems: 1 From patchwork Fri Jul 28 10:24:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127539 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp366616vqg; Fri, 28 Jul 2023 04:32:21 -0700 (PDT) X-Google-Smtp-Source: APBJJlGq8LyRAEoadCmZq6Cawnq598eSmpUTVRl1uCYQqSduC/kT/ybGvxXXVFQyQDRz0Rj5ePV0 X-Received: by 2002:a05:6a21:780a:b0:13b:a129:a6cd with SMTP id be10-20020a056a21780a00b0013ba129a6cdmr1348623pzc.58.1690543941417; Fri, 28 Jul 2023 04:32:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543941; cv=none; d=google.com; s=arc-20160816; b=H461zlsSI75RcrW18uC/Ow4JRZzZoSN7Cq4oePRBA+CmHXhqMEyg5r2eKDw3hDMfL9 W4bA5FefACI00/YyX6sY1ebneS1AmgsG45EAwcMuW5qgitH73eMwKJl/lm695p490cRv yiF8/KAGNTZKxp3p40Occkpn9cnTfowHT+u3lAptedTrEq08Ld7dbvfG5+GEQku6qjmm 3p2v7q9lGxNgi9IFCfawQpcx9KSAkIPlbGiHFMmy87OngDmVquUADwvmvVEq8tTyPvQD I6xH3jJsxLKG58uTpPLotpgHcpd+ldaFjMV6/XGqjBEWXUMPAgOIq9wYVsWmU0yU2rED 20sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=KUbn9f4OKvGF/VNy/PMmDQc5sqekNlLNym0kBq3F3VU=; fh=RNsGncnIU9yGcEt712XuGPCmwXUjFkgFaQAkWYoqOnY=; b=sisAV41tt9sVZ4cWxIYZMDY7ic3MqtN9WUqUGaJsNgab9zt7E/D8aqJ+bQ5/dsa5kv Al5/eADPWU0a8chc9EMP6xRIQ8USPJmXnJEBWtHjbOwWlSCWiWgDcxol8U8oj2MCRWaX teLQjrLEyxAkV/7ObRT1ygfi1rsoMiTk4Ymt2iBj9Q26fOK8e4H6/Zm65eVEL+1efpxm k2veDru+v3oGf1YA99V+HrhzHn5R3GLFwD7a1TYIDNaylP8R69Jc0Gepq4uBPEVPS4uC +GpU8ZTfILiQt5VsbME7ge+GVwxAEiPdPQ0PdbiCvHZeyV86/A9ReOBu0e+AxwSwBk7v 6EiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=NoYzhLd2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/dma/atmel-xdma.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt index 510b7f25ba24..76d649b3a25d 100644 --- a/Documentation/devicetree/bindings/dma/atmel-xdma.txt +++ b/Documentation/devicetree/bindings/dma/atmel-xdma.txt @@ -3,7 +3,8 @@ * XDMA Controller Required properties: - compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or - "microchip,sama7g5-dma". + "microchip,sama7g5-dma" or + "microchip,sam9x7-dma", "atmel,sama5d4-dma". - reg: Should contain DMA registers location and length. - interrupts: Should contain DMA interrupt. - #dma-cells: Must be <1>, used to represent the number of integer cells in From patchwork Fri Jul 28 10:25:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127627 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp424829vqg; Fri, 28 Jul 2023 06:12:15 -0700 (PDT) X-Google-Smtp-Source: APBJJlGKli5csAg8nzUBUbb40SsBpjz+Cwg1wztq8Dt2i0+o2GAyoGxLTeUstKT0pww45ckedk5E X-Received: by 2002:ac2:530a:0:b0:4fd:fe8f:4108 with SMTP id c10-20020ac2530a000000b004fdfe8f4108mr1673370lfh.62.1690549935197; Fri, 28 Jul 2023 06:12:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690549935; cv=none; d=google.com; s=arc-20160816; b=yX0C0IuYEtyOiEDEnmSqEhXZi78Nmrg56Xp390cd3WJsznXPkV1ymMN/f+VCyj5MvO USyrvGFFaHBuvgdK+Ltk6+n/qM27c4hcdqP+XoznBi71beYZiBLluUUNv7DOIZQ9w2B2 80Nfi92P2d+FF4Z4/YW4xkA8b7NuHvAFxvVLsMqfQsosxQ8FktmGYxRlyj/aOSJ0M7sb 9JWksFTPvnoEcM9gppNKIiqY4fJMtU7Zd1c+EtQm9KtfM5eSeRYqlnaxEcZXKrwkVEF7 vKs+mbZF8l3002074bFfzkMHpUwLN9ENrbguwE24iF/Rg/zfIyQsef9e+3a2bTIuGkC6 mhFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=6VqXznzthsYmrOI8c4IeNBr+RoMa29erB3QCOPOjpHQ=; fh=SGJzNJBsdITjNE2YMU83hPRmQDnuDgDD6yJ2Cu4sBfQ=; b=qmy6FbEHymf49D24+olldT7Xd8j3HdATijNwzHA4OJ5YEoNWNLdapjMWKwkgRIeWT6 ADHvBBK6uxdqJJPOqt4d7if6SoqLsNDtAvZkRrPsV/o/ni/SfkWLcw/U8RiTBt72OTKL V+nxQiVaAkkDu/uNQ1mu+UcQ5UZun/kzp9ZqIBFg8suvEgAs9q30ztDFL7RMMNzmwPOL B802lImV+gVkgOlP9D9c8ABftVe2ALwwWPPhUgWBouRsetqSs5h+DuSRJQZXLFA6Hn/2 ksho4PgE3NBQ63wDrSvc0p8/JNJqk3v8p6gtXxSvaE2IDKCGVWIzgOITIXPnCBoU2IAx SwQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=vU9cF4V9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml index 6adedd3ec399..6f3158604d02 100644 --- a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml @@ -27,6 +27,9 @@ properties: - items: - const: microchip,sama7g5-i2c - const: microchip,sam9x60-i2c + - items: + - const: microchip,sam9x7-i2c + - const: microchip,sam9x60-i2c reg: maxItems: 1 @@ -84,6 +87,7 @@ allOf: - atmel,sama5d4-i2c - atmel,sama5d2-i2c - microchip,sam9x60-i2c + - microchip,sam9x7-i2c - microchip,sama7g5-i2c then: properties: From patchwork Fri Jul 28 10:25:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127550 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp377659vqg; Fri, 28 Jul 2023 04:55:54 -0700 (PDT) X-Google-Smtp-Source: APBJJlH049AMyZVAm26yl6yrtNfwZoyA0TEaFCT5VWzaAuHuogHT8zsmJYf50UrZ6H2ZT3fl6u5k X-Received: by 2002:a17:906:32d6:b0:99b:56f1:3002 with SMTP id k22-20020a17090632d600b0099b56f13002mr1843256ejk.61.1690545353782; Fri, 28 Jul 2023 04:55:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690545353; cv=none; d=google.com; s=arc-20160816; b=BYA3XN+Kfzltp8zkt7X4QKrgIrqjEkquqYXPdri6/5bxnTUmnomQl3YeydSRyXFOZx jGsB71ax5jSFspCdz67aLzG1g0NBvY8FrxeqCHqS+gzyOQS6K+NNUnBJCJQ50BgxzZ9B Jayc/81wJ+6XEAfF4W0s5YCtZdl4C5Kv1bMpDQkd8v98apI9yDX+MuFxchBjmGfnMz/D UU/m+mVeUPMSbgdKwFgkF0vAO+0A9TlcBNwrsVkEjAuJdx6yCiQrJSCfc6Qv6tj0zKgn 2NvgboCGXN0HWZd5BZSL6MIjVMTXtqB4gjDvDupTJyCySQ/NFYhsTQ2W/g0gHuFWQza5 HY6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=0DYqPl8hKn1l+7L0ECcpxdK36t5VBsjmAuhm1VFagX4=; fh=YCGY+j9p5pIMBiy1+TKSBJbdtoHJj2RYxWSwAgn17B8=; b=ReM9Ahu56RfOVY2CcXORRKV/jYKBA3c33ZktC7cwXYsnR5zx5JBXaoGYkEeAR4cRFl VgY86UFgykjxFyUAYDn9MgZ1dnoxbOD6LiPndTsK98/B/TcYFu2up86KUN54NFgLXQ6l 9n0deeeq1NPuSbv/CQ7y4i1Zt/Qnn2kLDJLZvc9/BDxC2v8LjKs7FuQwmzMEl/Hkkgpt pJx+2odh6LAlIgJzWygGixSdty0j3iNxmpWVYbyfhJVccEhpTwZpyn4GOYI6bQxXr7pU HyQLl6rsMQBioE+asnCCcwlgLnmV1kCoxMgeAUUNfQu0HayXwPbL4rpvHrxK35GXbTkT 2kAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=A91Ri5tW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/atmel-flexcom.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt index 9d837535637b..af692e8833a5 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt @@ -6,6 +6,7 @@ at boot time according to the device tree. Required properties: - compatible: Should be "atmel,sama5d2-flexcom" + or "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom" - reg: Should be the offset/length value for Flexcom dedicated I/O registers (without USART, TWI or SPI registers). - clocks: Should be the Flexcom peripheral clock from PMC. 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Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/atmel-gpbr.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt index e8c525569f10..3c989d1760a2 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt @@ -6,6 +6,7 @@ Required properties: - compatible: Should be one of the following: "atmel,at91sam9260-gpbr", "syscon" "microchip,sam9x60-gpbr", "syscon" + "microchip,sam9x7-gpbr", "microchip,sam9x60-gpbr", "syscon" - reg: contains offset/length value of the GPBR memory region. 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Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/atmel-matrix.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt index 89d05c64fb01..6e5f83614e83 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt @@ -14,6 +14,7 @@ Required properties: "atmel,at91sam9x5-matrix", "syscon" "atmel,sama5d3-matrix", "syscon" "microchip,sam9x60-matrix", "syscon" + "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon" - reg: Contains offset/length value of the Bus Matrix memory region. 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Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/atmel-smc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-smc.txt b/Documentation/devicetree/bindings/mfd/atmel-smc.txt index 5696d9fcb5dc..fd62add38a79 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-smc.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-smc.txt @@ -10,6 +10,7 @@ Required properties: "atmel,sama5d3-smc", "syscon" "atmel,sama5d2-smc", "syscon" "microchip,sam9x60-smc", "syscon" + "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon" - reg: Contains offset/length value of the SMC memory region. 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Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/misc/atmel-ssc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt index f9fb412642fe..894875826de9 100644 --- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt +++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt @@ -2,6 +2,7 @@ Required properties: - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" + or "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc" - atmel,at91rm9200-ssc: support pdc transfer - atmel,at91sam9g45-ssc: support dma transfer - reg: Should contain SSC registers location and length From patchwork Fri Jul 28 10:26:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127530 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp364497vqg; Fri, 28 Jul 2023 04:28:33 -0700 (PDT) X-Google-Smtp-Source: APBJJlH8rylrGzlBHHhsNZyWIf6w0V30/5qfepCfgm8ac62NqudizhujNAlcE17irtooy1zHwGni X-Received: by 2002:a05:6a00:1512:b0:666:ad0c:c0f4 with SMTP id q18-20020a056a00151200b00666ad0cc0f4mr2040749pfu.23.1690543713225; Fri, 28 Jul 2023 04:28:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543713; cv=none; d=google.com; s=arc-20160816; b=Au48syiZ9Rud9rDtxx67qe5Ij0kAE0FAvn4MhsWWe+KmgjSKiBtRQf1Oh7Fnh58Ipv R4wvUA0jVLA3v0Iuq05zq9iJYr5JoZpxjItyEAtHxHieUVtLHh6/Rnf9Yzef/3xocsdA 7yNkb9nn88F/tTxsMLG94frWv6XLRH+9P6vPd0eRUB140iulpW6RhyPe8VQ4fYHLmCJD b7dCSNdiRcdwmUqZTqxwfH7+ikQlycIuItmUjfhOn8Ujgw4/PGw/FBxZc76DCGgas/Bs DdaTUy3ZUh/ZN0zUQUYv48Lmo1UHR3TlZJOH6DE0Xax2WMIDooTB1KROgFudodDFDe5R 9ftw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=nk6J81xtLv40hoJqv7Q4rq6LeRL5Se+bKUj/fTcElzo=; fh=sYtVFtvO8W4Zxp7n27mPr2eQvdPKw5xXPv/f9K0hDu4=; b=0RytyOdElc9fOC7fd2PRsRtEPFaOZ6pQmFpe5ZYOQcmrgbt+V7e7uP/oVLklWl3SKk 8AME/LUM+XU/CyITtv5g5pqcbIRQeRtEkW7pDB1gNSroU2BfqF0CmlYhBFtGb9J8fSMO fmFojN5AeZn1DNtqtRcfITmYYNUV0mKS+NcZ9xDnND9s9O/rz8Bm46dCMFT/c7D95A6j RxTC0dINFLclwnsBpcWIpQzge+h7we7j3QqC9Q4grD6g+6wPNAZszjpGYH0DLjqWXCKw DiyE0ARMXD4hAShiIRtbcQEI6eQ1iae/isvy8hF/afkhf4DS6CmFRdsYwdSHeUogtBEj PUpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=BeZktLdC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mmc/sdhci-atmel.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt b/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt index 69edfd4d3922..a9fb0a91245f 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt @@ -5,11 +5,13 @@ Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the sdhci-of-at91 driver. Required properties: -- compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci". +- compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci" + or "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci". - clocks: Phandlers to the clocks. - clock-names: Must be "hclock", "multclk", "baseclk" for "atmel,sama5d2-sdhci". Must be "hclock", "multclk" for "microchip,sam9x60-sdhci". + Must be "hclock", "multclk" for "microchip,sam9x7-sdhci". Optional properties: - assigned-clocks: The same with "multclk". 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt index 50645828ac20..4598930851d9 100644 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt @@ -56,6 +56,7 @@ Required properties: "atmel,sama5d4-pmecc" "atmel,sama5d2-pmecc" "microchip,sam9x60-pmecc" + "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc" - reg: should contain 2 register ranges. The first one is pointing to the PMECC block, and the second one to the PMECC_ERRLOC block. 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id va16-20020a17090711d000b0099b6becb10fsi2674019ejb.449.2023.07.28.05.05.24; Fri, 28 Jul 2023 05:06:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="0J/vbMW4"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234722AbjG1K3g (ORCPT + 99 others); Fri, 28 Jul 2023 06:29:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231280AbjG1K3G (ORCPT ); Fri, 28 Jul 2023 06:29:06 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36BE24C03; Fri, 28 Jul 2023 03:28:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1690540087; x=1722076087; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=V4BlTjamXLsIY4iiG3CLqens3Fto25dMoGbIlFyLjHw=; b=0J/vbMW4FVYJW+PVjRSkeaRgNH9m88LqB965a7t+Cp4gFivu8vMGMlh9 mJERwDO252dNTT9n4SeQrwBBwcqR1sWjrC+Zj+3yXtFZEDd5tvpeBG/IA dVKL8MsjcpPfkU5sTwgI2AnwodaheheJH1+2nkgFLM+UOQUVuiOPeeXz9 /TihaQH8moMjnTWSWedGIJw56he9iVOsRTjMQMp8Qm4yNvm1LK2Hb3bES desFk51B9C/4ag/790ZhHGZ/Far7artVzyV74Xw3EukAJA17Uxzm0b0PX 10yvN7QWb3XTetGKlEJqyurcHGjYNJ2LSOirTcVMRgVQE3BVPIFj7uJIa Q==; X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="225813448" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jul 2023 03:27:08 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 28 Jul 2023 03:27:00 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 28 Jul 2023 03:26:55 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: Subject: [PATCH v3 21/50] dt-bindings: pinctrl: at91: add sam9x7 Date: Fri, 28 Jul 2023 15:56:47 +0530 Message-ID: <20230728102647.266359-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772665923628481610 X-GMAIL-MSGID: 1772665923628481610 Add device tree binding for SAM9X7 pin controller. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index e8abbdad7b5d..0aa1a53012d6 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -20,6 +20,7 @@ such as pull-up, multi drive, etc. Required properties for iomux controller: - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl" + or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl" - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be configured in this periph mode. All the periph and bank need to be describe. @@ -120,6 +121,7 @@ Some requirements for using atmel,at91rm9200-pinctrl binding: For each bank the required properties are: - compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or "microchip,sam9x60-gpio" + or "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio" - reg: physical base address and length of the controller's registers - interrupts: interrupt outputs from the controller - interrupt-controller: marks the device node as an interrupt controller From patchwork Fri Jul 28 10:27:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127565 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp383243vqg; Fri, 28 Jul 2023 05:04:43 -0700 (PDT) X-Google-Smtp-Source: APBJJlEGxdRi4pgz5Vl0xYqK/RuoCJnU81ntbAJLcEYHy5YQA8vvk6fbyfDDcjWRN43cCjgfwD2u X-Received: by 2002:a05:6402:795:b0:522:2fec:3e60 with SMTP id d21-20020a056402079500b005222fec3e60mr2046040edy.20.1690545882818; Fri, 28 Jul 2023 05:04:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690545882; cv=none; d=google.com; s=arc-20160816; b=ke/Z+lS1OCJZWP/46goqVfRPTjEU7EkRYHxNe9EekzQG8Au3hCv+cL+OdNmiixSBOT Z5J8JN3KB8M7iBKq+sgZrIAureh0R9FK0rywncWdCb+h1gMiw8hzrC5R41o1FZ0EPdHg Lf5Tdvwf8VQ2Efk2JLzb5twHk+4wnVJ4HVnoLm+V+sNRgXouQLTaeTrjZpkwiHQdPKpu fc4AbhJunWHHEKVEQbEJOS+41Q1NU8H0j6pRO3Fr1V2lzFXlFbAnxxVZd42YGQgdv7HQ eBE9eFhPi5FSrzTYtHH+IX5EMxap1Slwjaor6p70fHPtjH7Z0zIU//y++MxIvXtTB+sP i9GA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:to:from:dkim-signature; bh=MUAGJMYy9z0YhWchgLba2d9JBDfozMwww3NybkckEiw=; fh=PhcTh+dL11m20HVFnh7xgSxijK5sC0GxRto/7ayh0Z0=; b=MMyLsXvzxhdv+JpFoxHz00mkmu2O+FpZBTMFjAE8Gkzkt+qIY0bQFcM5ttijDDeM8x nj0W4YRC1CMPDW+b38jbpkWJvpZafajzurRdGBkGOm6AcIMNjC6QY1k+EhwYru1yvSZH lkoec6c0PDmHF8D9ijCHMz5QfLBtF+ojUJqeg7OQmQhj5aJ8kMkaUFN0u25kf1VvVPGu maUh0gvb2F9h8Nxe1j+GGs8oPrR1i6MCovyvKu8m/7VrG6RgBAlPWhhLpYiWlitVZmhh A9AK4JpohW0FS2IsVgt1ttNV5NnR0P4hN8+ZJ7list0W8LqYhx6QzB2jRMOKhe22m2gQ SKOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=XssJloGM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml b/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml index 3ce45456d867..b38f8252342e 100644 --- a/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml +++ b/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml @@ -21,6 +21,10 @@ properties: - enum: - microchip,sama7g5-trng - const: atmel,at91sam9g45-trng + - items: + - enum: + - microchip,sam9x7-trng + - const: microchip,sam9x60-trng clocks: maxItems: 1 From patchwork Fri Jul 28 10:27:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127588 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp396005vqg; Fri, 28 Jul 2023 05:24:25 -0700 (PDT) X-Google-Smtp-Source: APBJJlGj0b0VtbBpsa/HVU2Jeqc80q3WMJ+OdP9ZB/vfKwc9hoQUQR/aNWvyRH/v0JWfZb5HyTy9 X-Received: by 2002:a05:6a00:a87:b0:682:4c1c:a0fc with SMTP id b7-20020a056a000a8700b006824c1ca0fcmr2009239pfl.19.1690547065309; Fri, 28 Jul 2023 05:24:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690547065; cv=none; d=google.com; s=arc-20160816; b=MC6la65XM0aqsbwonQ8sDdNRUx108Zh1xgayaREIlpPtbD7euQn//n5fdWxb9HCtVD le1Wea973XE70k/wjEYkJcKlZvoGx8WAAW3huEj+GFJvgRXpsNd3smAXAxDrzUhL0Eef qmSAr1UnGziAP6fBuQ64qxT63PLav36M46kYfATP98N5wrq+UiDtjnbtdk5XN6dVoCJ4 NDMqp0b3MILOtRAKOBjSBsMKke5tQ5GY9Okdy0rY6G5yx1gms1DOyeJpIuLo9oeQp6Fs mZGuHohFlOaIYdDNZA8lPdkJOTH/Barw/KFSvFy1DdSmaLTQKjD5VlTnq4BTZnW06Z1h eJHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=pZB0KqaTiGbSdqw2C1vNxlxexJR9AiIxuMkCBJ/hwC8=; fh=2safZw256kadySFdybnctWlwOMb8wsUXDYewzIWwUdM=; b=Tdt1vB9V9Bn36VjKRIpdfaKLr+vA9DhPPm9lMiO2ijtA2X4tKZ4zjChqhQjvBzVjuV Fvs8/L/NUuaDRsknzD+w7DYaF/bACGLDQXnVANf5X3rDFTzIRrPPIRx87/VOz6lJ/9lS KQI9oIG6hR+CdsT3r621kXs0rU/qxcjNczPYK0vLBQYoZvTFkEV6C2DgYfnv6Yei4YH5 Q52/9ZgN3o70CPm+BNx53CEYDA8QZEneV8zhp3AlXb3nZ4QVvKRj+PmfE9I/o59KfHhz ZlyhC7UPIuYcF9ERTS43veMsDtHMU7xu3RM+4DYpI0eY4dVOSCROH023Qj/pIv7b5f4B aIUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=SrLhSnKW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski --- .../bindings/rtc/atmel,at91rm9200-rtc.yaml | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml index 4d2bef15fb7a..c8bb2eef442d 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml @@ -14,13 +14,17 @@ maintainers: properties: compatible: - enum: - - atmel,at91rm9200-rtc - - atmel,at91sam9x5-rtc - - atmel,sama5d4-rtc - - atmel,sama5d2-rtc - - microchip,sam9x60-rtc - - microchip,sama7g5-rtc + oneOf: + - enum: + - atmel,at91rm9200-rtc + - atmel,at91sam9x5-rtc + - atmel,sama5d4-rtc + - atmel,sama5d2-rtc + - microchip,sam9x60-rtc + - microchip,sama7g5-rtc + - items: + - const: microchip,sam9x7-rtc + - const: microchip,sam9x60-rtc reg: maxItems: 1 From patchwork Fri Jul 28 10:27:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127586 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp394803vqg; Fri, 28 Jul 2023 05:22:18 -0700 (PDT) X-Google-Smtp-Source: APBJJlEUr7Xf/PcKo7r36LCFQ+jbqvKRBDXtp1qFVdu/FOyJ3sNR09m4KJCtfZrvpZUMBz9w3d79 X-Received: by 2002:a05:6512:3a8f:b0:4fe:ae7:d906 with SMTP id q15-20020a0565123a8f00b004fe0ae7d906mr1890983lfu.65.1690546937664; Fri, 28 Jul 2023 05:22:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690546937; cv=none; d=google.com; s=arc-20160816; b=Xqw1QoltCAYsf9UhI42U369wuoZ1M7+CuiTYT5munxxJOaPRsNVCpOwAjs7Jm79F1l i/mM4AZynYgXcmNmYLFejo3cIcRHZfgKl+9iQpwuLnuuewbY/zBh9jh1tFm6uzrshpRS 2cZMLqRwfkPXRjij7oAaBkoCxbQtFYbUsG1I9LIwHDLneQ3cpejaY4nGvEWN7SkbbGKq JgZy9NcyHmBZdr/WB1n5SsIet9WskFkiHV77H1D0Sz6TXyvmHNAtF+FlBRoWLGJnhAC8 n85/X0eF8BkQz9tGjSEEVUfNpe4zDQMmiLqy/ktoTO/Tm3wRSFTZpAl8RaVMf1t1gK5S Zb7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=+DCnGxtTwk8c60e/wM5o/bFlF1+az8Mkc6PMzemQDe8=; fh=2safZw256kadySFdybnctWlwOMb8wsUXDYewzIWwUdM=; b=A5gMr60IjQWP5AQYePXD4d7Zc/BYZvFhfTnZxhY/P635J0BE3wGKIa1BydGcEQGlKp bbyCSOBC+rlDHaZBPPF+/MZdI7qJkInKog8M1539Xf3Eu2SHIOf3pph+3bTTLvOF4enu 3bt1ZlZsLXSXS/nTy/QkkIfIY9RRsZe5S57ZkJ9a6VziXN195YrH5k96dJL4qK2YNNDv 8w30HEaM40PAkxF0JcJNodF9r1FyWye2mkVYm6B/zHh6lqz+4xhU1nPpnTj0ejCFizLO p2XFwydnMG/m9o7fKgmwB/dQ7X63A87H9N+P7/TSncj0HKR2OcCvAK+E4WgJdd+Tvizf 0lnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=pk4G6I0r; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml index b80b85c394ac..8426810518e1 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -21,6 +21,9 @@ properties: - items: - const: microchip,sam9x60-rtt - const: atmel,at91sam9260-rtt + - items: + - const: microchip,sam9x7-rtt + - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt - const: microchip,sam9x60-rtt From patchwork Fri Jul 28 10:27:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127661 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp463087vqg; Fri, 28 Jul 2023 07:11:40 -0700 (PDT) X-Google-Smtp-Source: APBJJlHZZKxDRoGfkL6tC7qbeHyZP28CJL37w3A+5paNFGYlO5opRdo6tGdYdJ0exDZkdouR8OFh X-Received: by 2002:a17:906:20f:b0:993:f127:2391 with SMTP id 15-20020a170906020f00b00993f1272391mr3108370ejd.32.1690553499543; Fri, 28 Jul 2023 07:11:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690553499; cv=none; d=google.com; s=arc-20160816; b=OIWAkLD/x4GIlVUlf/orMTtFeslc9aDKaJ3JtGVwnlLDX0b2hz3bQ+COZjPRENKUyY CL5uWwciqdeHTiuj5h85WJcIiyT1PoVLc4R5VNp5NOzm3sxXfwBxzomH1mtjHl9DCr/Q ntU4+mcFICd8bJa0zGA4dGAr5naDDI6CesNpgDZXiCtliJNh/6Ahq2/HZeyfxKDeW9E7 fN93HukCO6jQxaqWGKnBk7q9fKlY/cBGldFlTTvdxm4ZCl2xkPFdyPsHNPOGPiTw8fOI CCe/E6TXcYW/ixZeG4jqETiR2BGL5oKUKa6e3RQL+qauztqDD6cHH2SqWDxqRa8wGkFi sNZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=lEGZPQU9m2f+5l9s/QkLBFl6kxYi2M2vZKO/Z2T4a/I=; fh=JM7J7M5d/lo1rrX9oxj/2SOGJohw6TuZZZDfj/oA+jo=; b=YlAVZxwoKLm6WGrdybOZOLM3w7vV2bZhtzDDy8Rr1Da2GqJNVyHLasG7ZGDTfUKYHF K1+fDUmdCURVVeuT+s2g1GmwAVQ9Vt9ITUYG5jPfHeuNsuBcEInPIQEu0QhC/dcHoONZ gjLuCI/JLOqKMWt1uVbVe5iWzSzEcw0rPm0puitk4tzVYxcHCyHsXe1JHPcQwXAXc5hS gJ7z4FRhlw7w/vQC6uGEccwPoJpAx187C9X+6Zm+ZAZ09y75UWoVR3bF75joxegbBDTu AMqiWnDKwcow2zhg5WoHn3a/OV4/xY+yrNQaRCFItF/9vl0kRcgmraERIdl9MHZvxANY +edw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=1+QMwg34; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/serial/atmel,at91-usart.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index 30b2131b5860..42644d0f1104 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -17,6 +17,7 @@ properties: - atmel,at91rm9200-usart - atmel,at91sam9260-usart - microchip,sam9x60-usart + - microchip,sam9x7-usart - items: - const: atmel,at91rm9200-dbgu - const: atmel,at91rm9200-usart @@ -28,6 +29,14 @@ properties: - const: microchip,sam9x60-usart - const: atmel,at91sam9260-dbgu - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x7-usart + - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x7-dbgu + - const: microchip,sam9x7-usart + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart reg: maxItems: 1 From patchwork Fri Jul 28 10:27:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127555 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp378417vqg; Fri, 28 Jul 2023 04:57:50 -0700 (PDT) X-Google-Smtp-Source: APBJJlGBNmx1TzdClrDR7sGHt4jBRsolDvR1XFr+TbV8AKe3Ohjuft+I9sIn/w4OLb6q2TXJ4iw4 X-Received: by 2002:a05:6808:2a6c:b0:3a4:17b0:2b12 with SMTP id fu12-20020a0568082a6c00b003a417b02b12mr2434183oib.11.1690545469840; Fri, 28 Jul 2023 04:57:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690545469; cv=none; d=google.com; s=arc-20160816; b=VyGrAWTz5KtwyqVbBqKiAS6p8cWCWLlTSqxQxx312xXuYDSMq5c3f+XD0juT2VkDlY nkcQgEHKUdWpWvVciT6T3ANVYZQAJoMSTo3FkKvji2H9bsGi6GQfg4Du+jt2h5cWxTp4 1DWcz2MPTzSfYfE9jTK3Od2GsnCozTTD0yTp+5G+iTPcTvePQYjQhwfU+lQsqvHpdZUQ 9rh94Gry/1I7ECG5HCIwxt+1+IkxY0P46HuPQs/Uvhy3qXYuHVsLeBq+X98MgEcHI7Do Q4wn3D+M4s4QMJfCSvkxhh3oBhbQR0ExjPUdl9inmG4jZJ0lFwOxCMdsgOZDDpaUvwvc sMtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=OJjlNlLWXyJVF2xVn2WVAfNcOSc1oTZfy0zEC+WOjlE=; fh=rsJTGhvKhX9S+e1+qqqe2pKVJcP7BNTONvGg5HboqIE=; b=W2tRuu4p/pyLnGJkSS6tNev+BlWYCKNUN2Hig50ELHl03lSZg4535N0+PjZQlfP4Ur 05VFL6nqSTMKpxzoX0Fkm7xMLw75M3fqS5d7WmxfeqK6LJhKu6JXyBgGI30OKV4ggl2A usB+QiBpAuzoDo/i9dBE5+2Pqy+lhsJec8AvJZJSHgOqu8iO7JjT4tVm7N++R+xX/tW5 bEP9sPp5IkyCUwL2AbD3nhaNVtvPGtxp5WR8LEfsCPfnD8wNhlubGhaJa7LKr4+kEUNo UcKqeMMIFm1pjVmSLjSbmnupTk4VYmOF5/6Sk0jaBOe6msFwM0r5vLKIyeMD4P7QSQJI Sv2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=m4FdrrQO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/sound/atmel,sama5d2-classd.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml b/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml index 43d04702ac2d..ae3162fcfe02 100644 --- a/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml +++ b/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml @@ -18,7 +18,12 @@ description: properties: compatible: - const: atmel,sama5d2-classd + oneOf: + - items: + - const: atmel,sama5d2-classd + - items: + - const: microchip,sam9x7-classd + - const: atmel,sama5d2-classd reg: maxItems: 1 From patchwork Fri Jul 28 10:27:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127540 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp366693vqg; Fri, 28 Jul 2023 04:32:30 -0700 (PDT) X-Google-Smtp-Source: APBJJlFJNveEJIW0U01v5qiZgvo6FGyP9/NwP5+FjSP70fjaHKCmC9uaGsTljnrmesc+dV4T1Tgd X-Received: by 2002:a05:6a20:1396:b0:13c:bf8a:1236 with SMTP id hn22-20020a056a20139600b0013cbf8a1236mr673255pzc.41.1690543949865; Fri, 28 Jul 2023 04:32:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543949; cv=none; d=google.com; s=arc-20160816; b=u6QSp2QEE+ctoSeylRKQB609cYatNFeh0znHgxlPmn1KKCxTLgmXCBoHwHmLaRHT/Q vKFm688GKNpDGWcD12nklH3RwRUccuNt3nm4tOjSt++kG5CegyUJHM7CQYb9tuxyqDD3 WiDPEjmIJ4Za7wuJg+apmAh96gM9r4S6bsVHdkjBv04yjEvBo8TKKia2YQuM6hkpS9pO oubsbLZNrjAih28XBfxsAIcJEFZL+CWb9d3WGeQvdEZvnpSOiA67RCOKVTGt/llbRXRm ZPfmKqkT99irjeuGUCB9sqmsHru0WWvY6zIh9GrtlMIFzibyNSwCuMvGYFywBt8qcjgd RLuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=baXbn9jWJccJkopEEPsJkrwZ99dpIpmERI5zvYxdX3c=; fh=AonKjEH1ncq+SDly9R9NaV3eCgULlTZ7bwAEKKO6zSQ=; b=BJNf2NGem9ugIh7zyr1FZG4/mqfbckjuIDfN4Y8u/vBkU+z2YBKUqfOVvP3/rR7AAE Q0YXbiQAzeveJBvhv+SziHGHxqQ9OCcqIOgm0KidCh2VI31t7FBZ0yOrJZNwALfnw3ZT M3DCZkIdjYK8ZCugRxu4TftZwtyNP0f7/lkM1Zm/kn03MPgRJ66wl2SJYLYc1RIh6Yv5 e1oaDNUxAi+kVu1VRXJp1OmGwxWeKBlB4Mxbgcnq7p7kVmKTAFsNy1GtPK8PLsnIHD70 hlJfyptcEFWE5O23ilxKwpDqNWg2JaTkaVuTALWALDRkjxxit+Sp2sdvXeeZ5aX9Wmyy J6+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=graE0Eyj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/usb/atmel-usb.txt | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index 12183ef47ee4..82bd0dbc2a48 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -3,8 +3,9 @@ Atmel SOC USB controllers OHCI Required properties: - - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers - used in host mode. + - compatible: Should be "atmel,at91rm9200-ohci" or + "microchip,sam9x7-ohci", "atmel,at91rm9200-ohci" + for USB controllers used in host mode. - reg: Address and length of the register set for the device - interrupts: Should contain ohci interrupt - clocks: Should reference the peripheral, host and system clocks @@ -30,8 +31,9 @@ usb0: ohci@500000 { EHCI Required properties: - - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers - used in host mode. + - compatible: Should be "atmel,at91sam9g45-ehci" or + "microchip,sam9x7-ehci", "atmel,at91sam9g45-ehci" + for USB controllers used in host mode. - reg: Address and length of the register set for the device - interrupts: Should contain ehci interrupt - clocks: Should reference the peripheral and the UTMI clocks @@ -87,6 +89,7 @@ Required properties: "atmel,at91sam9g45-udc" "atmel,sama5d3-udc" "microchip,sam9x60-udc" + "microchip,sam9x7-udc", "microchip,sam9x60-udc" "microchip,lan9662-udc" For "microchip,lan9662-udc" the fallback "atmel,sama5d3-udc" is required. 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Signed-off-by: Varshini Rajendran --- .../bindings/watchdog/atmel,sama5d4-wdt.yaml | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml b/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml index 816f85ee2c77..ce3d046e7244 100644 --- a/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml @@ -14,10 +14,17 @@ allOf: properties: compatible: - enum: - - atmel,sama5d4-wdt - - microchip,sam9x60-wdt - - microchip,sama7g5-wdt + oneOf: + - items: + - enum: + - atmel,sama5d4-wdt + - microchip,sam9x60-wdt + - microchip,sama7g5-wdt + - items: + - enum: + - microchip,sam9x7-wdt + - enum: + - microchip,sam9x60-wdt reg: maxItems: 1 From patchwork Fri Jul 28 10:28:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127534 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp364917vqg; Fri, 28 Jul 2023 04:29:34 -0700 (PDT) X-Google-Smtp-Source: APBJJlE2r5y7FVw14tNbDpnwSrnU1Z19OiRLK4d/RubIahfQE1xyhCgMJIp28G8ojCVl6xfQYqJ6 X-Received: by 2002:a05:6808:48b:b0:3a4:2829:326d with SMTP id z11-20020a056808048b00b003a42829326dmr2554146oid.14.1690543774446; Fri, 28 Jul 2023 04:29:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543774; cv=none; d=google.com; s=arc-20160816; b=k/0Ta1PFNzCja1Uwa8M6h4KnfNFytrMNA2cpEhJr5vX4pjk2OJyUFOrz9Pt/Fc1vLl oNXjr53AsqRimOnfVDnbidXqZprWGqLpMWTNkgKrKuO1uIh3VJgdrevM9uxDP7gGm+54 8zVBhEBTP//8s8LmctadTLAr9wUXfogwRJ+SDiVhp5AG7ake4qKdyWtoWvGYRU096W9N udNhkMuuhWv7p+idpPoz9BetayCpyivwWWOq3LxBMBgTOY5owDWMRgmDqYfg5aYgDU15 bDDgWliek4XP//WGAkt7TE3UyptGattms/vtP2oLZ++qluAo834a+heHNGmKVwVg59tE FJMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=BOvYk5aU50J5eZIdKN8L21lpyVU8uGTXvUUsUFq4zBk=; fh=2ikMqJwfKRBMjuE+QI0GFmtr9+/aZRoYbQyqqTwvmAs=; b=vgnFM703Cim6RJlUsCSXBXIP+fcpi+uXirhrro0s5KNNhPvIjwSw804yZW714E8u21 NL1hwecuLWYn3AB5V6DvV3yqGQAQOV/kZ1EfYsG5MxjHGhB1nMZUPLlDgp7af+FSiEkM PWMUeNWb6yCelKA+77pvhWy7P2SbpBNalCNmTiMVCBQlVnIJVw03XSciykqpuuSd8rvK nD4oHN4MWWOOWpqS4nsPkumno+3HuS5ncM5+hGjUcUd6rKq3LuYzEc/ynzASt7qKJkQ6 mM6Zt4mPLjFqyCcX3VQCOUoUGsaFxgnQBFz4BgcbL52alQpAxCMkna6sBjD3hFb6zTVB /0gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="VW/rWcyF"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt index 7079d44bf3ba..5fb9366c94a1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt @@ -4,7 +4,7 @@ Required properties: - compatible: Should be: - "atmel,-aic" where can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" - - "microchip,-aic" where can be "sam9x60" + - "microchip,-aic" where can be "sam9x60" or "sam9x7" - interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. It should be 3. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml index 58367587bfbc..32e7c14033c2 100644 --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml @@ -22,7 +22,6 @@ properties: - const: atmel,at91rm9200-spi - items: - const: microchip,sam9x7-spi - - const: microchip,sam9x60-spi - const: atmel,at91rm9200-spi reg: From patchwork Fri Jul 28 10:28:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127528 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp362883vqg; Fri, 28 Jul 2023 04:25:01 -0700 (PDT) X-Google-Smtp-Source: APBJJlE08nwcOAsiakZCk5/RFjMl/JbtLJ8aP5j44j14iri9N9b/pMZpY1UHRS75ZXAy+9fFIw0y X-Received: by 2002:a05:6a20:3257:b0:136:ea2d:6d6a with SMTP id hm23-20020a056a20325700b00136ea2d6d6amr1090517pzc.17.1690543501635; Fri, 28 Jul 2023 04:25:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543501; cv=none; d=google.com; s=arc-20160816; b=wnNJ9oG9ig3zGYU0drvXH0wjPFcBFx21HFn2X4AFv52ZhMSDgmEqCaFc9AWWvVPArI aVKk9i4Ot3h7HDEnTeROA4FeI0YdSMf9yeBnEDM+lKx4ENtuZJMsiwxe61bBgxXxZ4cU zgNp8kwB12Onj5h5AksYVvpT40f8oasz/u0/djGlIuF25LjTqhh6FrrS459zYSl0dHIs ie/PTGF5EqujOtBCvUeGs0eCAjrWvFlxdGPgDI92CtHW+GKagXGiUj1kEONg2+36noY7 HOkFkYTfv8r+Ylq3sjxvP0Xc2gSLT8QM9XhBXLytXT0DxqyMEvyNu7hhHg4zZdPXTBGi qgMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=1BgYxpqN3/U3fPliW9zwvwa1ZKCfmlmeX1KIObfre14=; fh=r8g+QmgxMhtHIsKg8nIT8SaQVa/S/fOJyktLR2DFrIc=; b=tanvU5xQO+Svsu+W9G3lFYfKzV+NMNhxXlyiOHHrip36q6MMmEbaZffi9ImKHOIju8 Vml1TifdyEcusC0TqfRvK05FqBeGar90tEBg1NC2JjJINV1sCuaZ2Zlr28+3lxI0KlOZ jgKiEqSa21VtHdWGBDf4Ek+ijXuBI7veF0tueuuJSo89AlBr9xdJXNHKUOpPOg21cU8S aLTPj7/qoC3ks9QOcISE89ggBM14vmUW3CRGF7CUlybLLnx525WyWt9uwJ67JNVZ+BJg K/9VzG2ATh4+a6N45UF/0HGjJZx5Q4cAMWIEmqaYXweLCbHKdqf/yGnFAsLNPiPuEVfe a8jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=qAE93su+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- .../bindings/sound/microchip,sama7g5-i2smcc.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.yaml b/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.yaml index 651f61c7c25a..fb630a184350 100644 --- a/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.yaml +++ b/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.yaml @@ -24,9 +24,14 @@ properties: const: 0 compatible: - enum: - - microchip,sam9x60-i2smcc - - microchip,sama7g5-i2smcc + oneOf: + - enum: + - microchip,sam9x60-i2smcc + - microchip,sama7g5-i2smcc + - items: + - enum: + - microchip,sam9x7-i2smcc + - const: microchip,sam9x60-i2smcc reg: maxItems: 1 From patchwork Fri Jul 28 10:28:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127556 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp378795vqg; Fri, 28 Jul 2023 04:58:34 -0700 (PDT) X-Google-Smtp-Source: APBJJlGI59iVbcezHHeLjPZbx8OS0RQNWyQWdzcHThyssdMQ689RSn+ahBVuKnfOFZxci3AuMRq6 X-Received: by 2002:a17:90b:224d:b0:262:fa59:2908 with SMTP id hk13-20020a17090b224d00b00262fa592908mr2202937pjb.1.1690545514253; Fri, 28 Jul 2023 04:58:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690545514; cv=none; d=google.com; s=arc-20160816; b=TL4sWXntUrM886zaSQMR+Me7hnAjs84+XNsrnUMaaCjwWRCBd2scOHCiR8BEkePwfQ 1UwV0IHZ9cUHiVuZbl2VyhtmXwS4ezchkeDjJYl55NohMzRUTQoKycFW/bjT9L5m7fjs CD0JdI/ts0/Q/7JM7w5llROmujCXjNaCtegt69ZB3GVwhBYPY4qxdig+BKN8CtlXJL3W ktsxzXhU3A6JQS7+rSzzj1Wjb2jLtktb0wEWwZMGH2P4/DUH/zIGX1AeUU2cvUbFILw+ rc3ZFnf5cgvtRnOGoCDG9EZHbEp9yave6DT8dfQ7rDg9rmf/UggX15T1+4SLLH3r97g3 4NnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=T3CdntTN4sqdMAUcJ7Vt3XRwjKSLAPhJj2evCHyYHe0=; fh=JVGqnhxgDjQhgkZvcg74el+UeeT4q5mOS4xATfDjwAc=; b=v2NjXxekIcwpajqhXZACwAWRsXLKEgRLZA22mXWrsIuYNWib6plJ809j6QyXEIefgQ WxH7OQN5W+J0PPrS4HjQtgvkpBPU1UdEuyfwwyrGujAaqkzjgwmu4i6q9exBhtVvo2+v NAYHO+qlRIctdFOdW9Oy5dvzxsQ5gwPZZPLdL2LDdkBgBA/na5Ru8UQ/kjGe7LerpHH2 PMkQR3yCTIJGNn0GfBqrOnEGUyt+NA1I6UtU1GE8nTWSOtwTNZR6KYzQZ+WKDM+7RAoO APwljJX4dM3KLJsx/qILRmVhw6+1BmqI7AL3SrFJOS/ZXQZzmoLxcs3sOFB8gK2vgu+5 fWHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=ZoecFRhz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml index e5c8f4e085de..afc4da89dde5 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -82,6 +82,12 @@ properties: - nuvoton,npcm845-ehci - ti,ehci-omap - usb-ehci + - items: + - enum: + - microchip,sam9x7-ehci + - enum: + - atmel,at91sam9g45-ehci + - const: usb-ehci reg: minItems: 1 From patchwork Fri Jul 28 10:28:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127543 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp367210vqg; Fri, 28 Jul 2023 04:33:21 -0700 (PDT) X-Google-Smtp-Source: APBJJlE5tJZFPNp0RHQVZ/CD6sYrin2BOSVoQxydYtgw+d6SY700m44L5zLsGdSwYEe3zAmG4fzc X-Received: by 2002:a05:6a00:b56:b0:686:22de:634b with SMTP id p22-20020a056a000b5600b0068622de634bmr1828258pfo.1.1690544000722; Fri, 28 Jul 2023 04:33:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690544000; cv=none; d=google.com; s=arc-20160816; b=gTN/E6ANjb0ypBhFMQJ/X/Y7Oy/PP3ML+1NDwBsk9HyPguOYEbmnpA6PhmP3Q3EWBD P2pa0uLqRJv6nrwYwhwP6ZwUBiXKioYTR/f9nZu15MTZyyTV8MehoMQJZNCX9p/Grrq7 hb9tUM38VYs2S54920uYpzxDoPZUUr+BFzV1zY5vhFMW66iRVR/v+Nzesom4Wo0rxWu7 GU5jlabQAfapPZmRodBNXLxWn1GosJZRz0ZjdLL59+wTcDoKoXXm5TDtmFkxJLn5B0b4 joMeE/VWzpx+Ef5Cue1ifDRRXTzcM21gil6W5UNw9XQCXQWeREDZyrnenZu3DRpBQ8KG pUWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=EHWreK95+2R6VD3PKlNFqzlfN9l+npsNRygWrBQAdxE=; fh=JVGqnhxgDjQhgkZvcg74el+UeeT4q5mOS4xATfDjwAc=; b=OQlTF7DsUTmtFe1Jj+12nBvKSYr50Aayrv1q52vx+NP55R8o77GGnkKAS5mRJMMYnM uJRk3Yr00ucpJnmbaffRh7rxtAhAVK+vj074+FdOCvLVzwyf8Xxzx7aEKm4ABHQaVjBV PSmOzh5EQEehGN1YQbWewSigprRwwMnDtbVrb9v9e7+J9ulZc8kGi6wUTgJIe4NzbA5u MLYwnakZqGnV17C4+uU/BTs3jNuROyN0Et1r2eTZmQ/Ow6bb4yiwUH3kzuLdYrkVcEf6 QrgVgbJt8eHB73NUgqBlcpnGMbWIwunFDLUSw3S9W5o0bRRp0IYEUnHLyqHiypKJqAmC 0zrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=cfZvuJf3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml index be268e23ca79..a2490759f694 100644 --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml @@ -57,6 +57,12 @@ properties: - nxp,ohci-nxp - st,spear600-ohci - const: usb-ohci + - items: + - enum: + - microchip,sam9x7-ohci + - enum: + - atmel,at91rm9200-ohci + - const: usb-ohci reg: maxItems: 1 From patchwork Fri Jul 28 10:28:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127536 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp365948vqg; Fri, 28 Jul 2023 04:31:15 -0700 (PDT) X-Google-Smtp-Source: APBJJlEs+EQf6mkxRgKJ04BmKrUtSeF9vPZiUspa2IThpavWjfm4YAMbX1yBfT2RcCog3Z8pgWl5 X-Received: by 2002:a17:902:8f8b:b0:1b6:b445:36d4 with SMTP id z11-20020a1709028f8b00b001b6b44536d4mr909413plo.43.1690543874788; Fri, 28 Jul 2023 04:31:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543874; cv=none; d=google.com; s=arc-20160816; b=qMfXhk0UhaTIypdRT8WePweiuQvv2apUFzIhyvofpGOEBC58k5Bg14N0/x/65OYlnF dayE/lutEzFLtSZCpSorh6EI7io32dp3fFniR/U4il7wMZCDS7sxO6vVPnCMAvAe39xx QyU2xULMU1meVeQ0aoglT0LSzOGUShyOuvyqpqaI9fw1PLFsMUZ67w1dZOcAJhuW/oJm fZWn6bfVv9IVShDGiMDDG12Wg0jjq1wSpxQEJm3lVDm9GmQu50VACr+2VA6ZaGNYBRgj /+p1ILpOZAUtl2H1E3Gke0tF9+lH5bP2TQUPePzqYppJ0E00dkSRQihNKizgCAoOsIDE 9GlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=vfQj4W34p32fpKplbk8SCScCBCxlioIe0oZY7qd0UAI=; fh=WSzKNqLojcVl23JN2OirrokcvFofWNf682DO0OVLZ+0=; b=G9XsiiEi7a1Im5q1KQNAqlaOHQEhkzmxNoI5zt2TV/muhALJm+rgr+6lwn6fBl5mqx lZwF2DJWcdHmNwczdlyNq7G6GF4JYKHe79Zsef9jHbcqiqoxfHLR6QogblOLnhcLTYj/ aevltkoqokoO3pxG1pUb7uGdHrbml3XotkeazvLXKrBOna6C71lg59oue1kuxxqH5LFf HgGw/zqleCJSO7TDBO+BhPCDCi9X2977uEGgKiv6gaQjdw2+KNKkBU1dEF+GSgTdmpGZ 1mRhFIzKDvwFsW9GIlLUvxF+7pXAauFBJIDjMPwwmHQqpXlcVczj8mKAVpFO5q3Fiz/D E8IQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=X88ShCrP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e2-20020a170902f10200b001b8a699d248si2786293plb.389.2023.07.28.04.30.59; Fri, 28 Jul 2023 04:31:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=X88ShCrP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234096AbjG1KcT (ORCPT + 99 others); Fri, 28 Jul 2023 06:32:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235433AbjG1Kbz (ORCPT ); Fri, 28 Jul 2023 06:31:55 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3578E5264 for ; Fri, 28 Jul 2023 03:30:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1690540210; x=1722076210; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=TjFhqTnBLmMPxvyy40FYkm5ofg7q8wLKisUlMVjtAnk=; b=X88ShCrP6sLqYbcoe9HY01FIkVFssFB9el77hbaBe7qb+arYGSdkPMhR c4IUCiv4g+QTRrC4SLItX80kmEKaQWBs6m1WLrY0S+riXeJCJHChYc+2y G5P0Pphj76rHVvYDQMvwdEpfIFfIm5Hgb7TxJFN6SeIG8zfH2/OwphWbY RKn2NeqFUdty+BrZmQ5J9zaeV4scgHwN3Allqp8XxaVwAH/K4a8sAU0ER X8dUN9eZJHFVQbC3xySUnyQcoh/nLB+e5/aqQsX8IK9z/aHrhbggYWITP E1iqVC07sYzIqNIiend8GZS2g5VBSVtDnHrHLr1xssVj2NY6kX8WwyT61 A==; X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="163712795" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jul 2023 03:29:22 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 28 Jul 2023 03:28:57 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 28 Jul 2023 03:28:54 -0700 From: Varshini Rajendran To: , , , , , CC: Subject: [PATCH v3 34/50] ARM: at91: pm: add support for sam9x7 SoC family Date: Fri, 28 Jul 2023 15:58:51 +0530 Message-ID: <20230728102851.267029-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772663733909471404 X-GMAIL-MSGID: 1772663733909471404 Add support and pm init config for sam9x7 SoC. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- arch/arm/mach-at91/generic.h | 2 ++ arch/arm/mach-at91/pm.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 0c3960a8b3eb..acf0b3c82a30 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -12,6 +12,7 @@ extern void __init at91rm9200_pm_init(void); extern void __init at91sam9_pm_init(void); extern void __init sam9x60_pm_init(void); +extern void __init sam9x7_pm_init(void); extern void __init sama5_pm_init(void); extern void __init sama5d2_pm_init(void); extern void __init sama7_pm_init(void); @@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void); static inline void __init at91rm9200_pm_init(void) { } static inline void __init at91sam9_pm_init(void) { } static inline void __init sam9x60_pm_init(void) { } +static inline void __init sam9x7_pm_init(void) { } static inline void __init sama5_pm_init(void) { } static inline void __init sama5d2_pm_init(void) { } static inline void __init sama7_pm_init(void) { } diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 437dd0352fd4..b2d62a63e37a 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -232,6 +232,17 @@ static const struct of_device_id sama7g5_ws_ids[] = { { /* sentinel */ } }; +static const struct of_device_id sam9x7_ws_ids[] = { + { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] }, + { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, + { .compatible = "usb-ohci", .data = &ws_info[2] }, + { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, + { .compatible = "usb-ehci", .data = &ws_info[2] }, + { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] }, + { .compatible = "microchip,sam9x7-gem", .data = &ws_info[5] }, + { /* sentinel */ } +}; + static int at91_pm_config_ws(unsigned int pm_mode, bool set) { const struct wakeup_source_info *wsi; @@ -1131,6 +1142,7 @@ static const struct of_device_id gmac_ids[] __initconst = { { .compatible = "atmel,sama5d2-gem" }, { .compatible = "atmel,sama5d29-gem" }, { .compatible = "microchip,sama7g5-gem" }, + { .compatible = "microchip,sam9x7-gem" }, { }, }; @@ -1358,6 +1370,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = { { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, + { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] }, { /* sentinel */ }, }; @@ -1495,6 +1508,28 @@ void __init sam9x60_pm_init(void) soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; } +void __init sam9x7_pm_init(void) +{ + static const int modes[] __initconst = { + AT91_PM_STANDBY, AT91_PM_ULP0, + }; + + int ret; + + if (!IS_ENABLED(CONFIG_SOC_SAM9X7)) + return; + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); + ret = at91_dt_ramc(false); + if (ret) + return; + + at91_pm_init(NULL); + + soc_pm.ws_ids = sam9x7_ws_ids; + soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; +} + void __init at91sam9_pm_init(void) { int ret; From patchwork Fri Jul 28 10:28:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127520 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp355788vqg; Fri, 28 Jul 2023 04:10:44 -0700 (PDT) X-Google-Smtp-Source: APBJJlECpEPwHgCCJlAkpSp5Io8TKO92fBCesv9xKG2RyyrRpTPyh9t7obUont4Y7++xo61/Xr+H X-Received: by 2002:a05:6512:401e:b0:4f8:67f0:7253 with SMTP id br30-20020a056512401e00b004f867f07253mr1685731lfb.49.1690542644349; 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Signed-off-by: Varshini Rajendran --- arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/sam9x7.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 arch/arm/mach-at91/sam9x7.c diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 794bd12ab0a8..7d8a7bc44e65 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o obj-$(CONFIG_SOC_SAMA5) += sama5.o sam_secure.o obj-$(CONFIG_SOC_SAMA7) += sama7.o obj-$(CONFIG_SOC_SAMV7) += samv7.o diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c new file mode 100644 index 000000000000..d998fb327860 --- /dev/null +++ b/arch/arm/mach-at91/sam9x7.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Setup code for SAM9X7. + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include + +#include +#include + +#include "generic.h" + +static void __init sam9x7_init(void) +{ + of_platform_default_populate(NULL, NULL, NULL); + + sam9x7_pm_init(); +} + +static const char *const sam9x7_dt_board_compat[] __initconst = { + "microchip,sam9x7", + NULL +}; + +DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7") + /* Maintainer: Microchip */ + .init_machine = sam9x7_init, + .dt_compat = sam9x7_dt_board_compat, +MACHINE_END From patchwork Fri Jul 28 10:29:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127551 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp377728vqg; Fri, 28 Jul 2023 04:56:04 -0700 (PDT) X-Google-Smtp-Source: APBJJlG/PIu4GqfzAUo08eIfgQsRePGhCpcqIwbD6V4v4wIFJNQJ8c/HE8o6Qwsgc4mLmYYFUD+4 X-Received: by 2002:a17:906:29c:b0:98e:f13:e908 with SMTP id 28-20020a170906029c00b0098e0f13e908mr2001547ejf.60.1690545364057; Fri, 28 Jul 2023 04:56:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690545364; cv=none; d=google.com; s=arc-20160816; b=hp4Rgi1WeWb+Jo58asoluU20Pla/XzKIIZ64zWNKXOU0hQ2qxrriF1kTReb9/k3qZO CNcrX61DoxXvvU2HzuG12cR1U72NgXnub3AzVwgwgHU4iCGSIZ2ljMLb2t0+JzbHeLl/ F2Q5uy7xaXt7CBTvSbFKYs2pn8RxkCFLtUNOtX6bZCp5Jdv1ePZq4/8Mmz0px7BEkoKf uweB9woBL56j1ICf88PPM93NOrefBKU622FJBC5kCX3/hndYrgqGCemRtdmUp267gZaJ jgj5wf5fqDFq3PKpzORgHCMaxCgJ7PdeJ1h+OwnE0l7Evqwvqdwze0ZIyfk1do4I6CH2 eTSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:to:from:dkim-signature; bh=HuBhtEJ4rQqrsnpPfNKgnk1SRhraNkgHYRDiLLFyl0w=; fh=b0ppaqQ4ZEIP5FX8cMINLEd1YnSMyPVmBX2uqoTpK9c=; b=L+N4wECeWfgbUO7hgqBhjzERECT4wZtuRJhIVlSUvwbFJct3etgcY0CT+EjuXvKo40 3Jne+ffpAzme4xv3w5ZNZWxv36O6iDh++PxACMWD5B7zDI0Jh0Lqpa3nY6tBDQ1u+pvt 5bGYlbUc3Sbr0Nv4CI6vq2EFcnzf2nmeUh/Pea6bZn8oJYtNhz95AOCPDI3Bj9P4Z4g+ 2pmDOQpKDw5jFo2d68zREoLJaZcePHvlIaUrsu/xE4TPiIlTl1ixOnPtKVX0jl+9gBAp eGtvfjbbVJi9XLCpgOVtHXUnHfg+1QEVG/9H9KiT44QW6rTAfTuPA95H9G7+TJU7OHOV zkog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=ytDujWoy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++ drivers/soc/atmel/soc.h | 9 +++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index cc9a3e107479..cae3452cbc60 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst = { AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH, "sam9x60 8MiB SDRAM SiP", "sam9x60"), #endif +#ifdef CONFIG_SOC_SAM9X7 + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH, + "sam9x72", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH, + "sam9x70", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 1Gb DDR3L SiP ", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 512Mb DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 128Mb DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 2Gb DDR3L SiP", "sam9x7"), +#endif #ifdef CONFIG_SOC_SAMA5 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH, diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 7a9f47ce85fb..26dd26b4f179 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -45,6 +45,7 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 #define SAM9X60_CIDR_MATCH 0x019b35a0 #define SAMA7G5_CIDR_MATCH 0x00162100 +#define SAM9X7_CIDR_MATCH 0x09750020 #define AT91SAM9M11_EXID_MATCH 0x00000001 #define AT91SAM9M10_EXID_MATCH 0x00000002 @@ -74,6 +75,14 @@ at91_soc_init(const struct at91_soc *socs); #define SAMA7G54_D2G_EXID_MATCH 0x00000020 #define SAMA7G54_D4G_EXID_MATCH 0x00000028 +#define SAM9X75_EXID_MATCH 0x00000000 +#define SAM9X72_EXID_MATCH 0x00000004 +#define SAM9X70_EXID_MATCH 0x00000005 +#define SAM9X75_D1G_EXID_MATCH 0x00000001 +#define SAM9X75_D5M_EXID_MATCH 0x00000002 +#define SAM9X75_D1M_EXID_MATCH 0x00000003 +#define SAM9X75_D2G_EXID_MATCH 0x00000006 + #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 From patchwork Fri Jul 28 10:29:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127612 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp411510vqg; Fri, 28 Jul 2023 05:53:31 -0700 (PDT) X-Google-Smtp-Source: APBJJlHfBMjfxeCTXiJrDPNWYcYjn4gREMvvEmvYBlZyF3SIIqLUcJRbhC1NznPEBqPyi+ik1dra X-Received: by 2002:a17:902:e5c4:b0:1b8:e41:f43f with SMTP id u4-20020a170902e5c400b001b80e41f43fmr1940030plf.27.1690548811464; Fri, 28 Jul 2023 05:53:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690548811; cv=none; d=google.com; s=arc-20160816; b=dNDpkdychT6WnmVlwfEnluU9OdvL+VibDS0JE3ZIUumvzwBTJXC/KNIk73OSx8klVA Hgkg8OQui1oJE2l4vIoZrLYP/cRVZdcrOHGMAftoaJ9ybnHwP7H5+YqtMEFZKesHLz/4 QqeAqG8/dwkKGFYypAwkoAGaAmyItEjW5qwhK6hHh3La8UwuHFRX+0kyIEp/VPdpz2kn 0bPUk0oShtfqs4IgwVzbyB09A6bqQel9OyCuJgnQXzhJnTl6TwPjttH6lPMbxi1Gl8T8 DzxWcVl84nthS3xdkUpSW+RG2HiAXkWI8Fy5xTb3OgK2wF3XUilOPRaQ7AXFcYoQTWY9 xvwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:to:from:dkim-signature; bh=kfkWHmDH2ccixlU5fQHp7hs28wJxcr4ROkouneX9pAw=; fh=v+1g9mN+9S/UqVRA4XgevCgJzKSrWtUvl0aPJHLGya4=; b=spDboIYWpMGmimepJDwSUNm7Kai3JOj1QEIaUGIJ7z8YGlwo44iyupCQTBAu28DcOA NrzX8drTbFUGNM66IJo0ks7YQSzCbkaWVrQIlG5WeYOV7elC76X1A1QU4OMBL4KfGN7q EXChFmiVc1Kon4q4gb4ijLZlTBKZQeBJ079cE1/klYwQsmha9xC9p80xrvSeSGPLmu4B wS1qnfOU9tClT4FaBkiRIn0p6icFH9yDJveWvYI2ncXdWaLvdPtxLIr7mufGFJxnv4qD 6ot1OqF7yd+xsBj+V2Td4EB3sA/ejGF/MuchJbH+3kx4VS+BJ8k/o1NyEsA2ztaUtp8G /AgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=cdU6ggMj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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To handle the same in the PLL driver, a separate parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers are aligned to the PLL driver by adding the core output freq range in the PLL characteristics configurations. Signed-off-by: Varshini Rajendran --- drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------ drivers/clk/at91/pmc.h | 1 + drivers/clk/at91/sam9x60.c | 7 +++++++ drivers/clk/at91/sama7g5.c | 7 +++++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index ff65f7b916f0..b0314dfd7393 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -23,9 +23,6 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) -#define FCORE_MIN (600000000) -#define FCORE_MAX (1200000000) - #define PLL_MAX_ID 7 struct sam9x60_pll_core { @@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core, unsigned long nmul = 0; unsigned long nfrac = 0; - if (rate < FCORE_MIN || rate > FCORE_MAX) + if (rate < core->characteristics->core_output[0].min || + rate > core->characteristics->core_output[0].max) return -ERANGE; /* @@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core, } /* Check if resulted rate is a valid. */ - if (tmprate < FCORE_MIN || tmprate > FCORE_MAX) + if (tmprate < core->characteristics->core_output[0].min || + tmprate > core->characteristics->core_output[0].max) return -ERANGE; if (update) { @@ -669,7 +668,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, goto free; } - ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN, + ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, + characteristics->core_output[0].min, parent_rate, true); if (ret < 0) { hw = ERR_PTR(ret); diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0f52e80bcd49..bb9da35198d9 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -75,6 +75,7 @@ struct clk_pll_characteristics { struct clk_range input; int num_output; const struct clk_range *output; + const struct clk_range *core_output; u16 *icpll; u8 *out; u8 upll : 1; diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index e309cbf3cb9a..db6db9e2073e 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] = { { .min = 2343750, .max = 1200000000 }, }; +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] = { + { .min = 600000000, .max = 1200000000 }, +}; + static const struct clk_pll_characteristics plla_characteristics = { .input = { .min = 12000000, .max = 48000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, + .core_output = core_outputs, }; static const struct clk_range upll_outputs[] = { @@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characteristics = { .input = { .min = 12000000, .max = 48000000 }, .num_output = ARRAY_SIZE(upll_outputs), .output = upll_outputs, + .core_output = core_outputs, .upll = true, }; diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 91b5c6f14819..e6eb5afba93d 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -116,11 +116,17 @@ static const struct clk_range pll_outputs[] = { { .min = 2343750, .max = 1200000000 }, }; +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] = { + { .min = 600000000, .max = 1200000000 }, +}; + /* CPU PLL characteristics. */ static const struct clk_pll_characteristics cpu_pll_characteristics = { .input = { .min = 12000000, .max = 50000000 }, .num_output = ARRAY_SIZE(cpu_pll_outputs), .output = cpu_pll_outputs, + .core_output = core_outputs, }; /* PLL characteristics. */ @@ -128,6 +134,7 @@ static const struct clk_pll_characteristics pll_characteristics = { .input = { .min = 12000000, .max = 50000000 }, .num_output = ARRAY_SIZE(pll_outputs), .output = pll_outputs, + .core_output = core_outputs, }; /* From patchwork Fri Jul 28 10:29:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127577 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp389502vqg; Fri, 28 Jul 2023 05:13:54 -0700 (PDT) X-Google-Smtp-Source: APBJJlFOXkoX7z84lYa91dKMMeoMl240E5D4/5kRaLMk6VBIZ0LBoc+ly2vaCHYTjD+opCNitOnk X-Received: by 2002:a17:902:d48c:b0:1b8:a3a0:d9b3 with SMTP id c12-20020a170902d48c00b001b8a3a0d9b3mr1618480plg.47.1690546434056; Fri, 28 Jul 2023 05:13:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690546434; cv=none; d=google.com; s=arc-20160816; b=aKXkByiBE2X4PgqhECsi7DRKN0qA5UD/AYCuM3K5WlflI0UdGi7wzYAFrIPQ/igxP1 eOrdwg+smGJYHqgaRTZ4QlIbgsiTDcD6mObxspHPpu+I1L5/0seCru99V3K1ntJXL8hw a5xcAmnwA/mKnkVu974nJDb95PkMG4ime4w+FnIt9OWyvuDAfeOfo0EXtaRnKKt7oBxc itXXfLvHqe1lJvQtUGv4SdGkMbGCiITPZm0za9o6KvUI/R0RF42pVCXBxaUn4L+64ftK oNlLPa2mTH3nl/FJgrQMKZJKlv+ts3PBnS35HBb6+dM65HtUb+PV/jY4HS1cHrB61U11 X5IQ== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n10-20020a170903404a00b001b25e9a76d7si2819499pla.316.2023.07.28.05.13.39; Fri, 28 Jul 2023 05:13:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=bPO5meYI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234819AbjG1Kcl (ORCPT + 99 others); Fri, 28 Jul 2023 06:32:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234346AbjG1Kc1 (ORCPT ); Fri, 28 Jul 2023 06:32:27 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 162A05584; Fri, 28 Jul 2023 03:30:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1690540233; x=1722076233; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=+9RuzNpYmHyqf7fIjBX42rka1JAIk57K6KkiNE8I2wU=; b=bPO5meYIKfMiK7y3y7VOhDAynBAglYcOKp3HT74UBn+KxwxHsL+/ye5H Ag6G8bO1ihKQi4BBCCUOzKmAerjDLfXDSQn9lJ5HDT9b/ragBaRnOMZPE v0Xpq7tuePBuNx17t51yfAr3Ivu2sZyZ5dPVGjo+mbVFGdRVJ/0b/gq8z kJEbWZYxXWubplH+1KhdqkWJCoOZbUo9wgVOp/9HwGwOGyO1/+J882chE UX95UfxZhUeOO5SIApkk88UrdNnfbUGbH28GDFoDPVyogiyF1ThnRfAI6 ELEoSswDRLquYW1+SDYhT5yrS+ABmPlLGNzIrG4I7sFW3BZVnZrqFF1rV g==; X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="225813731" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jul 2023 03:29:44 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 28 Jul 2023 03:29:34 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 28 Jul 2023 03:29:30 -0700 From: Varshini Rajendran To: , , , , , , , , , Subject: [PATCH v3 38/50] clk: at91: sam9x7: add support for HW PLL freq dividers Date: Fri, 28 Jul 2023 15:59:28 +0530 Message-ID: <20230728102928.267237-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772666417151608844 X-GMAIL-MSGID: 1772666417151608844 Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and 4 respectively, both have a hardware divider /2. This has to taken into account in the software to obtain the right frequencies. Support for the same is added in the PLL driver. fcorepllack -----> HW Div = 2 -+--> fpllack | +--> HW Div = 2 ---> fplladiv2ck In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz after the hardware divider and the plladiv2 freq is 400 MHz after the hardware divider (Given that the DIVPMC is 0). Signed-off-by: Varshini Rajendran --- drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++---- drivers/clk/at91/pmc.h | 1 + 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index b0314dfd7393..1f80759309c0 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw, { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_frac *frac = to_sam9x60_frac(core); + unsigned long freq; - return parent_rate * (frac->mul + 1) + + freq = parent_rate * (frac->mul + 1) + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); + + if (core->layout->div2) + freq >>= 1; + + return freq; } static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw, return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1)); } +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate >> 1; +} + static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core, unsigned long *parent_rate, unsigned long rate) @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = { .restore_context = sam9x60_div_pll_restore_context, }; +static const struct clk_ops sam9x60_fixed_div_pll_ops = { + .prepare = sam9x60_div_pll_prepare, + .unprepare = sam9x60_div_pll_unprepare, + .is_prepared = sam9x60_div_pll_is_prepared, + .recalc_rate = sam9x60_fixed_div_pll_recalc_rate, + .round_rate = sam9x60_div_pll_round_rate, + .save_context = sam9x60_div_pll_save_context, + .restore_context = sam9x60_div_pll_restore_context, +}; + struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, @@ -725,10 +747,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, else init.parent_names = &parent_name; init.num_parents = 1; - if (flags & CLK_SET_RATE_GATE) - init.ops = &sam9x60_div_pll_ops; - else - init.ops = &sam9x60_div_pll_ops_chg; + + if (layout->div2) { + init.ops = &sam9x60_fixed_div_pll_ops; + } else { + if (flags & CLK_SET_RATE_GATE) + init.ops = &sam9x60_div_pll_ops; + else + init.ops = &sam9x60_div_pll_ops_chg; + } + init.flags = flags; div->core.id = id; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index bb9da35198d9..91d1c6305d95 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -64,6 +64,7 @@ struct clk_pll_layout { u8 frac_shift; u8 div_shift; u8 endiv_shift; + u8 div2; }; extern const struct clk_pll_layout at91rm9200_pll_layout; From patchwork Fri Jul 28 10:29:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127584 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp394484vqg; Fri, 28 Jul 2023 05:21:46 -0700 (PDT) X-Google-Smtp-Source: APBJJlEoZ29Zeg8IF4ro8NhyzkNfg5A5uaCJM+iDRM50eswPkLFwoBNVz8mbHspY/i5OffHwcHO5 X-Received: by 2002:a05:6402:613:b0:522:3fc6:91e6 with SMTP id n19-20020a056402061300b005223fc691e6mr1617264edv.9.1690546906114; Fri, 28 Jul 2023 05:21:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690546906; cv=none; d=google.com; s=arc-20160816; b=H9PrfFIPAKKeknf+EfzfzUV7qnyDRSfHIFSM7GnpJUDBVjdQPgIBKx7Gr3tQncSWiX aMX43e961rq2OOb46nnzlGGolQbJXNayNNxRB6xSK8C/FLXeLn/B5w02n29OBcIxW5lD dbnDMPnhF4PJ3Y2WExAd8beWUsGlo7M5uxcWZfrSYFAHjW3A8uyUSWiBY/9wVhrW3cQf vYQxUwQKZ8t/W+rK2T10JzeVvL5yVYgN/S4XxrmbL2jRtf/pgS0861fQDKNzeBXZnGVK cfHEvUd2Nz8QGA2k8vCJfWPvmyB+4zXZyEafTldQ3bvuxfg2R6gnVqzwY77oyLQeW1aJ OV0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:to:from:dkim-signature; bh=m7NFWWi5/ew1y4GgTxiNQ2OAbWClpSHHYvjHncsQvw0=; fh=+hP2lP1o+Z6v79dUFZStd+pUi1wmCbLJG4/NF83SMpY=; b=gNtCoj7AAsB90H0WyoIKKb23WBeFPcbrZXWDcoskbCUXIbsrKi6M5wYUf7iBDZ/DXH iysv7KC/8QI7R/6PibSzf3PzQbXrdxkln3ro/UgDIhX+4q5pop2anmQuLvge/N15u9vW ZEUU+VTQgcIXS6P5OtDQtn45e/pAJvmg6U2xMZzPZ7GArYkk00nxzTavQSurq+2rQWTI yHgb+De6TA1o26J/WgV7+rHCpFsdj9Y34M/N1ZMa/vbXUSWy0izVIDBSOQhaLZEibdCI k07mfaTx4HT6hdW/ZUY6Yboph2UNePM8zfTqvJPdV4+tFgd3QuQzE0L4NX73bWF9nOrp onPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=SIdC84ST; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u12-20020aa7d0cc000000b005219e26dddesi2297821edo.655.2023.07.28.05.21.21; Fri, 28 Jul 2023 05:21:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=SIdC84ST; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235626AbjG1KcA (ORCPT + 99 others); Fri, 28 Jul 2023 06:32:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235265AbjG1Kbl (ORCPT ); Fri, 28 Jul 2023 06:31:41 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 986B1524E; Fri, 28 Jul 2023 03:29:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1690540193; x=1722076193; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=f1dps+oGiDe/KHzYb18t8lFz4154pwNNCSulv4GCbrs=; b=SIdC84STOF9b087VL4m3alBzYCcrG+8TKXrfTSpTuGmLVWafh3qoISsH AEDqtkKyXg/G4gnzANUURsKWAi3QmCPxQ7787FY3U5STakVqnfX96oObc ES7182zY8m0HQSG6tg9RgczFFBBRWp8F8totxJVwD7/6uyfInoiRf2SKZ Q5AJwvSrFBkS1xiEqGu0xRCkLUNHBOBaoGpUir6Fv5kod7Ns9qBFXlelb ngKG/xAb7PK9qnGeXHA3FhA+/rJOVnGqW1c9ZiDgoY/eZuR8jBto4fN6a X+KjUSM8FLAXNKamDyVctdxcgNGq6AEJ4/L77AgGOhSJUsa8AoYsV0cMF Q==; X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="226623427" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jul 2023 03:29:44 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 28 Jul 2023 03:29:42 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 28 Jul 2023 03:29:38 -0700 From: Varshini Rajendran To: , , , , , , , , , Subject: [PATCH v3 39/50] clk: at91: sama7g5: move mux table macros to header file Date: Fri, 28 Jul 2023 15:59:35 +0530 Message-ID: <20230728102935.267294-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772666912467482275 X-GMAIL-MSGID: 1772666912467482275 Move the mux table init and fill macro function definitions from the sama7g5 pmc driver to the pmc.h header file since they will be used by other SoC's pmc drivers as well like sam9x7. Signed-off-by: Varshini Rajendran --- drivers/clk/at91/pmc.h | 16 ++++++++++++++++ drivers/clk/at91/sama7g5.c | 35 ++++++++++------------------------- 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 91d1c6305d95..4fb29ca111f7 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -121,6 +121,22 @@ struct at91_clk_pms { #define ndck(a, s) (a[s - 1].id + 1) #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) + +#define PMC_INIT_TABLE(_table, _count) \ + do { \ + u8 _i; \ + for (_i = 0; _i < (_count); _i++) \ + (_table)[_i] = _i; \ + } while (0) + +#define PMC_FILL_TABLE(_to, _from, _count) \ + do { \ + u8 _i; \ + for (_i = 0; _i < (_count); _i++) { \ + (_to)[_i] = (_from)[_i]; \ + } \ + } while (0) + struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, unsigned int nperiph, unsigned int ngck, unsigned int npck); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index e6eb5afba93d..6706d1305baa 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -16,21 +16,6 @@ #include "pmc.h" -#define SAMA7G5_INIT_TABLE(_table, _count) \ - do { \ - u8 _i; \ - for (_i = 0; _i < (_count); _i++) \ - (_table)[_i] = _i; \ - } while (0) - -#define SAMA7G5_FILL_TABLE(_to, _from, _count) \ - do { \ - u8 _i; \ - for (_i = 0; _i < (_count); _i++) { \ - (_to)[_i] = (_from)[_i]; \ - } \ - } while (0) - static DEFINE_SPINLOCK(pmc_pll_lock); static DEFINE_SPINLOCK(pmc_mck0_lock); static DEFINE_SPINLOCK(pmc_mckX_lock); @@ -1119,17 +1104,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (!mux_table) goto err_free; - SAMA7G5_INIT_TABLE(mux_table, 3); - SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, - sama7g5_mckx[i].ep_count); + PMC_INIT_TABLE(mux_table, 3); + PMC_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, + sama7g5_mckx[i].ep_count); for (j = 0; j < sama7g5_mckx[i].ep_count; j++) { u8 pll_id = sama7g5_mckx[i].ep[j].pll_id; u8 pll_compid = sama7g5_mckx[i].ep[j].pll_compid; tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw; } - SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7g5_mckx[i].ep_count); + PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, + sama7g5_mckx[i].ep_count); hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, num_parents, NULL, parent_hws, mux_table, @@ -1215,17 +1200,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (!mux_table) goto err_free; - SAMA7G5_INIT_TABLE(mux_table, 3); - SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, - sama7g5_gck[i].pp_count); + PMC_INIT_TABLE(mux_table, 3); + PMC_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, + sama7g5_gck[i].pp_count); for (j = 0; j < sama7g5_gck[i].pp_count; j++) { u8 pll_id = sama7g5_gck[i].pp[j].pll_id; u8 pll_compid = sama7g5_gck[i].pp[j].pll_compid; tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw; } - SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7g5_gck[i].pp_count); + PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, + sama7g5_gck[i].pp_count); hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7g5_pcr_layout, From patchwork Fri Jul 28 10:29:43 2023 Content-Type: text/plain; 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Signed-off-by: Varshini Rajendran --- include/dt-bindings/clock/at91.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index 3e3972a814c1..6ede88c3992d 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -38,6 +38,10 @@ #define PMC_CPU (PMC_MAIN + 9) #define PMC_MCK1 (PMC_MAIN + 10) +/* SAM9X7 */ +#define PMC_PLLADIV2 (PMC_MAIN + 11) +#define PMC_LVDSPLL (PMC_MAIN + 12) + #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ #define AT91_PMC_LOCKA 1 /* PLLA Lock */ From patchwork Fri Jul 28 10:29:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127546 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp372876vqg; Fri, 28 Jul 2023 04:45:25 -0700 (PDT) X-Google-Smtp-Source: APBJJlGJ5TCEFqwXZK04F5JTU1NtDg/lEygGW+pQ4MANdIQWVW+ZlgBjWgPkDoiDCXg4tvsr9tQX X-Received: by 2002:a17:906:1003:b0:99b:4afc:7714 with SMTP id 3-20020a170906100300b0099b4afc7714mr1645956ejm.44.1690544724883; Fri, 28 Jul 2023 04:45:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690544724; cv=none; d=google.com; s=arc-20160816; b=l2hymXbYR8RL1pRgbuXJjg1drlKW95kYSSWiJtvKpfX4l/0bjrvT/tC9uRQXmOoag1 ULvAWd333pFoo6McUsNjQsI8IwVrSo0m2MQeoefkTmWNNJmVxNynmWCAaMc02H+8FvvE Av0/VcGyMa9xgNAtmZHg+Fs9aTR/OWSmSbO3ZpZlRR7zoaKfaaAphbM/XsWv0/2zqaZK vXl+PBoXSZydjoRq0yESLw6Bv9DLgdWRz43oHpRB/prwlC2wgeH5+kSQ9dnv4z67Yg/Z TmaVS7iYROAK3cnuFRhvG2fDFgrsCTZK0XAJeq1TeCbvqHCM8wFHrtUp3pCaLMT80rkb vy7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:to:from:dkim-signature; bh=vz5l1+/2upM+YK9XNEoazvESW0OWFyDYS/nutM+BmQM=; fh=bj0XmSoC3JnD8B5SA0QWlp3wUTFbL6vSGHHqdRhQo8s=; b=yKvfhScHV8ZnBt0EOOMmhpWFrY/6AaXayN7Qy9/Wgd3yA++9kjid4PWwU1Osb1F8u+ p2ZMLkvkfG+0pMeky+oSD4dzN4q2k58OXusfI8cqfLr0juI8JApTnij1cx+Jf1UKcRMg fvGNLj21MH6BI/DLUD9jvrwZ+V4cliwcQ39MMqi+N5SBLKWYTlcaCOzCgu/3L3GEaGwm OrD0mSD8WP//sFqF42/XhVSMC3ukknuFpdQdaD3hO8IDBPQMXCHc2rQHMerG8foRxcwU 4X7u3+io9vMusrm1DV1QKYJ0rqFvoMhDD5zTPV4uxGhVAUpajBHVgpFSTlNehTh7y9ey 0JoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=ZbXEOno6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- drivers/clk/at91/Makefile | 1 + drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 947 insertions(+) create mode 100644 drivers/clk/at91/sam9x7.c diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 89061b85e7d2..8e3684ba2c74 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat. obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c new file mode 100644 index 000000000000..391c86f07df1 --- /dev/null +++ b/drivers/clk/at91/sam9x7.c @@ -0,0 +1,946 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SAM9X7 PMC code. + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + * + */ +#include +#include +#include +#include + +#include + +#include "pmc.h" + +static DEFINE_SPINLOCK(pmc_pll_lock); +static DEFINE_SPINLOCK(mck_lock); + +/** + * enum pll_ids - PLL clocks identifiers + * @PLL_ID_PLLA: PLLA identifier + * @PLL_ID_UPLL: UPLL identifier + * @PLL_ID_AUDIO: Audio PLL identifier + * @PLL_ID_LVDS: LVDS PLL identifier + * @PLL_ID_PLLA_DIV2: PLLA DIV2 identifier + * @PLL_ID_MAX: Max PLL Identifier + */ +enum pll_ids { + PLL_ID_PLLA, + PLL_ID_UPLL, + PLL_ID_AUDIO, + PLL_ID_LVDS, + PLL_ID_PLLA_DIV2, + PLL_ID_MAX, +}; + +/** + * enum pll_type - PLL type identifiers + * @PLL_TYPE_FRAC: fractional PLL identifier + * @PLL_TYPE_DIV: divider PLL identifier + */ +enum pll_type { + PLL_TYPE_FRAC, + PLL_TYPE_DIV, +}; + +static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 32000000, .max = 266666667 }, + .divisors = { 1, 2, 4, 3, 5}, + .have_div3_pres = 1, +}; + +static const struct clk_master_layout sam9x7_master_layout = { + .mask = 0x373, + .pres_shift = 4, + .offset = 0x28, +}; + +/* Fractional PLL core output range. */ +static const struct clk_range plla_core_outputs[] = { + { .min = 375000000, .max = 1600000000 }, +}; + +static const struct clk_range upll_core_outputs[] = { + { .min = 600000000, .max = 1200000000 }, +}; + +static const struct clk_range lvdspll_core_outputs[] = { + { .min = 400000000, .max = 800000000 }, +}; + +static const struct clk_range audiopll_core_outputs[] = { + { .min = 400000000, .max = 800000000 }, +}; + +static const struct clk_range plladiv2_core_outputs[] = { + { .min = 375000000, .max = 1600000000 }, +}; + +/* Fractional PLL output range. */ +static const struct clk_range plla_outputs[] = { + { .min = 732421, .max = 800000000 }, +}; + +static const struct clk_range upll_outputs[] = { + { .min = 300000000, .max = 600000000 }, +}; + +static const struct clk_range lvdspll_outputs[] = { + { .min = 10000000, .max = 800000000 }, +}; + +static const struct clk_range audiopll_outputs[] = { + { .min = 10000000, .max = 800000000 }, +}; + +static const struct clk_range plladiv2_outputs[] = { + { .min = 366210, .max = 400000000 }, +}; + +/* PLL characteristics. */ +static const struct clk_pll_characteristics plla_characteristics = { + .input = { .min = 20000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(plla_outputs), + .output = plla_outputs, + .core_output = plla_core_outputs, +}; + +static const struct clk_pll_characteristics upll_characteristics = { + .input = { .min = 20000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(upll_outputs), + .output = upll_outputs, + .core_output = upll_core_outputs, + .upll = true, +}; + +static const struct clk_pll_characteristics lvdspll_characteristics = { + .input = { .min = 20000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(lvdspll_outputs), + .output = lvdspll_outputs, + .core_output = lvdspll_core_outputs, +}; + +static const struct clk_pll_characteristics audiopll_characteristics = { + .input = { .min = 20000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(audiopll_outputs), + .output = audiopll_outputs, + .core_output = audiopll_core_outputs, +}; + +static const struct clk_pll_characteristics plladiv2_characteristics = { + .input = { .min = 20000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(plladiv2_outputs), + .output = plladiv2_outputs, + .core_output = plladiv2_core_outputs, +}; + +/* Layout for fractional PLL ID PLLA. */ +static const struct clk_pll_layout plla_frac_layout = { + .mul_mask = GENMASK(31, 24), + .frac_mask = GENMASK(21, 0), + .mul_shift = 24, + .frac_shift = 0, + .div2 = 1, +}; + +/* Layout for fractional PLLs. */ +static const struct clk_pll_layout pll_frac_layout = { + .mul_mask = GENMASK(31, 24), + .frac_mask = GENMASK(21, 0), + .mul_shift = 24, + .frac_shift = 0, +}; + +/* Layout for DIV PLLs. */ +static const struct clk_pll_layout pll_divpmc_layout = { + .div_mask = GENMASK(7, 0), + .endiv_mask = BIT(29), + .div_shift = 0, + .endiv_shift = 29, +}; + +/* Layout for DIV PLL ID PLLADIV2. */ +static const struct clk_pll_layout plladiv2_divpmc_layout = { + .div_mask = GENMASK(7, 0), + .endiv_mask = BIT(29), + .div_shift = 0, + .endiv_shift = 29, + .div2 = 1, +}; + +/* Layout for DIVIO dividers. */ +static const struct clk_pll_layout pll_divio_layout = { + .div_mask = GENMASK(19, 12), + .endiv_mask = BIT(30), + .div_shift = 12, + .endiv_shift = 30, +}; + +/* + * PLL clocks description + * @n: clock name + * @p: clock parent + * @l: clock layout + * @t: clock type + * @c: pll characteristics + * @f: true if clock is critical and cannot be disabled + * @eid: export index in sam9x7->chws[] array + */ +static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; + u8 t; + const struct clk_pll_characteristics *c; + unsigned long f; + u8 eid; +} sam9x7_plls[][PLL_ID_MAX] = { + [PLL_ID_PLLA] = { + { + .n = "plla_fracck", + .p = "mainck", + .l = &plla_frac_layout, + .t = PLL_TYPE_FRAC, + /* + * This feeds plla_divpmcck which feeds CPU. It should + * not be disabled. + */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c = &plla_characteristics, + }, + + { + .n = "plla_divpmcck", + .p = "plla_fracck", + .l = &pll_divpmc_layout, + .t = PLL_TYPE_DIV, + /* This feeds CPU. It should not be disabled */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .eid = PMC_PLLACK, + .c = &plla_characteristics, + }, + }, + + [PLL_ID_UPLL] = { + { + .n = "upll_fracck", + .p = "main_osc", + .l = &pll_frac_layout, + .t = PLL_TYPE_FRAC, + .f = CLK_SET_RATE_GATE, + .c = &upll_characteristics, + }, + + { + .n = "upll_divpmcck", + .p = "upll_fracck", + .l = &pll_divpmc_layout, + .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .eid = PMC_UTMI, + .c = &upll_characteristics, + }, + }, + + [PLL_ID_AUDIO] = { + { + .n = "audiopll_fracck", + .p = "main_osc", + .l = &pll_frac_layout, + .f = CLK_SET_RATE_GATE, + .c = &audiopll_characteristics, + .t = PLL_TYPE_FRAC, + }, + + { + .n = "audiopll_divpmcck", + .p = "audiopll_fracck", + .l = &pll_divpmc_layout, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c = &audiopll_characteristics, + .eid = PMC_AUDIOPMCPLL, + .t = PLL_TYPE_DIV, + }, + + { + .n = "audiopll_diviock", + .p = "audiopll_fracck", + .l = &pll_divio_layout, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c = &audiopll_characteristics, + .eid = PMC_AUDIOIOPLL, + .t = PLL_TYPE_DIV, + }, + }, + + [PLL_ID_LVDS] = { + { + .n = "lvdspll_fracck", + .p = "main_osc", + .l = &pll_frac_layout, + .f = CLK_SET_RATE_GATE, + .c = &lvdspll_characteristics, + .t = PLL_TYPE_FRAC, + }, + + { + .n = "lvdspll_divpmcck", + .p = "lvdspll_fracck", + .l = &pll_divpmc_layout, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c = &lvdspll_characteristics, + .eid = PMC_LVDSPLL, + .t = PLL_TYPE_DIV, + }, + }, + + [PLL_ID_PLLA_DIV2] = { + { + .n = "plla_div2pmcck", + .p = "plla_fracck", + .l = &plladiv2_divpmc_layout, + /* + * This may feed critical parts of the system like timers. + * It should not be disabled. + */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c = &plladiv2_characteristics, + .eid = PMC_PLLADIV2, + .t = PLL_TYPE_DIV, + }, + }, +}; + +static const struct clk_programmable_layout sam9x7_programmable_layout = { + .pres_mask = 0xff, + .pres_shift = 8, + .css_mask = 0x1f, + .have_slck_mck = 0, + .is_pres_direct = 1, +}; + +static const struct clk_pcr_layout sam9x7_pcr_layout = { + .offset = 0x88, + .cmd = BIT(31), + .gckcss_mask = GENMASK(12, 8), + .pid_mask = GENMASK(6, 0), +}; + +static const struct { + char *n; + char *p; + u8 id; + unsigned long flags; +} sam9x7_systemck[] = { + /* + * ddrck feeds DDR controller and is enabled by bootloader thus we need + * to keep it enabled in case there is no Linux consumer for it. + */ + { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, +}; + +/* + * Peripheral clocks description + * @n: clock name + * @f: true if clock is critical and cannot be disabled + * @id: peripheral id + */ +static const struct { + char *n; + unsigned long f; + u8 id; +} sam9x7_periphck[] = { + { .n = "pioA_clk", .id = 2, }, + { .n = "pioB_clk", .id = 3, }, + { .n = "pioC_clk", .id = 4, }, + { .n = "flex0_clk", .id = 5, }, + { .n = "flex1_clk", .id = 6, }, + { .n = "flex2_clk", .id = 7, }, + { .n = "flex3_clk", .id = 8, }, + { .n = "flex6_clk", .id = 9, }, + { .n = "flex7_clk", .id = 10, }, + { .n = "flex8_clk", .id = 11, }, + { .n = "sdmmc0_clk", .id = 12, }, + { .n = "flex4_clk", .id = 13, }, + { .n = "flex5_clk", .id = 14, }, + { .n = "flex9_clk", .id = 15, }, + { .n = "flex10_clk", .id = 16, }, + { .n = "tcb0_clk", .id = 17, }, + { .n = "pwm_clk", .id = 18, }, + { .n = "adc_clk", .id = 19, }, + { .n = "dma0_clk", .id = 20, }, + { .n = "uhphs_clk", .id = 22, }, + { .n = "udphs_clk", .id = 23, }, + { .n = "macb0_clk", .id = 24, }, + { .n = "lcd_clk", .id = 25, }, + { .n = "sdmmc1_clk", .id = 26, }, + { .n = "ssc_clk", .id = 28, }, + { .n = "can0_clk", .id = 29, }, + { .n = "can1_clk", .id = 30, }, + { .n = "flex11_clk", .id = 32, }, + { .n = "flex12_clk", .id = 33, }, + { .n = "i2s_clk", .id = 34, }, + { .n = "qspi_clk", .id = 35, }, + { .n = "gfx2d_clk", .id = 36, }, + { .n = "pit64b0_clk", .id = 37, }, + { .n = "trng_clk", .id = 38, }, + { .n = "aes_clk", .id = 39, }, + { .n = "tdes_clk", .id = 40, }, + { .n = "sha_clk", .id = 41, }, + { .n = "classd_clk", .id = 42, }, + { .n = "isi_clk", .id = 43, }, + { .n = "pioD_clk", .id = 44, }, + { .n = "tcb1_clk", .id = 45, }, + { .n = "dbgu_clk", .id = 47, }, + /* + * mpddr_clk feeds DDR controller and is enabled by bootloader thus we + * need to keep it enabled in case there is no Linux consumer for it. + */ + { .n = "mpddr_clk", .id = 49, .f = CLK_IS_CRITICAL }, + { .n = "csi2dc_clk", .id = 52, }, + { .n = "csi4l_clk", .id = 53, }, + { .n = "dsi4l_clk", .id = 54, }, + { .n = "lvdsc_clk", .id = 56, }, + { .n = "pit64b1_clk", .id = 58, }, + { .n = "puf_clk", .id = 59, }, + { .n = "gmactsu_clk", .id = 67, }, +}; + +/* + * Generic clock description + * @n: clock name + * @pp: PLL parents + * @pp_mux_table: PLL parents mux table + * @r: clock output range + * @pp_chg_id: id in parent array of changeable PLL parent + * @pp_count: PLL parents count + * @id: clock id + */ +static const struct { + const char *n; + const char *pp[8]; + const char pp_mux_table[8]; + struct clk_range r; + int pp_chg_id; + u8 pp_count; + u8 id; +} sam9x7_gck[] = { + { + .n = "flex0_gclk", + .id = 5, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex1_gclk", + .id = 6, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex2_gclk", + .id = 7, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex3_gclk", + .id = 8, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex6_gclk", + .id = 9, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex7_gclk", + .id = 10, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex8_gclk", + .id = 11, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "sdmmc0_gclk", + .id = 12, + .r = { .max = 105000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex4_gclk", + .id = 13, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex5_gclk", + .id = 14, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex9_gclk", + .id = 15, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex10_gclk", + .id = 16, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "tcb0_gclk", + .id = 17, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "adc_gclk", + .id = 19, + .pp = { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 5, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "lcd_gclk", + .id = 25, + .r = { .max = 75000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "sdmmc1_gclk", + .id = 26, + .r = { .max = 105000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "mcan0_gclk", + .id = 29, + .r = { .max = 80000000 }, + .pp = { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 5, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "mcan1_gclk", + .id = 30, + .r = { .max = 80000000 }, + .pp = { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 5, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex11_gclk", + .id = 32, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex12_gclk", + .id = 33, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "i2s_gclk", + .id = 34, + .r = { .max = 100000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "qspi_gclk", + .id = 35, + .r = { .max = 20000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "pit64b0_gclk", + .id = 37, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "classd_gclk", + .id = 42, + .r = { .max = 100000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "tcb1_gclk", + .id = 45, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "dbgu_gclk", + .id = 47, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "mipiphy_gclk", + .id = 55, + .r = { .max = 27000000 }, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "pit64b1_gclk", + .id = 58, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "gmac_gclk", + .id = 67, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, +}; + +static void __init sam9x7_pmc_setup(struct device_node *np) +{ + struct clk_range range = CLK_RANGE(0, 0); + const char *td_slck_name, *md_slck_name, *mainxtal_name; + struct pmc_data *sam9x7_pmc; + const char *parent_names[9]; + void **alloc_mem = NULL; + int alloc_mem_size = 0; + struct clk_hw *main_osc_hw; + struct regmap *regmap; + struct clk_hw *hw; + int i, j; + + i = of_property_match_string(np, "clock-names", "td_slck"); + if (i < 0) + return; + + td_slck_name = of_clk_get_parent_name(np, i); + + i = of_property_match_string(np, "clock-names", "md_slck"); + if (i < 0) + return; + + md_slck_name = of_clk_get_parent_name(np, i); + + i = of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name = of_clk_get_parent_name(np, i); + + regmap = device_node_to_regmap(np); + if (IS_ERR(regmap)) + return; + + sam9x7_pmc = pmc_data_allocate(PMC_LVDSPLL + 1, + nck(sam9x7_systemck), + nck(sam9x7_periphck), + nck(sam9x7_gck), 8); + if (!sam9x7_pmc) + return; + + alloc_mem = kmalloc(sizeof(void *) * + (ARRAY_SIZE(sam9x7_gck)), + GFP_KERNEL); + if (!alloc_mem) + goto err_free; + + hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, + 50000000); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0); + if (IS_ERR(hw)) + goto err_free; + main_osc_hw = hw; + + parent_names[0] = "main_rc_osc"; + parent_names[1] = "main_osc"; + hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MAIN] = hw; + + for (i = 0; i < PLL_ID_MAX; i++) { + for (j = 0; j < 3; j++) { + struct clk_hw *parent_hw; + + if (!sam9x7_plls[i][j].n) + continue; + + switch (sam9x7_plls[i][j].t) { + case PLL_TYPE_FRAC: + if (!strcmp(sam9x7_plls[i][j].p, "mainck")) + parent_hw = sam9x7_pmc->chws[PMC_MAIN]; + else if (!strcmp(sam9x7_plls[i][j].p, "main_osc")) + parent_hw = main_osc_hw; + else + parent_hw = __clk_get_hw(of_clk_get_by_name + (np, sam9x7_plls[i][j].p)); + + hw = sam9x60_clk_register_frac_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, + parent_hw, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f); + break; + + case PLL_TYPE_DIV: + hw = sam9x60_clk_register_div_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, NULL, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f, 0); + break; + + default: + continue; + } + + if (IS_ERR(hw)) + goto err_free; + + if (sam9x7_plls[i][j].eid) + sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw; + } + } + + parent_names[0] = md_slck_name; + parent_names[1] = "mainck"; + parent_names[2] = "plla_divpmcck"; + parent_names[3] = "upll_divpmcck"; + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, NULL, &sam9x7_master_layout, + &mck_characteristics, &mck_lock); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", NULL, &sam9x7_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MCK] = hw; + + parent_names[0] = "plla_divpmcck"; + parent_names[1] = "upll_divpmcck"; + parent_names[2] = "main_osc"; + hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + if (IS_ERR(hw)) + goto err_free; + + parent_names[0] = md_slck_name; + parent_names[1] = td_slck_name; + parent_names[2] = "mainck"; + parent_names[3] = "masterck_div"; + parent_names[4] = "plla_divpmcck"; + parent_names[5] = "upll_divpmcck"; + parent_names[6] = "audiopll_divpmcck"; + for (i = 0; i < 2; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw = at91_clk_register_programmable(regmap, name, + parent_names, NULL, 7, i, + &sam9x7_programmable_layout, + NULL); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->pchws[i] = hw; + } + + for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) { + hw = at91_clk_register_system(regmap, sam9x7_systemck[i].n, + sam9x7_systemck[i].p, NULL, + sam9x7_systemck[i].id, + sam9x7_systemck[i].flags); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->shws[sam9x7_systemck[i].id] = hw; + } + + for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) { + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_periphck[i].n, + "masterck_div", NULL, + sam9x7_periphck[i].id, + &range, INT_MIN, + sam9x7_periphck[i].f); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw; + } + + parent_names[0] = md_slck_name; + parent_names[1] = td_slck_name; + parent_names[2] = "mainck"; + parent_names[3] = "masterck_div"; + for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) { + u8 num_parents = 4 + sam9x7_gck[i].pp_count; + u32 *mux_table; + + mux_table = kmalloc_array(num_parents, sizeof(*mux_table), + GFP_KERNEL); + if (!mux_table) + goto err_free; + + PMC_INIT_TABLE(mux_table, 4); + PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table, + sam9x7_gck[i].pp_count); + PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp, + sam9x7_gck[i].pp_count); + + hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_gck[i].n, + parent_names, NULL, mux_table, + num_parents, + sam9x7_gck[i].id, + &sam9x7_gck[i].r, + sam9x7_gck[i].pp_chg_id); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->ghws[sam9x7_gck[i].id] = hw; + alloc_mem[alloc_mem_size++] = mux_table; + } + + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc); + kfree(alloc_mem); + + return; + +err_free: + if (alloc_mem) { + for (i = 0; i < alloc_mem_size; i++) + kfree(alloc_mem[i]); + kfree(alloc_mem); + } + kfree(sam9x7_pmc); +} + +/* Some clks are used for a clocksource */ +CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup); From patchwork Fri Jul 28 10:30:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m8-20020a170902db0800b001b85ab48092si3122803plx.499.2023.07.28.04.29.37; Fri, 28 Jul 2023 04:29:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=IGiU3Byw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235167AbjG1KfC (ORCPT + 99 others); Fri, 28 Jul 2023 06:35:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236241AbjG1Kdj (ORCPT ); Fri, 28 Jul 2023 06:33:39 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30A4A59DA for ; Fri, 28 Jul 2023 03:31:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1690540303; x=1722076303; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=xbMFJDkuvSAVzLORTJHW0ZL04qI1N0hFjbaAsJ5qgb0=; b=IGiU3Bywq02hm2Q3wY4HiXgC6osLByrgB5lzoqpOpIKSpmVSb6V8yg/S t/cebbBZL+y9ic/WZ7Chh6Ty7kXa8zrdvIxGDPephp3Z+WKYxaDQDT3Uw Ep/9Y9Ss6cYZwp1IbuW9WJRO/KMKqxbFN2l/aqDNAQp04t7VdzSTBIJhi 46VykHmH0F4P5J+A55XhLPira1FwKtQhbueYSB1FVDwuRT5D2wtlC0eBm 8+OwI//G19qBbMbkP4+DXVhubYIaiMn27TiqDxWi16Ebu7Ihoy4FKHQIc bMl1cSx8Fd3Xex9uCw8p/3QOKVVkEymJpRtoNbRN7jH7/XC7aiv3IPVzV w==; X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="222729088" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jul 2023 03:30:15 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 28 Jul 2023 03:30:14 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 28 Jul 2023 03:30:11 -0700 From: Varshini Rajendran To: , , , , , , CC: , Hari Prasath Subject: [PATCH v3 42/50] irqchip/atmel-aic5: Add support for sam9x7 aic Date: Fri, 28 Jul 2023 16:00:02 +0530 Message-ID: <20230728103002.267440-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772663646295666345 X-GMAIL-MSGID: 1772663646295666345 From: Hari Prasath Add support for the Advanced interrupt controller(AIC) chip in the sam9x7. Signed-off-by: Hari Prasath Signed-off-by: Varshini Rajendran --- drivers/irqchip/irq-atmel-aic5.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index 145535bd7560..bab11900f3ef 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -320,6 +320,7 @@ static const struct of_device_id aic5_irq_fixups[] __initconst = { { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup }, { .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup }, { .compatible = "microchip,sam9x60", .data = sam9x60_aic_irq_fixup }, + { .compatible = "microchip,sam9x7", .data = sam9x60_aic_irq_fixup }, { /* sentinel */ }, }; @@ -406,3 +407,12 @@ static int __init sam9x60_aic5_of_init(struct device_node *node, return aic5_of_init(node, parent, NR_SAM9X60_IRQS); } IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init); + +#define NR_SAM9X7_IRQS 70 + +static int __init sam9x7_aic5_of_init(struct device_node *node, + struct device_node *parent) +{ + return aic5_of_init(node, parent, NR_SAM9X7_IRQS); +} +IRQCHIP_DECLARE(sam9x7_aic5, "microchip,sam9x7-aic", sam9x7_aic5_of_init); From patchwork Fri Jul 28 10:30:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127524 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp359591vqg; Fri, 28 Jul 2023 04:17:55 -0700 (PDT) X-Google-Smtp-Source: APBJJlHNz0aQ6vYG/hHq4q+MM/AB8+0NcpOH+J3l6FmczDd2YbYcSRBDtQ5/pDnGaX4IpXpErzoN X-Received: by 2002:a17:90b:1910:b0:268:2f6:61c4 with SMTP id mp16-20020a17090b191000b0026802f661c4mr2163901pjb.12.1690543075098; Fri, 28 Jul 2023 04:17:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543075; cv=none; d=google.com; s=arc-20160816; b=UeOqT30tNs62AqB24r6Ge7jgo6cGrkgD49B0YsXp2gQSOSeMJ7lstLJPnIIJvpNPbO qYJv66Ua3ltM5qFT5MRQpl9Ko43sLLOviU5FihKxJU5E1TM5zjzvFDUI7LTnGFAOiErE Dwn9QGhKobom4GTW/c0alvn8m2bUZiC7BwHglDKFXteM0zgODgTcWrFhH0tDCpcNpQdr jbW8O/MvEodTFPMcYRlGwE7PNTu8oCZtePRldnH7nrePL31wWNX7qXJ1KAtRNl5JOkV6 SDH1BxFkn9WJOJVL1VUfr0xjcoBvdRbA+XNgYwWzVQ13BcHvy9JEe7849BQscorZROT9 u8SA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=xs/iqBBEHUNhN8oykbtnYWMaHPlfLJfOSBaLVA+C47w=; fh=JJOzCub310x9Qdc+Eq/0qOpq04Dk9fEhwMIqwuc+3RE=; b=yPYE9evVMGPK/6A7DqHdIFuKJohEYgOTN0XMnSq7CtUEFMaz4a3RQCXdyw7eXxaXLb FkjgD+7RLO+g3btP7+8gAOntjUkQSjjMf0711SNrzZ4OVXtBAjOJR4lhpXQ/HMv2jpun GrL47w66YXIa5C+wbjx6rSru2dspsSPjfH38Yyw2uw1lHf6Gk4KLwUDpn+3dd3Vi0g6q nrk7mIyhrnz4rqPKQY1AcAhetCJ33E5kUuO6JUdboptCx3bCfsTH2MeQv9FLUY7wOGKM i8mzGkUyUzbhLnOibrvKgoAmNX/KL+BV+0aG+obj4ZgD4xrmIYiWquWiM6jZiHlgeggz x3Vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=C2SizrP5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c index d8ecffe72f16..d0f29b99f25e 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = { { .compatible = "atmel,sama5d2-pmc" }, { .compatible = "microchip,sam9x60-pmc" }, { .compatible = "microchip,sama7g5-pmc" }, + { .compatible = "microchip,sam9x7-pmc" }, { /* Sentinel. */ } }; From patchwork Fri Jul 28 10:30:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127591 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp398552vqg; Fri, 28 Jul 2023 05:29:18 -0700 (PDT) X-Google-Smtp-Source: APBJJlGrMlvVUAwcdwhypngiypplnNw1bvdo9KwccR98JnX1/9n0QNOd1s19hJEpn6HI7FHYeNkL X-Received: by 2002:a05:6a00:3a27:b0:671:4b06:4ea7 with SMTP id fj39-20020a056a003a2700b006714b064ea7mr1584248pfb.15.1690547357841; Fri, 28 Jul 2023 05:29:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690547357; cv=none; d=google.com; s=arc-20160816; b=UBesEW9Lhu2f0JX5aO/ZKDkL3BrbTysqNhUTrVmDlo7ZWSJRFW7rrqA+tqevSxcT0i oK9xrlUTFdKiWu6IG9Ccc3TxPbotYBGeO5ORK0EBy6Lx1amhzZVppXGSqnpXRmg+eu/v AC5fK/JiFXCFGERedJh/oXgK6KBJ2puKjBV3T/RkAhHU7rDPT3/hBHf9yuBW4hxGVSvd 6vooBzVRyBeWmNzbK9m+oDisG9hMMf06cybrMG77xUO/m36CHg5X6eONeLm/S7HBkbjU 4dO71Pij2Qwr/YAP4PRoHBuj66VuJWaZ06JNhW6QOJPTK6T3It8+af0dECtT1W2wUDlZ vmeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=Qo9lAN7roaCIDmdnW7x+OFXpBIQICIIYFzBkNk7bf/c=; fh=bjc6H7KU9niG9Wjp5W3MhuG1w13PlQZZQSavf5aMebc=; b=QDy7etM7eEnTuefXBCwGbDV1OYoFjzS7UWMk3rGpKse7SNmVWC2b22LGeN5Ggl7V0A +LQ2iLHSXRCr052wZeRHrCw8lxPMpKtyT4cWwcPMwqfnq+osAEYXSDRgpI2CA9fflNyR H7+VJPBgO+zi3ok8RLeFYmfpzUe6oea8mKYz2Q+sBKYTmb4C8cAybL6mNTEz/VfxOm1g daHqiMnu5/r8LhbIRPHY6/ls+OpKOJORhDthFS1UDsKCSQOYyi/Xb6HBwrIJxohDUNul nPHuqCRTkDqF/rr09WKHKEJnU8GFRCUKHhbZYPRcXsedNDn//0AI00G21HV5h3pEgzJp 8QPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=h3wUSo6o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index fff07b2bd77b..518b232bfd3d 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -26,7 +26,7 @@ config POWER_RESET_AT91_POWEROFF config POWER_RESET_AT91_RESET tristate "Atmel AT91 reset driver" depends on ARCH_AT91 - default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports restart for Atmel AT91SAM9 and SAMA5 SoCs From patchwork Fri Jul 28 10:30:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127567 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp383503vqg; Fri, 28 Jul 2023 05:05:05 -0700 (PDT) X-Google-Smtp-Source: APBJJlH43mJ+o692pA0srNhG/Pm9R9U5BdVarhOGLsNNrBixS8K2ve4iEySoLGJu1YlIAlm1RyxM X-Received: by 2002:a19:e619:0:b0:4f8:5d0f:c779 with SMTP id d25-20020a19e619000000b004f85d0fc779mr1544949lfh.40.1690545904226; Fri, 28 Jul 2023 05:05:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690545904; cv=none; d=google.com; s=arc-20160816; b=zrFN1libWI1CxXcTtSN0pwVXProJ0oz9r98wwgFmn/PGwUQGrNyl5UnFEPQB+RLthO vZUWl7XCtnvJ07lKwdoyxIKVtuiOHCsQgJrLmTmAHV2VncVrmP+A7kt2MXYp1KrVwFYd QDtJUvolWncUYM+J/b6Zb/MRO5IraXj7dOwSI9mH+2ZBa4pozdXZBY19+VEeFrEul43Q mYrelJkGuuiLdhqItaly6NmzcsoLuySuXtfACNkbNMbb80sEANDqeHL2jEkwVcBbt7W1 4DfiY4X5ba+W8heE95s5/ptQOUjxeqnXmPcdg871AMLRA+VLwpq+649FjiYLaN8vtEVg j2+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=pxDSIRjKvoMWNHCSrUppbs/RSzeSvgUzWO3+42koQJY=; fh=bjc6H7KU9niG9Wjp5W3MhuG1w13PlQZZQSavf5aMebc=; b=Jf3uxzVKAzg6L+kSvFEqlW1MD9jygfMAM2D6T+7EMWhrEykdLKq64bGe7zEplGhl4r +fBTHB25xfpUjvInaVRYlPS1r7Cy4/aBfWuB8Wizbz8Zry0/cHV97GKQn1CbGOlXvGPX dV/GOiPSqC6eSQwD6xdD9v6/8/mKfhP1AO+skpu1Nd5/z69j+ZV5e09sPVhFDTvagQ/7 Qp76IZ2XgoIpmOvYG/8xwAMK6FZYMB4Oa5xle8Qi+/eyH3h+XQz0hrCri10DonwGaqb4 Oftv/RESJ2Z69ObhFxx2QR9lfdqJAk1DoiCzHBNSUjfhPPBkb7IYufJ1xFcqLq+jhxBS hF+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=WrCwuzPC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 518b232bfd3d..8571b592f257 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -34,7 +34,7 @@ config POWER_RESET_AT91_RESET config POWER_RESET_AT91_SAMA5D2_SHDWC tristate "Atmel AT91 SAMA5D2-Compatible shutdown controller driver" depends on ARCH_AT91 - default SOC_SAM9X60 || SOC_SAMA5 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports the alternate shutdown controller for some Atmel SAMA5 SoCs. It is present for example on SAMA5D2 SoC. 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id fi37-20020a056a0039a500b006826c8d5a31si977743pfb.21.2023.07.28.04.29.18; Fri, 28 Jul 2023 04:29:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=R0kdEcDY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235834AbjG1KeS (ORCPT + 99 others); Fri, 28 Jul 2023 06:34:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236082AbjG1KdK (ORCPT ); Fri, 28 Jul 2023 06:33:10 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62E404EE1 for ; Fri, 28 Jul 2023 03:31:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1690540277; x=1722076277; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=jCHL+Jd5EMSndMzWvV72eKzuixuestkfs6Y4izjdGGM=; b=R0kdEcDY1HTalcwk3xxdqsh/VZMOiNbKqtpyVgJobL4nRXMoR2vm1ALm yBx8vWalcjLZuWJhThx44xWHMi7g9d7IB9ztxYH1Of/dPQ5KV7mtsddyV 6rl171E05aEjhtjFD/y7RnyZiFujGo6e1nE01NGgsAAOcatI4/PSnR0y3 DTJtvtmPn/rdRNt0xklniq4tdrKCeE6UaDurnyxzdsNvPYD4FzZqbZ9+G aQeGNnJpsmz5G3P/ynWxN2LlCOW7F0F2zDL6CWExkCfSKxTOuap/SIb3U vsI9bCLUg5MkicJzprEu2bF2ZFRXRbMvwpzW9+9hZnx8vRYseXSXAc40q g==; X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="225813947" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jul 2023 03:30:50 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 28 Jul 2023 03:30:50 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 28 Jul 2023 03:30:47 -0700 From: Varshini Rajendran To: , , , , , CC: Subject: [PATCH v3 46/50] ARM: at91: Kconfig: add config flag for SAM9X7 SoC Date: Fri, 28 Jul 2023 16:00:42 +0530 Message-ID: <20230728103042.267646-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772663624877335057 X-GMAIL-MSGID: 1772663624877335057 Add config flag for sam9x7 SoC. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- arch/arm/mach-at91/Kconfig | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a8c022b4c053..49d38a3a47de 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -141,11 +141,28 @@ config SOC_SAM9X60 help Select this if you are using Microchip's SAM9X60 SoC +config SOC_SAM9X7 + bool "SAM9X7" + depends on ARCH_MULTI_V5 + select ATMEL_AIC5_IRQ + select ATMEL_PM if PM + select ATMEL_SDRAMC + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select MEMORY + select PINCTRL_AT91 + select SOC_SAM_V4_V5 + select SRAM if PM + help + Select this if you are using Microchip's SAM9X7 SoC + comment "Clocksource driver selection" config ATMEL_CLOCKSOURCE_PIT bool "Periodic Interval Timer (PIT) support" - depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAMA5 select ATMEL_PIT help @@ -155,7 +172,7 @@ config ATMEL_CLOCKSOURCE_PIT config ATMEL_CLOCKSOURCE_TCB bool "Timer Counter Blocks (TCB) support" - default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 select ATMEL_TCB_CLKSRC help Select this to get a high precision clocksource based on a @@ -166,7 +183,7 @@ config ATMEL_CLOCKSOURCE_TCB config MICROCHIP_CLOCKSOURCE_PIT64B bool "64-bit Periodic Interval Timer (PIT64B) support" - default SOC_SAM9X60 || SOC_SAMA7 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7 select MICROCHIP_PIT64B help Select this to get a high resolution clockevent (SAM9X60) or From patchwork Fri Jul 28 10:30:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127527 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp362870vqg; Fri, 28 Jul 2023 04:25:00 -0700 (PDT) X-Google-Smtp-Source: APBJJlFXcngHT85wIdL6R2JqEh+OD1uvF/qJPmgyuh4n4CTLNilaHnOROyu60ujLp1kjUk2BEPWY X-Received: by 2002:a17:90a:bb81:b0:268:5f1a:ede1 with SMTP id v1-20020a17090abb8100b002685f1aede1mr1122263pjr.36.1690543500014; Fri, 28 Jul 2023 04:25:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690543499; cv=none; d=google.com; s=arc-20160816; b=wBBTMdZImva6oo9r++nDeMtaU/saO9dIk9P9rIZ4ejhMgy0dpogvJ/Addp9ANr9keq Wbw5RYzvFMiQD329M/vl+C8e/48UHisxH5wZNAvIkRFzpQpCoCwGmp7xmjAwz7fxUenz IUvLAVLmiWQt34v6woB8VUGAXluocUgHqJVeg5jfoM4IcTcmQfTPPZPSMCpQbWeaq7xQ 5RaPfCtfUBOpoy43i4RGwfpMCazooaCdkzMapSwH1nJJRzRF7XppfbOR6Scb+vhOKExZ itZo+IE3k9hdvUK/fGMm8D4qikz+ir1IdF33xZOugY/9aCHxJ/1GdNqFU0iOb6Mra+UN RwqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:to:from:dkim-signature; bh=I5gZN5zPYbbTHryLKaStk51ZzkV4WJLGU5aVdio8SEE=; fh=F6mH++rIMIX4bYHyv0gEOXw2wZreWiXqMqMdH0rlINY=; b=IQ4dEyXiuhzJ5csMOiOFRqWVcrMi1CR2TFC1hDaQQ9SJEnDb9IuCIfDosfbDhvAaJC LYwLRZ6k1Oeh2NeijXA3zlGPZjqQsmFJJ9Ki07Skrd7NoGuq5DR3J8B+9efteeihVUKh vfdIVMXAraobPZgevKFsm7T6WyMxx0L2gLv/XrkCgk/beHKlQ+qKPJsvXOtlnRqNjMsR VYFZkFz0doPjbW93cCZ+RCibT7rrZAEoM2MHJs+MHRFtVdW2rY87tXtrbj3be+xcQadD 4VpB89fekVJ1609Ir4ZCOe4nbMsNb4i0Tu80ZYs1/C5kkaztcQSfw37jzF9wSN6teRps ANdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=1FGUear4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- arch/arm/configs/at91_dt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 8cc602853cc5..342ceeab5aaa 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_AT91=y CONFIG_SOC_AT91RM9200=y CONFIG_SOC_AT91SAM9=y CONFIG_SOC_SAM9X60=y +CONFIG_SOC_SAM9X7=y # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set CONFIG_AEABI=y CONFIG_UACCESS_WITH_MEMCPY=y From patchwork Fri Jul 28 10:30:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127578 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp389510vqg; Fri, 28 Jul 2023 05:13:55 -0700 (PDT) X-Google-Smtp-Source: APBJJlEEUILBLIx+n6xQPGch4/jU3InMcbKrO+mUwkRuBZNTRjEe6ZXeNcplaB6khKLeOgb0IcVp X-Received: by 2002:a17:90a:cf93:b0:267:f2f4:feb1 with SMTP id i19-20020a17090acf9300b00267f2f4feb1mr1121251pju.28.1690546434794; Fri, 28 Jul 2023 05:13:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690546434; cv=none; d=google.com; s=arc-20160816; b=eCoQgmWyVecdIaRn0jrse9W1maRPjG18MT29KXdDkYOZmqRfJ0Z22EnU0Klo9FgG8F AHDQFZPhk7QLdB3lv0uk9Rrsz3oHC9/GMzTMRdHC66IZzhB76CcmVVjlFBB/fUCK0jV4 ly61aDXqcHrGI0MUwESR++Y0xhMIydiilAZQRS32D3XNcIa8mtExqG7AoFN44aYD7H4r L0KixtjcSK8bsVkqMEMbZOKPUUJT3CSZVGEEa2iyi2ONQBdFkzqy7nPXY4EkoD23Kgfl o4TjS4juAB5KEdQQxvQps5CA1PowUDZOAUkDyBI1M09BrN+HE0Zh1MwthPQZTEq8oUF4 vtAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:to:from:dkim-signature; bh=c2MlEuUWEOo9XsveiXIjNDzVAKkmfG9EyiWZKlxOSLo=; fh=86+ZPKM115X4iGF9sTGDEieV7nLOtWXscdpqfUVNPR0=; b=fLrFD1mxvxxeJV1p02ZUy8k1I80rkG16wENMpknFAgjGat1C2hCgkpWkV1YVVrvK4l O1vEymkIKILT9Wn7NqKSVxbBb6wABPUD1ycDon1puXAOzyJACGzUPvERpB5N4zOGWEf6 3KUJezgPPqG+k3NGUVkh2q8/tAmcmDowYqb1p3x4d7PndVmpEX5+BY7t4AaU4skvgj72 NkyV/SMZ4DTBCpGZY0h4UP/Y68vuSs9Mhzt1JUSbp42YB0BGOZDlkMtxUFvls9pKOO97 i7tdjVDcEEQQL4s02dnEhuKO4Q1YggLL9LUlSs5ZPTlfwmCErWB30chMNhwvWTILY8F/ 2G8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=bsE8M23O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ob13-20020a17090b390d00b002675d988010si3137917pjb.91.2023.07.28.05.13.39; Fri, 28 Jul 2023 05:13:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=bsE8M23O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235942AbjG1Key (ORCPT + 99 others); Fri, 28 Jul 2023 06:34:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235929AbjG1Ke3 (ORCPT ); Fri, 28 Jul 2023 06:34:29 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EBDE44A0; Fri, 28 Jul 2023 03:32:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1690540325; x=1722076325; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=2Y9F/k/W6RU22AsxZ0osCWu7qd8w+YqRH3Au/xgAwEE=; b=bsE8M23OT4lQPiyomiCgqBluHzg7zUx7oFsfoX7LXwiG1gL+KfupQv7D w9bhCQxnpq5LVyXJqWSjfy6H4pF5wOqe58jzfwFxnKr4BMs4GDQXszawD wkcat/ECEQp3n1F/zhbYjFHJI/1uKe1X8UvpRL6ZLDhdd0e4cdvPcxXjS y1VN7XnrkcSHx0B/lTZ1jGGj5ZYOa7znXQHEu3QhYzS9h2a3CFfVFHxAL rwR8QB2w0woq6Zs87kyhEgmBYCuX39+inHgeFeTgo/FaSaikYbmbh+R9b 78ZIpBsSFe2qNMwiQqXK7LpD9wrgsv4gEeT18dIX/4TajchnZNGUJqr9r g==; X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="238401858" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jul 2023 03:31:07 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 28 Jul 2023 03:31:04 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 28 Jul 2023 03:31:01 -0700 From: Varshini Rajendran To: , , , , , , Subject: [PATCH v3 48/50] ARM: dts: at91: sam9x7: add device tree for SoC Date: Fri, 28 Jul 2023 16:00:59 +0530 Message-ID: <20230728103059.267743-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772666418496781825 X-GMAIL-MSGID: 1772666418496781825 Add device tree file for SAM9X7 SoC family. Co-developed-by: Nicolas Ferre Signed-off-by: Nicolas Ferre Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 1238 +++++++++++++++++++++++ 1 file changed, 1238 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi new file mode 100644 index 000000000000..ee7f6dd14443 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -0,0 +1,1238 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Microchip SAM9X7 SoC"; + compatible = "microchip,sam9x7"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + clocks { + slow_xtal: clock-slowxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + main_xtal: clock-mainxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + sram: sram@300000 { + compatible = "mmio-sram"; + reg = <0x300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x300000 0x10000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usb0: gadget@500000 { + compatible = "microchip,sam9x7-udc", "microchip,sam9x60-udc"; + reg = <0x500000 0x100000>, + <0xf803c000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + clock-names = "pclk", "hclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + + ohci0: usb@600000 { + compatible = "microchip,sam9x7-ohci", "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x600000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + ehci0: usb@700000 { + compatible = "microchip,sam9x7-ehci", "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x700000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usb_clk", "ehci_clk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + + sdmmc0: mmc@80000000 { + compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg = <0x80000000 0x300>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 12>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + sdmmc1: mmc@90000000 { + compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg = <0x90000000 0x300>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flx4: flexcom@f0000000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0000000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0000000 0x800>; + status = "disabled"; + + uart4: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx5: flexcom@f0004000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0004000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0004000 0x800>; + status = "disabled"; + + uart5: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c5: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + dma0: dma-controller@f0008000 { + compatible = "microchip,sam9x7-dma", "atmel,sama5d4-dma"; + reg = <0xf0008000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + ssc: ssc@f0010000 { + compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names = "pclk"; + status = "disabled"; + }; + + i2s: i2s@f001c000 { + compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; + reg = <0xf001c000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + flx11: flexcom@f0020000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0020000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0020000 0x800>; + status = "disabled"; + + uart11: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c11: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx12: flexcom@f0024000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0024000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0024000 0x800>; + status = "disabled"; + + uart12: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c12: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + pit64b0: timer@f0028000 { + compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xf0028000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names = "pclk", "gclk"; + }; + + sha: crypto@f002c000 { + compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; + reg = <0xf002c000 0x100>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(34))>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "sha_clk"; + }; + + trng: rng@f0030000 { + compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng"; + reg = <0xf0030000 0x100>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + status = "disabled"; + }; + + aes: crypto@f0034000 { + compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; + reg = <0xf0034000 0x100>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(32))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(33))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names = "aes_clk"; + }; + + tdes: crypto@f0038000 { + compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; + reg = <0xf0038000 0x100>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(31))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "tdes_clk"; + }; + + classd: classd@f003c000 { + compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd"; + reg = <0xf003c000 0x100>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(35))>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + pit64b1: timer@f0040000 { + compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xf0040000 0x100>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names = "pclk", "gclk"; + }; + + can0: can@f8000000 { + compatible = "bosch,m_can"; + reg = <0xf8000000 0x100>, <0x300000 0x7800>; + reg-names = "m_can", "message_ram"; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0 + 68 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>; + assigned-clock-rates = <480000000>, <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@f8004000 { + compatible = "bosch,m_can"; + reg = <0xf8004000 0x100>, <0x300000 0xbc00>; + reg-names = "m_can", "message_ram"; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0 + 69 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>; + assigned-clock-rates = <480000000>, <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + tcb: timer@f8008000 { + compatible = "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd", "syscon"; + reg = <0xf8008000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>; + clock-names = "t0_clk", "gclk", "slow_clk"; + status = "disabled"; + }; + + flx6: flexcom@f8010000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8010000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8010000 0x800>; + status = "disabled"; + + uart6: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx7: flexcom@f8014000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8014000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8014000 0x800>; + status = "disabled"; + + uart7: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c7: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx8: flexcom@f8018000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8018000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8018000 0x800>; + status = "disabled"; + + uart8: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c8: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx0: flexcom@f801c000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf801c000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf801c000 0x800>; + status = "disabled"; + + uart0: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi0: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx1: flexcom@f8020000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8020000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8020000 0x800>; + status = "disabled"; + + uart1: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi1: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx2: flexcom@f8024000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8024000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8024000 0x800>; + status = "disabled"; + + uart2: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx3: flexcom@f8028000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8028000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8028000 0x800>; + status = "disabled"; + + uart3: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + gmac: ethernet@f802c000 { + compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem" ; + reg = <0xf802c000 0x1000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ + 60 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ + 61 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 2 */ + 62 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 3 */ + 63 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 4 */ + 64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>; + clock-names = "hclk", "pclk", "tx_clk", "tsu_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 67>; + status = "disabled"; + }; + + flx9: flexcom@f8040000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8040000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8040000 0x800>; + status = "disabled"; + + uart9: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c9: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx10: flexcom@f8044000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8044000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8044000 0x800>; + status = "disabled"; + + uart10: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c10: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + sfr: sfr@f8050000 { + compatible = "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon"; + reg = <0xf8050000 0x100>; + }; + + matrix: matrix@ffffde00 { + compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon"; + reg = <0xffffde00 0x200>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x300>, + <0xffffe600 0x100>; + }; + + mpddrc: mpddrc@ffffe800 { + compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; + reg = <0xffffe800 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "ddrck", "mpddr"; + }; + + smc: smc@ffffea00 { + compatible = "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x100>; + }; + + aic: interrupt-controller@fffff100 { + compatible = "microchip,sam9x7-aic"; + reg = <0xfffff100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + atmel,external-irqs = <31>; + }; + + dbgu: serial@fffff200 { + compatible = "microchip,sam9x7-dbgu", "microchip,sam9x7-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + atmel,usart-mode = ; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(28))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(29))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; + clock-names = "usart"; + status = "disabled"; + }; + + pinctrl: pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl", "simple-mfd"; + ranges = <0xfffff400 0xfffff400 0x800>; + + /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ + atmel,mux-mask = < + /* A B C D */ + 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ + 0x07ffffff 0x0805fe7f 0x01ff9f80 0x06078000 /* pioB */ + 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ + 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <26>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + }; + }; + + pmc: clock-controller@fffffc00 { + compatible = "microchip,sam9x7-pmc", "syscon"; + reg = <0xfffffc00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names = "td_slck", "md_slck", "main_xtal"; + }; + + reset_controller: reset-controller@fffffe00 { + compatible = "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k 0>; + }; + + power_management: power-management@fffffe10 { + compatible = "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + + rtt: rtc@fffffe20 { + compatible = "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt"; + reg = <0xfffffe20 0x20>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + }; + + clk32k: sckc@fffffe50 { + compatible = "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; + reg = <0xfffffe50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <1>; + }; + + gpbr: syscon@fffffe60 { + compatible = "microchip,sam9x7-gbpr", "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffe60 0x10>; + }; + + rtc: rtc@fffffea8 { + compatible = "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; + reg = <0xfffffea8 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + }; + + watchdog: watchdog@ffffff80 { + compatible = "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; + reg = <0xffffff80 0x24>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + status = "disabled"; + }; + }; +}; From patchwork Fri Jul 28 10:31:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127544 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp367334vqg; Fri, 28 Jul 2023 04:33:32 -0700 (PDT) X-Google-Smtp-Source: APBJJlFdpU+wjwHA+SbC6IOPDBYzu3M2BPypovATbpwWydhrP4VQckAr1ej6gTAiX9Bh+KoqfNar X-Received: by 2002:a17:903:11d2:b0:1b8:7e53:704 with SMTP id q18-20020a17090311d200b001b87e530704mr1517008plh.27.1690544012614; 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index dfb8fd089197..15b11feae46a 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -99,6 +99,12 @@ properties: - const: microchip,sam9x60 - const: atmel,at91sam9 + - description: Microchip SAM9X7 Evaluation Boards + items: + - const: microchip,sam9x75-curiosity + - const: microchip,sam9x7 + - const: atmel,at91sam9 + - description: Nattis v2 board with Natte v2 power board items: - const: axentia,nattis-2 From patchwork Fri Jul 28 10:31:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 127521 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp357720vqg; Fri, 28 Jul 2023 04:14:22 -0700 (PDT) X-Google-Smtp-Source: APBJJlFVfRKyIau0X9ywZiaVpHgOFdl/0yHJHPuk7FCYwz/BkaBWxiMmGswdY8Pc7MWPtgJS6TiM X-Received: by 2002:a2e:8545:0:b0:2b6:d7d1:95bf with SMTP id u5-20020a2e8545000000b002b6d7d195bfmr1616547ljj.9.1690542862145; Fri, 28 Jul 2023 04:14:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690542862; cv=none; d=google.com; s=arc-20160816; b=JmCcrFdM4pwI+8P/aABG8eJlAPnokmqlE1di8pp5M2C71Jtg73d02WW/JXS0F7miVD RSlC6CpUNI44y8vBrEsG4nm+RSW6BRX3P9P2517AuH3NkxDBsGg2U2RMhOa1haGBzkEo S+xgX80xmZQGQ7DjsrdPN9ompv6+PPKL5GA0AQOSEAIos6eVfTvbrWAtBkCowSvGMU17 9/rmFCuTwDKB3DZqtgUvML4sjCPAb1pZR7KY3dRMBbAa1jUFbfcyfPJL1srvRxlJC/Le z3Jviy1Li0HG4dK9h+50EA4exmlAsW64HF6Pn5/ttinuDOEzXv3YPqu1FCgmHcLzhoSY 8L4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:to:from:dkim-signature; bh=gAgRmRVFwq7DZzjfaqkV05pRUenMEuw9IGzlF7/setM=; fh=5gb9YgyyEWo0ji332XyQ4AP2uefTSkIPtFBHWjFgufE=; b=qKGABJM+o8H60Pv41cLm4aDATO4JXlmFVQGiNPtfxqN9ottAsvqRm5KoqqPBkEW0qE XwLZecIxRBmQ1E8Zutg/UNHCIX+a7tJ2rRyObYTDKNpsoqTKKPyD3nJdrlbqpTp47IVd i7zKUREiT+uHCcafLJ3sNMkx6mVbmGUG+yoZTjDzK9aQpn6o7Gidl6SiwMBLTJFzexlL 4KVpxSuk8VX3Mynq2CA5y44UmCjaNYNxTpTu9+REsKr5dcX97YR+Efw1ci6lVyKJzSzr uqlGlve++WDpyI5GApgNR+3uvEFnTxEfSxicyvMJyTBovc4sL34hqXHrKpHuler5JD1P Dbiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="c3xyDGq/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/Makefile | 5 + .../dts/microchip/at91-sam9x75_curiosity.dts | 311 ++++++++++++++++++ 2 files changed, 316 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile index 0f5193d05a31..f3d604c30325 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -10,6 +10,7 @@ DTC_FLAGS_at91-sama5d3_eds := -@ DTC_FLAGS_at91-sama5d3_xplained := -@ DTC_FLAGS_at91-sama5d4_xplained := -@ DTC_FLAGS_at91-sama7g5ek := -@ +DTC_FLAGS_at91-sam9x75_curiosity := -@ dtb-$(CONFIG_SOC_AT91RM9200) += \ at91rm9200ek.dtb \ mpa1600.dtb @@ -61,6 +62,10 @@ dtb-$(CONFIG_SOC_SAM9X60) += \ at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb # Enables support for device-tree overlays +DTC_FLAGS_at91-sam9x75_curiosity := -@ +dtb-$(CONFIG_SOC_SAM9X7) += \ + at91-sam9x75_curiosity.dtb +# Enables support for device-tree overlays DTC_FLAGS_at91-sama5d27_som1_ek := -@ DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ DTC_FLAGS_at91-sama5d2_icp := -@ diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts new file mode 100644 index 000000000000..a9ecb02a9f3c --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ +/dts-v1/; +#include "sam9x7.dtsi" +#include + +/ { + model = "Microchip SAM9X75 Curiosity"; + compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9"; + + aliases { + i2c0 = &i2c6; + i2c1 = &i2c7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + clock-slowxtal { + clock-frequency = <32768>; + }; + + clock-mainxtal { + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-user { + label = "USER"; + gpios = <&pioC 9 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + + led-0 { + label = "red"; + gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "green"; + gpios = <&pioC 21 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "blue"; + gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x10000000>; + }; +}; + +&dbgu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&flx6 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c6 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + + regulators { + vdd_3v3: VDD-IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-mode = <4>; + }; + }; + + vddioddr: VDD-DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1283000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + }; + + vddcore: VDD-CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1210000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-mode = <4>; + }; + }; + + vddcpu: VDD-OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-ramp-delay = <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-mode = <4>; + }; + }; + + vldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + }; + }; + }; +}; + +&ohci0 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioC 27 GPIO_ACTIVE_HIGH + &pioB 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&pinctrl { + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = ; + }; + }; + + flexcom { + pinctrl_flx6_default: flx6-twi { + atmel,pins = + ; + }; + }; + + gpio-keys { + pinctrl_key_gpio_default: key-gpio-default { + atmel,pins = ; + }; + }; + + leds { + pinctrl_led_gpio_default: led-gpio-default { + atmel,pins = ; + }; + }; + + ohci0 { + pinctrl_usb_default: usb-default { + atmel,pins = ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0 { + atmel,pins = + ; /* PA5 DAT3 periph A with pullup */ + }; + }; + + usb0 { + pinctrl_usba_vbus: usba-vbus { + atmel,pins = ; + }; + }; +}; /* pinctrl */ + +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + +&sdmmc0 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>; + disable-wp; + status = "okay"; +}; + +&power_management { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&trng { + status = "okay"; +}; + +&usb0 { + atmel,vbus-gpio = <&pioC 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&watchdog { + status = "okay"; +};