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[2620:137:e000::1:20]) by mx.google.com with ESMTP id jg26-20020a170907971a00b0078266dc4b8csi13173342ejc.719.2022.11.01.09.32.36; Tue, 01 Nov 2022 09:33:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eHDpHWaO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230335AbiKAQbm (ORCPT + 99 others); Tue, 1 Nov 2022 12:31:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230178AbiKAQb2 (ORCPT ); Tue, 1 Nov 2022 12:31:28 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E41B1CFDE for ; Tue, 1 Nov 2022 09:31:23 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id a11-20020a05600c2d4b00b003cf6f5fd9f1so4036194wmg.2 for ; Tue, 01 Nov 2022 09:31:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=01HzRHVXEtsQePy5MUh5KjUIoIybwQ7UjUNynMGQ3Eo=; b=eHDpHWaO/fVWvGoR02QYa/dnPpxM+uxWx2BYSazW83Evi65Ef2BbZd9m2eE5it9dEu OU1VdcbKQUUzJ0BKoBwRi+pOjhPue+P3bVelRG/5T/D2WI62SArxpLX3vMhVCQoNeLKV yvRjVRowzkxPbsrfYZgaUj8WexOh1WVfnNs3VdPW8ttwsRKTElFlyBItG6ZbSIw78/vq jUI0F32HqBU07ilmxkup2osEuxYDImJdi/6DpT+vLmehtywyP32N/yLUvoiRnGbWGoya JXOagZAGC5j5XHaUT2QWMNx8v8fHTdPo9Qn/5hLlL9nI8xXAANBVlzOTHsOEAsyldHcO A+qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=01HzRHVXEtsQePy5MUh5KjUIoIybwQ7UjUNynMGQ3Eo=; b=K3bm5Sr+vdlzx671qvAMpwOp7kdt3Mu7ruiZT4rXw0Qbp/5VO3Ludm0zcW8dhPAfTd Zg80S5jxVK97L0fNUsjaN0z8Y3isciTR7A2ZUqMjLKdj6yLC/D3bJe1ro6IImCegh8ai orKzTOWMneAVceUjJUN3qEeWYgG0PsJYnYu2z6JLqJLiQDQbvmPAr2q3HTT4HvARnb1J RObRQ5V4cy3/vYD3bjiHvNB2AY5E86jc05UlY7Bz9xi39d9ujnDHgnwyBZftG8RiwjFr AsbZFrFhrGVyo9/MWCXn7nGAqo8pBRnivZqrve1kcrG/7NlTvxxevfFIkxgZqKRBPkc1 MwhQ== X-Gm-Message-State: ACrzQf1J30vHMptyc0trGqpHL0uKWsUl/96Y6OCg2YA/P9+1QOVUoXun bImvggYC5P6FyXrK3NN1nLS2jw== X-Received: by 2002:a05:600c:3107:b0:3c6:ff0a:c42 with SMTP id g7-20020a05600c310700b003c6ff0a0c42mr22177330wmo.141.1667320282012; Tue, 01 Nov 2022 09:31:22 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:e844:18b6:fc5:bbc9]) by smtp.gmail.com with ESMTPSA id bu15-20020a056000078f00b0022ac1be009esm8339844wrb.16.2022.11.01.09.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 09:31:21 -0700 (PDT) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v5 01/14] coresight: trace-id: Add API to dynamically assign Trace ID values Date: Tue, 1 Nov 2022 16:30:50 +0000 Message-Id: <20221101163103.17921-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221101163103.17921-1-mike.leach@linaro.org> References: <20221101163103.17921-1-mike.leach@linaro.org> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748312138572359213?= X-GMAIL-MSGID: =?utf-8?q?1748312138572359213?= The existing mechanism to assign Trace ID values to sources is limited and does not scale for larger multicore / multi trace source systems. The API introduces functions that reserve IDs based on availabilty represented by a coresight_trace_id_map structure. This records the used and free IDs in a bitmap. CPU bound sources such as ETMs use the coresight_trace_id_get_cpu_id coresight_trace_id_put_cpu_id pair of functions. The API will record the ID associated with the CPU. This ensures that the same ID will be re-used while perf events are active on the CPU. The put_cpu_id function will pend release of the ID until all perf cs_etm sessions are complete. For backward compatibility the functions will attempt to use the same CPU IDs as the legacy system would have used if these are still available. Non-cpu sources, such as the STM can use coresight_trace_id_get_system_id / coresight_trace_id_put_system_id. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 4 + .../hwtracing/coresight/coresight-trace-id.c | 225 ++++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 154 ++++++++++++ include/linux/coresight-pmu.h | 10 + 5 files changed, 394 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index b6c4a48140ec..329a0c704b87 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \ coresight-cfg-preload.o coresight-cfg-afdo.o \ - coresight-syscfg-configfs.o + coresight-syscfg-configfs.o coresight-trace-id.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index f3068175ca9d..554a18039e10 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -22,6 +22,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); @@ -1804,6 +1805,9 @@ static int __init coresight_init(void) if (ret) goto exit_bus_unregister; + /* initialise the trace ID allocator */ + coresight_trace_id_init(); + /* initialise the coresight syscfg API */ ret = cscfg_init(); if (!ret) diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c new file mode 100644 index 000000000000..8e05a244c9d6 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Linaro Limited, All rights reserved. + * Author: Mike Leach + */ +#include +#include +#include +#include + +#include "coresight-trace-id.h" + +/* default trace ID map. Used for systems that do not require per sink mappings */ +static struct coresight_trace_id_map id_map_default; + +/* maintain a record of the current mapping of cpu IDs and pending releases per cpu */ +static DEFINE_PER_CPU(atomic_t, cpu_id); +static DECLARE_BITMAP(cpu_id_release_pending, NR_CPUS); + +/* perf session active counter */ +static atomic_t perf_cs_etm_session_active = ATOMIC_INIT(0); + +/* lock to protect id_map and cpu data */ +static DEFINE_SPINLOCK(id_map_lock); + +/* + * allocate new ID and set in use + * if @preferred_id is a valid id then try to use that value if available. + */ +static int coresight_trace_id_alloc_new_id(struct coresight_trace_id_map *id_map, + int preferred_id) +{ + int id; + + /* for backwards compatibility reasons, cpu Ids may have a preferred value */ + if (IS_VALID_ID(preferred_id) && !test_bit(preferred_id, id_map->used_ids)) + id = preferred_id; + else { + /* skip reserved bit 0, look from bit 1 to CORESIGHT_TRACE_ID_RES_TOP */ + id = find_next_zero_bit(id_map->used_ids, 1, CORESIGHT_TRACE_ID_RES_TOP); + if (id >= CORESIGHT_TRACE_ID_RES_TOP) + return -EINVAL; + } + + /* mark as used */ + set_bit(id, id_map->used_ids); + return id; +} + +static void coresight_trace_id_free(int id, struct coresight_trace_id_map *id_map) +{ + if (WARN(!IS_VALID_ID(id), "%s: Invalid Trace ID %d\n", __func__, id)) + return; + if (WARN(!test_bit(id, id_map->used_ids), + "%s: Freeing unused ID %d\n", __func__, id)) + return; + clear_bit(id, id_map->used_ids); +} + +static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace_id_map *id_map) +{ + if (WARN(!IS_VALID_ID(id), "%s: Invalid Trace ID %d\n", __func__, id)) + return; + set_bit(id, id_map->pend_rel_ids); +} + +/* release all pending IDs for all current maps & clear CPU associations */ +static void coresight_trace_id_release_all_pending(void) +{ + struct coresight_trace_id_map *id_map = &id_map_default; + unsigned long flags; + int cpu, bit; + + spin_lock_irqsave(&id_map_lock, flags); + for_each_set_bit(bit, id_map->pend_rel_ids, CORESIGHT_TRACE_ID_RES_TOP) { + clear_bit(bit, id_map->used_ids); + clear_bit(bit, id_map->pend_rel_ids); + } + for_each_set_bit(cpu, cpu_id_release_pending, NR_CPUS) { + atomic_set(&per_cpu(cpu_id, cpu), 0); + clear_bit(cpu, cpu_id_release_pending); + } + spin_unlock_irqrestore(&id_map_lock, flags); +} + +static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + + /* check for existing allocation for this CPU */ + id = atomic_read(&per_cpu(cpu_id, cpu)); + if (id) + goto get_cpu_id_clr_pend; + + /* + * Find a new ID. + * + * Use legacy values where possible in the dynamic trace ID allocator to + * allow older tools to continue working if they are not upgraded at the same + * time as the kernel drivers. + * + * If the generated legacy ID is invalid, or not available then the next + * available dynamic ID will be used. + */ + id = coresight_trace_id_alloc_new_id(id_map, CORESIGHT_LEGACY_CPU_TRACE_ID(cpu)); + if (!IS_VALID_ID(id)) + goto get_cpu_id_out_unlock; + + /* allocate the new id to the cpu */ + atomic_set(&per_cpu(cpu_id, cpu), id); + +get_cpu_id_clr_pend: + /* we are (re)using this ID - so ensure it is not marked for release */ + clear_bit(cpu, cpu_id_release_pending); + clear_bit(id, id_map->pend_rel_ids); + +get_cpu_id_out_unlock: + spin_unlock_irqrestore(&id_map_lock, flags); + + return id; +} + +static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + /* check for existing allocation for this CPU */ + id = atomic_read(&per_cpu(cpu_id, cpu)); + if (!id) + return; + + spin_lock_irqsave(&id_map_lock, flags); + + if (atomic_read(&perf_cs_etm_session_active)) { + /* set release at pending if perf still active */ + coresight_trace_id_set_pend_rel(id, id_map); + set_bit(cpu, cpu_id_release_pending); + } else { + /* otherwise clear id */ + coresight_trace_id_free(id, id_map); + atomic_set(&per_cpu(cpu_id, cpu), 0); + } + + spin_unlock_irqrestore(&id_map_lock, flags); +} + +static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + id = coresight_trace_id_alloc_new_id(id_map, 0); + spin_unlock_irqrestore(&id_map_lock, flags); + + return id; +} + +static void coresight_trace_id_map_put_system_id(struct coresight_trace_id_map *id_map, int id) +{ + unsigned long flags; + + spin_lock_irqsave(&id_map_lock, flags); + coresight_trace_id_free(id, id_map); + spin_unlock_irqrestore(&id_map_lock, flags); +} + +/* API functions */ + +int coresight_trace_id_get_cpu_id(int cpu) +{ + return coresight_trace_id_map_get_cpu_id(cpu, &id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_cpu_id); + +void coresight_trace_id_put_cpu_id(int cpu) +{ + coresight_trace_id_map_put_cpu_id(cpu, &id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_cpu_id); + +int coresight_trace_id_read_cpu_id(int cpu) +{ + return atomic_read(&per_cpu(cpu_id, cpu)); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_read_cpu_id); + +int coresight_trace_id_get_system_id(void) +{ + return coresight_trace_id_map_get_system_id(&id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_system_id); + +void coresight_trace_id_put_system_id(int id) +{ + coresight_trace_id_map_put_system_id(&id_map_default, id); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id); + +void coresight_trace_id_perf_start(void) +{ + atomic_inc(&perf_cs_etm_session_active); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start); + +void coresight_trace_id_perf_stop(void) +{ + if (!atomic_dec_return(&perf_cs_etm_session_active)) + coresight_trace_id_release_all_pending(); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop); + +void coresight_trace_id_init(void) +{ + int cpu; + + /* initialise the atomic trace ID values */ + for_each_possible_cpu(cpu) + atomic_set(&per_cpu(cpu_id, cpu), 0); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_init); diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwtracing/coresight/coresight-trace-id.h new file mode 100644 index 000000000000..1d27977346b3 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright(C) 2022 Linaro Limited. All rights reserved. + * Author: Mike Leach + */ + +#ifndef _CORESIGHT_TRACE_ID_H +#define _CORESIGHT_TRACE_ID_H + +/* + * Coresight trace ID allocation API + * + * With multi cpu systems, and more additional trace sources a scalable + * trace ID reservation system is required. + * + * The system will allocate Ids on a demand basis, and allow them to be + * released when done. + * + * In order to ensure that a consistent cpu / ID matching is maintained + * throughout a perf cs_etm event session - a session in progress flag will + * be maintained, and released IDs not cleared until the perf session is + * complete. This allows the same CPU to be re-allocated its prior ID. + * + * + * Trace ID maps will be created and initialised to prevent architecturally + * reserved IDs from being allocated. + * + * API permits multiple maps to be maintained - for large systems where + * different sets of cpus trace into different independent sinks. + */ + +#include +#include + + +/* architecturally we have 128 IDs some of which are reserved */ +#define CORESIGHT_TRACE_IDS_MAX 128 + +/* ID 0 is reserved */ +#define CORESIGHT_TRACE_ID_RES_0 0 + +/* ID 0x70 onwards are reserved */ +#define CORESIGHT_TRACE_ID_RES_TOP 0x70 + +/* check an ID is in the valid range */ +#define IS_VALID_ID(id) \ + ((id > CORESIGHT_TRACE_ID_RES_0) && (id < CORESIGHT_TRACE_ID_RES_TOP)) + +/** + * Trace ID map. + * + * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs. + * Initialised so that the reserved IDs are permanently marked as in use. + * @pend_rel_ids: CPU IDs that have been released by the trace source but not yet marked + * as available, to allow re-allocation to the same CPU during a perf session. + */ +struct coresight_trace_id_map { + DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); + DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); +}; + +/* Allocate and release IDs for a single default trace ID map */ + +/** + * Read and optionally allocate a CoreSight trace ID and associate with a CPU. + * + * Function will read the current trace ID for the associated CPU, + * allocating an new ID if one is not currently allocated. + * + * Numeric ID values allocated use legacy allocation algorithm if possible, + * otherwise any available ID is used. + * + * @cpu: The CPU index to allocate for. + * + * return: CoreSight trace ID or -EINVAL if allocation impossible. + */ +int coresight_trace_id_get_cpu_id(int cpu); + +/** + * Release an allocated trace ID associated with the CPU. + * + * This will release the CoreSight trace ID associated with the CPU, + * unless a perf session is in operation. + * + * If a perf session is in operation then the ID will be marked as pending release. + * + * @cpu: The CPU index to release the associated trace ID. + */ +void coresight_trace_id_put_cpu_id(int cpu); + +/** + * Read the current allocated CoreSight Trace ID value for the CPU. + * + * Fast read of the current value that does not allocate if no ID allocated for the CPU. + + * Used in perf context where it is known that the value for the CPU will not be changing, + * when perf starts and event on a core and outputs the Trace ID for the CPU + * as a packet in the data file. IDs cannot change during a perf session. + * + * This function does not take the lock protecting the ID lists, avoiding locking dependency + * issues with perf locks. + * + * @cpu: The CPU index to read. + * + * return: current value, will be 0 if unallocated. + */ +int coresight_trace_id_read_cpu_id(int cpu); + +/** + * Allocate a CoreSight trace ID for a system component. + * + * Unconditionally allocates as Trace ID, without associating the ID with any CPU. + * + * Used to allocate IDs for system trace sources such as STM. + * + * return: Trace ID or -EINVAL if allocation is impossible. + */ +int coresight_trace_id_get_system_id(void); + +/** + * Release an allocated system trace ID. + * + * Unconditionally release a trace ID previously allocated to a system component. + * + * @id: value of trace ID allocated. + */ +void coresight_trace_id_put_system_id(int id); + +/* notifiers for perf session start and stop */ + +/** + * Notify the Trace ID allocator that a perf session is starting. + * + * Increase the perf session reference count - called by perf when setting up + * a trace event. + * + * This reference count is used by the ID allocator to ensure that trace IDs associated with + * a CPU cannot change or be released during a perf session. + */ +void coresight_trace_id_perf_start(void); + +/** + * Notify the ID allocator that a perf session is stopping. + * + * Decrease the perf session reference count. + * if this causes the count to go to zero, then all Trace IDs marked as pending release + * will be released. + */ +void coresight_trace_id_perf_stop(void); + +/* initialisation */ +void coresight_trace_id_init(void); + +#endif /* _CORESIGHT_TRACE_ID_H */ diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 6c2fd6cc5a98..ffff4e6277e5 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -10,6 +10,16 @@ #define CORESIGHT_ETM_PMU_NAME "cs_etm" #define CORESIGHT_ETM_PMU_SEED 0x10 +/* + * The legacy Trace ID system based on fixed calculation from the cpu + * number. This has been replaced by drivers using a dynamic allocation + * system - but need to retain the legacy algorithm for backward comparibility + * in certain situations:- + * a) new perf running on older systems that generate the legacy mapping + * b) older tools that may not update at the same time as the kernel. + */ +#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. 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Tue, 01 Nov 2022 09:31:23 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:e844:18b6:fc5:bbc9]) by smtp.gmail.com with ESMTPSA id bu15-20020a056000078f00b0022ac1be009esm8339844wrb.16.2022.11.01.09.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 09:31:22 -0700 (PDT) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v5 02/14] coresight: Remove obsolete Trace ID unniqueness checks Date: Tue, 1 Nov 2022 16:30:51 +0000 Message-Id: <20221101163103.17921-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221101163103.17921-1-mike.leach@linaro.org> References: <20221101163103.17921-1-mike.leach@linaro.org> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748312130086483996?= X-GMAIL-MSGID: =?utf-8?q?1748312130086483996?= The checks for sources to have unique IDs has been removed - this is now guaranteed by the ID allocation mechanisms, and inappropriate where multiple ID maps are in use in larger systems Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-core.c | 45 -------------------- 1 file changed, 45 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 554a18039e10..45828564f0c8 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -113,45 +113,6 @@ struct coresight_device *coresight_get_percpu_sink(int cpu) } EXPORT_SYMBOL_GPL(coresight_get_percpu_sink); -static int coresight_id_match(struct device *dev, void *data) -{ - int trace_id, i_trace_id; - struct coresight_device *csdev, *i_csdev; - - csdev = data; - i_csdev = to_coresight_device(dev); - - /* - * No need to care about oneself and components that are not - * sources or not enabled - */ - if (i_csdev == csdev || !i_csdev->enable || - i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE) - return 0; - - /* Get the source ID for both components */ - trace_id = source_ops(csdev)->trace_id(csdev); - i_trace_id = source_ops(i_csdev)->trace_id(i_csdev); - - /* All you need is one */ - if (trace_id == i_trace_id) - return 1; - - return 0; -} - -static int coresight_source_is_unique(struct coresight_device *csdev) -{ - int trace_id = source_ops(csdev)->trace_id(csdev); - - /* this shouldn't happen */ - if (trace_id < 0) - return 0; - - return !bus_for_each_dev(&coresight_bustype, NULL, - csdev, coresight_id_match); -} - static int coresight_find_link_inport(struct coresight_device *csdev, struct coresight_device *parent) { @@ -460,12 +421,6 @@ static int coresight_enable_source(struct coresight_device *csdev, u32 mode) { int ret; - if (!coresight_source_is_unique(csdev)) { - dev_warn(&csdev->dev, "traceID %d not unique\n", - source_ops(csdev)->trace_id(csdev)); - return -EINVAL; - } - if (!csdev->enable) { if (source_ops(csdev)->enable) { ret = coresight_control_assoc_ectdev(csdev, true); From patchwork Tue Nov 1 16:30:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13772 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076106wru; Tue, 1 Nov 2022 09:33:50 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5IqWGDnUhfhy3Md8CsMgjuSEZQd9oM8s3OnH3mnHN18gaBOgw7PxaQeIBPdLfLf+HwoJ2g X-Received: by 2002:aa7:d80a:0:b0:462:2c1c:8716 with SMTP id v10-20020aa7d80a000000b004622c1c8716mr20312117edq.185.1667320430172; Tue, 01 Nov 2022 09:33:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320430; cv=none; d=google.com; s=arc-20160816; b=wbFo9e/FaUuIMeRroU2OQy1GRgtEK31DHABr9KfKDmIRwdDaxKhsdIPRQepoOXG6Px 2qPxh8nq2I7uDBzGHYqtfxi/qkqdKqQVizF+YR/OYhdlaKVVt3JCoxchjJe7itOg9sKG O/Z+wmD2lMTU5+31Mg/q7+O99o546l24nCBenJRA6jRLb2RHz/peN85se0OuIH54NWC+ ymVr0LUk0e7EEtamU12dgxyfTimA/LCVsaWCdaC3hLahYV5hfZAYSKKBZ+8PkqKIGaKO UbCwZIQxrn2Sya9TKUaCWS0GIV8FSVkMVejauPvh4nauc/xYtLLHWza2Q9mcjU7SZZa9 ntRQ== ARC-Message-Signature: i=1; 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Adds in notifier calls to the trace ID allocator that perf events are starting and stopping. This ensures that Trace IDs associated with CPUs remain the same throughout the perf session, and are only released when all perf sessions are complete. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm-perf.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 43bbd5dc3d3b..6166f716a6ac 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -22,6 +22,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static struct pmu etm_pmu; static bool etm_perf_up; @@ -228,8 +229,12 @@ static void free_event_data(struct work_struct *work) if (!(IS_ERR_OR_NULL(*ppath))) coresight_release_path(*ppath); *ppath = NULL; + coresight_trace_id_put_cpu_id(cpu); } + /* mark perf event as done for trace id allocator */ + coresight_trace_id_perf_stop(); + free_percpu(event_data->path); kfree(event_data); } @@ -300,6 +305,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, { u32 id, cfg_hash; int cpu = event->cpu; + int trace_id; cpumask_t *mask; struct coresight_device *sink = NULL; struct coresight_device *user_sink = NULL, *last_sink = NULL; @@ -316,6 +322,9 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, sink = user_sink = coresight_get_sink_by_id(id); } + /* tell the trace ID allocator that a perf event is starting up */ + coresight_trace_id_perf_start(); + /* check if user wants a coresight configuration selected */ cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); if (cfg_hash) { @@ -388,6 +397,13 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, continue; } + /* ensure we can allocate a trace ID for this CPU */ + trace_id = coresight_trace_id_get_cpu_id(cpu); + if (!IS_VALID_ID(trace_id)) { + cpumask_clear_cpu(cpu, mask); + continue; + } + *etm_event_cpu_path_ptr(event_data, cpu) = path; } From patchwork Tue Nov 1 16:30:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13780 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076757wru; Tue, 1 Nov 2022 09:35:12 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4anfUtHX92Z308DnxPAYt2It9IkZu53f2OUa6iEqhCaenaJn+JbUVz3XLbK6Bf/Aovw4Mv X-Received: by 2002:a17:906:9bee:b0:7ad:c4a1:b8e4 with SMTP id de46-20020a1709069bee00b007adc4a1b8e4mr14568109ejc.283.1667320512112; Tue, 01 Nov 2022 09:35:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320512; cv=none; d=google.com; s=arc-20160816; b=B4FLbRqv9f7JqUe77PHNcelWsb0q5jCbzzg1ap1EENxekl+EQH1160R6Fh3GvzslXE UvwRhRTFDmmGBuSu9gtMP1NIf+Gj/NanHMY77R1pEMNkQQIDdccjZFlIJzeGqdheZXCO EqXcP5vRkDV/b8Nj+hd2JUqIGCfNESxNUt7os1wTALUXN7hMjYsF8PMardAk+r3FdY3W 5+dY9WV+Gd5/auiYyjv0NISjDt2aXIOeE7ttZf/Jk3eN/8v4XKf2vF0EZPgyWWltcsTm q2X0dBdSMQDQhhjt3diU9LRNoc50bVOPLRTeC7SvfbYa0NC5KI2aNytID+GvS1VvDZ6k wm8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Msiba57uIoQyW0yBXGfGPLCUUWKUrx8bYCzahjs4eQE=; b=qvhZEKFQ688qnbVf38c2eQEdmMwOPqapZ3i2EZUWFQpkYPlrz3u/bDWe0jOsbJKK8Y FoEk4BWyNbqQFWp00CnYGV2YAwdpfEp/7m1E68wvPzf7Uqnzu+maL2dN7k4zZEGgoTl7 EqibVbHO31eMF52p/1yzTcJ6tsQtipyijQyGQA6kTQxskHED0y+yPYoxFsk6K+k5LrZr yy0tJVRt5YdjDf5SVj+PmZQsJQklEAQu0Z+VadIH1u8sZrIxriM8qNyw9UyrzfEVqePM PlfyGj7Qj+C5XR9ElSWN/6jfr777JpPdZ6LDGVqF6NeaENQKEQe3k8/fRS00k7UwwoPH hrog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="xkyBzfZ/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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This uses the _system_id calls to allocate an ID on device poll, and release on device remove. The sysfs access to the STMTRACEIDR register has been changed from RW to RO. Having this value as writable is not appropriate for the new Trace ID scheme - and had potential to cause errors in the previous scheme if values clashed with other sources. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-stm.c | 41 +++++++-------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 463f449cfb79..6af1b996af6f 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -31,6 +31,7 @@ #include #include "coresight-priv.h" +#include "coresight-trace-id.h" #define STMDMASTARTR 0xc04 #define STMDMASTOPR 0xc08 @@ -615,24 +616,7 @@ static ssize_t traceid_show(struct device *dev, val = drvdata->traceid; return sprintf(buf, "%#lx\n", val); } - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; - struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; - - /* traceid field is 7bit wide on STM32 */ - drvdata->traceid = val & 0x7f; - return size; -} -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); static struct attribute *coresight_stm_attrs[] = { &dev_attr_hwevent_enable.attr, @@ -803,14 +787,6 @@ static void stm_init_default_data(struct stm_drvdata *drvdata) */ drvdata->stmsper = ~0x0; - /* - * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and - * anything equal to or higher than 0x70 is reserved. Since 0x00 is - * also reserved the STM trace ID needs to be higher than 0x00 and - * lowner than 0x10. - */ - drvdata->traceid = 0x1; - /* Set invariant transaction timing on all channels */ bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); } @@ -838,7 +814,7 @@ static void stm_init_generic_data(struct stm_drvdata *drvdata, static int stm_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; + int ret, trace_id; void __iomem *base; struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; @@ -922,12 +898,22 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) goto stm_unregister; } + trace_id = coresight_trace_id_get_system_id(); + if (trace_id < 0) { + ret = trace_id; + goto cs_unregister; + } + drvdata->traceid = (u8)trace_id; + pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); return 0; +cs_unregister: + coresight_unregister(drvdata->csdev); + stm_unregister: stm_unregister_device(&drvdata->stm); return ret; @@ -937,6 +923,7 @@ static void stm_remove(struct amba_device *adev) { struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + coresight_trace_id_put_system_id(drvdata->traceid); coresight_unregister(drvdata->csdev); stm_unregister_device(&drvdata->stm); From patchwork Tue Nov 1 16:30:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13773 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076121wru; Tue, 1 Nov 2022 09:33:51 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4bbAqcE1jKdSmkZt5v0U3m1ZgIgBjROcnMnkFKg9CGR3vlIN281NF1xsFMBXi/9H/yz2r+ X-Received: by 2002:a17:906:6a1a:b0:7a1:a9e5:7869 with SMTP id qw26-20020a1709066a1a00b007a1a9e57869mr19699476ejc.708.1667320431644; Tue, 01 Nov 2022 09:33:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320431; cv=none; d=google.com; s=arc-20160816; b=X87PVSgsarFHR+lFfF3AzxQiqls0Dwi8tEnqjGDcZwGUK00XxWYKly1REMrwJgIfoe 58OH8Afqv+qcOylalBX+fW/uRXZxplxErBlAtCveys8qRARq8ZMIcr3qR28mcoJz8beT TfLGz1/diz0Qud2Y6tqdM5zVjhVuIqRW9uhexUlHDG64L7SKJt5ji3ZoRJsLyfixJITs yFS1dG4acgKfJIZjwVMCHSZOEI0sOhU75Uq7UkKtoINh8ab2Ez9OcToSPvPjyZ5OYddL ZYh3FbvZhdVLCZZb5zrVaKFE9wwZr5zjE55Vd6DcCiTxF04smr/LvIlJKe12sEqnHnKT NUFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=jbkw4FiHpe9WvP+c1c+jQ4hmFyTe7g3DYVUX3geH+Ng=; b=HYKVuLORProejZSfdXhO/8V0/snvX+c50TT/wVB/PXCloeWADptymoHq7AKQWi46qU kDgOysQtyckBnOIP/MHArtV2zPGD2CSPKRudT0m8uwILIV9Of2YmK+G4HdtSH1pfkrBl +A9zrWnA/9xzIOZYv2k6/iRGPcn13tYt66KhP9AmL5C0zsTaOf/dde0f7wbULpr+ZUft 7rPvac9QS+69NaB1xBRv8XHBPxyJRyuLlm1U7qyoKjsZr9YR7Phd0xMcZVrHILqBf/T5 gD8fwPtV88i/7+3/PqX5BTsQnfZhHZA8blOK6T13HrevjTvO1ibNKZuqHbNb61gLUa4x mwYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XbUH4tpB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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For perf sessions, these will be allocated on enable, and released on disable. For sysfs sessions, these will be allocated on enable, but only released on reset. This allows the sysfs session to interrogate the Trace ID used after the session is over - maintaining functional consistency with the previous allocation scheme. The trace ID will also be allocated on read of the mgmt/trctraceid file. This ensures that if perf or sysfs read this before enabling trace, the value will be the one used for the trace session. Trace ID initialisation is removed from the _probe() function. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- .../coresight/coresight-etm4x-core.c | 70 +++++++++++++++++-- .../coresight/coresight-etm4x-sysfs.c | 27 ++++++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + 3 files changed, 90 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 80fefaba58ee..0e361d35c611 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -42,6 +42,7 @@ #include "coresight-etm4x-cfg.h" #include "coresight-self-hosted-trace.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static int boot_enable; module_param(boot_enable, int, 0444); @@ -234,6 +235,30 @@ static int etm4_trace_id(struct coresight_device *csdev) return drvdata->trcid; } +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) +{ + int trace_id; + + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + * The trace id function has its own lock + */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); + if (IS_VALID_ID(trace_id)) + drvdata->trcid = (u8)trace_id; + else + dev_err(&drvdata->csdev->dev, + "Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + return trace_id; +} + +void etm4_release_trace_id(struct etmv4_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu); +} + struct etm4_enable_arg { struct etmv4_drvdata *drvdata; int rc; @@ -717,7 +742,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, static int etm4_enable_perf(struct coresight_device *csdev, struct perf_event *event) { - int ret = 0; + int ret = 0, trace_id; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { @@ -729,6 +754,24 @@ static int etm4_enable_perf(struct coresight_device *csdev, ret = etm4_parse_event_config(csdev, event); if (ret) goto out; + + /* + * perf allocates cpu ids as part of _setup_aux() - device needs to use + * the allocated ID. This reads the current version without allocation. + * + * This does not use the trace id lock to prevent lock_dep issues + * with perf locks - we know the ID cannot change until perf shuts down + * the session + */ + trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu); + if (!IS_VALID_ID(trace_id)) { + dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + ret = -EINVAL; + goto out; + } + drvdata->trcid = (u8)trace_id; + /* And enable it */ ret = etm4_enable_hw(drvdata); @@ -753,6 +796,11 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) spin_lock(&drvdata->spinlock); + /* sysfs needs to read and allocate a trace ID */ + ret = etm4_read_alloc_trace_id(drvdata); + if (ret < 0) + goto unlock_sysfs_enable; + /* * Executing etm4_enable_hw on the cpu whose ETM is being enabled * ensures that register writes occur when cpu is powered. @@ -764,6 +812,11 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) ret = arg.rc; if (!ret) drvdata->sticky_enable = true; + + if (ret) + etm4_release_trace_id(drvdata); + +unlock_sysfs_enable: spin_unlock(&drvdata->spinlock); if (!ret) @@ -895,6 +948,8 @@ static int etm4_disable_perf(struct coresight_device *csdev, /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus = (control & BIT(9)); + /* perf will release trace ids when _free_aux() is called at the end of the session */ + return 0; } @@ -920,6 +975,13 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) spin_unlock(&drvdata->spinlock); cpus_read_unlock(); + /* + * we only release trace IDs when resetting sysfs. + * This permits sysfs users to read the trace ID after the trace + * session has completed. This maintains operational behaviour with + * prior trace id allocation method + */ + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); } @@ -1562,11 +1624,6 @@ static int etm4_dying_cpu(unsigned int cpu) return 0; } -static void etm4_init_trace_id(struct etmv4_drvdata *drvdata) -{ - drvdata->trcid = coresight_get_trace_id(drvdata->cpu); -} - static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) { int i, ret = 0; @@ -1971,7 +2028,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) if (!desc.name) return -ENOMEM; - etm4_init_trace_id(drvdata); etm4_set_default(&drvdata->config); pdata = coresight_get_platform_data(dev); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 9cac848cffaf..5e62aa40ecd0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -266,10 +266,11 @@ static ssize_t reset_store(struct device *dev, config->vmid_mask0 = 0x0; config->vmid_mask1 = 0x0; - drvdata->trcid = drvdata->cpu + 1; - spin_unlock(&drvdata->spinlock); + /* for sysfs - only release trace id when resetting */ + etm4_release_trace_id(drvdata); + cscfg_csdev_reset_feats(to_coresight_device(dev)); return size; @@ -2392,6 +2393,26 @@ static struct attribute *coresight_etmv4_attrs[] = { NULL, }; +/* + * Trace ID allocated dynamically on enable - but also allocate on read + * in case sysfs or perf read before enable to ensure consistent metadata + * information for trace decode + */ +static ssize_t trctraceid_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int trace_id; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + trace_id = etm4_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; + + return sysfs_emit(buf, "0x%x\n", trace_id); +} +static DEVICE_ATTR_RO(trctraceid); + struct etmv4_reg { struct coresight_device *csdev; u32 offset; @@ -2528,7 +2549,7 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = { coresight_etm4x_reg(trcpidr3, TRCPIDR3), coresight_etm4x_reg(trcoslsr, TRCOSLSR), coresight_etm4x_reg(trcconfig, TRCCONFIGR), - coresight_etm4x_reg(trctraceid, TRCTRACEIDR), + &dev_attr_trctraceid.attr, coresight_etm4x_reg(trcdevarch, TRCDEVARCH), NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 4b21bb79f168..434f4e95ee17 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1095,4 +1095,7 @@ static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) { return drvdata->arch >= ETM_ARCH_ETE; } + +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata); +void etm4_release_trace_id(struct etmv4_drvdata *drvdata); #endif From patchwork Tue Nov 1 16:30:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13769 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076014wru; Tue, 1 Nov 2022 09:33:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7GhsgFN4mKsyPW6vFanJhxylZcpXxtduUlnfv/qf6jacBRUlCz37WIqXohJcOvhVY7P/fO X-Received: by 2002:a17:906:2a93:b0:78d:b87e:6aab with SMTP id l19-20020a1709062a9300b0078db87e6aabmr19402354eje.157.1667320421522; Tue, 01 Nov 2022 09:33:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320421; cv=none; d=google.com; s=arc-20160816; b=jbBk5VqwepqBijrhdto98NhJz5bE9DVKSPzIH4blkcgiFpWakOmmkP4ESdPOCemATa TMW62YbVhb0tFJMp9XHR1/a0TyeMikfO07tdsBKtZzrPW/Z2U9drDY/y2sy9ydAbzIQb 2tn6wREpDbac5/KgQ5+wDWXtfMNSosI2Z+ZSlZWO1PlYm91KzqhvBQpF5WYf/OoR1QaC /+1WvNFOwRG8oQxOcRMnZg7BrLGhcqpC3ftPhrmgXdJ/AyTnH0OBGx8Zj11dSwB25MPk A0TmFH3QHnMk4EXLR9hJqA76kcNo4zEI0BTk0i7FLm8/UmuXdambpyHL3AKW7nn2zru5 a42g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=fdNBgmLA0ARtvmJ0vN5Z/w6aKfYyu8s0U0URVnDv14o=; b=pdvNlcl1pSsw11n19IlDIbHAzC7FpwXZ2K06zegnSSBzPSokx0R1cJtebIhR4UWUMW a+3M/9c0b4fxa1tfZuH/Yo1U+MSuTOtPvmIPkXMiYBczP5/mVaPRrDHmhkbj1cpqeghe 6j1v4hiEQ66a0yxvGdmrJX7y+Nj0f0ohfHm0rfDZhd0eexFH0F5zgaptW90u1Us9c9yv +ldAwV8x3LzMMsXvec2M2RcV0n4AfktChOjfjFvfBHn2APZ84Ic1dn81es3tgwLebh5K 7SeVZ7d5tDSC0mLNKEIrzycpLdbMQZTAASAqiIqek8utPYmSSBjQkbxF7NZVFsqbeT84 Fyrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GmBttxW5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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As with the etm4x we allocate on enable / disable for perf, allocate on enable / reset for sysfs. Additionally we allocate on sysfs file read as both perf and sysfs can read the ID before enabling the hardware. Remove sysfs option to write trace ID - which is inconsistent with both the dynamic allocation method and the fixed allocation method previously used. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm.h | 2 + .../coresight/coresight-etm3x-core.c | 69 +++++++++++++++++-- .../coresight/coresight-etm3x-sysfs.c | 27 ++------ 3 files changed, 72 insertions(+), 26 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index f3ab96eaf44e..3667428d38b6 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -287,4 +287,6 @@ int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata); +void etm_release_trace_id(struct etm_drvdata *drvdata); #endif diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index d0ab9933472b..9a7a9e974d41 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -32,6 +32,7 @@ #include "coresight-etm.h" #include "coresight-etm-perf.h" +#include "coresight-trace-id.h" /* * Not really modular but using module_param is the easiest way to @@ -490,16 +491,59 @@ static int etm_trace_id(struct coresight_device *csdev) return etm_get_trace_id(drvdata); } +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) +{ + int trace_id; + + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + * + * trace id function has its own lock + */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); + if (IS_VALID_ID(trace_id)) + drvdata->traceid = (u8)trace_id; + else + dev_err(&drvdata->csdev->dev, + "Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + return trace_id; +} + +void etm_release_trace_id(struct etm_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu); +} + static int etm_enable_perf(struct coresight_device *csdev, struct perf_event *event) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int trace_id; if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) return -EINVAL; /* Configure the tracer based on the session's specifics */ etm_parse_event_config(drvdata, event); + + /* + * perf allocates cpu ids as part of _setup_aux() - device needs to use + * the allocated ID. This reads the current version without allocation. + * + * This does not use the trace id lock to prevent lock_dep issues + * with perf locks - we know the ID cannot change until perf shuts down + * the session + */ + trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu); + if (!IS_VALID_ID(trace_id)) { + dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + return -EINVAL; + } + drvdata->traceid = (u8)trace_id; + /* And enable it */ return etm_enable_hw(drvdata); } @@ -512,6 +556,11 @@ static int etm_enable_sysfs(struct coresight_device *csdev) spin_lock(&drvdata->spinlock); + /* sysfs needs to allocate and set a trace ID */ + ret = etm_read_alloc_trace_id(drvdata); + if (ret < 0) + goto unlock_enable_sysfs; + /* * Configure the ETM only if the CPU is online. If it isn't online * hw configuration will take place on the local CPU during bring up. @@ -528,6 +577,10 @@ static int etm_enable_sysfs(struct coresight_device *csdev) ret = -ENODEV; } + if (ret) + etm_release_trace_id(drvdata); + +unlock_enable_sysfs: spin_unlock(&drvdata->spinlock); if (!ret) @@ -611,6 +664,9 @@ static void etm_disable_perf(struct coresight_device *csdev) coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); + + /* perf will release trace ids when _free_aux() is called at the end of the session */ + } static void etm_disable_sysfs(struct coresight_device *csdev) @@ -635,6 +691,13 @@ static void etm_disable_sysfs(struct coresight_device *csdev) spin_unlock(&drvdata->spinlock); cpus_read_unlock(); + /* + * we only release trace IDs when resetting sysfs. + * This permits sysfs users to read the trace ID after the trace + * session has completed. This maintains operational behaviour with + * prior trace id allocation method + */ + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); } @@ -781,11 +844,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_trace_id(struct etm_drvdata *drvdata) -{ - drvdata->traceid = coresight_get_trace_id(drvdata->cpu); -} - static int __init etm_hp_setup(void) { int ret; @@ -871,7 +929,6 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) if (etm_arch_supported(drvdata->arch) == false) return -EINVAL; - etm_init_trace_id(drvdata); etm_set_default(&drvdata->config); pdata = coresight_get_platform_data(dev); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index fd81eca3ec18..2f271b7fb048 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -85,6 +85,7 @@ static ssize_t reset_store(struct device *dev, } etm_set_default(config); + etm_release_trace_id(drvdata); spin_unlock(&drvdata->spinlock); } @@ -1189,30 +1190,16 @@ static DEVICE_ATTR_RO(cpu); static ssize_t traceid_show(struct device *dev, struct device_attribute *attr, char *buf) { - unsigned long val; - struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - val = etm_get_trace_id(drvdata); - - return sprintf(buf, "%#lx\n", val); -} - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; + int trace_id; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; + trace_id = etm_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; - drvdata->traceid = val & ETM_TRACEID_MASK; - return size; + return sysfs_emit(buf, "%#x\n", trace_id); } -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); static struct attribute *coresight_etm_attrs[] = { &dev_attr_nr_addr_cmp.attr, From patchwork Tue Nov 1 16:30:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13768 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076007wru; Tue, 1 Nov 2022 09:33:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7bPLb3Q5Bu6mq9u/BtOYDfFDuW9lEJWBV66HfIgkFdJ8/DLIifvqY7obWEgJlTlCR+pGIL X-Received: by 2002:a17:906:cc48:b0:7a8:4a3b:11f7 with SMTP id mm8-20020a170906cc4800b007a84a3b11f7mr19575450ejb.388.1667320420859; Tue, 01 Nov 2022 09:33:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320420; cv=none; d=google.com; s=arc-20160816; b=XiquvUb/v3oQ6JGhBBUpM/kOKZgYpNztlg3SqsHnWiuk+do4sxcEv0aDgwmZRHxHxo 8rkmkwMatw9ngd+v3cpBqrJDH8BWI2HaJepIyGwHrBK3rojrK1mMvRelzihS1ZFh77dq Fn2yPenPcrzu1np/cG2xFpt5T6IOjq3p/R8/FJHLIuQXeCdIcCOX3a07S3vrUwnzlqQ3 tCrxJq1geMx58TlWm1cqi9eF8uTQuzIGo4bmlYO524ECeB7hFwXWQUrM92MU1TWVCUht G04pPwgnuWgGMl//46hE6zW9hx3PUjLmGf0pAw3O/SUWKlaxz8/u4l8NR5QZk48cRjVP 57Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=XWMyRHYi9GSvvTwgSnz9MwrsuUiuK9dGOVjtPqiNkAw=; b=h2VpAmkTsxBczwDwfH0hsN3aD8qrRcmRB2TIU2OAEd9qqdqtXcbERSWfmqZOCqJKVH lVfoSDtFdRhNX6anzIxOngmqRqNuzF18HlazatXTJjRcexZhKj9mCihFeyIHADNvzybU /cNT+2fOF6PzQLnK+AMBnY4I6Q2ovYdJIpo+U23+CeyatGvbTgSsX8DuGPyg97wrmWvp 0PyjPywOHIaKb1fGh4UQa4402GHt/2FzjlswQ5tWc4ku9w3iptN1EYa0zLYxUjcioADG piB+0tZSsyQulTAZ1th4os3NOnlQh7OCvhKu1soEDO9BpyeL5fLh0kw4s71dDLPRv5fi cLhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xblief49; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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This was used to check that sources all had a unique Trace ID. Uniqueness is now gauranteed by the Trace ID allocation system, and the check code has been removed from the core. This patch removes the unneeded and unused .trace_id source ops from the ops structure and implementations in etm3x, etm4x and stm. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm.h | 1 - .../coresight/coresight-etm3x-core.c | 37 ------------------- .../coresight/coresight-etm4x-core.c | 8 ---- drivers/hwtracing/coresight/coresight-stm.c | 8 ---- include/linux/coresight.h | 3 -- 5 files changed, 57 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 3667428d38b6..9a0d08b092ae 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -283,7 +283,6 @@ static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off) } extern const struct attribute_group *coresight_etm_groups[]; -int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 9a7a9e974d41..96b8b86bd436 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -455,42 +455,6 @@ static int etm_cpu_id(struct coresight_device *csdev) return drvdata->cpu; } -int etm_get_trace_id(struct etm_drvdata *drvdata) -{ - unsigned long flags; - int trace_id = -1; - struct device *etm_dev; - - if (!drvdata) - goto out; - - etm_dev = drvdata->csdev->dev.parent; - if (!local_read(&drvdata->mode)) - return drvdata->traceid; - - pm_runtime_get_sync(etm_dev); - - spin_lock_irqsave(&drvdata->spinlock, flags); - - CS_UNLOCK(drvdata->base); - trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK); - CS_LOCK(drvdata->base); - - spin_unlock_irqrestore(&drvdata->spinlock, flags); - pm_runtime_put(etm_dev); - -out: - return trace_id; - -} - -static int etm_trace_id(struct coresight_device *csdev) -{ - struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return etm_get_trace_id(drvdata); -} - int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) { int trace_id; @@ -734,7 +698,6 @@ static void etm_disable(struct coresight_device *csdev, static const struct coresight_ops_source etm_source_ops = { .cpu_id = etm_cpu_id, - .trace_id = etm_trace_id, .enable = etm_enable, .disable = etm_disable, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 0e361d35c611..edce9628916a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -228,13 +228,6 @@ static int etm4_cpu_id(struct coresight_device *csdev) return drvdata->cpu; } -static int etm4_trace_id(struct coresight_device *csdev) -{ - struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return drvdata->trcid; -} - int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) { int trace_id; @@ -1015,7 +1008,6 @@ static void etm4_disable(struct coresight_device *csdev, static const struct coresight_ops_source etm4_source_ops = { .cpu_id = etm4_cpu_id, - .trace_id = etm4_trace_id, .enable = etm4_enable, .disable = etm4_disable, }; diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 6af1b996af6f..66a614c5492c 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -281,15 +281,7 @@ static void stm_disable(struct coresight_device *csdev, } } -static int stm_trace_id(struct coresight_device *csdev) -{ - struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return drvdata->traceid; -} - static const struct coresight_ops_source stm_source_ops = { - .trace_id = stm_trace_id, .enable = stm_enable, .disable = stm_disable, }; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 1554021231f9..e241eb88dfb9 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -314,14 +314,11 @@ struct coresight_ops_link { * Operations available for sources. * @cpu_id: returns the value of the CPU number this component * is associated to. - * @trace_id: returns the value of the component's trace ID as known - * to the HW. * @enable: enables tracing for a source. * @disable: disables tracing for a source. */ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); - int (*trace_id)(struct coresight_device *csdev); int (*enable)(struct coresight_device *csdev, struct perf_event *event, u32 mode); void (*disable)(struct coresight_device *csdev, From patchwork Tue Nov 1 16:30:57 2022 Content-Type: text/plain; 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Date: Tue, 1 Nov 2022 16:30:57 +0000 Message-Id: <20221101163103.17921-9-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221101163103.17921-1-mike.leach@linaro.org> References: <20221101163103.17921-1-mike.leach@linaro.org> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748312181378051897?= X-GMAIL-MSGID: =?utf-8?q?1748312181378051897?= Removes legacy coresight_get_trace_id() function now its use has been removed from the ETM code. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- include/linux/coresight-pmu.h | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index ffff4e6277e5..624f4843453e 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -8,7 +8,6 @@ #define _LINUX_CORESIGHT_PMU_H #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 /* * The legacy Trace ID system based on fixed calculation from the cpu @@ -44,15 +43,4 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} - #endif From patchwork Tue Nov 1 16:30:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13771 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076056wru; Tue, 1 Nov 2022 09:33:45 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5GUYjCc4vgwz++aToD1vZQQ4XqPBS70MAB9Z5VNf0AAE/hhNF7iTInWow9pUh93KrDi8dX X-Received: by 2002:a17:906:9752:b0:78d:d2e1:d745 with SMTP id o18-20020a170906975200b0078dd2e1d745mr19069239ejy.452.1667320425333; Tue, 01 Nov 2022 09:33:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320425; cv=none; d=google.com; s=arc-20160816; b=anPHpZEslMIthcv8waaoikLWkjxYaxNtqPehnvsCoziMn0mubeAAjOrWo983q2KRAC D5QPnHzHtJESzcKvQNBtWHzvBx+26S8ErlV3xG9E5oR+8omtOsdBD7+aNLzaUlJIFOhd Fdjf4cwflZ3zQKXuLLga3mY5zRN2FvBe7spwROrwEwXkPehcTHje1Aq/xYj1xABajAi/ sMbpaa7Xt6pPWT8O5UpCjbJKpGXrEotfs2nSxdK0nFr6Y9bDjnVch46r2NNrLoNjAFRw bEDcuQTZMlCkwDwyezHK9BgECd1MocDM2/pInAX+QARl6HKTeqdIwqWlRYp6woPab4t6 +oZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=4piIjBBSKKW5sIyFoW3hMNWYvv72XBKBYPL6wKArJpU=; b=BrIBGt1IF1/NtwMj13X+DrkSQYgyUCVgo4z2TC84FReVaBj/UaLhEhAQoSBq1mN1XN uxIk8v3aFf2JyVxkFqDbsH08S63twWwXijeHU+6cJ6DkKqBDXQKV6bAUQdmKoL2l3rM2 7Vg13JHBfJCqvgsrpQfLCGRriw8J6NNWIErpwszCOOgp/cuDJL9FzvG+rQu+rcQvcBxB dukP5xlFCU5sn6IBHgjQMdKWG3C/crAmGZDa9gzyiiH9hqX62N8gNwQ5RSvn/I4RZ4Y9 A/cu8pstmFUQGZ0CTMplmnBWKrld52vr3K3J43wtFRfjKppyRKGOs4iV5prLHNKWbsyh 50KQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NVomVUym; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Drivers will start outputting this as a hardware ID packet in the data file which if present will be used in preference to the AUXINFO values. To prepare for this we provide a helper functions to do the individual ID mapping, and one to extract the IDs from the completed metadata blocks. Signed-off-by: Mike Leach Reviewed-by: James Clark Acked-by: Suzuki K Poulose --- tools/include/linux/coresight-pmu.h | 5 ++ tools/perf/util/cs-etm.c | 92 +++++++++++++++++++---------- tools/perf/util/cs-etm.h | 14 ++++- 3 files changed, 77 insertions(+), 34 deletions(-) diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index 6c2fd6cc5a98..db9c7c0abb6a 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -7,9 +7,14 @@ #ifndef _LINUX_CORESIGHT_PMU_H #define _LINUX_CORESIGHT_PMU_H +#include + #define CORESIGHT_ETM_PMU_NAME "cs_etm" #define CORESIGHT_ETM_PMU_SEED 0x10 +/* CoreSight trace ID is currently the bottom 7 bits of the value */ +#define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 16db965ac995..11026c9694a4 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -193,6 +193,30 @@ int cs_etm__get_pid_fmt(u8 trace_chan_id, u64 *pid_fmt) return 0; } +static int cs_etm__map_trace_id(u8 trace_chan_id, u64 *cpu_metadata) +{ + struct int_node *inode; + + /* Get an RB node for this CPU */ + inode = intlist__findnew(traceid_list, trace_chan_id); + + /* Something went wrong, no need to continue */ + if (!inode) + return -ENOMEM; + + /* + * The node for that CPU should not be taken. + * Back out if that's the case. + */ + if (inode->priv) + return -EINVAL; + + /* All good, associate the traceID with the metadata pointer */ + inode->priv = cpu_metadata; + + return 0; +} + void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, u8 trace_chan_id) { @@ -2881,18 +2905,47 @@ static int cs_etm__queue_aux_records(struct perf_session *session) return 0; } +/* map trace ids to correct metadata block, from information in metadata */ +static int cs_etm__map_trace_ids_metadata(int num_cpu, u64 **metadata) +{ + u64 cs_etm_magic; + u8 trace_chan_id; + int i, err; + + for (i = 0; i < num_cpu; i++) { + cs_etm_magic = metadata[i][CS_ETM_MAGIC]; + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + trace_chan_id = (u8)((metadata[i][CS_ETM_ETMTRACEIDR]) & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + trace_chan_id = (u8)((metadata[i][CS_ETMV4_TRCTRACEIDR]) & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + default: + /* unknown magic number */ + return -EINVAL; + } + err = cs_etm__map_trace_id(trace_chan_id, metadata[i]); + if (err) + return err; + } + return 0; +} + int cs_etm__process_auxtrace_info(union perf_event *event, struct perf_session *session) { struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info; struct cs_etm_auxtrace *etm = NULL; - struct int_node *inode; unsigned int pmu_type; int event_header_size = sizeof(struct perf_event_header); int info_header_size; int total_size = auxtrace_info->header.size; int priv_size = 0; - int num_cpu, trcidr_idx; + int num_cpu; int err = 0; int i, j; u64 *ptr, *hdr = NULL; @@ -2962,23 +3015,13 @@ int cs_etm__process_auxtrace_info(union perf_event *event, cs_etm__create_meta_blk(ptr, &i, CS_ETM_PRIV_MAX, CS_ETM_NR_TRC_PARAMS_V0); - - /* The traceID is our handle */ - trcidr_idx = CS_ETM_ETMTRACEIDR; - } else if (ptr[i] == __perf_cs_etmv4_magic) { metadata[j] = cs_etm__create_meta_blk(ptr, &i, CS_ETMV4_PRIV_MAX, CS_ETMV4_NR_TRC_PARAMS_V0); - - /* The traceID is our handle */ - trcidr_idx = CS_ETMV4_TRCTRACEIDR; } else if (ptr[i] == __perf_cs_ete_magic) { metadata[j] = cs_etm__create_meta_blk(ptr, &i, CS_ETE_PRIV_MAX, -1); - - /* ETE shares first part of metadata with ETMv4 */ - trcidr_idx = CS_ETMV4_TRCTRACEIDR; } else { ui__error("CS ETM Trace: Unrecognised magic number %#"PRIx64". File could be from a newer version of perf.\n", ptr[i]); @@ -2990,26 +3033,6 @@ int cs_etm__process_auxtrace_info(union perf_event *event, err = -ENOMEM; goto err_free_metadata; } - - /* Get an RB node for this CPU */ - inode = intlist__findnew(traceid_list, metadata[j][trcidr_idx]); - - /* Something went wrong, no need to continue */ - if (!inode) { - err = -ENOMEM; - goto err_free_metadata; - } - - /* - * The node for that CPU should not be taken. - * Back out if that's the case. - */ - if (inode->priv) { - err = -EINVAL; - goto err_free_metadata; - } - /* All good, associate the traceID with the metadata pointer */ - inode->priv = metadata[j]; } /* @@ -3090,6 +3113,11 @@ int cs_etm__process_auxtrace_info(union perf_event *event, if (err) goto err_delete_thread; + /* before aux records are queued, need to map metadata to trace IDs */ + err = cs_etm__map_trace_ids_metadata(num_cpu, metadata); + if (err) + goto err_delete_thread; + err = cs_etm__queue_aux_records(session); if (err) goto err_delete_thread; diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 90c83f932d9a..712a6f855f0e 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -28,13 +28,17 @@ enum { /* * Update the version for new format. * - * New version 1 format adds a param count to the per cpu metadata. + * Version 1: format adds a param count to the per cpu metadata. * This allows easy adding of new metadata parameters. * Requires that new params always added after current ones. * Also allows client reader to handle file versions that are different by * checking the number of params in the file vs the number expected. + * + * Version 2: Drivers will use PERF_RECORD_AUX_OUTPUT_HW_ID to output + * CoreSight Trace ID. ...TRACEIDR metadata will be set to unused ID. */ -#define CS_HEADER_CURRENT_VERSION 1 +#define CS_HEADER_CURRENT_VERSION 2 +#define CS_AUX_HW_ID_VERSION_MIN 2 /* Beginning of header common to both ETMv3 and V4 */ enum { @@ -85,6 +89,12 @@ enum { CS_ETE_PRIV_MAX }; +/* + * Check for valid CoreSight trace ID. If an invalid value is present in the metadata, + * then IDs are present in the hardware ID packet in the data file. + */ +#define CS_IS_VALID_TRACE_ID(id) ((id > 0) && (id < 0x70)) + /* * ETMv3 exception encoding number: * See Embedded Trace Macrocell specification (ARM IHI 0014Q) From patchwork Tue Nov 1 16:30:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13774 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076130wru; Tue, 1 Nov 2022 09:33:52 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5M1dbSkxVZkAN8pr9XVH4lJLFj5s9f4PR7V8Q42FK6Qj99Iu9sMkSRf6hZfKLpBeRxi3Wj X-Received: by 2002:a05:6402:46:b0:45c:bd68:6ab0 with SMTP id f6-20020a056402004600b0045cbd686ab0mr19910230edu.16.1667320432240; Tue, 01 Nov 2022 09:33:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320432; cv=none; d=google.com; s=arc-20160816; b=Qk+zGsE6gA6v41FiBAcWKSLQMVDPOAiKSjwO3yCkFqoO4L5M+pJNJdgMMAYdpSOnnk hrswMs7kxEB095bSCnxMOD7vxj/VZ8yqkDPlOLIafPBNUVYEMvRuLBQ5oH1fN2mIhjzE ORv/l4k3o7DCXobHX4VvGioLFDRTgQkr3cxo2K/X0NqQv+sv9t1lSFmt8Lj6Pj9dy/rD mMAfEGGgNLSegeCOADo0vYmFMn/j4K3YHLccZLROPMwalbeh9xmn19/kZqG8UK9CYIGx 1eGH51wvBHGAEGWZ3KAtFMgP2ZhDV2AV5tWY8XnCtzuafVYtoSHt+8Oc9dho7lz3Yf52 cGag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=AZXktW+Z8HgOtdq+KcdLQaKYvh8MjYbaciOiUrNcWBY=; b=oMHp0fQNN1Oue8pIqA3YtdT/e+eDKa1kNLYASn0uKNi/cWveWZr+S9+AdrOVmNPtkP 5LImgZaEoUscW3q7k8QuUw0xHIJcNFi6iMlRsahwClu+RaCBXyy6Fn5y69kmMrvhZSaZ VLHarl4y1yEyKfjYstIT9CgJfq/8uA2Hv3WB1moEX/zjVC+Hbi4TXNGriurdglR+Xkkd 4TAy4hkyp4+nSM9feRkRfCmtbQ9Gt+aaudddkopHKpqaL0VKWtbnBQY3A3HPRITI9RE4 WnfBDKUUcCW2PY8jTZ8N3Nfsdhu2IQMOrzm5KiCEZouVwR/XrI33PfCrBdcdQmM/zfM4 WxhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="y/WHtqmw"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Previously used the static association algorithm that is no longer used. The 'cpu * 2 + seed' was outdated and broken for systems with high core counts (>46). as it did not scale and was broken for larger core counts. Trace ID will now be sent in PERF_RECORD_AUX_OUTPUT_HW_ID record. Legacy ID algorithm renamed and retained for limited backward compatibility use. Signed-off-by: Mike Leach Reviewed-by: James Clark Acked-by: Suzuki K Poulose --- tools/include/linux/coresight-pmu.h | 30 +++++++++++++++++------------ tools/perf/arch/arm/util/cs-etm.c | 21 ++++++++++++-------- 2 files changed, 31 insertions(+), 20 deletions(-) diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index db9c7c0abb6a..307f357defe9 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -10,11 +10,28 @@ #include #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 + +/* + * The legacy Trace ID system based on fixed calculation from the cpu + * number. This has been replaced by drivers using a dynamic allocation + * system - but need to retain the legacy algorithm for backward comparibility + * in certain situations:- + * a) new perf running on older systems that generate the legacy mapping + * b) older tools e.g. simpleperf in Android, that may not update at the same + * time as the kernel. + */ +#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) /* CoreSight trace ID is currently the bottom 7 bits of the value */ #define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) +/* + * perf record will set the legacy meta data values as unused initially. + * This allows perf report to manage the decoders created when dynamic + * allocation in operation. + */ +#define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. @@ -39,15 +56,4 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} - #endif diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index a346d5f3dafa..c7e4b543259f 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -421,13 +421,16 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, evlist__to_front(evlist, cs_etm_evsel); /* - * In the case of per-cpu mmaps, we need the CPU on the - * AUX event. We also need the contextID in order to be notified + * get the CPU on the sample - need it to associate trace ID in the + * AUX_OUTPUT_HW_ID event, and the AUX event for per-cpu mmaps. + */ + evsel__set_sample_bit(cs_etm_evsel, CPU); + + /* + * Also the case of per-cpu mmaps, need the contextID in order to be notified * when a context switch happened. */ if (!perf_cpu_map__empty(cpus)) { - evsel__set_sample_bit(cs_etm_evsel, CPU); - err = cs_etm_set_option(itr, cs_etm_evsel, BIT(ETM_OPT_CTXTID) | BIT(ETM_OPT_TS)); if (err) @@ -633,8 +636,10 @@ static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr, /* Get trace configuration register */ data[CS_ETMV4_TRCCONFIGR] = cs_etmv4_get_config(itr); - /* Get traceID from the framework */ - data[CS_ETMV4_TRCTRACEIDR] = coresight_get_trace_id(cpu); + /* traceID set to legacy version, in case new perf running on older system */ + data[CS_ETMV4_TRCTRACEIDR] = + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG; + /* Get read-only information from sysFS */ data[CS_ETMV4_TRCIDR0] = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]); @@ -681,9 +686,9 @@ static void cs_etm_get_metadata(int cpu, u32 *offset, magic = __perf_cs_etmv3_magic; /* Get configuration register */ info->priv[*offset + CS_ETM_ETMCR] = cs_etm_get_config(itr); - /* Get traceID from the framework */ + /* traceID set to legacy value in case new perf running on old system */ info->priv[*offset + CS_ETM_ETMTRACEIDR] = - coresight_get_trace_id(cpu); + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG; /* Get read-only information from sysFS */ info->priv[*offset + CS_ETM_ETMCCER] = cs_etm_get_ro(cs_etm_pmu, cpu, From patchwork Tue Nov 1 16:31:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13775 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076174wru; Tue, 1 Nov 2022 09:33:58 -0700 (PDT) X-Google-Smtp-Source: AMsMyM69U4G2UGIathh6hQpSSyl9s9MTfmegB3dc2KrxuwcYHX9EIZb4EvsERMOgQE/XH4ThJt19 X-Received: by 2002:a17:906:5dae:b0:78e:3109:36d1 with SMTP id n14-20020a1709065dae00b0078e310936d1mr19310539ejv.470.1667320438759; Tue, 01 Nov 2022 09:33:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320438; cv=none; d=google.com; s=arc-20160816; b=WYMrUsxoaMY0LT2uVTB3q+0/pqBPw8N47ivWAq55HDls7TVnCN7g9e0QSLG0lPQsWK EDyRmegxL6KwA6ZLgSRGnvtrbLjWjHVOw4PJeLmDSQRUNVlYAlvBOSBqx95svKMZedBO kAQa9POPYe57qPOL5T0bQ27BnTYrH8RRDyCCefWInVUFyZYsUIZfCQK97waElBbs0R0L lwob4VCHqDrXU73PrqSWSAbsJWeDsrAWJWrxZk8CjGuVfVGpAKqp9Gy6VP/euUl1CG5E Vf1FGoQ32Kwb4KiGM0cFxnXYpn30gSk5NEE2qWcECiVxeABHLNo7ZU9HoD2JXsah5s4Q E3gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=q/rZtCQJIH1tcdWsQUgVvKDosjDAE+Gq7OIwmjNOiDI=; b=Bv4yZbKqmEFEwzwViYZuu528KKAyR3szPb6M9v+JD0DEdN0DXuOeZX32N38OozbAq9 rueAE82YMy8OUvj6ej1iXvYKAcRLTxjkRXCTrYGswNs4Paj2vhwvSzePjFbfCeSQsSjX Oa2q/5ARdddekayZElhHwiYJxGMqJy2EEBVUwo3hjp9dK/4i5G9WxJb6ng6SbR8tNpjl G/j6Mpeu/WgKQEgsXCxUgPyfVTU9Wp48GWeY/Ha4scROBv37SPS1KBwmNTtRBZq5josi C93QSqKCHHukirRO1Ua0buZJdB9Ar/OM7kbEvfO0gw2y3/y4PpmNa5ngdCyWmyLu0PFr UaOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=obRRjsLU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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This function in needs export visibility to allow it to be called from kernel loadable modules, which CoreSight may configured to be built as. Signed-off-by: Mike Leach Acked-by: Suzuki K Poulose --- kernel/events/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/events/core.c b/kernel/events/core.c index 4ec3717003d5..ad388552f1d5 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -9231,6 +9231,7 @@ void perf_report_aux_output_id(struct perf_event *event, u64 hw_id) perf_output_end(&handle); } +EXPORT_SYMBOL_GPL(perf_report_aux_output_id); static int __perf_event_account_interrupt(struct perf_event *event, int throttle) From patchwork Tue Nov 1 16:31:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13776 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076224wru; Tue, 1 Nov 2022 09:34:05 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4DGBcT8N75rZmVZZKYYAuVEvKWbkgmjDY6o2zyvN0qhGmWtJeYmfZTWc/5OhgEW1zYz8+w X-Received: by 2002:a05:6402:249b:b0:460:cb11:27d4 with SMTP id q27-20020a056402249b00b00460cb1127d4mr19869689eda.410.1667320445141; Tue, 01 Nov 2022 09:34:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320445; cv=none; d=google.com; s=arc-20160816; b=QLgswUxBOk5RCso/Xowt2wQgCvBWnxLWVfW1udo4tphOK+oT8fxDSXcf3gtegXswKD uPOxTfUV1mO07a2be5QBbMjoHDPUfZnJ9MnaND/ZEn99hm6tE0FISfzxnu4ktrYnj9ID LLZhi7srDTG1OhonyyXVBVvkXHDeiNlRxXMpyfBj3WYP6zYq3ypHsVvt7ELWrq+rxidx Ndb0X7OSP5M3wcscSroH8x1JDw2kH1g52xYkdfWhXl7cQOqdRVyf7l1520pPHcGlm5o0 eyciUNP/mKVDoyTspfc4yf1KRr+lPT0zTpyxNEzBR+7XBBqUulsboaW3BXl+WwS7+bP7 TnAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=5XbI9B9yxP0ljArYrUO46YMbiPZr+4/932PHPfOfLcQ=; b=ynD4fL2E+8wbgLXk2X3tm0Xp76GgCNNzmL/3UezkwVDSB6tFF0wgBU0KX7LYu6hIIL d/EHM7o8P2UDOwlldvt9hHb3Qqy/KoxTlXEK7LDLo2cyMHOJwrudAGtWTAZXFGj2lK8e uk6cPahVOuZ62z0W18rkBQs3yHW496J5yYJoaMQhZ28nG/EGcK4VI2zy4jGt2WAV2thw 44HaqOtOOjSxWMfLfUgUKNW1IB1/mkA+LMiATp1FVkReF4sqhtHEh3OaJHwm6roNqeXH xl8XYLEGOETgg+qlTyQWiagfmUFDANel6b+zKD7ZTpXRRE9ZatY0nBeRd5zSGFRYpqzc piLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ml746xg/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Update cs-etm decoder to handle this packet by setting the CPU/Trace ID mapping. Signed-off-by: Mike Leach Reviewed-by: James Clark Acked-by: Suzuki K Poulose --- tools/include/linux/coresight-pmu.h | 15 ++ .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 248 ++++++++++++++++-- 3 files changed, 251 insertions(+), 19 deletions(-) diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index 307f357defe9..57ba1abf1224 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -32,6 +32,9 @@ */ #define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31) +/* Value to set for unused trace ID values */ +#define CORESIGHT_TRACE_ID_UNUSED_VAL 0x7F + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. @@ -56,4 +59,16 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 +/* + * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. + * Used to associate a CPU with the CoreSight Trace ID. + * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. + * [59:08] - Unused (SBZ) + * [63:60] - Version + */ +#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) +#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) + +#define CS_AUX_HW_ID_CURR_VERSION 0 + #endif diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index 31fa3b45134a..fa3aa9c0fb2e 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -625,6 +625,7 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decoder_params *d_params, switch (t_params->protocol) { case CS_ETM_PROTO_ETMV3: case CS_ETM_PROTO_PTM: + csid = (t_params->etmv3.reg_idr & CORESIGHT_TRACE_ID_VAL_MASK); cs_etm_decoder__gen_etmv3_config(t_params, &config_etmv3); decoder->decoder_name = (t_params->protocol == CS_ETM_PROTO_ETMV3) ? OCSD_BUILTIN_DCD_ETMV3 : @@ -632,11 +633,13 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decoder_params *d_params, trace_config = &config_etmv3; break; case CS_ETM_PROTO_ETMV4i: + csid = (t_params->etmv4.reg_traceidr & CORESIGHT_TRACE_ID_VAL_MASK); cs_etm_decoder__gen_etmv4_config(t_params, &trace_config_etmv4); decoder->decoder_name = OCSD_BUILTIN_DCD_ETMV4I; trace_config = &trace_config_etmv4; break; case CS_ETM_PROTO_ETE: + csid = (t_params->ete.reg_traceidr & CORESIGHT_TRACE_ID_VAL_MASK); cs_etm_decoder__gen_ete_config(t_params, &trace_config_ete); decoder->decoder_name = OCSD_BUILTIN_DCD_ETE; trace_config = &trace_config_ete; @@ -645,6 +648,10 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decoder_params *d_params, return -1; } + /* if the CPU has no trace ID associated, no decoder needed */ + if (csid == CORESIGHT_TRACE_ID_UNUSED_VAL) + return 0; + if (d_params->operation == CS_ETM_OPERATION_DECODE) { if (ocsd_dt_create_decoder(decoder->dcd_tree, decoder->decoder_name, diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 11026c9694a4..f9f7d16a55d1 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -217,6 +217,143 @@ static int cs_etm__map_trace_id(u8 trace_chan_id, u64 *cpu_metadata) return 0; } +static int cs_etm__metadata_get_trace_id(u8 *trace_chan_id, u64 *cpu_metadata) +{ + u64 cs_etm_magic = cpu_metadata[CS_ETM_MAGIC]; + + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + *trace_chan_id = (u8)(cpu_metadata[CS_ETM_ETMTRACEIDR] & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + *trace_chan_id = (u8)(cpu_metadata[CS_ETMV4_TRCTRACEIDR] & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + default: + return -EINVAL; + } + return 0; +} + +/* + * update metadata trace ID from the value found in the AUX_HW_INFO packet. + * This will also clear the CORESIGHT_TRACE_ID_UNUSED_FLAG flag if present. + */ +static int cs_etm__metadata_set_trace_id(u8 trace_chan_id, u64 *cpu_metadata) +{ + u64 cs_etm_magic = cpu_metadata[CS_ETM_MAGIC]; + + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + cpu_metadata[CS_ETM_ETMTRACEIDR] = trace_chan_id; + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + cpu_metadata[CS_ETMV4_TRCTRACEIDR] = trace_chan_id; + break; + + default: + return -EINVAL; + } + return 0; +} + +/* + * FIELD_GET (linux/bitfield.h) not available outside kernel code, + * and the header contains too many dependencies to just copy over, + * so roll our own based on the original + */ +#define __bf_shf(x) (__builtin_ffsll(x) - 1) +#define FIELD_GET(_mask, _reg) \ + ({ \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + +/* + * Handle the PERF_RECORD_AUX_OUTPUT_HW_ID event. + * + * The payload associates the Trace ID and the CPU. + * The routine is tolerant of seeing multiple packets with the same association, + * but a CPU / Trace ID association changing during a session is an error. + */ +static int cs_etm__process_aux_output_hw_id(struct perf_session *session, + union perf_event *event) +{ + struct cs_etm_auxtrace *etm; + struct perf_sample sample; + struct int_node *inode; + struct evsel *evsel; + u64 *cpu_data; + u64 hw_id; + int cpu, version, err; + u8 trace_chan_id, curr_chan_id; + + /* extract and parse the HW ID */ + hw_id = event->aux_output_hw_id.hw_id; + version = FIELD_GET(CS_AUX_HW_ID_VERSION_MASK, hw_id); + trace_chan_id = FIELD_GET(CS_AUX_HW_ID_TRACE_ID_MASK, hw_id); + + /* check that we can handle this version */ + if (version > CS_AUX_HW_ID_CURR_VERSION) + return -EINVAL; + + /* get access to the etm metadata */ + etm = container_of(session->auxtrace, struct cs_etm_auxtrace, auxtrace); + if (!etm || !etm->metadata) + return -EINVAL; + + /* parse the sample to get the CPU */ + evsel = evlist__event2evsel(session->evlist, event); + if (!evsel) + return -EINVAL; + err = evsel__parse_sample(evsel, event, &sample); + if (err) + return err; + cpu = sample.cpu; + if (cpu == -1) { + /* no CPU in the sample - possibly recorded with an old version of perf */ + pr_err("CS_ETM: no CPU AUX_OUTPUT_HW_ID sample. Use compatible perf to record."); + return -EINVAL; + } + + /* See if the ID is mapped to a CPU, and it matches the current CPU */ + inode = intlist__find(traceid_list, trace_chan_id); + if (inode) { + cpu_data = inode->priv; + if ((int)cpu_data[CS_ETM_CPU] != cpu) { + pr_err("CS_ETM: map mismatch between HW_ID packet CPU and Trace ID\n"); + return -EINVAL; + } + + /* check that the mapped ID matches */ + err = cs_etm__metadata_get_trace_id(&curr_chan_id, cpu_data); + if (err) + return err; + if (curr_chan_id != trace_chan_id) { + pr_err("CS_ETM: mismatch between CPU trace ID and HW_ID packet ID\n"); + return -EINVAL; + } + + /* mapped and matched - return OK */ + return 0; + } + + /* not one we've seen before - lets map it */ + cpu_data = etm->metadata[cpu]; + err = cs_etm__map_trace_id(trace_chan_id, cpu_data); + if (err) + return err; + + /* + * if we are picking up the association from the packet, need to plug + * the correct trace ID into the metadata for setting up decoders later. + */ + err = cs_etm__metadata_set_trace_id(trace_chan_id, cpu_data); + return err; +} + void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, u8 trace_chan_id) { @@ -2662,7 +2799,7 @@ static void cs_etm__print_auxtrace_info(__u64 *val, int num) for (i = CS_HEADER_VERSION_MAX; cpu < num; cpu++) { if (version == 0) err = cs_etm__print_cpu_metadata_v0(val, &i); - else if (version == 1) + else if (version == 1 || version == 2) err = cs_etm__print_cpu_metadata_v1(val, &i); if (err) return; @@ -2774,11 +2911,16 @@ static int cs_etm__queue_aux_fragment(struct perf_session *session, off_t file_o } /* - * In per-thread mode, CPU is set to -1, but TID will be set instead. See - * auxtrace_mmap_params__set_idx(). Return 'not found' if neither CPU nor TID match. + * In per-thread mode, auxtrace CPU is set to -1, but TID will be set instead. See + * auxtrace_mmap_params__set_idx(). However, the sample AUX event will contain a + * CPU as we set this always for the AUX_OUTPUT_HW_ID event. + * So now compare only TIDs if auxtrace CPU is -1, and CPUs if auxtrace CPU is not -1. + * Return 'not found' if mismatch. */ - if ((auxtrace_event->cpu == (__u32) -1 && auxtrace_event->tid != sample->tid) || - auxtrace_event->cpu != sample->cpu) + if (auxtrace_event->cpu == (__u32) -1) { + if (auxtrace_event->tid != sample->tid) + return 1; + } else if (auxtrace_event->cpu != sample->cpu) return 1; if (aux_event->flags & PERF_AUX_FLAG_OVERWRITE) { @@ -2827,6 +2969,17 @@ static int cs_etm__queue_aux_fragment(struct perf_session *session, off_t file_o return 1; } +static int cs_etm__process_aux_hw_id_cb(struct perf_session *session, union perf_event *event, + u64 offset __maybe_unused, void *data __maybe_unused) +{ + /* look to handle PERF_RECORD_AUX_OUTPUT_HW_ID early to ensure decoders can be set up */ + if (event->header.type == PERF_RECORD_AUX_OUTPUT_HW_ID) { + (*(int *)data)++; /* increment found count */ + return cs_etm__process_aux_output_hw_id(session, event); + } + return 0; +} + static int cs_etm__queue_aux_records_cb(struct perf_session *session, union perf_event *event, u64 offset __maybe_unused, void *data __maybe_unused) { @@ -2916,13 +3069,13 @@ static int cs_etm__map_trace_ids_metadata(int num_cpu, u64 **metadata) cs_etm_magic = metadata[i][CS_ETM_MAGIC]; switch (cs_etm_magic) { case __perf_cs_etmv3_magic: - trace_chan_id = (u8)((metadata[i][CS_ETM_ETMTRACEIDR]) & - CORESIGHT_TRACE_ID_VAL_MASK); + metadata[i][CS_ETM_ETMTRACEIDR] &= CORESIGHT_TRACE_ID_VAL_MASK; + trace_chan_id = (u8)(metadata[i][CS_ETM_ETMTRACEIDR]); break; case __perf_cs_etmv4_magic: case __perf_cs_ete_magic: - trace_chan_id = (u8)((metadata[i][CS_ETMV4_TRCTRACEIDR]) & - CORESIGHT_TRACE_ID_VAL_MASK); + metadata[i][CS_ETMV4_TRCTRACEIDR] &= CORESIGHT_TRACE_ID_VAL_MASK; + trace_chan_id = (u8)(metadata[i][CS_ETMV4_TRCTRACEIDR]); break; default: /* unknown magic number */ @@ -2935,6 +3088,35 @@ static int cs_etm__map_trace_ids_metadata(int num_cpu, u64 **metadata) return 0; } +/* + * If we found AUX_HW_ID packets, then set any metadata marked as unused to the + * unused value to reduce the number of unneeded decoders created. + */ +static int cs_etm__clear_unused_trace_ids_metadata(int num_cpu, u64 **metadata) +{ + u64 cs_etm_magic; + int i; + + for (i = 0; i < num_cpu; i++) { + cs_etm_magic = metadata[i][CS_ETM_MAGIC]; + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + if (metadata[i][CS_ETM_ETMTRACEIDR] & CORESIGHT_TRACE_ID_UNUSED_FLAG) + metadata[i][CS_ETM_ETMTRACEIDR] = CORESIGHT_TRACE_ID_UNUSED_VAL; + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + if (metadata[i][CS_ETMV4_TRCTRACEIDR] & CORESIGHT_TRACE_ID_UNUSED_FLAG) + metadata[i][CS_ETMV4_TRCTRACEIDR] = CORESIGHT_TRACE_ID_UNUSED_VAL; + break; + default: + /* unknown magic number */ + return -EINVAL; + } + } + return 0; +} + int cs_etm__process_auxtrace_info(union perf_event *event, struct perf_session *session) { @@ -2947,6 +3129,7 @@ int cs_etm__process_auxtrace_info(union perf_event *event, int priv_size = 0; int num_cpu; int err = 0; + int aux_hw_id_found; int i, j; u64 *ptr, *hdr = NULL; u64 **metadata = NULL; @@ -3113,8 +3296,43 @@ int cs_etm__process_auxtrace_info(union perf_event *event, if (err) goto err_delete_thread; - /* before aux records are queued, need to map metadata to trace IDs */ - err = cs_etm__map_trace_ids_metadata(num_cpu, metadata); + /* + * Map Trace ID values to CPU metadata. + * + * Trace metadata will always contain Trace ID values from the legacy algorithm. If the + * files has been recorded by a "new" perf updated to handle AUX_HW_ID then the metadata + * ID value will also have the CORESIGHT_TRACE_ID_UNUSED_FLAG set. + * + * The updated kernel drivers that use AUX_HW_ID to sent Trace IDs will attempt to use + * the same IDs as the old algorithm as far as is possible, unless there are clashes + * in which case a different value will be used. This means an older perf may still + * be able to record and read files generate on a newer system. + * + * For a perf able to interpret AUX_HW_ID packets we first check for the presence of + * those packets. If they are there then the values will be mapped and plugged into + * the metadata. We then set any remaining metadata values with the used flag to a + * value CORESIGHT_TRACE_ID_UNUSED_VAL - which indicates no decoder is required. + * + * If no AUX_HW_ID packets are present - which means a file recorded on an old kernel + * then we map Trace ID values to CPU directly from the metadata - clearing any unused + * flags if present. + */ + + /* first scan for AUX_OUTPUT_HW_ID records to map trace ID values to CPU metadata */ + aux_hw_id_found = 0; + err = perf_session__peek_events(session, session->header.data_offset, + session->header.data_size, + cs_etm__process_aux_hw_id_cb, &aux_hw_id_found); + if (err) + goto err_delete_thread; + + /* if HW ID found then clear any unused metadata ID values */ + if (aux_hw_id_found) + err = cs_etm__clear_unused_trace_ids_metadata(num_cpu, metadata); + /* otherwise, this is a file with metadata values only, map from metadata */ + else + err = cs_etm__map_trace_ids_metadata(num_cpu, metadata); + if (err) goto err_delete_thread; @@ -3123,14 +3341,6 @@ int cs_etm__process_auxtrace_info(union perf_event *event, goto err_delete_thread; etm->data_queued = etm->queues.populated; - /* - * Print warning in pipe mode, see cs_etm__process_auxtrace_event() and - * cs_etm__queue_aux_fragment() for details relating to limitations. - */ - if (!etm->data_queued) - pr_warning("CS ETM warning: Coresight decode and TRBE support requires random file access.\n" - "Continuing with best effort decoding in piped mode.\n\n"); - return 0; err_delete_thread: From patchwork Tue Nov 1 16:31:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13778 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076281wru; Tue, 1 Nov 2022 09:34:12 -0700 (PDT) X-Google-Smtp-Source: AMsMyM52z40gLMEx0YEK4e+j9pC+MQh1EU6JaQDAXcFR/1YRcyWCwUHPiuuZS/tDlnYZfrugo52x X-Received: by 2002:a17:907:3f0c:b0:78e:2090:6924 with SMTP id hq12-20020a1709073f0c00b0078e20906924mr19562090ejc.332.1667320451927; Tue, 01 Nov 2022 09:34:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320451; cv=none; d=google.com; s=arc-20160816; b=TcE+g/XYRHWbBx5S5IBnH1jj5J+zEmZxYaGy7+wfn/hCfXU5H6XjprsdYmAvb0xWj2 VQp+Z1cLRIubqW0HPyLglpLOvKRjks8VW+IlJJZnJxUmnUhC34xS9h8EIkHTz15wrlv9 f5tQu/qKjx2f5H/Hb4RGWcXeiQBGjeBR9JcaMLtgwk636Tyk2Ec2Y7ZJ0uFzAYrwm1r4 /cpObbgGEmm/5EZjlsdpeK3nLJb4f46R/uP61Hw2gApJRI6MLZWpsXgNTewkVnpGBNt3 kiqO54MU81jOtULykRruHpBuvx2cpjzonzHwRaXK4xUXmmFSRja8NC8fsPva693tgPI4 EYFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=/OkoZY2NT7ICxt6pxMECbhZ/ZuX+9qnqpKwLzS1JpjA=; b=RAXtNzI0U/+f6fc8w2ExC9Ae4D8vDKc9D6blnTaFGNJTgRfIXShDJKFKttugIsjUcJ hvOD+qJQ+CUidzArYCb1B8+lcmimDRvO90TEZtfY3HjYkaS1uPbogXFJt6X94hGfbgs5 gB6Zi5NzA1RKcYM+hoLE8Ilpe649mROOl5dNSaCLtsMRqJSSBRjzcYHzRs7LG1KRsRCC xLbzSYOS3d6BzkLP6cYV1hG10NAr0QiSQWQp5MK7BDVEH3BuysSoKcY98gmdpzI+sh9p igvPJznqBul2qKfUGBK5hEH7hg+mmt4lht6ZHSn79KRVL5ny1rFjAV4JwGQ/lgTPO23y oxqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EhKSmM7w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm-perf.c | 7 +++++++ include/linux/coresight-pmu.h | 14 ++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 6166f716a6ac..59a2ad95c1dc 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier */ +#include #include #include #include @@ -448,6 +449,7 @@ static void etm_event_start(struct perf_event *event, int flags) struct perf_output_handle *handle = &ctxt->handle; struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu); struct list_head *path; + u64 hw_id; if (!csdev) goto fail; @@ -493,6 +495,11 @@ static void etm_event_start(struct perf_event *event, int flags) if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) goto fail_disable_path; + /* output cpu / trace ID in perf record */ + hw_id = FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK, CS_AUX_HW_ID_CURR_VERSION) | + FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, coresight_trace_id_read_cpu_id(cpu)); + perf_report_aux_output_id(event, hw_id); + out: /* Tell the perf core the event is alive */ event->hw.state = 0; diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 624f4843453e..51ac441a37c3 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -7,6 +7,8 @@ #ifndef _LINUX_CORESIGHT_PMU_H #define _LINUX_CORESIGHT_PMU_H +#include + #define CORESIGHT_ETM_PMU_NAME "cs_etm" /* @@ -43,4 +45,16 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 +/* + * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. + * Used to associate a CPU with the CoreSight Trace ID. + * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. + * [59:08] - Unused (SBZ) + * [63:60] - Version + */ +#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) +#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) + +#define CS_AUX_HW_ID_CURR_VERSION 0 + #endif From patchwork Tue Nov 1 16:31:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 13777 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3076251wru; Tue, 1 Nov 2022 09:34:08 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5rduwHwMQAVZEh8Cs7AgWo5cmYmK8lYMVYokIiRq1g9n9P09+qTnCnwItoqnvTZaT63xYa X-Received: by 2002:a05:6402:5296:b0:461:b6e5:ea63 with SMTP id en22-20020a056402529600b00461b6e5ea63mr19819881edb.248.1667320448620; Tue, 01 Nov 2022 09:34:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320448; cv=none; d=google.com; s=arc-20160816; b=b1HWSVUk9mjP3LWCO4LLkfeCovZBNt0ZaIEdNwuT+9aofyTWmLPsmMi2NXhO+3AFDc Da2dB8NXsgX7fTBvdzkbgOe0o2aT1lFsKfB6xVA7WcKOKhjQatsiTw9iujNys8/QH4Li hF8WwntJF/Nd5eV9cXk9Ihox3AaCKQvC6EbHioZljlkHMi8AWuCrLtjOvvPdwGFcGNNq XgKOc2E6pYTPLMBofL6AbCUkfaz8DzHeZFIjgCWJA/By62fd/MZzRfHo4Y0eDTA0At8A wgVmOWgi3hLyQCKmRTndQlKA8TOMrRzrviOiuwJClYKfvV3EFUo34dyFexjxCiwlo0Xw zq3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=0n8UTexiHKIiqpxO27R+y1dDLs4IJMQEzjh508MgLvo=; b=dIHAiiZmGxcfnsSuMvsgPTUMmJYtAJEGKfaFTVhf2wf0xwKyedgSzEI4dGkbsuJP0J 9U32pzf1V0RLatWJ37bnG5J2wFXWJ6jtuiGzgctdXORFe5KAF6FU7qDXXcEWhngaAM7e SIBRjLX3JZTNXmDWULngccW/bNCXnbNBWUjL0uC4HWpZp3MIOxKBR2nadbiLLNgcBWmN eNeLdyi2x6qrff4UTOs6asURERZLAU+Zz3bsmmpcKylKT/ngsOxz9VnhNq/EGXnQH+um fhjTSeMqFdNQceQStGTMNM/TtUc0L+4VToEf51+HiX/EpDCwT8hI2tyK6EihNcjFe6Gy G1Ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yaj1GT32; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Mike Leach --- .../hwtracing/coresight/coresight-trace-id.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c index 8e05a244c9d6..1588bad60715 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -64,6 +64,27 @@ static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace_id_ma set_bit(id, id_map->pend_rel_ids); } +/* #define TRACE_ID_DEBUG 1 */ +#ifdef TRACE_ID_DEBUG + +static void coresight_trace_id_dump_table(struct coresight_trace_id_map *id_map, + const char *func_name) +{ + pr_debug("%s id_map::\n", func_name); + pr_debug("Avial= %*pb\n", CORESIGHT_TRACE_IDS_MAX, id_map->used_ids); + pr_debug("Pend = %*pb\n", CORESIGHT_TRACE_IDS_MAX, id_map->pend_rel_ids); +} +#define DUMP_ID_MAP(map) coresight_trace_id_dump_table(map, __func__) +#define DUMP_ID_CPU(cpu, id) pr_debug("%s called; cpu=%d, id=%d\n", __func__, cpu, id) +#define DUMP_ID(id) pr_debug("%s called; id=%d\n", __func__, id) +#define PERF_SESSION(n) pr_debug("%s perf count %d\n", __func__, n) +#else +#define DUMP_ID_MAP(map) +#define DUMP_ID(id) +#define DUMP_ID_CPU(cpu, id) +#define PERF_SESSION(n) +#endif + /* release all pending IDs for all current maps & clear CPU associations */ static void coresight_trace_id_release_all_pending(void) { @@ -81,6 +102,7 @@ static void coresight_trace_id_release_all_pending(void) clear_bit(cpu, cpu_id_release_pending); } spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID_MAP(id_map); } static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_map *id_map) @@ -120,6 +142,8 @@ static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_ get_cpu_id_out_unlock: spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID_CPU(cpu, id); + DUMP_ID_MAP(id_map); return id; } @@ -146,6 +170,8 @@ static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_trace_id } spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID_CPU(cpu, id); + DUMP_ID_MAP(id_map); } static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *id_map) @@ -157,6 +183,8 @@ static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *i id = coresight_trace_id_alloc_new_id(id_map, 0); spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID(id); + DUMP_ID_MAP(id_map); return id; } @@ -167,6 +195,9 @@ static void coresight_trace_id_map_put_system_id(struct coresight_trace_id_map * spin_lock_irqsave(&id_map_lock, flags); coresight_trace_id_free(id, id_map); spin_unlock_irqrestore(&id_map_lock, flags); + + DUMP_ID(id); + DUMP_ID_MAP(id_map); } /* API functions */ @@ -204,6 +235,7 @@ EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id); void coresight_trace_id_perf_start(void) { atomic_inc(&perf_cs_etm_session_active); + PERF_SESSION(atomic_read(&perf_cs_etm_session_active)); } EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start); @@ -211,6 +243,7 @@ void coresight_trace_id_perf_stop(void) { if (!atomic_dec_return(&perf_cs_etm_session_active)) coresight_trace_id_release_all_pending(); + PERF_SESSION(atomic_read(&perf_cs_etm_session_active)); } EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop);