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[8.43.85.97]) by mx.google.com with ESMTPS id qq7-20020a17090720c700b00997dbbda750si2348764ejb.839.2023.07.28.00.21.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 00:21:50 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1F5C5385DC33 for ; Fri, 28 Jul 2023 07:21:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id CE3333858D33 for ; Fri, 28 Jul 2023 07:20:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CE3333858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp86t1690528812tnm781ke Received: from server1.localdomain ( [58.60.1.10]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 28 Jul 2023 15:20:11 +0800 (CST) X-QQ-SSF: 01400000000000G0U000000A0000000 X-QQ-FEAT: zT6n3Y95oi0gyXmdlgyKVn4F616QERgwflk6uxtwO5iYgfSMTBwDSryVYLIzF DmdZkOkBZAs6ck+kchhUt/uVw+g7BBNE28WJt//cPPDks8hSJxJ3cIacyaaiueSx4XPzPJv 5Z0FEo1q1kZOVdJZ2Q6EFuhm31GdGFbQdWAAYx4geyPueY2JIvHCQeO+uo3KFNQkPknqOu7 GojgIPaGHQpePNgSkw9dC6A7qkp2GpSr0a6tkewve/nhO7xe1D0uZ8WToCww5F7Xn3aAOl4 rN659s+KRYTzshajy0EaXVSNKMyAfJcOX+PE8nTVAVLNxltN/iLibuodVz2edXawOsjXMTD DmdeItItMQpxUXhVjHmQL7hkGmBuM5q50NE23fygAGb7RvYdjGRHw4VYK8MSZJd52XKF+V0 pYi2QWc93Akxz2yJjTEngYqliNTnmQXM X-QQ-GoodBg: 2 X-BIZMAIL-ID: 15906451364969349639 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Support CALL conditional autovec patterns Date: Fri, 28 Jul 2023 15:20:10 +0800 Message-Id: <20230728072010.108620-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772648042978924994 X-GMAIL-MSGID: 1772648042978924994 This patch is depending on middle-end support: https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625696.html Consider this following case: void foo (float * __restrict a, float * __restrict b, int * __restrict cond, int n) { for (int i = 0; i < n; i++) if (cond[i]) a[i] = b[i] + a[i]; } Before this patch (**NO** -ffast-math): :5:21: missed: couldn't vectorize loop :5:21: missed: not vectorized: control flow in loop. After this patch: foo: ble a3,zero,.L5 mv a6,a0 .L3: vsetvli a5,a3,e8,mf4,ta,ma vle32.v v0,0(a2) vsetvli a7,zero,e32,m1,ta,ma slli a4,a5,2 vmsne.vi v0,v0,0 sub a3,a3,a5 vsetvli zero,a5,e32,m1,tu,mu ------> must be TUMU vle32.v v2,0(a0),v0.t vle32.v v1,0(a1),v0.t vfadd.vv v1,v1,v2,v0.t ------> generated by COND_LEN_ADD with real mask and len. vse32.v v1,0(a6),v0.t add a2,a2,a4 add a1,a1,a4 add a0,a0,a4 add a6,a6,a4 bne a3,zero,.L3 .L5: ret gcc/ChangeLog: * config/riscv/autovec.md (cond_): New pattern. (cond_len_): Ditto. (cond_fma): Ditto. * config/riscv/riscv-protos.h (enum insn_type): New macro. * config/riscv/riscv-v.cc (emit_vlmax_masked_fp_mu_insn): New function. (emit_nonvlmax_tumu_insn): Ditto. (emit_nonvlmax_fp_tumu_insn): Ditto. (expand_cond_len_binop): Add condtional len patterns. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add cond tests. * gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_logical_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_logical_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_logical_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_logical_run-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_logical_run-5.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: New test. --- gcc/config/riscv/autovec.md | 107 ++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 90 +++++++++++++-- .../riscv/rvv/autovec/cond/cond_arith-1.c | 48 ++++++++ .../riscv/rvv/autovec/cond/cond_arith-2.c | 27 +++++ .../riscv/rvv/autovec/cond/cond_arith-3.c | 55 +++++++++ .../riscv/rvv/autovec/cond/cond_arith-4.c | 21 ++++ .../riscv/rvv/autovec/cond/cond_arith-5.c | 48 ++++++++ .../riscv/rvv/autovec/cond/cond_arith-6.c | 27 +++++ .../riscv/rvv/autovec/cond/cond_arith-7.c | 50 ++++++++ .../riscv/rvv/autovec/cond/cond_arith-8.c | 64 +++++++++++ .../riscv/rvv/autovec/cond/cond_arith-9.c | 34 ++++++ .../riscv/rvv/autovec/cond/cond_arith_run-1.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_arith_run-2.c | 4 + .../riscv/rvv/autovec/cond/cond_arith_run-3.c | 34 ++++++ .../riscv/rvv/autovec/cond/cond_arith_run-4.c | 4 + .../riscv/rvv/autovec/cond/cond_arith_run-5.c | 34 ++++++ .../riscv/rvv/autovec/cond/cond_arith_run-6.c | 4 + .../riscv/rvv/autovec/cond/cond_arith_run-7.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_arith_run-8.c | 35 ++++++ .../riscv/rvv/autovec/cond/cond_arith_run-9.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_fadd-1.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_fadd-2.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_fadd-3.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_fadd-4.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_fadd_run-1.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_fadd_run-2.c | 31 +++++ .../riscv/rvv/autovec/cond/cond_fadd_run-3.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_fadd_run-4.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_fmax-1.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_fmax-2.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_fmax-3.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_fmax-4.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_fmax_run-1.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_fmax_run-2.c | 31 +++++ .../riscv/rvv/autovec/cond/cond_fmax_run-3.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_fmax_run-4.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_fmin-1.c | 10 ++ .../riscv/rvv/autovec/cond/cond_fmin-2.c | 9 ++ .../riscv/rvv/autovec/cond/cond_fmin-3.c | 9 ++ .../riscv/rvv/autovec/cond/cond_fmin-4.c | 9 ++ .../riscv/rvv/autovec/cond/cond_fmin_run-1.c | 5 + .../riscv/rvv/autovec/cond/cond_fmin_run-2.c | 5 + .../riscv/rvv/autovec/cond/cond_fmin_run-3.c | 5 + .../riscv/rvv/autovec/cond/cond_fmin_run-4.c | 5 + .../riscv/rvv/autovec/cond/cond_fmul-1.c | 29 +++++ .../riscv/rvv/autovec/cond/cond_fmul-2.c | 28 +++++ .../riscv/rvv/autovec/cond/cond_fmul-3.c | 29 +++++ .../riscv/rvv/autovec/cond/cond_fmul-4.c | 29 +++++ .../riscv/rvv/autovec/cond/cond_fmul_run-1.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_fmul_run-2.c | 31 +++++ .../riscv/rvv/autovec/cond/cond_fmul_run-3.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_fmul_run-4.c | 32 ++++++ .../riscv/rvv/autovec/cond/cond_logical-1.c | 43 +++++++ .../riscv/rvv/autovec/cond/cond_logical-2.c | 43 +++++++ .../riscv/rvv/autovec/cond/cond_logical-3.c | 43 +++++++ .../riscv/rvv/autovec/cond/cond_logical-4.c | 43 +++++++ .../riscv/rvv/autovec/cond/cond_logical-5.c | 43 +++++++ .../rvv/autovec/cond/cond_logical_run-1.c | 33 ++++++ .../rvv/autovec/cond/cond_logical_run-2.c | 33 ++++++ .../rvv/autovec/cond/cond_logical_run-3.c | 33 ++++++ .../rvv/autovec/cond/cond_logical_run-4.c | 33 ++++++ .../rvv/autovec/cond/cond_logical_run-5.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_shift-1.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_shift-2.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_shift-3.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_shift-4.c | 33 ++++++ .../riscv/rvv/autovec/cond/cond_shift-5.c | 29 +++++ .../riscv/rvv/autovec/cond/cond_shift-6.c | 27 +++++ .../riscv/rvv/autovec/cond/cond_shift-7.c | 29 +++++ .../riscv/rvv/autovec/cond/cond_shift-8.c | 29 +++++ .../riscv/rvv/autovec/cond/cond_shift-9.c | 29 +++++ .../riscv/rvv/autovec/cond/cond_shift_run-1.c | 27 +++++ .../riscv/rvv/autovec/cond/cond_shift_run-2.c | 28 +++++ .../riscv/rvv/autovec/cond/cond_shift_run-3.c | 27 +++++ .../riscv/rvv/autovec/cond/cond_shift_run-4.c | 27 +++++ .../riscv/rvv/autovec/cond/cond_shift_run-5.c | 28 +++++ .../riscv/rvv/autovec/cond/cond_shift_run-6.c | 28 +++++ .../riscv/rvv/autovec/cond/cond_shift_run-7.c | 28 +++++ .../riscv/rvv/autovec/cond/cond_shift_run-8.c | 28 +++++ .../riscv/rvv/autovec/cond/cond_shift_run-9.c | 28 +++++ gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + 82 files changed, 2499 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index b7ea3101f5a..b5152bc91fd 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1448,6 +1448,45 @@ DONE; }) +;; ------------------------------------------------------------------------- +;; ---- [INT] Conditional binary operations +;; ------------------------------------------------------------------------- +;; Includes: +;; - vsra/vsrl/vsll +;; ------------------------------------------------------------------------- + +(define_expand "cond_" + [(match_operand:VI 0 "register_operand") + (match_operand: 1 "vector_mask_operand") + (any_shift:VI + (match_operand:VI 2 "register_operand") + (match_operand:VI 3 "vector_shift_operand")) + (match_operand:VI 4 "register_operand")] + "TARGET_VECTOR" +{ + /* Normalize into cond_len_* operations. */ + emit_insn (gen_cond_len_ (operands[0], operands[1], operands[2], + operands[3], operands[4], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode), + const0_rtx)); + DONE; +}) + +(define_expand "cond_len_" + [(match_operand:VI 0 "register_operand") + (match_operand: 1 "vector_mask_operand") + (any_shift:VI + (match_operand:VI 2 "register_operand") + (match_operand:VI 3 "vector_shift_operand")) + (match_operand:VI 4 "register_operand") + (match_operand 5 "autovec_length_operand") + (match_operand 6 "const_0_operand")] + "TARGET_VECTOR" +{ + riscv_vector::expand_cond_len_binop (, operands); + DONE; +}) + ;; ------------------------------------------------------------------------- ;; ---- [INT] Conditional binary operations ;; ------------------------------------------------------------------------- @@ -1456,6 +1495,23 @@ ;; - vadd.vi/vsub.vi/... ;; ------------------------------------------------------------------------- +(define_expand "cond_" + [(match_operand:VI 0 "register_operand") + (match_operand: 1 "vector_mask_operand") + (any_int_binop_no_shift:VI + (match_operand:VI 2 "") + (match_operand:VI 3 "")) + (match_operand:VI 4 "register_operand")] + "TARGET_VECTOR" +{ + /* Normalize into cond_len_* operations. */ + emit_insn (gen_cond_len_ (operands[0], operands[1], operands[2], + operands[3], operands[4], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode), + const0_rtx)); + DONE; +}) + (define_expand "cond_len_" [(match_operand:VI 0 "register_operand") (match_operand: 1 "vector_mask_operand") @@ -1479,6 +1535,23 @@ ;; - vfadd.vf/vfsub.vf/... ;; ------------------------------------------------------------------------- +(define_expand "cond_" + [(match_operand:VF 0 "register_operand") + (match_operand: 1 "vector_mask_operand") + (any_float_binop:VF + (match_operand:VF 2 "register_operand") + (match_operand:VF 3 "register_operand")) + (match_operand:VF 4 "register_operand")] + "TARGET_VECTOR" +{ + /* Normalize into cond_len_* operations. */ + emit_insn (gen_cond_len_ (operands[0], operands[1], operands[2], + operands[3], operands[4], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode), + const0_rtx)); + DONE; +}) + (define_expand "cond_len_" [(match_operand:VF 0 "register_operand") (match_operand: 1 "vector_mask_operand") @@ -1500,6 +1573,23 @@ ;; - vfmin.vf/vfmax.vf ;; ------------------------------------------------------------------------- +(define_expand "cond_" + [(match_operand:VF 0 "register_operand") + (match_operand: 1 "vector_mask_operand") + (any_float_binop_nofrm:VF + (match_operand:VF 2 "register_operand") + (match_operand:VF 3 "register_operand")) + (match_operand:VF 4 "register_operand")] + "TARGET_VECTOR" +{ + /* Normalize into cond_len_* operations. */ + emit_insn (gen_cond_len_ (operands[0], operands[1], operands[2], + operands[3], operands[4], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode), + const0_rtx)); + DONE; +}) + (define_expand "cond_len_" [(match_operand:VF 0 "register_operand") (match_operand: 1 "vector_mask_operand") @@ -1522,6 +1612,23 @@ ;; - vfmacc/... ;; ------------------------------------------------------------------------- +(define_expand "cond_fma" + [(match_operand:VF 0 "register_operand") + (match_operand: 1 "vector_mask_operand") + (match_operand:VF 2 "register_operand") + (match_operand:VF 3 "register_operand") + (match_operand:VF 4 "register_operand") + (match_operand:VF 5 "register_operand")] + "TARGET_VECTOR" +{ + /* Normalize into cond_len_* operations. */ + emit_insn (gen_cond_len_fma (operands[0], operands[1], operands[2], + operands[3], operands[4], operands[5], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode), + const0_rtx)); + DONE; +}) + (define_expand "cond_len_fma" [(match_operand:VF 0 "register_operand") (match_operand: 1 "vector_mask_operand") diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 7d8bf2b81f8..a729db44c32 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -186,6 +186,7 @@ enum insn_type RVV_BINOP = 3, RVV_BINOP_MU = RVV_BINOP + 2, RVV_BINOP_TU = RVV_BINOP + 2, + RVV_BINOP_TUMU = RVV_BINOP + 2, RVV_MERGE_OP = 4, RVV_CMP_OP = 4, RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand. */ diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 4cfbcf79801..9e89f970a4c 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -991,6 +991,25 @@ emit_vlmax_masked_mu_insn (unsigned icode, int op_num, rtx *ops) e.emit_insn ((enum insn_code) icode, ops); } +/* This function emits a masked instruction. */ +static void +emit_vlmax_masked_fp_mu_insn (unsigned icode, int op_num, rtx *ops) +{ + machine_mode dest_mode = GET_MODE (ops[0]); + machine_mode mask_mode = get_mask_mode (dest_mode).require (); + insn_expander e (/*OP_NUM*/ op_num, + /*HAS_DEST_P*/ true, + /*FULLY_UNMASKED_P*/ false, + /*USE_REAL_MERGE_P*/ true, + /*HAS_AVL_P*/ true, + /*VLMAX_P*/ true, dest_mode, + mask_mode); + e.set_policy (TAIL_ANY); + e.set_policy (MASK_UNDISTURBED); + e.set_rounding_mode (FRM_DYN); + e.emit_insn ((enum insn_code) icode, ops); +} + /* This function emits a TU instruction. */ static void emit_nonvlmax_tu_insn (unsigned icode, int op_num, rtx *ops, rtx avl) @@ -1030,6 +1049,45 @@ emit_nonvlmax_fp_tu_insn (unsigned icode, int op_num, rtx *ops, rtx avl) e.emit_insn ((enum insn_code) icode, ops); } +/* This function emits a TUMU instruction. */ +static void +emit_nonvlmax_tumu_insn (unsigned icode, int op_num, rtx *ops, rtx avl) +{ + machine_mode dest_mode = GET_MODE (ops[0]); + machine_mode mask_mode = get_mask_mode (dest_mode).require (); + insn_expander e (/*OP_NUM*/ op_num, + /*HAS_DEST_P*/ true, + /*FULLY_UNMASKED_P*/ false, + /*USE_REAL_MERGE_P*/ true, + /*HAS_AVL_P*/ true, + /*VLMAX_P*/ false, dest_mode, + mask_mode); + e.set_policy (TAIL_UNDISTURBED); + e.set_policy (MASK_UNDISTURBED); + e.set_vl (avl); + e.emit_insn ((enum insn_code) icode, ops); +} + +/* This function emits a TUMU instruction. */ +static void +emit_nonvlmax_fp_tumu_insn (unsigned icode, int op_num, rtx *ops, rtx avl) +{ + machine_mode dest_mode = GET_MODE (ops[0]); + machine_mode mask_mode = get_mask_mode (dest_mode).require (); + insn_expander e (/*OP_NUM*/ op_num, + /*HAS_DEST_P*/ true, + /*FULLY_UNMASKED_P*/ false, + /*USE_REAL_MERGE_P*/ true, + /*HAS_AVL_P*/ true, + /*VLMAX_P*/ false, dest_mode, + mask_mode); + e.set_policy (TAIL_UNDISTURBED); + e.set_policy (MASK_UNDISTURBED); + e.set_rounding_mode (FRM_DYN); + e.set_vl (avl); + e.emit_insn ((enum insn_code) icode, ops); +} + /* Emit vmv.s.x instruction. */ void @@ -3272,22 +3330,40 @@ expand_cond_len_binop (rtx_code code, rtx *ops) machine_mode mode = GET_MODE (dest); machine_mode mask_mode = GET_MODE (mask); - poly_uint64 value; + poly_int64 value; bool is_dummy_mask = rtx_equal_p (mask, CONSTM1_RTX (mask_mode)); + bool is_vlmax_len + = poly_int_rtx_p (len, &value) && known_eq (value, GET_MODE_NUNITS (mode)); + rtx cond_ops[] = {dest, mask, merge, src1, src2}; + insn_code icode = code_for_pred (code, mode); if (is_dummy_mask) { /* Use TU, MASK ANY policy. */ - rtx ops[] = {dest, mask, merge, src1, src2}; - insn_code icode = code_for_pred (code, mode); if (needs_fp_rounding (code, mode)) - emit_nonvlmax_fp_tu_insn (icode, RVV_BINOP_TU, ops, len); + emit_nonvlmax_fp_tu_insn (icode, RVV_BINOP_TU, cond_ops, len); else - emit_nonvlmax_tu_insn (icode, RVV_BINOP_TU, ops, len); + emit_nonvlmax_tu_insn (icode, RVV_BINOP_TU, cond_ops, len); } else - /* FIXME: Enable this case when we support it in the middle-end. */ - gcc_unreachable (); + { + if (is_vlmax_len) + { + /* Use TAIL ANY, MU policy. */ + if (needs_fp_rounding (code, mode)) + emit_vlmax_masked_fp_mu_insn (icode, RVV_BINOP_TU, cond_ops); + else + emit_vlmax_masked_mu_insn (icode, RVV_BINOP_TU, cond_ops); + } + else + { + /* Use TU, MU policy. */ + if (needs_fp_rounding (code, mode)) + emit_nonvlmax_fp_tumu_insn (icode, RVV_BINOP_TUMU, cond_ops, len); + else + emit_nonvlmax_tumu_insn (icode, RVV_BINOP_TUMU, cond_ops, len); + } + } } /* Prepare insn_code for gather_load/scatter_store according to diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c new file mode 100644 index 00000000000..e05226cb2e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ + +#include + +#define TEST(TYPE, NAME, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, TYPE *__restrict y, \ + TYPE *__restrict z, TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? y[i] OP z[i] : y[i]; \ + } + +#define TEST_TYPE(TYPE) \ + TEST (TYPE, add, +) \ + TEST (TYPE, sub, -) \ + TEST (TYPE, mul, *) \ + TEST (TYPE, div, /) + +#define TEST_ALL \ + TEST_TYPE (int8_t) \ + TEST_TYPE (uint8_t) \ + TEST_TYPE (int16_t) \ + TEST_TYPE (uint16_t) \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) \ + TEST_TYPE (_Float16) \ + TEST_TYPE (float) \ + TEST_TYPE (double) + +TEST_ALL + +/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_ADD" 11 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_SUB" 11 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_MUL" 11 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_RDIV" 3 "optimized" } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c new file mode 100644 index 00000000000..2b73536b13a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ + +#include "cond_arith-1.c" + +/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_ADD" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_SUB" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_MUL" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_ADD" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_SUB" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_MUL" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 3 "optimized" } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c new file mode 100644 index 00000000000..5fdeb3837ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ + +#include + +#define TEST(DATA_TYPE, PRED_TYPE, NAME, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##DATA_TYPE##_##PRED_TYPE##_##NAME (DATA_TYPE *__restrict x, \ + DATA_TYPE *__restrict y, \ + DATA_TYPE *__restrict z, \ + PRED_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? y[i] OP z[i] : y[i]; \ + } + +#define TEST_TYPE(DATA_TYPE, PRED_TYPE) \ + TEST (DATA_TYPE, PRED_TYPE, add, +) \ + TEST (DATA_TYPE, PRED_TYPE, sub, -) \ + TEST (DATA_TYPE, PRED_TYPE, mul, *) \ + TEST (DATA_TYPE, PRED_TYPE, div, /) + +#define TEST_ALL \ + TEST_TYPE (int32_t, int8_t) \ + TEST_TYPE (uint32_t, int8_t) \ + TEST_TYPE (int32_t, int16_t) \ + TEST_TYPE (uint32_t, int16_t) \ + TEST_TYPE (int64_t, int8_t) \ + TEST_TYPE (uint64_t, int8_t) \ + TEST_TYPE (int64_t, int16_t) \ + TEST_TYPE (uint64_t, int16_t) \ + TEST_TYPE (int64_t, int32_t) \ + TEST_TYPE (uint64_t, int32_t) \ + TEST_TYPE (_Float16, int8_t) \ + TEST_TYPE (float, int8_t) \ + TEST_TYPE (float, int16_t) \ + TEST_TYPE (double, int8_t) \ + TEST_TYPE (double, int16_t) \ + TEST_TYPE (double, int32_t) + +TEST_ALL + +/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 10 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_ADD" 16 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_SUB" 16 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_MUL" 16 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_RDIV" 6 "optimized" } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */ +/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */ +/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c new file mode 100644 index 00000000000..0cbe9bbb479 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ + +#include "cond_arith-3.c" + +/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 10 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_ADD" 10 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_SUB" 10 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_MUL" 10 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 6 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 6 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 6 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */ +/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */ +/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c new file mode 100644 index 00000000000..cf9c95066c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ + +#include + +#define TEST(TYPE, NAME, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, TYPE *__restrict y, \ + TYPE *__restrict z, TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? y[i] OP z[i] : 1; \ + } + +#define TEST_TYPE(TYPE) \ + TEST (TYPE, add, +) \ + TEST (TYPE, sub, -) \ + TEST (TYPE, mul, *) \ + TEST (TYPE, div, /) + +#define TEST_ALL \ + TEST_TYPE (int8_t) \ + TEST_TYPE (uint8_t) \ + TEST_TYPE (int16_t) \ + TEST_TYPE (uint16_t) \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) \ + TEST_TYPE (_Float16) \ + TEST_TYPE (float) \ + TEST_TYPE (double) + +TEST_ALL + +/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_ADD" 11 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_SUB" 11 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_MUL" 11 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_RDIV" 3 "optimized" } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c new file mode 100644 index 00000000000..487cf51a411 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ + +#include "cond_arith-5.c" + +/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_ADD" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_SUB" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_MUL" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_ADD" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_SUB" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_MUL" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 3 "optimized" } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c new file mode 100644 index 00000000000..8d4fa880710 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ + +#include + +#define TEST(TYPE, NAME, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, TYPE *__restrict y, TYPE z1, \ + TYPE z2, TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; i += 2) \ + { \ + x[i] = (pred[i] != 1 ? y[i] OP z1 : y[i]); \ + x[i + 1] = (pred[i + 1] != 1 ? y[i + 1] OP z2 : y[i + 1]); \ + } \ + } + +#define TEST_TYPE(TYPE) \ + TEST (TYPE, add, +) \ + TEST (TYPE, sub, -) \ + TEST (TYPE, mul, *) \ + TEST (TYPE, div, /) + +#define TEST_ALL \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) \ + TEST_TYPE (_Float16) \ + TEST_TYPE (float) \ + TEST_TYPE (double) + +TEST_ALL + +/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 4 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_ADD" 4 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_SUB" 4 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 3 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_MUL" 4 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 3 "optimized" } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c new file mode 100644 index 00000000000..d191d4cebab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ + +#include + +#define TEST(DATA_TYPE, OTHER_TYPE, NAME, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##DATA_TYPE##_##OTHER_TYPE##_##NAME (DATA_TYPE *__restrict x, \ + DATA_TYPE *__restrict y, \ + DATA_TYPE z1, DATA_TYPE z2, \ + DATA_TYPE *__restrict pred, \ + OTHER_TYPE *__restrict foo, int n) \ + { \ + for (int i = 0; i < n; i += 2) \ + { \ + x[i] = (pred[i] != 1 ? y[i] OP z1 : y[i]); \ + x[i + 1] = (pred[i + 1] != 1 ? y[i + 1] OP z2 : y[i + 1]); \ + foo[i] += 1; \ + foo[i + 1] += 2; \ + } \ + } + +#define TEST_TYPE(DATA_TYPE, OTHER_TYPE) \ + TEST (DATA_TYPE, OTHER_TYPE, add, +) \ + TEST (DATA_TYPE, OTHER_TYPE, sub, -) \ + TEST (DATA_TYPE, OTHER_TYPE, mul, *) \ + TEST (DATA_TYPE, OTHER_TYPE, div, /) + +#define TEST_ALL \ + TEST_TYPE (int32_t, int8_t) \ + TEST_TYPE (int32_t, int16_t) \ + TEST_TYPE (uint32_t, int8_t) \ + TEST_TYPE (uint32_t, int16_t) \ + TEST_TYPE (int64_t, int8_t) \ + TEST_TYPE (int64_t, int16_t) \ + TEST_TYPE (int64_t, int32_t) \ + TEST_TYPE (uint64_t, int8_t) \ + TEST_TYPE (uint64_t, int16_t) \ + TEST_TYPE (uint64_t, int32_t) \ + TEST_TYPE (_Float16, int8_t) \ + TEST_TYPE (float, int8_t) \ + TEST_TYPE (float, int16_t) \ + TEST_TYPE (double, int8_t) \ + TEST_TYPE (double, int16_t) \ + TEST_TYPE (double, int32_t) + +TEST_ALL + +/* { dg-final { scan-tree-dump-times "\.COND_ADD" 40 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_SUB" 40 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_MUL" 40 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 22 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 22 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 22 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 40 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 22 "optimized" } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+} 104 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 40 } } */ +/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 40 } } */ +/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 40 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */ +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c new file mode 100644 index 00000000000..38bb613c67e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized-details" } */ + +#include + +#define TEST(TYPE, NAME, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, TYPE *__restrict y, \ + TYPE *__restrict z, TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < 128; ++i) \ + x[i] = pred[i] != 1 ? y[i] OP z[i] : y[i]; \ + } + +#define TEST_TYPE(TYPE) \ + TEST (TYPE, add, +) \ + TEST (TYPE, sub, -) \ + TEST (TYPE, mul, *) \ + TEST (TYPE, div, /) + +#define TEST_ALL \ + TEST_TYPE (int8_t) \ + TEST_TYPE (uint8_t) \ + TEST_TYPE (int16_t) \ + TEST_TYPE (uint16_t) \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) \ + TEST_TYPE (_Float16) \ + TEST_TYPE (float) \ + TEST_TYPE (double) + +TEST_ALL diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c new file mode 100644 index 00000000000..9d0ba59ba82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_arith-1.c" + +#define N 99 + +#undef TEST +#define TEST(TYPE, NAME, OP) \ + { \ + TYPE x[N], y[N], z[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + z[i] = ((i + 2) % 3) * (i + 1); \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, z, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? y[i] OP z[i] : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c new file mode 100644 index 00000000000..608354de60a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_arith_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c new file mode 100644 index 00000000000..20e49e7563a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_arith-3.c" + +#define N 99 + +#undef TEST +#define TEST(DATA_TYPE, PRED_TYPE, NAME, OP) \ + { \ + DATA_TYPE x[N], y[N], z[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + z[i] = ((i + 2) % 3) * (i + 1); \ + pred[i] = i % 3; \ + } \ + test_##DATA_TYPE##_##PRED_TYPE##_##NAME (x, y, z, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + DATA_TYPE expected = i % 3 != 1 ? y[i] OP z[i] : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c new file mode 100644 index 00000000000..a47243c0f8a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_arith_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c new file mode 100644 index 00000000000..e4cb7a66438 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_arith-5.c" + +#define N 99 + +#undef TEST +#define TEST(TYPE, NAME, OP) \ + { \ + TYPE x[N], y[N], z[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + x[i] = -1; \ + y[i] = i * i; \ + z[i] = ((i + 2) % 3) * (i + 1); \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, z, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? y[i] OP z[i] : 1; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c new file mode 100644 index 00000000000..717790de0ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_arith_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c new file mode 100644 index 00000000000..a49525f296c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_arith-7.c" + +#define N 98 + +#undef TEST +#define TEST(TYPE, NAME, OP) \ + { \ + TYPE x[N], y[N], pred[N], z[2] = { 5, 7 }; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, z[0], z[1], pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? y[i] OP z[i & 1] : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c new file mode 100644 index 00000000000..3f06a213591 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_arith-8.c" + +#define N 98 + +#undef TEST +#define TEST(DATA_TYPE, OTHER_TYPE, NAME, OP) \ + { \ + DATA_TYPE x[N], y[N], pred[N], z[2] = { 5, 7 }; \ + OTHER_TYPE foo[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + foo[i] = i * 5; \ + } \ + test_##DATA_TYPE##_##OTHER_TYPE##_##NAME (x, y, z[0], z[1], \ + pred, foo, N); \ + for (int i = 0; i < N; ++i) \ + { \ + DATA_TYPE expected = i % 3 != 1 ? y[i] OP z[i & 1] : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c new file mode 100644 index 00000000000..280479df542 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */ + +#include "cond_arith-9.c" + +#define N 128 + +#undef TEST +#define TEST(TYPE, NAME, OP) \ + { \ + TYPE x[N], y[N], z[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + z[i] = ((i + 2) % 3) * (i + 1); \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, z, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? y[i] OP z[i] : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c new file mode 100644 index 00000000000..11c5c54309b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? y[i] + (TYPE) CONST : y[i]; \ + } + +#define TEST_TYPE(T, TYPE, PRED_TYPE) \ + T (TYPE, PRED_TYPE, half, 0.5) \ + T (TYPE, PRED_TYPE, one, 1.0) \ + T (TYPE, PRED_TYPE, two, 2.0) \ + T (TYPE, PRED_TYPE, minus_half, -0.5) \ + T (TYPE, PRED_TYPE, minus_one, -1.0) \ + T (TYPE, PRED_TYPE, minus_two, -2.0) + +#define TEST_ALL(T) \ + TEST_TYPE (T, _Float16, int16_t) \ + TEST_TYPE (T, float, int32_t) \ + TEST_TYPE (T, double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c new file mode 100644 index 00000000000..e992459a7b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + TYPE *__restrict z, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = y[i] < 8 ? z[i] + (TYPE) CONST : y[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, half, 0.5) \ + T (TYPE, one, 1.0) \ + T (TYPE, two, 2.0) \ + T (TYPE, minus_half, -0.5) \ + T (TYPE, minus_one, -1.0) \ + T (TYPE, minus_two, -2.0) + +#define TEST_ALL(T) \ + TEST_TYPE (T, float) \ + TEST_TYPE (T, double) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c new file mode 100644 index 00000000000..f940d64742e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? y[i] + (TYPE) CONST : 4; \ + } + +#define TEST_TYPE(T, TYPE, PRED_TYPE) \ + T (TYPE, PRED_TYPE, half, 0.5) \ + T (TYPE, PRED_TYPE, one, 1.0) \ + T (TYPE, PRED_TYPE, two, 2.0) \ + T (TYPE, PRED_TYPE, minus_half, -0.5) \ + T (TYPE, PRED_TYPE, minus_one, -1.0) \ + T (TYPE, PRED_TYPE, minus_two, -2.0) + +#define TEST_ALL(T) \ + TEST_TYPE (T, _Float16, int16_t) \ + TEST_TYPE (T, float, int32_t) \ + TEST_TYPE (T, double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c new file mode 100644 index 00000000000..e4f3e823819 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? y[i] + (TYPE) CONST : 0; \ + } + +#define TEST_TYPE(T, TYPE, PRED_TYPE) \ + T (TYPE, PRED_TYPE, half, 0.5) \ + T (TYPE, PRED_TYPE, one, 1.0) \ + T (TYPE, PRED_TYPE, two, 2.0) \ + T (TYPE, PRED_TYPE, minus_half, -0.5) \ + T (TYPE, PRED_TYPE, minus_one, -1.0) \ + T (TYPE, PRED_TYPE, minus_two, -2.0) + +#define TEST_ALL(T) \ + TEST_TYPE (T, _Float16, int16_t) \ + TEST_TYPE (T, float, int32_t) \ + TEST_TYPE (T, double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c new file mode 100644 index 00000000000..4ceedeb8a72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_fadd-1.c" + +#define N 99 + +#define TEST_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? y[i] + (TYPE) CONST : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c new file mode 100644 index 00000000000..d10c42c373b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_fadd-2.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N], z[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i % 13; \ + z[i] = i * i; \ + } \ + test_##TYPE##_##NAME (x, y, z, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = y[i] < 8 ? z[i] + (TYPE) CONST : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c new file mode 100644 index 00000000000..7ee291b4951 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_fadd-3.c" + +#define N 99 + +#define TEST_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? y[i] + (TYPE) CONST : 4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c new file mode 100644 index 00000000000..2502b6014a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_fadd-4.c" + +#define N 99 + +#define TEST_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? y[i] + (TYPE) CONST : 0; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c new file mode 100644 index 00000000000..fe37794afeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include + +#ifndef FN +#define FN(X) __builtin_fmax##X +#endif + +#define DEF_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? FN (y[i], CONST) : y[i]; \ + } + +#define TEST_TYPE(T, FN, TYPE, PRED_TYPE) \ + T (FN, TYPE, PRED_TYPE, zero, 0) \ + T (FN, TYPE, PRED_TYPE, one, 1) \ + T (FN, TYPE, PRED_TYPE, two, 2) + +#define TEST_ALL(T) \ + TEST_TYPE (T, FN (f16), _Float16, int16_t) \ + TEST_TYPE (T, FN (f32), float, int32_t) \ + TEST_TYPE (T, FN (f64), double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c new file mode 100644 index 00000000000..f25562b22dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include + +#ifndef FN +#define FN(X) __builtin_fmax##X +#endif + +#define DEF_LOOP(FN, TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + TYPE *__restrict z, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = y[i] < 8 ? FN (z[i], CONST) : y[i]; \ + } + +#define TEST_TYPE(T, FN, TYPE) \ + T (FN, TYPE, zero, 0) \ + T (FN, TYPE, one, 1) \ + T (FN, TYPE, two, 2) + +#define TEST_ALL(T) \ + TEST_TYPE (T, FN (f32), float) \ + TEST_TYPE (T, FN (f64), double) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c new file mode 100644 index 00000000000..a23f4916caa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include + +#ifndef FN +#define FN(X) __builtin_fmax##X +#endif + +#define DEF_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? FN (y[i], CONST) : 4; \ + } + +#define TEST_TYPE(T, FN, TYPE, PRED_TYPE) \ + T (FN, TYPE, PRED_TYPE, zero, 0) \ + T (FN, TYPE, PRED_TYPE, one, 1) \ + T (FN, TYPE, PRED_TYPE, two, 2) + +#define TEST_ALL(T) \ + TEST_TYPE (T, FN (f16), _Float16, int16_t) \ + TEST_TYPE (T, FN (f32), float, int32_t) \ + TEST_TYPE (T, FN (f64), double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c new file mode 100644 index 00000000000..79e4771eaf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include + +#ifndef FN +#define FN(X) __builtin_fmax##X +#endif + +#define DEF_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? FN (y[i], CONST) : 0; \ + } + +#define TEST_TYPE(T, FN, TYPE, PRED_TYPE) \ + T (FN, TYPE, PRED_TYPE, zero, 0) \ + T (FN, TYPE, PRED_TYPE, one, 1) \ + T (FN, TYPE, PRED_TYPE, two, 2) + +#define TEST_ALL(T) \ + TEST_TYPE (T, FN (f16), _Float16, int16_t) \ + TEST_TYPE (T, FN (f32), float, int32_t) \ + TEST_TYPE (T, FN (f64), double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c new file mode 100644 index 00000000000..bbf04f61daa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_fmax-1.c" + +#define N 99 + +#define TEST_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? FN (y[i], CONST) : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c new file mode 100644 index 00000000000..ae2740f3bfe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_fmax-2.c" + +#define N 99 + +#define TEST_LOOP(FN, TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N], z[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i % 13; \ + z[i] = i * i; \ + } \ + test_##TYPE##_##NAME (x, y, z, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = y[i] < 8 ? FN (z[i], CONST) : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c new file mode 100644 index 00000000000..d02eba1bf71 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_fmax-3.c" + +#define N 99 + +#define TEST_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? FN (y[i], CONST) : 4; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c new file mode 100644 index 00000000000..608a3dd0fea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_fmax-4.c" + +#define N 99 + +#define TEST_LOOP(FN, TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? FN (y[i], CONST) : 0; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c new file mode 100644 index 00000000000..f1596409312 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include + +#define FN(X) __builtin_fmin##X +#include "cond_fmax-1.c" + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c new file mode 100644 index 00000000000..7c8c79ee251 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include + +#define FN(X) __builtin_fmin##X +#include "cond_fmax-2.c" + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c new file mode 100644 index 00000000000..aee0e3572b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include + +#define FN(X) __builtin_fmin##X +#include "cond_fmax-3.c" + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c new file mode 100644 index 00000000000..223c8a6938b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include + +#define FN(X) __builtin_fmin##X +#include "cond_fmax-4.c" + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c new file mode 100644 index 00000000000..31fa50aea18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c @@ -0,0 +1,5 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmax_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c new file mode 100644 index 00000000000..13b21896c2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c @@ -0,0 +1,5 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmax_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c new file mode 100644 index 00000000000..61e347bb09e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c @@ -0,0 +1,5 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmax_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c new file mode 100644 index 00000000000..4921464c8dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c @@ -0,0 +1,5 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#define FN(X) __builtin_fmin##X +#include "cond_fmax_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c new file mode 100644 index 00000000000..94cec7ff0b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? y[i] * (TYPE) CONST : y[i]; \ + } + +#define TEST_TYPE(T, TYPE, PRED_TYPE) \ + T (TYPE, PRED_TYPE, half, 0.5) \ + T (TYPE, PRED_TYPE, two, 2.0) \ + T (TYPE, PRED_TYPE, four, 4.0) + +#define TEST_ALL(T) \ + TEST_TYPE (T, _Float16, int16_t) \ + TEST_TYPE (T, float, int32_t) \ + TEST_TYPE (T, double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c new file mode 100644 index 00000000000..c8ada38c002 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + TYPE *__restrict z, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = y[i] < 8 ? z[i] * (TYPE) CONST : y[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, half, 0.5) \ + T (TYPE, two, 2.0) \ + T (TYPE, four, 4.0) + +#define TEST_ALL(T) \ + TEST_TYPE (T, float) \ + TEST_TYPE (T, double) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c new file mode 100644 index 00000000000..bd325ea84ee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? y[i] * (TYPE) CONST : 8; \ + } + +#define TEST_TYPE(T, TYPE, PRED_TYPE) \ + T (TYPE, PRED_TYPE, half, 0.5) \ + T (TYPE, PRED_TYPE, two, 2.0) \ + T (TYPE, PRED_TYPE, four, 4.0) + +#define TEST_ALL(T) \ + TEST_TYPE (T, _Float16, int16_t) \ + TEST_TYPE (T, float, int32_t) \ + TEST_TYPE (T, double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c new file mode 100644 index 00000000000..118c9a40e8f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict x, \ + TYPE *__restrict y, \ + PRED_TYPE *__restrict pred, \ + int n) \ + { \ + for (int i = 0; i < n; ++i) \ + x[i] = pred[i] != 1 ? y[i] * (TYPE) CONST : 0; \ + } + +#define TEST_TYPE(T, TYPE, PRED_TYPE) \ + T (TYPE, PRED_TYPE, half, 0.5) \ + T (TYPE, PRED_TYPE, two, 2.0) \ + T (TYPE, PRED_TYPE, four, 4.0) + +#define TEST_ALL(T) \ + TEST_TYPE (T, _Float16, int16_t) \ + TEST_TYPE (T, float, int32_t) \ + TEST_TYPE (T, double, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c new file mode 100644 index 00000000000..49290a878d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_fmul-1.c" + +#define N 99 + +#define TEST_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? y[i] * (TYPE) CONST : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c new file mode 100644 index 00000000000..f25a24cdb9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_fmul-2.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N], z[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i % 13; \ + z[i] = i * i; \ + } \ + test_##TYPE##_##NAME (x, y, z, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = y[i] < 8 ? z[i] * (TYPE) CONST : y[i]; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c new file mode 100644 index 00000000000..fc958e1f02e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_fmul-3.c" + +#define N 99 + +#define TEST_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? y[i] * (TYPE) CONST : 8; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c new file mode 100644 index 00000000000..692f4cd394c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_fmul-4.c" + +#define N 99 + +#define TEST_LOOP(TYPE, PRED_TYPE, NAME, CONST) \ + { \ + TYPE x[N], y[N]; \ + PRED_TYPE pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + y[i] = i * i; \ + pred[i] = i % 3; \ + } \ + test_##TYPE##_##NAME (x, y, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = i % 3 != 1 ? y[i] * (TYPE) CONST : 0; \ + if (x[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c new file mode 100644 index 00000000000..af1a2614f52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define bit_and(A, B) ((A) & (B)) +#define bit_or(A, B) ((A) | (B)) +#define bit_xor(A, B) ((A) ^ (B)) +#define bit_bic(A, B) ((A) & ~(B)) + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE##_##OP (TYPE *__restrict r, \ + TYPE *__restrict a, \ + TYPE *__restrict b, \ + TYPE *__restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] < 20 ? OP (b[i], c[i]) : b[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, bit_and) \ + T (TYPE, bit_or) \ + T (TYPE, bit_xor) \ + T (TYPE, bit_bic) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, uint8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, uint16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c new file mode 100644 index 00000000000..5f7614dd092 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define bit_and(A, B) ((A) & (B)) +#define bit_or(A, B) ((A) | (B)) +#define bit_xor(A, B) ((A) ^ (B)) +#define bit_bic(A, B) ((A) & ~(B)) + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE##_##OP (TYPE *__restrict r, \ + TYPE *__restrict a, \ + TYPE *__restrict b, \ + TYPE *__restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] < 20 ? OP (b[i], c[i]) : c[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, bit_and) \ + T (TYPE, bit_or) \ + T (TYPE, bit_xor) \ + T (TYPE, bit_bic) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, uint8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, uint16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c new file mode 100644 index 00000000000..032d12c393f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define bit_and(A, B) ((A) & (B)) +#define bit_or(A, B) ((A) | (B)) +#define bit_xor(A, B) ((A) ^ (B)) +#define bit_bic(A, B) ((A) & ~(B)) + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE##_##OP (TYPE *__restrict r, \ + TYPE *__restrict a, \ + TYPE *__restrict b, \ + TYPE *__restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] < 20 ? OP (b[i], c[i]) : a[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, bit_and) \ + T (TYPE, bit_or) \ + T (TYPE, bit_xor) \ + T (TYPE, bit_bic) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, uint8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, uint16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c new file mode 100644 index 00000000000..e8d93377861 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define bit_and(A, B) ((A) & (B)) +#define bit_or(A, B) ((A) | (B)) +#define bit_xor(A, B) ((A) ^ (B)) +#define bit_bic(A, B) ((A) & ~(B)) + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE##_##OP (TYPE *__restrict r, \ + TYPE *__restrict a, \ + TYPE *__restrict b, \ + TYPE *__restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] < 20 ? OP (b[i], c[i]) : 42; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, bit_and) \ + T (TYPE, bit_or) \ + T (TYPE, bit_xor) \ + T (TYPE, bit_bic) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, uint8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, uint16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c new file mode 100644 index 00000000000..c59ef510fd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define bit_and(A, B) ((A) & (B)) +#define bit_or(A, B) ((A) | (B)) +#define bit_xor(A, B) ((A) ^ (B)) +#define bit_bic(A, B) ((A) & ~(B)) + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE##_##OP (TYPE *__restrict r, \ + TYPE *__restrict a, \ + TYPE *__restrict b, \ + TYPE *__restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] < 20 ? OP (b[i], c[i]) : 0; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, bit_and) \ + T (TYPE, bit_or) \ + T (TYPE, bit_xor) \ + T (TYPE, bit_bic) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, uint8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, uint16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-1.c new file mode 100644 index 00000000000..e741f7d6aac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-1.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_logical-1.c" + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], b[N], c[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + c[i] = ((i + 2) % 3) * (i + 1); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, b, c, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = a[i] < 20 ? OP (b[i], c[i]) : b[i]; \ + if (r[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-2.c new file mode 100644 index 00000000000..bdd697ec991 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-2.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_logical-2.c" + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], b[N], c[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + c[i] = ((i + 2) % 3) * (i + 1); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, b, c, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = a[i] < 20 ? OP (b[i], c[i]) : c[i]; \ + if (r[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-3.c new file mode 100644 index 00000000000..b48bcb19d26 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-3.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_logical-3.c" + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], b[N], c[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + c[i] = ((i + 2) % 3) * (i + 1); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, b, c, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = a[i] < 20 ? OP (b[i], c[i]) : a[i]; \ + if (r[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-4.c new file mode 100644 index 00000000000..0d04e69177f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-4.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_logical-4.c" + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], b[N], c[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + c[i] = ((i + 2) % 3) * (i + 1); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, b, c, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = a[i] < 20 ? OP (b[i], c[i]) : 42; \ + if (r[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-5.c new file mode 100644 index 00000000000..87501057c20 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-5.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_logical-5.c" + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], b[N], c[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + c[i] = ((i + 2) % 3) * (i + 1); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, b, c, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = a[i] < 20 ? OP (b[i], c[i]) : 0; \ + if (r[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c new file mode 100644 index 00000000000..6bf25383dee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] > 20 ? b[i] OP 3 : b[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, shl, <<) \ + T (TYPE, shr, >>) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, uint8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, uint16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c new file mode 100644 index 00000000000..2edf38f89bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] > 20 ? b[i] OP 3 : a[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, shl, <<) \ + T (TYPE, shr, >>) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, uint8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, uint16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c new file mode 100644 index 00000000000..84f91ee2668 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] > 20 ? b[i] OP 3 : 72; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, shl, <<) \ + T (TYPE, shr, >>) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, uint8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, uint16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c new file mode 100644 index 00000000000..a4be0b35aaf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] > 20 ? b[i] OP 3 : 0; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, shl, <<) \ + T (TYPE, shr, >>) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, uint8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, uint16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } } */ +/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c new file mode 100644 index 00000000000..06a0a1aaecd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, TYPE *__restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] > 20 ? b[i] OP c[i] : b[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, shl, <<) \ + T (TYPE, shr, >>) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c new file mode 100644 index 00000000000..3b1c4859e05 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, TYPE *__restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] > 20 ? b[i] OP c[i] : c[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, shl, <<) \ + T (TYPE, shr, >>) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c new file mode 100644 index 00000000000..d44cf43eeb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, TYPE *__restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] > 20 ? b[i] OP c[i] : a[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, shl, <<) \ + T (TYPE, shr, >>) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c new file mode 100644 index 00000000000..e68289be5e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, TYPE *__restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] > 20 ? b[i] OP c[i] : 91; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, shl, <<) \ + T (TYPE, shr, >>) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c new file mode 100644 index 00000000000..892bc08407d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include + +#define DEF_LOOP(TYPE, NAME, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, TYPE *__restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] > 20 ? b[i] OP c[i] : 0; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, shl, <<) \ + T (TYPE, shr, >>) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, uint32_t) \ + TEST_TYPE (T, int64_t) \ + TEST_TYPE (T, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c new file mode 100644 index 00000000000..d4ddc1cfa48 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c @@ -0,0 +1,27 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_shift-1.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, OP) \ + { \ + TYPE r[N], a[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##NAME (r, a, b, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE) (a[i] > 20 ? b[i] OP 3 : b[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c new file mode 100644 index 00000000000..a2eb673fbcf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_shift-2.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, OP) \ + { \ + TYPE r[N], a[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##NAME (r, a, b, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE) (a[i] > 20 ? b[i] OP 3 : a[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c new file mode 100644 index 00000000000..e1bb44ed00f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c @@ -0,0 +1,27 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_shift-3.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, OP) \ + { \ + TYPE r[N], a[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##NAME (r, a, b, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE) (a[i] > 20 ? b[i] OP 3 : 72)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c new file mode 100644 index 00000000000..c1bbe6bcc67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c @@ -0,0 +1,27 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_shift-4.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, OP) \ + { \ + TYPE r[N], a[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##NAME (r, a, b, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE) (a[i] > 20 ? b[i] OP 3 : 0)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c new file mode 100644 index 00000000000..ff6b78ce576 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_shift-5.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, OP) \ + { \ + TYPE r[N], a[N], b[N], c[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + c[i] = ~i & 7; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##NAME (r, a, b, c, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE) (a[i] > 20 ? b[i] OP c[i] : b[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c new file mode 100644 index 00000000000..1a3a6e938d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_shift-6.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, OP) \ + { \ + TYPE r[N], a[N], b[N], c[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + c[i] = ~i & 7; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##NAME (r, a, b, c, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE) (a[i] > 20 ? b[i] OP c[i] : c[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c new file mode 100644 index 00000000000..45823c8c888 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_shift-7.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, OP) \ + { \ + TYPE r[N], a[N], b[N], c[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + c[i] = ~i & 7; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##NAME (r, a, b, c, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE) (a[i] > 20 ? b[i] OP c[i] : a[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c new file mode 100644 index 00000000000..dd34df0b4cd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_shift-8.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, OP) \ + { \ + TYPE r[N], a[N], b[N], c[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + c[i] = ~i & 7; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##NAME (r, a, b, c, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE) (a[i] > 20 ? b[i] OP c[i] : 91)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c new file mode 100644 index 00000000000..d822796372b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_shift-9.c" + +#define N 99 + +#define TEST_LOOP(TYPE, NAME, OP) \ + { \ + TYPE r[N], a[N], b[N], c[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i); \ + b[i] = (i >> 4) << (i & 15); \ + c[i] = ~i & 7; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##NAME (r, a, b, c, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE) (a[i] > 20 ? b[i] OP c[i] : 0)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index b41553bc2f5..1bc53cef891 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -75,6 +75,8 @@ foreach op $AUTOVEC_TEST_OPTS { "" "$op" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/reduc/*.\[cS\]]] \ "" "$op" + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/cond/*.\[cS\]]] \ + "" "$op" } # widening operation only test on LMUL < 8