From patchwork Tue Nov 1 16:26:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Monakov X-Patchwork-Id: 13759 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3073107wru; Tue, 1 Nov 2022 09:28:20 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4CP646N4qudqxGtl49KM6t/DTbMHTCNGtbiE89Hs6xY+V3jRflJ2mljMZeCtAwz5UcAuXQ X-Received: by 2002:a17:907:2c6b:b0:7ad:c587:bc5b with SMTP id ib11-20020a1709072c6b00b007adc587bc5bmr13755172ejc.425.1667320100511; Tue, 01 Nov 2022 09:28:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320100; cv=none; d=google.com; s=arc-20160816; b=XYXY6kGpu+V5BYRav5FmN5bilkoMOJzIrHXrudBgB2alBbSuMXv40zk6gl5rsADfTa ggdryAHx9DmpvOcPXxS/S6k7P5rzt0Uy7Gos55LOS00eno9rM51FGkVEHSpVjgRatbqu SxMYQZ65yarWoJIWrT63vJbLYNexP7k4ec++WV1x/job44oxtvx0RVgMIe6mhrsL8Rm3 o6QkKYF1UA2oGquPCB9a4DEwnev8QP7AX99uR1rdeMejbIivbW2xXURzyYdco1tJcrF+ u0Z+ClVf9WgAfQ1Ye9GWRnVBOoSSeWIdsYRLxDWpSLHWB4rZ6gKinnYWzKZH8OuVfXC2 uyxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-filter:dmarc-filter:delivered-to; bh=uQpsFJ4XOl3jkZLwhzNoLxNRGSJ7p1eQ4hZ5UkMl198=; b=O4+vaBL/HbOiwmVt1LUvHEljAWvxeGkKgIfSs9ICyTdvbD6AjJmwaxr9503jMwz4xO XFhnZN4LAv779HrGMoCgRZtvceQ664ScEpYeHZIlSVRq8p5v3orFJPjaSOFsPNIrB4Kf cs3Pl8EpDfHLiCx+C82ohZytEMeDioHtLQO1kWj/0ESh5/QCb/nH0ZViDtxA5rb6IiUA oWQjjCzaud4B7HevIW5puyyvRO2ZxYrUu3LpnVFPZOvtUqmjwZFxGH+iDC+sIRGd+MFs Om5QF1S10NI5AR55qNLTpYswIY12jNOCnOEWwT7N9qJ6IWT5xtAk5mgmKkKIxXvVGHwu l4Xg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ispras.ru Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id i4-20020a17090685c400b0077d1df3967asi8594790ejy.563.2022.11.01.09.28.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 09:28:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ispras.ru Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E637D385355B for ; Tue, 1 Nov 2022 16:27:29 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.ispras.ru (mail.ispras.ru [83.149.199.84]) by sourceware.org (Postfix) with ESMTPS id 197753858D35 for ; Tue, 1 Nov 2022 16:26:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 197753858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=ispras.ru Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ispras.ru Received: from localhost.intra.ispras.ru (unknown [10.10.3.121]) by mail.ispras.ru (Postfix) with ESMTP id DFC20419E9E6; Tue, 1 Nov 2022 16:26:55 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru DFC20419E9E6 From: Alexander Monakov To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/2] i386: correct x87&SSE division modeling in znver.md Date: Tue, 1 Nov 2022 19:26:36 +0300 Message-Id: <20221101162637.14238-2-amonakov@ispras.ru> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221101162637.14238-1-amonakov@ispras.ru> References: <20221101162637.14238-1-amonakov@ispras.ru> MIME-Version: 1.0 X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, MEDICAL_SUBJECT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Monakov , "Joshi, Tejas Sanjay" , =?utf-8?q?Jan_Hubi=C4=8Dka?= Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748311841557481465?= X-GMAIL-MSGID: =?utf-8?q?1748311841557481465?= Correct modeling of division instructions in the SIMD/FP domain for AMD Zen architectures and avoid combinatorial explosion of automaton tables by modeling the separate floating-point division unit and correcting reservations to reflect reciprocal throughput of the corresponding instructions, similar to earlier commit 5cee5f94000 ("i386: correct integer division modeling in znver.md"). Division is partially pipelined and some instructions have fractional throughput (e.g. Zen 3 can issue divss and divsd each 3.5 and 4.5 cycles on average, respectively). Considering these CPUs implement out-of-order execution, the model doesn't need to be exact to the last cycle, so simplify it by using 4/5 cycles for SF/DF modes, and not modeling the fact that FP3 pipe is occupied for one cycle. Top znver table sizes in insn-automata.o: Before: 428108 r znver1_fp_min_issue_delay 856216 r znver1_fp_transitions After: 30056 r znver1_fp_min_issue_delay 120224 r znver1_fp_transitions gcc/ChangeLog: PR target/87832 * config/i386/znver.md (znver1_fdiv): New automaton. (znver1-fdiv): New unit. (znver1_fp_op_div): Correct unit and cycles in the reservation. (znver1_fp_op_div_load): Ditto. (znver1_fp_op_idiv_load): Ditto. (znver2_fp_op_idiv_load): Ditto. (znver1_ssediv_ss_ps): Ditto. (znver1_ssediv_ss_ps_load): Ditto. (znver1_ssediv_sd_pd): Ditto. (znver1_ssediv_sd_pd_load): Ditto. (znver1_ssediv_avx256_ps): Ditto. (znver1_ssediv_avx256_ps_load): Ditto. (znver1_ssediv_avx256_pd): Ditto. (znver1_ssediv_avx256_pd_load): Ditto. --- gcc/config/i386/znver.md | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/gcc/config/i386/znver.md b/gcc/config/i386/znver.md index 4aa098fd8..c52f8b532 100644 --- a/gcc/config/i386/znver.md +++ b/gcc/config/i386/znver.md @@ -24,7 +24,7 @@ (define_attr "znver1_decode" "direct,vector,double" ;; AMD znver1, znver2 and znver3 Scheduling ;; Modeling automatons for zen decoders, integer execution pipes, ;; SIMD/FP domain, AGU pipes, and dividers. -(define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu, znver1_idiv") +(define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu, znver1_idiv, znver1_fdiv") ;; Decoders unit has 4 decoders and all of them can decode fast path ;; and vector type instructions. @@ -95,6 +95,7 @@ (define_reservation "znver2-fvector" "znver1-fp0+znver1-fp1 ;; Dividers (define_cpu_unit "znver1-idiv" "znver1_idiv") +(define_cpu_unit "znver1-fdiv" "znver1_fdiv") ;; Call instruction (define_insn_reservation "znver1_call" 1 @@ -591,27 +592,27 @@ (define_insn_reservation "znver1_fp_op_div" 15 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "type" "fdiv") (eq_attr "memory" "none"))) - "znver1-direct,znver1-fp3*15") + "znver1-direct,znver1-fdiv*6") (define_insn_reservation "znver1_fp_op_div_load" 22 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "type" "fdiv") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,znver1-fp3*15") + "znver1-direct,znver1-load,znver1-fdiv*6") (define_insn_reservation "znver1_fp_op_idiv_load" 27 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "fdiv") (and (eq_attr "fp_int_src" "true") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-fp3*19") + "znver1-double,znver1-load,znver1-fdiv*6") (define_insn_reservation "znver2_fp_op_idiv_load" 26 (and (eq_attr "cpu" "znver2,znver3") (and (eq_attr "type" "fdiv") (and (eq_attr "fp_int_src" "true") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-fp3*19") + "znver1-double,znver1-load,znver1-fdiv*6") ;; MMX, SSE, SSEn.n, AVX, AVX2 instructions @@ -1088,7 +1089,7 @@ (define_insn_reservation "znver1_ssediv_ss_ps" 10 (eq_attr "mode" "V8SF,V4SF,SF"))) (and (eq_attr "type" "ssediv") (eq_attr "memory" "none"))) - "znver1-direct,znver1-fp3*10") + "znver1-direct,znver1-fdiv*4") (define_insn_reservation "znver1_ssediv_ss_ps_load" 17 (and (ior (and (eq_attr "cpu" "znver1") @@ -1099,7 +1100,7 @@ (define_insn_reservation "znver1_ssediv_ss_ps_load" 17 (eq_attr "mode" "V8SF,V4SF,SF"))) (and (eq_attr "type" "ssediv") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,znver1-fp3*10") + "znver1-direct,znver1-load,znver1-fdiv*4") (define_insn_reservation "znver1_ssediv_sd_pd" 13 (and (ior (and (eq_attr "cpu" "znver1") @@ -1110,7 +1111,7 @@ (define_insn_reservation "znver1_ssediv_sd_pd" 13 (eq_attr "mode" "V4DF,V2DF,DF"))) (and (eq_attr "type" "ssediv") (eq_attr "memory" "none"))) - "znver1-direct,znver1-fp3*13") + "znver1-direct,znver1-fdiv*5") (define_insn_reservation "znver1_ssediv_sd_pd_load" 20 (and (ior (and (eq_attr "cpu" "znver1") @@ -1121,35 +1122,35 @@ (define_insn_reservation "znver1_ssediv_sd_pd_load" 20 (eq_attr "mode" "V4DF,V2DF,DF"))) (and (eq_attr "type" "ssediv") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,znver1-fp3*13") + "znver1-direct,znver1-load,znver1-fdiv*5") (define_insn_reservation "znver1_ssediv_avx256_ps" 12 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF") (and (eq_attr "memory" "none") (eq_attr "type" "ssediv")))) - "znver1-double,znver1-fp3*12") + "znver1-double,znver1-fdiv*8") (define_insn_reservation "znver1_ssediv_avx256_ps_load" 19 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF") (and (eq_attr "type" "ssediv") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-fp3*12") + "znver1-double,znver1-load,znver1-fdiv*8") (define_insn_reservation "znver1_ssediv_avx256_pd" 15 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4DF") (and (eq_attr "type" "ssediv") (eq_attr "memory" "none")))) - "znver1-double,znver1-fp3*15") + "znver1-double,znver1-fdiv*10") (define_insn_reservation "znver1_ssediv_avx256_pd_load" 22 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4DF") (and (eq_attr "type" "ssediv") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-fp3*15") + "znver1-double,znver1-load,znver1-fdiv*10") ;; SSE MUL (define_insn_reservation "znver1_ssemul_ss_ps" 3 (and (ior (and (eq_attr "cpu" "znver1") From patchwork Tue Nov 1 16:26:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Monakov X-Patchwork-Id: 13760 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3073716wru; Tue, 1 Nov 2022 09:29:44 -0700 (PDT) X-Google-Smtp-Source: AMsMyM54xz2SNbwzKLspacIK4lbxqkbsWYTw3WSJa0zhPIAgaxy/BILPwUby/6RjgRhutMtMzPzJ X-Received: by 2002:a17:906:33d8:b0:7ad:a195:ce51 with SMTP id w24-20020a17090633d800b007ada195ce51mr18908279eja.365.1667320184607; Tue, 01 Nov 2022 09:29:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667320184; cv=none; d=google.com; s=arc-20160816; b=Rlx/CB7ev6OI6M+czryVwVG0Lk+f8978lR8e/iop8zg93oW4CzsR22wvqDwPTUem2/ vF532hdY2MZbhXEBx5rO7WbnyoHy5o2f99upW53SfTOLxUn4W4s/Nb3B5Aja/+J5j+/s ZK4c5j9b7yO37JLbnRZJEOr8USkKy2PmVTdbmMFWzfxTxffB1X2DVboCk9YGmC8emf7x zh8emBfOr22HvzyXmf5WIYyCnYxlgbHwxUrijhzhlXRrMbMQl3ukOC+dxcWQctQU8MVA Cj8RjeboVXPOl8Qp1ysergz6FsG8DPjz+DywyL9tp0M0C8IhylRQhc4KN+y2ebsvtdYb kh5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-filter:dmarc-filter:delivered-to; bh=MXbwwWm7C0mjyB13V/+LeSh8/kcyQf/KsyuyDAtDd24=; b=VphPXiZ97RfbB3brHhwlB9xzCwlyIgij1EciKQcw6kAg0EsiD+3yzJet6aKQdbufk3 sLDMG+twni4kVwi8shgqhyq/vkFzyqIKdq3onQC/n2oGfp/yr/xnehe9i46EoG4YfopP WHvlf4caN4+TnjKGinMyd0zK8IUYyAmFWqm/jkew46gTg+uwxqOJp9UdmhsS3cbXvIYl 1v/2JMGEX+F2elm4Z+ng22MYajs2lMp5P7HfK/DAe9D+5ZlXWip8Eng4IQSBhJshXKAX ebBWvNJ1sOhI7luxaUjpjQ04tgnnRvOMqcxE8c9ccKp7XVYRDdkbNEOzzJpYKfv5zwSd bmjg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ispras.ru Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id nd30-20020a170907629e00b0078d2848bca9si12916229ejc.704.2022.11.01.09.29.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 09:29:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ispras.ru Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 51AA33865C27 for ; Tue, 1 Nov 2022 16:28:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.ispras.ru (mail.ispras.ru [83.149.199.84]) by sourceware.org (Postfix) with ESMTPS id 480FC3857373 for ; Tue, 1 Nov 2022 16:26:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 480FC3857373 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=ispras.ru Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ispras.ru Received: from localhost.intra.ispras.ru (unknown [10.10.3.121]) by mail.ispras.ru (Postfix) with ESMTP id 0F455419E9EA; Tue, 1 Nov 2022 16:26:57 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 0F455419E9EA From: Alexander Monakov To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/2] i386: correct x87&SSE multiplication modeling in znver.md Date: Tue, 1 Nov 2022 19:26:37 +0300 Message-Id: <20221101162637.14238-3-amonakov@ispras.ru> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221101162637.14238-1-amonakov@ispras.ru> References: <20221101162637.14238-1-amonakov@ispras.ru> MIME-Version: 1.0 X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, MEDICAL_SUBJECT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Monakov , "Joshi, Tejas Sanjay" , =?utf-8?q?Jan_Hubi=C4=8Dka?= Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748311929710575458?= X-GMAIL-MSGID: =?utf-8?q?1748311929710575458?= All multiplication instructions are fully pipelined, except AVX256 instructions on Zen 1, which issue over two cycles on a 128-bit unit. Correct the model accordingly to reduce combinatorial explosion in automaton tables. Top znver table sizes in insn-automata.o: Before: 30056 r znver1_fp_min_issue_delay 120224 r znver1_fp_transitions After: 6720 r znver1_fp_min_issue_delay 53760 r znver1_fp_transitions gcc/ChangeLog: PR target/87832 * config/i386/znver.md: (znver1_fp_op_mul): Correct cycles in the reservation. (znver1_fp_op_mul_load): Ditto. (znver1_mmx_mul): Ditto. (znver1_mmx_load): Ditto. (znver1_ssemul_ss_ps): Ditto. (znver1_ssemul_ss_ps_load): Ditto. (znver1_ssemul_avx256_ps): Ditto. (znver1_ssemul_avx256_ps_load): Ditto. (znver1_ssemul_sd_pd): Ditto. (znver1_ssemul_sd_pd_load): Ditto. (znver2_ssemul_sd_pd): Ditto. (znver2_ssemul_sd_pd_load): Ditto. (znver1_ssemul_avx256_pd): Ditto. (znver1_ssemul_avx256_pd_load): Ditto. (znver1_sseimul): Ditto. (znver1_sseimul_avx256): Ditto. (znver1_sseimul_load): Ditto. (znver1_sseimul_avx256_load): Ditto. (znver1_sseimul_di): Ditto. (znver1_sseimul_load_di): Ditto. --- gcc/config/i386/znver.md | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/gcc/config/i386/znver.md b/gcc/config/i386/znver.md index c52f8b532..882f250f1 100644 --- a/gcc/config/i386/znver.md +++ b/gcc/config/i386/znver.md @@ -573,13 +573,13 @@ (define_insn_reservation "znver1_fp_op_mul" 5 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "type" "fop,fmul") (eq_attr "memory" "none"))) - "znver1-direct,znver1-fp0*5") + "znver1-direct,znver1-fp0") (define_insn_reservation "znver1_fp_op_mul_load" 12 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "type" "fop,fmul") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,znver1-fp0*5") + "znver1-direct,znver1-load,znver1-fp0") (define_insn_reservation "znver1_fp_op_imul_load" 16 (and (eq_attr "cpu" "znver1,znver2,znver3") @@ -684,13 +684,13 @@ (define_insn_reservation "znver1_mmx_mul" 3 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "type" "mmxmul") (eq_attr "memory" "none"))) - "znver1-direct,znver1-fp0*3") + "znver1-direct,znver1-fp0") (define_insn_reservation "znver1_mmx_load" 10 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "type" "mmxmul") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,znver1-fp0*3") + "znver1-direct,znver1-load,znver1-fp0") ;; TODO (define_insn_reservation "znver1_avx256_log" 1 @@ -1161,7 +1161,7 @@ (define_insn_reservation "znver1_ssemul_ss_ps" 3 (eq_attr "mode" "V8SF,V4SF,SF,V4DF,V2DF,DF"))) (and (eq_attr "type" "ssemul") (eq_attr "memory" "none"))) - "znver1-direct,(znver1-fp0|znver1-fp1)*3") + "znver1-direct,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_ssemul_ss_ps_load" 10 (and (ior (and (eq_attr "cpu" "znver1") @@ -1172,47 +1172,47 @@ (define_insn_reservation "znver1_ssemul_ss_ps_load" 10 (eq_attr "mode" "V8SF,V4SF,SF"))) (and (eq_attr "type" "ssemul") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3") + "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_ssemul_avx256_ps" 3 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF") (and (eq_attr "type" "ssemul") (eq_attr "memory" "none")))) - "znver1-double,(znver1-fp0|znver1-fp1)*3") + "znver1-double,znver1-fp0*2|znver1-fp1*2") (define_insn_reservation "znver1_ssemul_avx256_ps_load" 10 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF") (and (eq_attr "type" "ssemul") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*3") + "znver1-double,znver1-load,znver1-fp0*2|znver1-fp1*2") (define_insn_reservation "znver1_ssemul_sd_pd" 4 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V2DF,DF") (and (eq_attr "type" "ssemul") (eq_attr "memory" "none")))) - "znver1-direct,(znver1-fp0|znver1-fp1)*4") + "znver1-direct,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_ssemul_sd_pd_load" 11 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V2DF,DF") (and (eq_attr "type" "ssemul") (eq_attr "memory" "load")))) - "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*4") + "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") (define_insn_reservation "znver2_ssemul_sd_pd" 3 (and (eq_attr "cpu" "znver2,znver3") (and (eq_attr "type" "ssemul") (eq_attr "memory" "none"))) - "znver1-direct,(znver1-fp0|znver1-fp1)*3") + "znver1-direct,znver1-fp0|znver1-fp1") (define_insn_reservation "znver2_ssemul_sd_pd_load" 10 (and (eq_attr "cpu" "znver2,znver3") (and (eq_attr "type" "ssemul") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3") + "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") (define_insn_reservation "znver1_ssemul_avx256_pd" 5 @@ -1220,14 +1220,14 @@ (define_insn_reservation "znver1_ssemul_avx256_pd" 5 (and (eq_attr "mode" "V4DF") (and (eq_attr "type" "ssemul") (eq_attr "memory" "none")))) - "znver1-double,(znver1-fp0|znver1-fp1)*4") + "znver1-double,znver1-fp0*2|znver1-fp1*2") (define_insn_reservation "znver1_ssemul_avx256_pd_load" 12 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4DF") (and (eq_attr "type" "ssemul") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*4") + "znver1-double,znver1-load,znver1-fp0*2|znver1-fp1*2") ;;SSE imul (define_insn_reservation "znver1_sseimul" 3 @@ -1239,14 +1239,14 @@ (define_insn_reservation "znver1_sseimul" 3 (eq_attr "mode" "TI,OI"))) (and (eq_attr "type" "sseimul") (eq_attr "memory" "none"))) - "znver1-direct,znver1-fp0*3") + "znver1-direct,znver1-fp0") (define_insn_reservation "znver1_sseimul_avx256" 4 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "mode" "OI") (and (eq_attr "type" "sseimul") (eq_attr "memory" "none")))) - "znver1-double,znver1-fp0*4") + "znver1-double,znver1-fp0*2") (define_insn_reservation "znver1_sseimul_load" 10 (and (ior (and (eq_attr "cpu" "znver1") @@ -1257,28 +1257,28 @@ (define_insn_reservation "znver1_sseimul_load" 10 (eq_attr "mode" "TI,OI"))) (and (eq_attr "type" "sseimul") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,znver1-fp0*3") + "znver1-direct,znver1-load,znver1-fp0") (define_insn_reservation "znver1_sseimul_avx256_load" 11 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "mode" "OI") (and (eq_attr "type" "sseimul") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-fp0*4") + "znver1-double,znver1-load,znver1-fp0*2") (define_insn_reservation "znver1_sseimul_di" 3 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "mode" "DI") (and (eq_attr "memory" "none") (eq_attr "type" "sseimul")))) - "znver1-direct,znver1-fp0*3") + "znver1-direct,znver1-fp0") (define_insn_reservation "znver1_sseimul_load_di" 10 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "mode" "DI") (and (eq_attr "type" "sseimul") (eq_attr "memory" "load")))) - "znver1-direct,znver1-load,znver1-fp0*3") + "znver1-direct,znver1-load,znver1-fp0") ;; SSE compares (define_insn_reservation "znver1_sse_cmp" 1