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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z17-20020a170906815100b00982c06b45d9si1691849ejw.816.2023.07.27.15.08.03; Thu, 27 Jul 2023 15:08:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=jeNSAkBi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232387AbjG0Vw3 (ORCPT + 99 others); Thu, 27 Jul 2023 17:52:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230319AbjG0VwZ (ORCPT ); Thu, 27 Jul 2023 17:52:25 -0400 Received: from qs51p00im-qukt01071901.me.com (qs51p00im-qukt01071901.me.com [17.57.155.8]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11C952135 for ; Thu, 27 Jul 2023 14:52:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1690494743; bh=VW6b43RiCPE3QnUespHmOiG7y2sCgca0aeMtTf9e+VA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=jeNSAkBiazZ7ilht3HQ5YFI3j8xbybPri4Gwx93zjGM6gERB/RlG9D/BU2Sby0rar QkS3f0chejbRn0YoL3AbGH37tMzDmlVtnsyNXAjPMmdmfEhHciIqqVTm+PJk6rMYXw 5P51tD2JQagfSjN3DDTTwF1uO/Bl8u6M7qV69nj5rxa5vW0dqkYBvP8dE4B2oAIMpn QGSwcIEFuubCPQI0i8KjChVkht68n/th/kGpsvipG9mpTtLDl/LcTySMATexgJaA+i m6rS80NBdk8yIDc1Y56Mcj0fsmmHF2QmhZzjGRFisswV8tlvlSJBHQZquvGbj/SUjt L5UG69zmA5FCA== Received: from localhost (qs51p00im-dlb-asmtp-mailmevip.me.com [17.57.155.28]) by qs51p00im-qukt01071901.me.com (Postfix) with ESMTPSA id 8D7C46280983; Thu, 27 Jul 2023 21:52:22 +0000 (UTC) From: Alain Volmat To: Alain Volmat , David Airlie , Daniel Vetter , Philipp Zabel Cc: Alain Volmat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 01/14] drm/sti: add hdmi tx6g0c28 phy for STi platform Date: Thu, 27 Jul 2023 21:51:25 +0000 Message-Id: <20230727215141.53910-2-avolmat@me.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727215141.53910-1-avolmat@me.com> References: <20230727215141.53910-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: v5HQ8jZsSIpQLpsIVn4-AcK87utIRtUT X-Proofpoint-GUID: v5HQ8jZsSIpQLpsIVn4-AcK87utIRtUT X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E170-?= =?utf-8?q?22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E138=2C18=2E0?= =?utf-8?q?=2E790=2C17=2E11=2E62=2E513=2E0000000_definitions=3D2022-01-12=5F?= =?utf-8?q?02=3A2020-02-14=5F02=2C2022-01-12=5F02=2C2021-12-02=5F01_signatur?= =?utf-8?q?es=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 mlxscore=0 clxscore=1015 malwarescore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2307270199 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_SBL_A autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772613227518298232 X-GMAIL-MSGID: 1772613227518298232 Addition of the HDMI TX PHY driver for use in the STiH418 SoC platform and more especially the 4KOpen (B2264) board. Signed-off-by: Alain Volmat --- drivers/gpu/drm/sti/Makefile | 1 + drivers/gpu/drm/sti/sti_hdmi.c | 4 + drivers/gpu/drm/sti/sti_hdmi_tx6g0c28phy.c | 292 +++++++++++++++++++++ drivers/gpu/drm/sti/sti_hdmi_tx6g0c28phy.h | 13 + 4 files changed, 310 insertions(+) create mode 100644 drivers/gpu/drm/sti/sti_hdmi_tx6g0c28phy.c create mode 100644 drivers/gpu/drm/sti/sti_hdmi_tx6g0c28phy.h diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile index f203ac5514ae..bf52edb7dba5 100644 --- a/drivers/gpu/drm/sti/Makefile +++ b/drivers/gpu/drm/sti/Makefile @@ -11,6 +11,7 @@ sti-drm-y := \ sti_plane.o \ sti_hdmi.o \ sti_hdmi_tx3g4c28phy.o \ + sti_hdmi_tx6g0c28phy.o \ sti_dvo.o \ sti_awg_utils.o \ sti_vtg.o \ diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c index 500936d5743c..988a5de0fcd2 100644 --- a/drivers/gpu/drm/sti/sti_hdmi.c +++ b/drivers/gpu/drm/sti/sti_hdmi.c @@ -27,6 +27,7 @@ #include "sti_hdmi.h" #include "sti_hdmi_tx3g4c28phy.h" +#include "sti_hdmi_tx6g0c28phy.h" #include "sti_vtg.h" #define HDMI_CFG 0x0000 @@ -1363,6 +1364,9 @@ static const struct of_device_id hdmi_of_match[] = { { .compatible = "st,stih407-hdmi", .data = &tx3g4c28phy_ops, + }, { + .compatible = "st,stih418-hdmi", + .data = &tx6g0c28phy_ops, }, { /* end node */ } diff --git a/drivers/gpu/drm/sti/sti_hdmi_tx6g0c28phy.c b/drivers/gpu/drm/sti/sti_hdmi_tx6g0c28phy.c new file mode 100644 index 000000000000..7bd260429044 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_hdmi_tx6g0c28phy.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author: Alain Volmat + * + * This driver is highly inspired from sti_hdmi_tx3g4c28phy.c copyright by ST Microelectronics + * with IP behavior understood by looking at the display package from 4kopen.com + * https://bitbucket.org/4kopen/display/src/master/display/ip/hdmi/stmhdmitx6g0_c28_phy.cpp + */ + +#include +#include +#include +#include + +#include "sti_hdmi_tx6g0c28phy.h" + +#define HDMI_SRZ_CFG 0x504 +#define HDMI_SRZ_PWR_CFG 0x508 +#define HDMI_SRZ_PLL_CFG 0x510 +#define HDMI_SRZ_STR_1 0x518 +#define HDMI_SRZ_STR_2 0x51C +#define HDMI_SRZ_CALCODE_EXT 0x530 +#define HDMI_SRZ_TX_RSVR_BITS 0x560 + +/* ******************************* */ +/* register : HDMI_SRZ_CFG */ +/* ******************************* */ +#define HDMI_SRZ_CFG_EN BIT(0) +#define HDMI_SRZ_CFG_EN_PE_C0_MASK GENMASK(6, 4) +#define HDMI_SRZ_CFG_EN_PE_C1_MASK GENMASK(10, 8) +#define HDMI_SRZ_CFG_EN_PE_C2_MASK GENMASK(14, 12) + +#define HDMI_SRZ_CFG_EXTERNAL_DATA BIT(16) +#define HDMI_SRZ_CFG_RBIAS_EXT BIT(17) +#define HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION BIT(18) +#define HDMI_SRZ_CFG_ISNKCTRL_MASK GENMASK(21, 20) + +#define HDMI_SRZ_CFG_EN_SRC_TERM_SHIFT (24) +#define HDMI_SRZ_CFG_EN_SRC_TERM_VAL_0_165MHZ (0x0) +#define HDMI_SRZ_CFG_EN_SRC_TERM_VAL_165_340MHZ (0x2) +#define HDMI_SRZ_CFG_EN_SRC_TERM_VAL_ABV_340MHZ (0x3) + +#define HDMI_SRZ_CFG_CKCH_LOWSW_EN_SHIFT (29) +#define HDMI_SRZ_CFG_CKCH_LOWSW_EN_VAL_500MV (0x0) /* for below or equal 3.4 Gbps */ +#define HDMI_SRZ_CFG_CKCH_LOWSW_EN_VAL_300MV (0x1) /* for above 3.4 Gbps */ + +#define HDMI_SRZ_CFG_CKBY10_OR_40_SHIFT (30) +#define HDMI_SRZ_CFG_CKBY10_OR_40_VAL_DIV_BY_10 (0x0) /* for below or equal 3.4 Gbps */ +#define HDMI_SRZ_CFG_CKBY10_OR_40_VAL_DIV_BY_40 (0x1) /* for above 3.4 Gbps */ + +#define HDMI_SRZ_CFG_DATA20BIT10BIT_SHIFT (31) +#define HDMI_SRZ_CFG_DATA20BIT10BIT_VAL_10_BPC (0x0) +#define HDMI_SRZ_CFG_DATA20BIT10BIT_VAL_20_BPC (0x1) + +/* ******************************* */ +/* register : HDMI_SRZ_PLL_CFG */ +/* ******************************* */ +#define HDMI_PLL_CFG_EN BIT(0) +#define HDMI_PLL_CFG_NDIV_SHIFT (8) +#define HDMI_PLL_CFG_IDF_SHIFT (16) +#define HDMI_PLL_CFG_ODF_SHIFT (24) + +#define ODF_DIV_1 (0) +#define ODF_DIV_2 (1) +#define ODF_DIV_4 (2) +#define ODF_DIV_8 (3) +#define ODF_DIV_16 (4) + +/* ******************************* */ +/* register : HDMI_SRZ_STR_1 */ +/* ******************************* */ +#define HDMI_SRZ_STR1_MSK_PEXC0 GENMASK(11, 0) +#define HDMI_SRZ_STR1_MSK_PEXC1 GENMASK(27, 16) + +/* ******************************* */ +/* register : HDMI_SRZ_STR_2 */ +/* ******************************* */ +#define HDMI_SRZ_STR2_PEXC2 (0) +#define HDMI_SRZ_STR2_MSK_PEXC2 (0xFFF << HDMI_SRZ_STR2_PEXC2) + +/* ******************************* */ +/* register : HDMI_SRZ_CALCODE_EXT */ +/* ******************************* */ +#define HDMI_SRZ_CALCODE_EXT_MASK GENMASK(27, 0) + +/* ******************************** */ +/* register : HDMI_SRZ_TX_RSVR_BITS */ +/* ******************************** */ +#define HDMI_SRZ_TX_RSVR_BITS_BELOW_340MHZ (0) +#define HDMI_SRZ_TX_RSVR_BITS_ABOVE_340MHZ (0x0800000) + +/* *********************************** */ +/* Configuration */ +/* *********************************** */ +/* Config 0 => HDMI_SRZ_CFG */ +#define HDMI_SRZ_CONFIG_0_MASK (HDMI_SRZ_CFG_EN_PE_C0_MASK | \ + HDMI_SRZ_CFG_EN_PE_C1_MASK | \ + HDMI_SRZ_CFG_EN_PE_C2_MASK | \ + HDMI_SRZ_CFG_ISNKCTRL_MASK) +/* Config 1 => HDMI_SRZ_STR_1 */ +#define HDMI_SRZ_CONFIG_1_MASK (HDMI_SRZ_STR1_MSK_PEXC0 | HDMI_SRZ_STR1_MSK_PEXC1) + +/* Config 2 => HDMI_SRZ_STR_2 */ +#define HDMI_SRZ_CONFIG_2_MASK (HDMI_SRZ_STR2_MSK_PEXC2) + +/* Config 3 => HDMI_SRZ_CALCODE_EXT */ +#define HDMI_SRZ_CONFIG_3_MASK (HDMI_SRZ_CALCODE_EXT_MASK) + +#define STM_HDMI_THOLD_CLK_600MHZ (600000000) +#define STM_HDMI_THOLD_CLK_340MHZ (340000000) +#define STM_HDMI_THOLD_CLK_165MHZ (165000000) + +#define HDMI_TIMEOUT_PLL_LOCK 50 /*milliseconds */ + +struct plldividers_s { + u32 min; + u32 max; + u32 idf; + u32 odf; +}; + +/* + * Functional specification recommended values + */ +static struct plldividers_s plldividers[] = { + {0, 37500000, 1, ODF_DIV_16 }, + {37500000, 75000000, 2, ODF_DIV_8 }, + {75000000, 150000000, 4, ODF_DIV_4 }, + {150000000, 300000000, 8, ODF_DIV_2 }, + {300000000, 600000000, 16, ODF_DIV_1 } +}; + +static struct hdmi_phy_config hdmiphy_config[] = { + {0, 145000000, {0x0, 0x0, 0x0, 0x0} }, + {145000000, 165000000, {0x1110, 0x0, 0x0, 0x0} }, + {165000000, 340000000, {0x1110, 0x30003, 0x3, 0x0} }, + {340000000, 600000000, {0x200000, 0x0, 0x0, 0x0} }, +}; + +/** + * sti_hdmi_tx6g0c28phy_start - Start hdmi phy macro cell tx6g0c28 + * + * @hdmi: pointer on the hdmi internal structure + * + * Return false if an error occur + */ +static bool sti_hdmi_tx6g0c28phy_start(struct sti_hdmi *hdmi) +{ + u32 ckpxpll = hdmi->mode.clock * 1000; + u32 cfg, val, tmdsck, idf, odf, pllctrl = 0; + bool foundplldivides = false; + u32 tx_rsvr_bits = HDMI_SRZ_TX_RSVR_BITS_BELOW_340MHZ; + int i; + + drm_dbg_driver(hdmi->drm_dev, "%s: ckpxpll = %dHz\n", __func__, ckpxpll); + + for (i = 0; i < ARRAY_SIZE(plldividers); i++) { + if (ckpxpll >= plldividers[i].min && + ckpxpll < plldividers[i].max) { + idf = plldividers[i].idf; + odf = plldividers[i].odf; + foundplldivides = true; + break; + } + } + + if (!foundplldivides) { + dev_err(&hdmi->dev, "%s: input TMDS clock speed (%d) not supported\n", + __func__, ckpxpll); + return false; + } + + /* Assuming no pixel repetition and 24bits color */ + tmdsck = ckpxpll; + pllctrl |= 20 << HDMI_PLL_CFG_NDIV_SHIFT; + + if (tmdsck > STM_HDMI_THOLD_CLK_600MHZ) { + dev_err(&hdmi->dev, "%s: output TMDS clock (%d) out of range\n", __func__, tmdsck); + return false; + } + + pllctrl |= idf << HDMI_PLL_CFG_IDF_SHIFT; + pllctrl |= odf << HDMI_PLL_CFG_ODF_SHIFT; + + cfg = (HDMI_SRZ_CFG_EN | + HDMI_SRZ_CFG_EXTERNAL_DATA | + HDMI_SRZ_CFG_RBIAS_EXT | + HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION | + (HDMI_SRZ_CFG_DATA20BIT10BIT_VAL_10_BPC << HDMI_SRZ_CFG_DATA20BIT10BIT_SHIFT)); + + if (tmdsck > STM_HDMI_THOLD_CLK_340MHZ) { + cfg |= (HDMI_SRZ_CFG_EN_SRC_TERM_VAL_ABV_340MHZ << HDMI_SRZ_CFG_EN_SRC_TERM_SHIFT) | + (HDMI_SRZ_CFG_CKCH_LOWSW_EN_VAL_300MV << HDMI_SRZ_CFG_CKCH_LOWSW_EN_SHIFT) | + (HDMI_SRZ_CFG_CKBY10_OR_40_VAL_DIV_BY_40 << HDMI_SRZ_CFG_CKBY10_OR_40_SHIFT); + tx_rsvr_bits = HDMI_SRZ_TX_RSVR_BITS_ABOVE_340MHZ; + } else if (tmdsck > STM_HDMI_THOLD_CLK_165MHZ) { + cfg |= (HDMI_SRZ_CFG_EN_SRC_TERM_VAL_165_340MHZ << HDMI_SRZ_CFG_EN_SRC_TERM_SHIFT) | + (HDMI_SRZ_CFG_CKCH_LOWSW_EN_VAL_500MV << HDMI_SRZ_CFG_CKCH_LOWSW_EN_SHIFT) | + (HDMI_SRZ_CFG_CKBY10_OR_40_VAL_DIV_BY_10 << HDMI_SRZ_CFG_CKBY10_OR_40_SHIFT); + } else { + cfg |= (HDMI_SRZ_CFG_EN_SRC_TERM_VAL_0_165MHZ << HDMI_SRZ_CFG_EN_SRC_TERM_SHIFT) | + (HDMI_SRZ_CFG_CKCH_LOWSW_EN_VAL_500MV << HDMI_SRZ_CFG_CKCH_LOWSW_EN_SHIFT) | + (HDMI_SRZ_CFG_CKBY10_OR_40_VAL_DIV_BY_10 << HDMI_SRZ_CFG_CKBY10_OR_40_SHIFT); + } + + /* + * To configure the source termination and pre-emphasis appropriately + * for different high speed TMDS clock frequencies a phy configuration + * table must be provided, tailored to the SoC and board combination. + */ + for (i = 0; i < ARRAY_SIZE(hdmiphy_config); i++) { + if (hdmiphy_config[i].min_tmds_freq <= tmdsck && + hdmiphy_config[i].max_tmds_freq >= tmdsck) { + cfg |= (hdmiphy_config[i].config[0] & HDMI_SRZ_CONFIG_0_MASK); + hdmi_write(hdmi, cfg, HDMI_SRZ_CFG); + hdmi_write(hdmi, 0, HDMI_SRZ_PWR_CFG); + + val = hdmiphy_config[i].config[1] & HDMI_SRZ_CONFIG_1_MASK; + hdmi_write(hdmi, val, HDMI_SRZ_STR_1); + + val = hdmiphy_config[i].config[2] & HDMI_SRZ_CONFIG_2_MASK; + hdmi_write(hdmi, val, HDMI_SRZ_STR_2); + + val = hdmiphy_config[i].config[3] & HDMI_SRZ_CONFIG_3_MASK; + hdmi_write(hdmi, val, HDMI_SRZ_CALCODE_EXT); + + hdmi_write(hdmi, tx_rsvr_bits, HDMI_SRZ_TX_RSVR_BITS); + + /* + * Configure and power up the PHY PLL + */ + hdmi->event_received = false; + hdmi_write(hdmi, (pllctrl | HDMI_PLL_CFG_EN), HDMI_SRZ_PLL_CFG); + + /* wait PLL interrupt */ + wait_event_interruptible_timeout(hdmi->wait_event, hdmi->event_received, + msecs_to_jiffies(HDMI_TIMEOUT_PLL_LOCK)); + + if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) == 0) { + dev_err(&hdmi->dev, "%s: hdmi phy pll not locked\n", __func__); + return false; + } + + /* Reset the HDMI_TX_PHY */ + reset_control_assert(hdmi->reset); + usleep_range(15, 20); + reset_control_deassert(hdmi->reset); + + return true; + } + } + + /* + * Default, power up the serializer with no pre-emphasis or + * output swing correction + */ + hdmi_write(hdmi, cfg, HDMI_SRZ_CFG); + hdmi_write(hdmi, 0, HDMI_SRZ_PWR_CFG); + hdmi_write(hdmi, 0, HDMI_SRZ_STR_1); + hdmi_write(hdmi, 0, HDMI_SRZ_STR_2); + hdmi_write(hdmi, 0, HDMI_SRZ_CALCODE_EXT); + hdmi_write(hdmi, 0, HDMI_SRZ_TX_RSVR_BITS); + + return true; +} + +/** + * sti_hdmi_tx6g0c28phy_stop - Stop hdmi phy macro cell tx6g0c28 + * + * @hdmi: pointer on the hdmi internal structure + */ +static void sti_hdmi_tx6g0c28phy_stop(struct sti_hdmi *hdmi) +{ + hdmi->event_received = false; + + hdmi_write(hdmi, HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION, HDMI_SRZ_CFG); + hdmi_write(hdmi, 0, HDMI_SRZ_PLL_CFG); + + /* wait PLL interrupt */ + wait_event_interruptible_timeout(hdmi->wait_event, + hdmi->event_received, + msecs_to_jiffies + (HDMI_TIMEOUT_PLL_LOCK)); + + if (hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) + dev_err(&hdmi->dev, "%s: hdmi phy pll not well disabled\n", __func__); +} + +struct hdmi_phy_ops tx6g0c28phy_ops = { + .start = sti_hdmi_tx6g0c28phy_start, + .stop = sti_hdmi_tx6g0c28phy_stop, +}; diff --git a/drivers/gpu/drm/sti/sti_hdmi_tx6g0c28phy.h b/drivers/gpu/drm/sti/sti_hdmi_tx6g0c28phy.h new file mode 100644 index 000000000000..bcb8b70d36ea --- /dev/null +++ b/drivers/gpu/drm/sti/sti_hdmi_tx6g0c28phy.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Author: Alain Volmat + */ + +#ifndef _STI_HDMI_TX6G0C28PHY_H_ +#define _STI_HDMI_TX6G0C28PHY_H_ + +#include "sti_hdmi.h" + +extern struct hdmi_phy_ops tx6g0c28phy_ops; + +#endif From patchwork Thu Jul 27 21:51:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 127223 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp43774vqg; Thu, 27 Jul 2023 15:21:42 -0700 (PDT) X-Google-Smtp-Source: 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Signed-off-by: Alain Volmat Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/st,stih4xx.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/st,stih4xx.txt b/Documentation/devicetree/bindings/display/st,stih4xx.txt index 6778b3e7ad5b..5450e1db8b8d 100644 --- a/Documentation/devicetree/bindings/display/st,stih4xx.txt +++ b/Documentation/devicetree/bindings/display/st,stih4xx.txt @@ -2,7 +2,7 @@ STMicroelectronics stih4xx platforms - sti-vtg: video timing generator Required properties: - - compatible: "st,vtg" + - compatible: "st,vtg" or "st,stih418-vtg" - reg: Physical base address of the IP registers and length of memory mapped region. Optional properties: - interrupts : VTG interrupt number to the CPU. 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id b26-20020a6567da000000b0056003c53094si1773978pgs.433.2023.07.27.14.54.44; Thu, 27 Jul 2023 14:54:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=0RBvR1s3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232466AbjG0Vwi (ORCPT + 99 others); Thu, 27 Jul 2023 17:52:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232257AbjG0Vwb (ORCPT ); Thu, 27 Jul 2023 17:52:31 -0400 Received: from qs51p00im-qukt01072102.me.com (qs51p00im-qukt01072102.me.com [17.57.155.11]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19FAC2135 for ; Thu, 27 Jul 2023 14:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1690494749; bh=4Q2kPpx9tnkAzIsBSu0lR+5VOLaRmSNvSKU5kR9IbKY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=0RBvR1s3gPsmnwWxF3fgSp6Vr5lH/sKdAVs7b3TKhp7TfOQsxqRFPin8qLOvAfTgX GXdmWe2m/l+ywwqZv5Ihnm/rfJFvuyWutgL1AXJQs0txL870Zm6ViDH2Hge/8Twxpm 1Dhv3i90ExxqIWhwsVCEUbDgccbaDFTtZNTHiRlmx0pPi4JtMAMWuQUGUWPRdByuNp +boLnefyT5BWdh6L+DN0ki6SbX/CTiGzkxkl/s0sIJMDWtEK0i28IDuI/H0JrhSQTU c8tQsfOnaoeuA7FtdlGeaDQlAyvQScsjI8N8BCSelzqKx3C7JH4FBv3ee8v0w/7nnS a3ThaBe9L7aSw== Received: from localhost (qs51p00im-dlb-asmtp-mailmevip.me.com [17.57.155.28]) by qs51p00im-qukt01072102.me.com (Postfix) with ESMTPSA id 7940734099C; Thu, 27 Jul 2023 21:52:28 +0000 (UTC) From: Alain Volmat To: Alain Volmat , David Airlie , Daniel Vetter Cc: Alain Volmat , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/14] drm/sti: add support for VTG on the stih418 platform Date: Thu, 27 Jul 2023 21:51:27 +0000 Message-Id: <20230727215141.53910-4-avolmat@me.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727215141.53910-1-avolmat@me.com> References: <20230727215141.53910-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: TYCF9UE_guExnaT3ERZOGvZzEjQFonTj X-Proofpoint-GUID: TYCF9UE_guExnaT3ERZOGvZzEjQFonTj X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E170-?= =?utf-8?q?22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E138=2C18=2E0?= =?utf-8?q?=2E790=2C17=2E11=2E62=2E513=2E0000000_definitions=3D2022-01-12=5F?= =?utf-8?q?02=3A2020-02-14=5F02=2C2022-01-12=5F02=2C2021-12-02=5F01_signatur?= =?utf-8?q?es=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2307270199 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772612377440393053 X-GMAIL-MSGID: 1772612377440393053 VTG integrated into the STiH418 differ in the number of outputs available and allocation of each output. Indeed on STiH418, there are 6 outputs (4 on the STiH407/STiH410) and HDMI is connected to the 5th output in case of STiH418 while it is on the 1st output in case of STiH407/STiH410. A new compatible st,stih418-vtg is added to differentiate that. Signed-off-by: Alain Volmat --- drivers/gpu/drm/sti/sti_vtg.c | 62 +++++++++++++++++++++++++++++------ 1 file changed, 52 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c index 5e5f82b6a5d9..b0cab72ea502 100644 --- a/drivers/gpu/drm/sti/sti_vtg.c +++ b/drivers/gpu/drm/sti/sti_vtg.c @@ -60,6 +60,18 @@ #define VTG_TOP_V_HD_4 0x012c #define VTG_BOT_V_HD_4 0x0130 +#define VTG_H_HD_5 0x0140 +#define VTG_TOP_V_VD_5 0x0144 +#define VTG_BOT_V_VD_5 0x0148 +#define VTG_TOP_V_HD_5 0x014c +#define VTG_BOT_V_HD_5 0x0150 + +#define VTG_H_HD_6 0x0160 +#define VTG_TOP_V_VD_6 0x0164 +#define VTG_BOT_V_VD_6 0x0168 +#define VTG_TOP_V_HD_6 0x016c +#define VTG_BOT_V_HD_6 0x0170 + #define VTG_IRQ_BOTTOM BIT(0) #define VTG_IRQ_TOP BIT(1) #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM) @@ -92,7 +104,12 @@ struct sti_vtg_regs_offs { u32 bot_v_hd; }; -#define VTG_MAX_SYNC_OUTPUT 4 +struct sti_vtg_data { + unsigned int nb_sync_output; + unsigned int hdmi_sync_id; +}; + +#define VTG_MAX_SYNC_OUTPUT 6 static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = { { VTG_H_HD_1, VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 }, @@ -101,7 +118,11 @@ static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = { { VTG_H_HD_3, VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 }, { VTG_H_HD_4, - VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 } + VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 }, + { VTG_H_HD_5, + VTG_TOP_V_VD_5, VTG_BOT_V_VD_5, VTG_TOP_V_HD_5, VTG_BOT_V_HD_5 }, + { VTG_H_HD_6, + VTG_TOP_V_VD_6, VTG_BOT_V_VD_6, VTG_TOP_V_HD_6, VTG_BOT_V_HD_6 } }; /* @@ -138,6 +159,7 @@ struct sti_vtg { u32 irq_status; struct raw_notifier_head notifier_list; struct drm_crtc *crtc; + struct sti_vtg_data data; }; struct sti_vtg *of_vtg_find(struct device_node *np) @@ -252,7 +274,7 @@ static void vtg_set_mode(struct sti_vtg *vtg, vtg_set_output_window(vtg->regs, mode); /* Set hsync and vsync position for HDMI */ - vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode); + vtg_set_hsync_vsync_pos(&sync[vtg->data.hdmi_sync_id - 1], HDMI_DELAY, mode); /* Set hsync and vsync position for HD DCS */ vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode); @@ -264,7 +286,7 @@ static void vtg_set_mode(struct sti_vtg *vtg, vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], DVO_DELAY, mode); /* Progam the syncs outputs */ - for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) { + for (i = 0; i < vtg->data.nb_sync_output ; i++) { writel(sync[i].hsync, vtg->regs + vtg_regs_offs[i].h_hd); writel(sync[i].vsync_line_top, @@ -376,9 +398,27 @@ static irqreturn_t vtg_irq(int irq, void *arg) return IRQ_WAKE_THREAD; } +static const struct sti_vtg_data stih407_vtg_data = { + .nb_sync_output = 4, + .hdmi_sync_id = 1, +}; + +static const struct sti_vtg_data stih418_vtg_data = { + .nb_sync_output = 6, + .hdmi_sync_id = 5, +}; + +static const struct of_device_id vtg_of_match[] = { + { .compatible = "st,vtg", .data = &stih407_vtg_data, }, + { .compatible = "st,stih418-vtg", .data = &stih418_vtg_data, }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vtg_of_match); + static int vtg_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct sti_vtg *vtg; struct resource *res; int ret; @@ -387,6 +427,14 @@ static int vtg_probe(struct platform_device *pdev) if (!vtg) return -ENOMEM; + memcpy(&vtg->data, of_match_node(vtg_of_match, np)->data, + sizeof(struct sti_vtg_data)); + + if (vtg->data.nb_sync_output > VTG_MAX_SYNC_OUTPUT) { + dev_err(dev, "Invalid number of VTG sync output\n"); + return -EINVAL; + } + /* Get Memory ressources */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { @@ -422,12 +470,6 @@ static int vtg_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id vtg_of_match[] = { - { .compatible = "st,vtg", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, vtg_of_match); - struct platform_driver sti_vtg_driver = { .driver = { .name = "sti-vtg", From patchwork Thu Jul 27 21:51:28 2023 Content-Type: text/plain; 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Some registers as well differ between STiH407 and STiH418 leading on relying on the st,stih418-compositor compatible to distinguish proper behavior. Signed-off-by: Alain Volmat --- drivers/gpu/drm/sti/sti_mixer.c | 71 ++++++++++++++++++++++++++------- 1 file changed, 57 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_mixer.c b/drivers/gpu/drm/sti/sti_mixer.c index 7e5f14646625..9cd780403d7b 100644 --- a/drivers/gpu/drm/sti/sti_mixer.c +++ b/drivers/gpu/drm/sti/sti_mixer.c @@ -7,6 +7,7 @@ */ #include +#include #include #include @@ -23,10 +24,12 @@ module_param_named(bkgcolor, bkg_color, int, 0644); /* regs offset */ #define GAM_MIXER_CTL 0x00 #define GAM_MIXER_BKC 0x04 +#define GAM_MIXER_OFF 0x08 /* Only for STiH418 */ #define GAM_MIXER_BCO 0x0C #define GAM_MIXER_BCS 0x10 #define GAM_MIXER_AVO 0x28 #define GAM_MIXER_AVS 0x2C +#define GAM_MIXER_CRB2 0x30 /* Only for STiH418 */ #define GAM_MIXER_CRB 0x34 #define GAM_MIXER_ACT 0x38 #define GAM_MIXER_MBP 0x3C @@ -102,13 +105,22 @@ static void mixer_dbg_ctl(struct seq_file *s, int val) seq_puts(s, "Nothing"); } -static void mixer_dbg_crb(struct seq_file *s, int val) +static void mixer_dbg_crb(struct seq_file *s, struct sti_mixer *mixer, u64 val) { int i; + u32 shift, mask_id; + + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) { + shift = 4; + mask_id = 0x0f; + } else { + shift = 3; + mask_id = 0x07; + } seq_puts(s, "\tDepth: "); for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) { - switch (val & GAM_DEPTH_MASK_ID) { + switch (val & mask_id) { case GAM_DEPTH_VID0_ID: seq_puts(s, "VID0"); break; @@ -133,7 +145,7 @@ static void mixer_dbg_crb(struct seq_file *s, int val) if (i < GAM_MIXER_NB_DEPTH_LEVEL - 1) seq_puts(s, " < "); - val = val >> 3; + val = val >> shift; } } @@ -149,6 +161,7 @@ static int mixer_dbg_show(struct seq_file *s, void *arg) { struct drm_info_node *node = s->private; struct sti_mixer *mixer = (struct sti_mixer *)node->info_ent->data; + u64 val; seq_printf(s, "%s: (vaddr = 0x%p)", sti_mixer_to_str(mixer), mixer->regs); @@ -161,11 +174,18 @@ static int mixer_dbg_show(struct seq_file *s, void *arg) DBGFS_DUMP(GAM_MIXER_AVO); DBGFS_DUMP(GAM_MIXER_AVS); DBGFS_DUMP(GAM_MIXER_CRB); - mixer_dbg_crb(s, sti_mixer_reg_read(mixer, GAM_MIXER_CRB)); + val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) { + DBGFS_DUMP(GAM_MIXER_CRB2); + val |= ((u64)sti_mixer_reg_read(mixer, GAM_MIXER_CRB2) << 32); + } + mixer_dbg_crb(s, mixer, val); DBGFS_DUMP(GAM_MIXER_ACT); - DBGFS_DUMP(GAM_MIXER_MBP); - DBGFS_DUMP(GAM_MIXER_MX0); - mixer_dbg_mxn(s, mixer->regs + GAM_MIXER_MX0); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih407-compositor")) { + DBGFS_DUMP(GAM_MIXER_MBP); + DBGFS_DUMP(GAM_MIXER_MX0); + mixer_dbg_mxn(s, mixer->regs + GAM_MIXER_MX0); + } seq_putc(s, '\n'); return 0; } @@ -238,7 +258,16 @@ int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane) { int plane_id, depth = plane->drm_plane.state->normalized_zpos; unsigned int i; - u32 mask, val; + u64 mask, val; + u32 shift, mask_id; + + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) { + shift = 4; + mask_id = 0x0f; + } else { + shift = 3; + mask_id = 0x07; + } switch (plane->desc) { case STI_GDP_0: @@ -266,26 +295,37 @@ int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane) /* Search if a previous depth was already assigned to the plane */ val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) + val |= ((u64)sti_mixer_reg_read(mixer, GAM_MIXER_CRB2) << 32); for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) { - mask = GAM_DEPTH_MASK_ID << (3 * i); - if ((val & mask) == plane_id << (3 * i)) + mask = mask_id << (shift * i); + if ((val & mask) == plane_id << (shift * i)) break; } - mask |= GAM_DEPTH_MASK_ID << (3 * depth); - plane_id = plane_id << (3 * depth); + mask |= mask_id << (shift * depth); + plane_id = plane_id << (shift * depth); DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer), sti_plane_to_str(plane), depth); dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n", - plane_id, mask); + plane_id, (u32)(mask & 0xffffffff)); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) + dev_dbg(mixer->dev, "GAM_MIXER_CRB2 val 0x%x mask 0x%x\n", + plane_id, (u32)(mask >> 32)); val &= ~mask; val |= plane_id; - sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val); + sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val & 0xffffffff); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) + sti_mixer_reg_write(mixer, GAM_MIXER_CRB2, val >> 32); dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n", sti_mixer_reg_read(mixer, GAM_MIXER_CRB)); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) + dev_dbg(mixer->dev, "Read GAM_MIXER_CRB2 0x%x\n", + sti_mixer_reg_read(mixer, GAM_MIXER_CRB2)); + return 0; } @@ -352,6 +392,9 @@ int sti_mixer_set_plane_status(struct sti_mixer *mixer, val |= status ? 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id a21-20020a63e855000000b00563e904db63si1879020pgk.137.2023.07.27.16.08.50; Thu, 27 Jul 2023 16:09:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=IJgqXLWr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232404AbjG0VxG (ORCPT + 99 others); Thu, 27 Jul 2023 17:53:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232528AbjG0Vwn (ORCPT ); Thu, 27 Jul 2023 17:52:43 -0400 Received: from qs51p00im-qukt01072301.me.com (qs51p00im-qukt01072301.me.com [17.57.155.12]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90A6C3A80 for ; Thu, 27 Jul 2023 14:52:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1690494755; bh=XpyNIdF2uhZAhQUKpx12L3Gpl72rWCRfsfzIB7HNnLk=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=IJgqXLWrQv7ZqRRd1SPCqOO7HHye4jaYz47x9dg7NbM6TIErBkVQ8MH8Sb4G42/9K 0sGo9iHeuh6jIbYsmJR1sWfGgmsoWbgCeytnx/ET2Z9lJAz2EPyShYcozxM/3Q8cOB +44mc6qbSaRy4uhU7cmVsUNzUIzFKt5f8YFGuwEl+lBlnvEw0/5L7oWUKaJSKKU5+1 QokDbvi81mb7olxqmjZhRzGUAVmRpzm7tIpCACV+c3rLS12DLSDEk/XliyB27m3GQO QzG6rvyI/oiZu7wNVOirzPt5vxETdjIZ72Mdd4W933Q9JVorr9vjC4uogefrmi9nlU WEzI3J3Jb1FEQ== Received: from localhost (qs51p00im-dlb-asmtp-mailmevip.me.com [17.57.155.28]) by qs51p00im-qukt01072301.me.com (Postfix) with ESMTPSA id 8BF6225401AC; Thu, 27 Jul 2023 21:52:34 +0000 (UTC) From: Alain Volmat To: Alain Volmat , David Airlie , Daniel Vetter Cc: Alain Volmat , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/14] drm/sti: add support for stih418 in tvout Date: Thu, 27 Jul 2023 21:51:29 +0000 Message-Id: <20230727215141.53910-6-avolmat@me.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727215141.53910-1-avolmat@me.com> References: <20230727215141.53910-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-GUID: kRQ2cwLkVgPsl2ICV2Gw1qVI7RyokRPq X-Proofpoint-ORIG-GUID: kRQ2cwLkVgPsl2ICV2Gw1qVI7RyokRPq X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E170-?= =?utf-8?q?22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E138=2C18=2E0?= =?utf-8?q?=2E790=2C17=2E11=2E62=2E513=2E0000000_definitions=3D2022-01-12=5F?= =?utf-8?q?02=3A2020-02-14=5F02=2C2022-01-12=5F02=2C2021-12-02=5F01_signatur?= =?utf-8?q?es=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2307270198 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772617040132290123 X-GMAIL-MSGID: 1772617040132290123 The tvout for stih407 and stih418 differ in the connection with the vtg regarding to the hdmi output. In order to cop with that, introduce a new compatible st,stih418-tvout in order to have the hdmi_sync_id being part of the data attached to each compatible. Signed-off-by: Alain Volmat --- drivers/gpu/drm/sti/sti_tvout.c | 35 +++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_tvout.c b/drivers/gpu/drm/sti/sti_tvout.c index 64615638b79a..685c0a4ba1be 100644 --- a/drivers/gpu/drm/sti/sti_tvout.c +++ b/drivers/gpu/drm/sti/sti_tvout.c @@ -118,6 +118,7 @@ struct sti_tvout { struct drm_encoder *hda; struct drm_encoder *dvo; bool debugfs_registered; + unsigned int hdmi_sync_id; }; struct sti_tvout_encoder { @@ -130,6 +131,10 @@ struct sti_tvout_encoder { #define to_sti_tvout(x) to_sti_tvout_encoder(x)->tvout +struct sti_tvout_data { + unsigned int hdmi_sync_id; +}; + /* preformatter conversion matrix */ static const u32 rgb_to_ycbcr_601[8] = { 0xF927082E, 0x04C9FEAB, 0x01D30964, 0xFA95FD3D, @@ -359,14 +364,14 @@ static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path) DRM_DEBUG_DRIVER("main vip for hdmi\n"); /* select the input sync for hdmi */ tvout_write(tvout, - TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDMI, + TVO_SYNC_MAIN_VTG_SET_REF | tvout->hdmi_sync_id, TVO_HDMI_SYNC_SEL); tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT; } else { DRM_DEBUG_DRIVER("aux vip for hdmi\n"); /* select the input sync for hdmi */ tvout_write(tvout, - TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDMI, + TVO_SYNC_AUX_VTG_SET_REF | tvout->hdmi_sync_id, TVO_HDMI_SYNC_SEL); tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT; } @@ -833,10 +838,26 @@ static const struct component_ops sti_tvout_ops = { .unbind = sti_tvout_unbind, }; +static const struct sti_tvout_data stih407_tvout_data = { + .hdmi_sync_id = 1, +}; + +static const struct sti_tvout_data stih418_tvout_data = { + .hdmi_sync_id = 5, +}; + +static const struct of_device_id tvout_of_match[] = { + { .compatible = "st,stih407-tvout", .data = &stih407_tvout_data, }, + { .compatible = "st,stih418-tvout", .data = &stih418_tvout_data, }, + { /* end node */ } +}; +MODULE_DEVICE_TABLE(of, tvout_of_match); + static int sti_tvout_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; + const struct sti_tvout_data *data; struct sti_tvout *tvout; struct resource *res; @@ -851,6 +872,10 @@ static int sti_tvout_probe(struct platform_device *pdev) tvout->dev = dev; + /* populate data structure depending on compatibility */ + data = of_match_node(tvout_of_match, node)->data; + tvout->hdmi_sync_id = data->hdmi_sync_id; + /* get memory resources */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tvout-reg"); if (!res) { @@ -877,12 +902,6 @@ static void sti_tvout_remove(struct platform_device *pdev) component_del(&pdev->dev, &sti_tvout_ops); } -static const struct of_device_id tvout_of_match[] = { - { .compatible = "st,stih407-tvout", }, - { /* end node */ } -}; -MODULE_DEVICE_TABLE(of, tvout_of_match); - struct platform_driver sti_tvout_driver = { .driver = { .name = "sti-tvout", From patchwork Thu Jul 27 21:51:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 127238 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp59113vqg; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l19-20020a637013000000b00563519244dbsi1824634pgc.169.2023.07.27.16.01.37; Thu, 27 Jul 2023 16:01:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=QUK2Minu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232502AbjG0VxJ (ORCPT + 99 others); Thu, 27 Jul 2023 17:53:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232542AbjG0Vw4 (ORCPT ); Thu, 27 Jul 2023 17:52:56 -0400 Received: from qs51p00im-qukt01072301.me.com (qs51p00im-qukt01072301.me.com [17.57.155.12]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 432BC2736 for ; Thu, 27 Jul 2023 14:52:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1690494758; bh=YktwkpXyaGBIT8GsziofZlNMbhT2j8LgV+O0AEQuBJU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=QUK2MinujpZIVzM9jqSwTClsGYBGoJnXMLPmEYJTXNIYv1CKGNPvScMaW/CUV7u5H qnECqzPJpsQrb0VfPu+GNHedd8umWgLVfuTmslj8WGnXSQK4Zsxd3hH45klyQVJdj3 GA5JaUUguVIKc9IN1qxSVLuTWsS6pnYugh/Ua9NnbR1g5fMxnFpL3ebagpLagdFRr6 zCsGaMHBY2B/Q1JlruyDnk7E37+aJouBeSaYLebGveEHiFbeLPvRGXLZP3PL4e2Anx UEXBV+EjJLp+a5XAUoMJOj1plbqxEd9zKO4tr65rjfVUaBSxUuasSKHfzKiNk0h20h K8UY3cjgEBrmA== Received: from localhost (qs51p00im-dlb-asmtp-mailmevip.me.com [17.57.155.28]) by qs51p00im-qukt01072301.me.com (Postfix) with ESMTPSA id 8353F254016F; Thu, 27 Jul 2023 21:52:37 +0000 (UTC) From: Alain Volmat To: Alain Volmat , David Airlie , Daniel Vetter Cc: Alain Volmat , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/14] drm/sti: remove VTG_SYNC_ID_HDMI from sti_vtg.h Date: Thu, 27 Jul 2023 21:51:30 +0000 Message-Id: <20230727215141.53910-7-avolmat@me.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727215141.53910-1-avolmat@me.com> References: <20230727215141.53910-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: mB9QGKLmq2zplK26TClZnVryBqDr75Nm X-Proofpoint-GUID: mB9QGKLmq2zplK26TClZnVryBqDr75Nm X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E170-?= =?utf-8?q?22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E138=2C18=2E0?= =?utf-8?q?=2E790=2C17=2E11=2E62=2E513=2E0000000_definitions=3D2022-01-12=5F?= =?utf-8?q?02=3A2020-02-14=5F02=2C2022-01-12=5F02=2C2021-12-02=5F01_signatur?= =?utf-8?q?es=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 mlxlogscore=923 suspectscore=0 mlxscore=0 clxscore=1015 malwarescore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2307270199 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772616585490609067 X-GMAIL-MSGID: 1772616585490609067 Since the synchro signal used for hdmi output and coming from the VTG differs between the stih407 and stih418 platforms, we cannot rely anymore on hardcoded value and involve drivers use compatible to figure out the value. The macro VTG_SYNC_ID_HDMI can thus be removed. Signed-off-by: Alain Volmat --- drivers/gpu/drm/sti/sti_vtg.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/sti/sti_vtg.h b/drivers/gpu/drm/sti/sti_vtg.h index 46faf141b2d9..bd0437bd1c8d 100644 --- a/drivers/gpu/drm/sti/sti_vtg.h +++ b/drivers/gpu/drm/sti/sti_vtg.h @@ -10,7 +10,6 @@ #define VTG_TOP_FIELD_EVENT 1 #define VTG_BOTTOM_FIELD_EVENT 2 -#define VTG_SYNC_ID_HDMI 1 #define VTG_SYNC_ID_HDDCS 2 #define VTG_SYNC_ID_HDF 3 #define VTG_SYNC_ID_DVO 4 From patchwork Thu Jul 27 21:51:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 127244 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp64695vqg; Thu, 27 Jul 2023 16:12:17 -0700 (PDT) X-Google-Smtp-Source: APBJJlG5CDViQvjvbXIvziYJ6XBWMi4TXyYPuzdQ/AFo7ZSKMbd/o0JZYkwdGti2KHdbBkHj2YhG X-Received: by 2002:a05:6a00:1388:b0:681:6169:e403 with SMTP id t8-20020a056a00138800b006816169e403mr78076pfg.8.1690499537527; Thu, 27 Jul 2023 16:12:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690499537; cv=none; d=google.com; s=arc-20160816; b=hq/155gCUCwAB267byJZ3Cdnt4z+nQmv/zFRlxsk7hzy8ggFN2dZc7gf6edF3CaETM INeJUrvNleqEzoT/ycdM2Hy7nb80yGlZkWVx8dP/JZEjlW8ktHDFTn+x/UluGvSUtL/i nHxPV9kMmdLXB072BJWuqeSsEJUi69lN36sR72H3IClyWaCXTkAejrD0rKz4aEL1axBA HzbI6Yw+IufOGWGWqxb3/w7pTSs1LAJeTOYmyTU+1VdZORBG45XGRV82WzRE5XvryVRw NKhBaDu8e+DQ2lkyQ563ojC97lUgYENnxbMvlPq0AlXlvzy4te1LZr7cF5a4G0tqcBc1 B0Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kgGzA4dJRcbkTCFkI8WKFmpxvWUvUAQu2bilJrVHeBw=; fh=YlaQJ3TP8tbT2RGJU1jM+MHAbXw6RYFhYgmjWx/ZxUI=; b=j7Imry8gCCPtKt3IaOnIE76NixMsDSYePR6e0AEcqz0vwfHmkpngbBTepUl0W8gJej 7wv+8oZB9zX7Y7kMFJOKAhNLsVsmSZAFH8irM8LLhKw3fPhNxHLRXRYlXtMWsdi5BPcW eYXaZt6VNeECLzA3BXL3wzMVWdVfbnO5g1q33LscCrT4dFTfL7/O2NqprFJHUK732+r/ WOZexXY/o89bTuBFMN7MxW146Ilhi5WPPDS6TCz8KUSG1JhGeiKmSB+AgrUYGksBHVXY qQTQq2uOLa4pFM4c1ldwgbZZXxAc1l2n0lnLkGmKCRqqq3ROeu2Ls0rj76TyBcxvPqhB NuNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=lOgjzsYj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: from out1.vger.email (out1.vger.email. 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Thu, 27 Jul 2023 14:52:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1690494761; bh=kgGzA4dJRcbkTCFkI8WKFmpxvWUvUAQu2bilJrVHeBw=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=lOgjzsYj3O24lMtX7deLh2NMJOaknYNi4dG3G7pJAlC2tpYVbUbR89MwUBNYxLyGo bxakESUnPGEprmHFo768pGBNc73smnhJsu8d+3BnRBYNKPFlS+AMbCoChH1tm2cy1P AceGT2ZVSXqewMUfTbfk27YcaknLlYejy/cclN4tShbUWy4K8CxTxBmZZzzu3nFJvQ kWaDcag4Rt7ChsHhulbej5p8VZOwMovG/ZDunwnaqJEezXdQ3Wp0r4trdEzd7K4I5o 3DWMfSw1kn6ZIOc3aF3IWiF0PwvoGWNChpBCUsANuXph75mOXTONN+RHsOPeM2VzoA Tmjz3rDCz3q/g== Received: from localhost (qs51p00im-dlb-asmtp-mailmevip.me.com [17.57.155.28]) by qs51p00im-qukt01080101.me.com (Postfix) with ESMTPSA id 5BC196180164; Thu, 27 Jul 2023 21:52:40 +0000 (UTC) From: Alain Volmat To: Alain Volmat , David Airlie , Daniel Vetter Cc: Alain Volmat , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/14] drm/sti: add more possible GDP / VID planes entries in sti_plane Date: Thu, 27 Jul 2023 21:51:31 +0000 Message-Id: <20230727215141.53910-8-avolmat@me.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727215141.53910-1-avolmat@me.com> References: <20230727215141.53910-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: wpH9KuNuuv4dX_dTTxW3ntkSM4BIxeZ0 X-Proofpoint-GUID: wpH9KuNuuv4dX_dTTxW3ntkSM4BIxeZ0 X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E170-?= =?utf-8?q?22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E138=2C18=2E0?= =?utf-8?q?=2E790=2C17=2E0=2E605=2E474=2E0000000_definitions=3D2022-01-12=5F?= =?utf-8?q?02=3A2020-02-14=5F02=2C2022-01-12=5F02=2C2020-01-23=5F02_signatur?= =?utf-8?q?es=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1015 suspectscore=0 spamscore=0 mlxlogscore=771 adultscore=0 mlxscore=0 phishscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2307270199 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772617243013607264 X-GMAIL-MSGID: 1772617243013607264 In order to address the STiH418, add more entries in sti_plane Signed-off-by: Alain Volmat --- drivers/gpu/drm/sti/sti_plane.c | 8 ++++++++ drivers/gpu/drm/sti/sti_plane.h | 8 +++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sti/sti_plane.c b/drivers/gpu/drm/sti/sti_plane.c index 29e669ccec5b..f8d65d608b64 100644 --- a/drivers/gpu/drm/sti/sti_plane.c +++ b/drivers/gpu/drm/sti/sti_plane.c @@ -28,8 +28,16 @@ const char *sti_plane_to_str(struct sti_plane *plane) return "GDP2"; case STI_GDP_3: return "GDP3"; + case STI_GDP_4: + return "GDP4"; + case STI_GDP_5: + return "GDP5"; case STI_HQVDP_0: return "HQVDP0"; + case STI_HQVDP_1: + return "HQVDP1"; + case STI_HQVDP_2: + return "HQVDP2"; case STI_CURSOR: return "CURSOR"; default: diff --git a/drivers/gpu/drm/sti/sti_plane.h b/drivers/gpu/drm/sti/sti_plane.h index 2c0156bede9c..51fc25ed0287 100644 --- a/drivers/gpu/drm/sti/sti_plane.h +++ b/drivers/gpu/drm/sti/sti_plane.h @@ -25,7 +25,9 @@ enum sti_plane_id_of_type { STI_ID_0 = 0, STI_ID_1 = 1, STI_ID_2 = 2, - STI_ID_3 = 3 + STI_ID_3 = 3, + STI_ID_4 = 4, + STI_ID_5 = 5, }; enum sti_plane_desc { @@ -33,7 +35,11 @@ enum sti_plane_desc { STI_GDP_1 = STI_GDP | STI_ID_1, STI_GDP_2 = STI_GDP | STI_ID_2, STI_GDP_3 = STI_GDP | STI_ID_3, + STI_GDP_4 = STI_GDP | STI_ID_4, + STI_GDP_5 = STI_GDP | STI_ID_5, STI_HQVDP_0 = STI_VDP | STI_ID_0, + STI_HQVDP_1 = STI_VDP | STI_ID_1, + STI_HQVDP_2 = STI_VDP | STI_ID_2, STI_CURSOR = STI_CUR, STI_BACK = STI_BCK }; From patchwork Thu Jul 27 21:51:32 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ch14-20020a056a00288e00b00686babe2eb4si1923893pfb.222.2023.07.27.15.15.59; Thu, 27 Jul 2023 15:16:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=vpuxvcx3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232505AbjG0Vx1 (ORCPT + 99 others); Thu, 27 Jul 2023 17:53:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232438AbjG0VxH (ORCPT ); Thu, 27 Jul 2023 17:53:07 -0400 Received: from qs51p00im-qukt01071501.me.com (qs51p00im-qukt01071501.me.com [17.57.155.4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC5FA3C11 for ; Thu, 27 Jul 2023 14:52:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1690494764; bh=6Y5rmpwqO9RIngtw3twLpHFk4RjqozKiV85QZdnBP8A=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=vpuxvcx3yQpRL49XjgN8c+mV0Wgx7BRyEVXPj/a2NF7OI/u2gxvO+Yi6jdz/VZhAI FUYTytATJuogqg62sDF3BZmfmbskKuZLR0RMCDuVq7/Of956Bsy0P7bVwhMekeuEBx 1MEIj571IW8KLTRKV9929ILuRIxgi7cae58Kz/oQXqPENHA/TKb+6gta7e40+X7npG An9TfB14dnv+1MKDbzhdj5O3fZ0Rpo8EK3GxZWDqAaMfCGTk0KPOmhAkp1lKiJ8ucO wlDBDyLPacAY+7QVbgocdPMmAjE0qDuUtOpnhno7NISNfgqFP8H6VZvuB7MdEkgI3V Q42i+J317F9xA== Received: from localhost (qs51p00im-dlb-asmtp-mailmevip.me.com [17.57.155.28]) by qs51p00im-qukt01071501.me.com (Postfix) with ESMTPSA id A2C1A1C406DA; Thu, 27 Jul 2023 21:52:43 +0000 (UTC) From: Alain Volmat To: Alain Volmat , David Airlie , Daniel Vetter Cc: Alain Volmat , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/14] drm/sti: add more planes supports in sti_mixer Date: Thu, 27 Jul 2023 21:51:32 +0000 Message-Id: <20230727215141.53910-9-avolmat@me.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727215141.53910-1-avolmat@me.com> References: <20230727215141.53910-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-GUID: MjTwYVc_lutVqaTkRR6pG5QDvwo5FQqo X-Proofpoint-ORIG-GUID: MjTwYVc_lutVqaTkRR6pG5QDvwo5FQqo X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E170-?= =?utf-8?q?22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E425=2C18=2E0?= =?utf-8?q?=2E572=2C17=2E0=2E605=2E474=2E0000000_definitions=3D2022-01-11=5F?= =?utf-8?q?01=3A2022-01-11=5F01=2C2020-02-14=5F11=2C2020-01-23=5F02_signatur?= =?utf-8?q?es=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 clxscore=1015 mlxlogscore=999 spamscore=0 bulkscore=0 malwarescore=0 adultscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2307270199 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772613714737232455 X-GMAIL-MSGID: 1772613714737232455 On STiH418, the mixer is able to driver more layers of planes. For this purpose, add those new possible entries and allow it to work in either STiH407 or STiH418 mode. Signed-off-by: Alain Volmat --- drivers/gpu/drm/sti/sti_mixer.c | 66 ++++++++++++++++++++++++++++----- drivers/gpu/drm/sti/sti_mixer.h | 3 +- 2 files changed, 58 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_mixer.c b/drivers/gpu/drm/sti/sti_mixer.c index 9cd780403d7b..d30e31e62268 100644 --- a/drivers/gpu/drm/sti/sti_mixer.c +++ b/drivers/gpu/drm/sti/sti_mixer.c @@ -42,7 +42,9 @@ module_param_named(bkgcolor, bkg_color, int, 0644); #define GAM_DEPTH_GDP1_ID 4 #define GAM_DEPTH_GDP2_ID 5 #define GAM_DEPTH_GDP3_ID 6 -#define GAM_DEPTH_MASK_ID 7 +#define GAM_DEPTH_GDP4_ID 7 +#define GAM_DEPTH_GDP5_ID 8 +#define GAM_DEPTH_VID2_ID 9 /* mask in CTL reg */ #define GAM_CTL_BACK_MASK BIT(0) @@ -52,6 +54,10 @@ module_param_named(bkgcolor, bkg_color, int, 0644); #define GAM_CTL_GDP1_MASK BIT(4) #define GAM_CTL_GDP2_MASK BIT(5) #define GAM_CTL_GDP3_MASK BIT(6) +#define GAM_CTL_GDP4_MASK BIT(7) +#define GAM_CTL_GDP5_MASK BIT(8) +/* CURSOR doesn't exist on STiH418 where VID2 exist */ +#define GAM_CTL_VID2_MASK BIT(9) #define GAM_CTL_CURSOR_MASK BIT(9) const char *sti_mixer_to_str(struct sti_mixer *mixer) @@ -80,15 +86,16 @@ static inline void sti_mixer_reg_write(struct sti_mixer *mixer, #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ sti_mixer_reg_read(mixer, reg)) -static void mixer_dbg_ctl(struct seq_file *s, int val) +static void mixer_dbg_ctl(struct seq_file *s, int val, int depth) { unsigned int i; int count = 0; char *const disp_layer[] = {"BKG", "VID0", "VID1", "GDP0", - "GDP1", "GDP2", "GDP3"}; + "GDP1", "GDP2", "GDP3", "GDP4", + "GDP5", "VID2"}; seq_puts(s, "\tEnabled: "); - for (i = 0; i < 7; i++) { + for (i = 0; i < depth; i++) { if (val & 1) { seq_printf(s, "%s ", disp_layer[i]); count++; @@ -108,18 +115,20 @@ static void mixer_dbg_ctl(struct seq_file *s, int val) static void mixer_dbg_crb(struct seq_file *s, struct sti_mixer *mixer, u64 val) { int i; - u32 shift, mask_id; + u32 shift, mask_id, mixer_depth; if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) { shift = 4; mask_id = 0x0f; + mixer_depth = GAM_MIXER_NB_DEPTH_LEVEL_STIH418; } else { shift = 3; mask_id = 0x07; + mixer_depth = GAM_MIXER_NB_DEPTH_LEVEL_STIH407; } seq_puts(s, "\tDepth: "); - for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) { + for (i = 0; i < mixer_depth; i++) { switch (val & mask_id) { case GAM_DEPTH_VID0_ID: seq_puts(s, "VID0"); @@ -139,11 +148,20 @@ static void mixer_dbg_crb(struct seq_file *s, struct sti_mixer *mixer, u64 val) case GAM_DEPTH_GDP3_ID: seq_puts(s, "GDP3"); break; + case GAM_DEPTH_GDP4_ID: + seq_puts(s, "GDP4"); + break; + case GAM_DEPTH_GDP5_ID: + seq_puts(s, "GDP5"); + break; + case GAM_DEPTH_VID2_ID: + seq_puts(s, "VID2"); + break; default: seq_puts(s, "---"); } - if (i < GAM_MIXER_NB_DEPTH_LEVEL - 1) + if (i < mixer_depth - 1) seq_puts(s, " < "); val = val >> shift; } @@ -161,13 +179,19 @@ static int mixer_dbg_show(struct seq_file *s, void *arg) { struct drm_info_node *node = s->private; struct sti_mixer *mixer = (struct sti_mixer *)node->info_ent->data; + int depth; u64 val; + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) + depth = GAM_MIXER_NB_DEPTH_LEVEL_STIH418 + 1; + else + depth = GAM_MIXER_NB_DEPTH_LEVEL_STIH407 + 1; + seq_printf(s, "%s: (vaddr = 0x%p)", sti_mixer_to_str(mixer), mixer->regs); DBGFS_DUMP(GAM_MIXER_CTL); - mixer_dbg_ctl(s, sti_mixer_reg_read(mixer, GAM_MIXER_CTL)); + mixer_dbg_ctl(s, sti_mixer_reg_read(mixer, GAM_MIXER_CTL), depth); DBGFS_DUMP(GAM_MIXER_BKC); DBGFS_DUMP(GAM_MIXER_BCO); DBGFS_DUMP(GAM_MIXER_BCS); @@ -259,14 +283,16 @@ int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane) int plane_id, depth = plane->drm_plane.state->normalized_zpos; unsigned int i; u64 mask, val; - u32 shift, mask_id; + u32 shift, mask_id, mixer_depth; if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) { shift = 4; mask_id = 0x0f; + mixer_depth = GAM_MIXER_NB_DEPTH_LEVEL_STIH418; } else { shift = 3; mask_id = 0x07; + mixer_depth = GAM_MIXER_NB_DEPTH_LEVEL_STIH407; } switch (plane->desc) { @@ -285,6 +311,18 @@ int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane) case STI_HQVDP_0: plane_id = GAM_DEPTH_VID0_ID; break; + case STI_HQVDP_1: + plane_id = GAM_DEPTH_VID1_ID; + break; + case STI_GDP_4: + plane_id = GAM_DEPTH_GDP4_ID; + break; + case STI_GDP_5: + plane_id = GAM_DEPTH_GDP5_ID; + break; + case STI_HQVDP_2: + plane_id = GAM_DEPTH_VID2_ID; + break; case STI_CURSOR: /* no need to set depth for cursor */ return 0; @@ -297,7 +335,7 @@ int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane) val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB); if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) val |= ((u64)sti_mixer_reg_read(mixer, GAM_MIXER_CRB2) << 32); - for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) { + for (i = 0; i < mixer_depth; i++) { mask = mask_id << (shift * i); if ((val & mask) == plane_id << (shift * i)) break; @@ -366,6 +404,14 @@ static u32 sti_mixer_get_plane_mask(struct sti_plane *plane) return GAM_CTL_GDP3_MASK; case STI_HQVDP_0: return GAM_CTL_VID0_MASK; + case STI_HQVDP_1: + return GAM_CTL_VID1_MASK; + case STI_GDP_4: + return GAM_CTL_GDP4_MASK; + case STI_GDP_5: + return GAM_CTL_GDP5_MASK; + case STI_HQVDP_2: + return GAM_CTL_VID2_MASK; case STI_CURSOR: return GAM_CTL_CURSOR_MASK; default: diff --git a/drivers/gpu/drm/sti/sti_mixer.h b/drivers/gpu/drm/sti/sti_mixer.h index ab06beb7b258..1ce7c6b4b4f3 100644 --- a/drivers/gpu/drm/sti/sti_mixer.h +++ b/drivers/gpu/drm/sti/sti_mixer.h @@ -61,7 +61,8 @@ void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable); void sti_mixer_debugfs_init(struct sti_mixer *mixer, struct drm_minor *minor); /* depth in Cross-bar control = z order */ -#define GAM_MIXER_NB_DEPTH_LEVEL 6 +#define GAM_MIXER_NB_DEPTH_LEVEL_STIH407 6 +#define GAM_MIXER_NB_DEPTH_LEVEL_STIH418 9 #define STI_MIXER_MAIN 0 #define STI_MIXER_AUX 1 From patchwork Thu Jul 27 21:51:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 127212 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp40968vqg; Thu, 27 Jul 2023 15:15:06 -0700 (PDT) X-Google-Smtp-Source: APBJJlHjH3LbypO9I5KUIqOY9ekxKNgCaCOoIBlcAx6Hp8PCaDJ6i77P0wS+4EpRx03Dl1p/HlQH X-Received: by 2002:a17:902:db0f:b0:1b8:ad90:7af8 with SMTP id m15-20020a170902db0f00b001b8ad907af8mr4975625plx.17.1690496106529; Thu, 27 Jul 2023 15:15:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690496106; cv=none; d=google.com; s=arc-20160816; b=WPhBNw4Pubfgnvbx/5cseHIDbAkM39p51EYeu7EZGRME+8q7trXV2zR3BtvZCvQOk5 rc9ZxupBwMNRN7jSxHTVzQ0BqnE/13pfsJT3epDXbJ1deWmVDiv2/ibWub7cd/yIUxyJ AFwccL2KM3t3q+UpBrXa3VGFHWlECd8J3TJLN97+lh4mm5IoGoKpcrwwFEi05ZTdiXWD QVodTG4KJndkB5CjoDelEx/GTXmo2sxHKRMrJlcGPUpTAiqItoxscCOEOcSWGm5W2ESg BBu0rzDy28riSpBjeHoEVaTR7CEwcRgYS6NZ+b/z9mCGvnWr53wi7a2b/Ub5Oxi0Pb2I OCKA== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id jz14-20020a170903430e00b001b53c722c3fsi1779841plb.597.2023.07.27.15.14.51; Thu, 27 Jul 2023 15:15:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=IQ2y9FWG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232784AbjG0Vxf (ORCPT + 99 others); Thu, 27 Jul 2023 17:53:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232604AbjG0VxP (ORCPT ); Thu, 27 Jul 2023 17:53:15 -0400 Received: from qs51p00im-qukt01072101.me.com (qs51p00im-qukt01072101.me.com [17.57.155.10]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD3AD3C3B for ; Thu, 27 Jul 2023 14:52:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1690494767; bh=mguhDgGjsBNB0fhbVis30YaUXi1UXdYfdMasDcaxP0c=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=IQ2y9FWGHs0BG2Gco/IW9dcM+R71hK8rvu4P6/oa6/64wiO6ECiyZFaAWEouvZBBB 2YUGCeUjJ+Hb5V8yupap0+WxQqe8/n4jVeLtl3/61QgC9x3vL9iwVMfO9UBtP3mppw BWH10kl2DBY0SGBLI30EwP4rbWUDMtMB0oS8FDdtw2lEgY0Rpp+y6tFf/NMNPtkK7I i7NUhtqgb8cAQqyDBxsXBrBnmkB9O8FFA+G5efjU4cM8LnP9tFunH8W9+6IwWTRcSh 1BXQbl+OMNOOwr4/NdyiSUomhrY78m/LblERwKWey6487GVw2Cmu56/c8v8rr4bChH 9dw4DP/FGsC8A== Received: from localhost (qs51p00im-dlb-asmtp-mailmevip.me.com [17.57.155.28]) by qs51p00im-qukt01072101.me.com (Postfix) with ESMTPSA id F0CE9409F5; Thu, 27 Jul 2023 21:52:46 +0000 (UTC) From: Alain Volmat To: Alain Volmat , David Airlie , Daniel Vetter Cc: Alain Volmat , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/14] drm/sti: add support for GDPPLUS / stih418 GDPs Date: Thu, 27 Jul 2023 21:51:33 +0000 Message-Id: <20230727215141.53910-10-avolmat@me.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727215141.53910-1-avolmat@me.com> References: <20230727215141.53910-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-GUID: nKb5f2cpnaihHY5bXmpaeaKvag7Hfgjh X-Proofpoint-ORIG-GUID: nKb5f2cpnaihHY5bXmpaeaKvag7Hfgjh X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E170-?= =?utf-8?q?22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E425=2C18=2E0?= =?utf-8?q?=2E572=2C17=2E0=2E605=2E474=2E0000000_definitions=3D2022-01-11=5F?= =?utf-8?q?01=3A2022-01-11=5F01=2C2020-02-14=5F11=2C2020-01-23=5F02_signatur?= =?utf-8?q?es=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 malwarescore=0 clxscore=1015 suspectscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2307270199 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772613645783914670 X-GMAIL-MSGID: 1772613645783914670 The STiH418 platform embeds two kinds of graphical planes (GDP), so called GDPPLUS which has additional (yet unimplemented) features compared to the GDP, and also the GDP. Register map of GDPPLUS slightly differ from the GDP even if, for common functionalities registers name and behavior are the same (but not at same addresses). For that purpose, this commit rework the way of addressing the GDP(PLUS) registers. Signed-off-by: Alain Volmat --- drivers/gpu/drm/sti/sti_compositor.c | 4 + drivers/gpu/drm/sti/sti_compositor.h | 1 + drivers/gpu/drm/sti/sti_gdp.c | 250 ++++++++++++++++----------- drivers/gpu/drm/sti/sti_gdp.h | 8 +- 4 files changed, 163 insertions(+), 100 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_compositor.c b/drivers/gpu/drm/sti/sti_compositor.c index 33487a1fed8f..4bd7e305ab75 100644 --- a/drivers/gpu/drm/sti/sti_compositor.c +++ b/drivers/gpu/drm/sti/sti_compositor.c @@ -87,6 +87,7 @@ static int sti_compositor_bind(struct device *dev, compo->regs + desc[i].offset); break; case STI_GPD_SUBDEV: + case STI_GPDPLUS_SUBDEV: case STI_CURSOR_SUBDEV: /* Nothing to do, wait for the second round */ break; @@ -120,7 +121,10 @@ static int sti_compositor_bind(struct device *dev, } break; case STI_GPD_SUBDEV: + case STI_GPDPLUS_SUBDEV: primary = sti_gdp_create(drm_dev, compo->dev, + desc[i].type == STI_GPD_SUBDEV ? + STI_GDP_TYPE_GDP : STI_GDP_TYPE_GDPPLUS, desc[i].id, compo->regs + desc[i].offset, (1 << mixer_id) - 1, diff --git a/drivers/gpu/drm/sti/sti_compositor.h b/drivers/gpu/drm/sti/sti_compositor.h index 25bb01bdd013..62545210b96d 100644 --- a/drivers/gpu/drm/sti/sti_compositor.h +++ b/drivers/gpu/drm/sti/sti_compositor.h @@ -24,6 +24,7 @@ enum sti_compositor_subdev_type { STI_MIXER_MAIN_SUBDEV, STI_MIXER_AUX_SUBDEV, STI_GPD_SUBDEV, + STI_GPDPLUS_SUBDEV, STI_VID_SUBDEV, STI_CURSOR_SUBDEV, }; diff --git a/drivers/gpu/drm/sti/sti_gdp.c b/drivers/gpu/drm/sti/sti_gdp.c index 43c72c2604a0..1f4064d64f15 100644 --- a/drivers/gpu/drm/sti/sti_gdp.c +++ b/drivers/gpu/drm/sti/sti_gdp.c @@ -55,6 +55,7 @@ static struct gdp_format_to_str { GDP2STR(ARGB4444) }; +/* GDP register offsets */ #define GAM_GDP_CTL_OFFSET 0x00 #define GAM_GDP_AGC_OFFSET 0x04 #define GAM_GDP_VPO_OFFSET 0x0C @@ -67,8 +68,45 @@ static struct gdp_format_to_str { #define GAM_GDP_KEY2_OFFSET 0x2C #define GAM_GDP_PPT_OFFSET 0x34 #define GAM_GDP_CML_OFFSET 0x3C +#define GAM_GDP_NODE_SIZE 0x40 #define GAM_GDP_MST_OFFSET 0x68 +/* GDPPLUS register offsets */ +#define GAM_GDPPLUS_CTL_OFFSET 0x00 +#define GAM_GDPPLUS_AGC_OFFSET 0x04 +#define GAM_GDPPLUS_VPO_OFFSET 0x08 +#define GAM_GDPPLUS_VPS_OFFSET 0x0C +#define GAM_GDPPLUS_PML_OFFSET 0x10 +#define GAM_GDPPLUS_PMP_OFFSET 0x14 +#define GAM_GDPPLUS_SIZE_OFFSET 0x18 +#define GAM_GDPPLUS_NVN_OFFSET 0x1C +#define GAM_GDPPLUS_KEY1_OFFSET 0x20 +#define GAM_GDPPLUS_KEY2_OFFSET 0x24 +#define GAM_GDPPLUS_HFP_OFFSET 0x28 +#define GAM_GDPPLUS_PPT_OFFSET 0x2C +#define GAM_GDPPLUS_VFP_OFFSET 0x30 +#define GAM_GDPPLUS_CML_OFFSET 0x34 +#define GAM_GDPPLUS_CROP_OFFSET 0x38 +#define GAM_GDPPLUS_BT0_OFFSET 0x3C +#define GAM_GDPPLUS_BT1_OFFSET 0x40 +#define GAM_GDPPLUS_BT2_OFFSET 0x44 +#define GAM_GDPPLUS_BT3_OFFSET 0x48 +#define GAM_GDPPLUS_BT4_OFFSET 0x4C +#define GAM_GDPPLUS_HSRC_OFFSET 0x50 +#define GAM_GDPPLUS_HIP_OFFSET 0x54 +#define GAM_GDPPLUS_HP1_OFFSET 0x58 +#define GAM_GDPPLUS_HP2_OFFSET 0x5C +#define GAM_GDPPLUS_VSRC_OFFSET 0x60 +#define GAM_GDPPLUS_VIP_OFFSET 0x64 +#define GAM_GDPPLUS_VP1_OFFSET 0x68 +#define GAM_GDPPLUS_VP2_OFFSET 0x6C +#define GAM_GDPPLUS_NODE_SIZE 0x500 + +/* Accessor for common registers */ +#define GAM_OFFSET(reg, type) ((type) == STI_GDP_TYPE_GDP ? GAM_GDP_ ## reg ## _OFFSET :\ + GAM_GDPPLUS_ ## reg ## _OFFSET) +#define GAM_OFFSET_U32(reg, type) (GAM_OFFSET(reg, type) >> 2) + #define GAM_GDP_ALPHARANGE_255 BIT(5) #define GAM_GDP_AGC_FULL_RANGE 0x00808080 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) @@ -79,29 +117,10 @@ static struct gdp_format_to_str { #define GDP_NODE_NB_BANK 2 #define GDP_NODE_PER_FIELD 2 -struct sti_gdp_node { - u32 gam_gdp_ctl; - u32 gam_gdp_agc; - u32 reserved1; - u32 gam_gdp_vpo; - u32 gam_gdp_vps; - u32 gam_gdp_pml; - u32 gam_gdp_pmp; - u32 gam_gdp_size; - u32 reserved2; - u32 gam_gdp_nvn; - u32 gam_gdp_key1; - u32 gam_gdp_key2; - u32 reserved3; - u32 gam_gdp_ppt; - u32 reserved4; - u32 gam_gdp_cml; -}; - struct sti_gdp_node_list { - struct sti_gdp_node *top_field; + u32 *top_field; dma_addr_t top_field_paddr; - struct sti_gdp_node *btm_field; + u32 *btm_field; dma_addr_t btm_field_paddr; }; @@ -130,6 +149,7 @@ struct sti_gdp { bool is_curr_top; struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; struct sti_vtg *vtg; + enum sti_gdp_type type; }; #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) @@ -145,8 +165,8 @@ static const uint32_t gdp_supported_formats[] = { DRM_FORMAT_RGB888, }; -#define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ - readl(gdp->regs + reg ## _OFFSET)) +#define DBGFS_DUMP(reg, offset) seq_printf(s, "\n %-25s 0x%08X", #reg, \ + readl(gdp->regs + (offset))) static void gdp_dbg_ctl(struct seq_file *s, int val) { @@ -216,6 +236,7 @@ static int gdp_dbg_show(struct seq_file *s, void *data) { struct drm_info_node *node = s->private; struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; + struct device_node *np = gdp->dev->of_node; struct drm_plane *drm_plane = &gdp->plane.drm_plane; struct drm_crtc *crtc; @@ -226,26 +247,28 @@ static int gdp_dbg_show(struct seq_file *s, void *data) seq_printf(s, "%s: (vaddr = 0x%p)", sti_plane_to_str(&gdp->plane), gdp->regs); - DBGFS_DUMP(GAM_GDP_CTL); - gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); - DBGFS_DUMP(GAM_GDP_AGC); - DBGFS_DUMP(GAM_GDP_VPO); - gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); - DBGFS_DUMP(GAM_GDP_VPS); - gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); - DBGFS_DUMP(GAM_GDP_PML); - DBGFS_DUMP(GAM_GDP_PMP); - DBGFS_DUMP(GAM_GDP_SIZE); - gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); - DBGFS_DUMP(GAM_GDP_NVN); - gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET)); - DBGFS_DUMP(GAM_GDP_KEY1); - DBGFS_DUMP(GAM_GDP_KEY2); - DBGFS_DUMP(GAM_GDP_PPT); - gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); - DBGFS_DUMP(GAM_GDP_CML); - DBGFS_DUMP(GAM_GDP_MST); - gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); + DBGFS_DUMP(CTL, GAM_OFFSET(CTL, gdp->type)); + gdp_dbg_ctl(s, readl(gdp->regs + GAM_OFFSET(CTL, gdp->type))); + DBGFS_DUMP(AGC, GAM_OFFSET(AGC, gdp->type)); + DBGFS_DUMP(VPO, GAM_OFFSET(VPO, gdp->type)); + gdp_dbg_vpo(s, readl(gdp->regs + GAM_OFFSET(VPO, gdp->type))); + DBGFS_DUMP(VPS, GAM_OFFSET(VPS, gdp->type)); + gdp_dbg_vps(s, readl(gdp->regs + GAM_OFFSET(VPS, gdp->type))); + DBGFS_DUMP(PML, GAM_OFFSET(PML, gdp->type)); + DBGFS_DUMP(PMP, GAM_OFFSET(PMP, gdp->type)); + DBGFS_DUMP(SIZE, GAM_OFFSET(SIZE, gdp->type)); + gdp_dbg_size(s, readl(gdp->regs + GAM_OFFSET(SIZE, gdp->type))); + DBGFS_DUMP(NVN, GAM_OFFSET(NVN, gdp->type)); + gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_OFFSET(NVN, gdp->type))); + DBGFS_DUMP(KEY1, GAM_OFFSET(KEY1, gdp->type)); + DBGFS_DUMP(KEY2, GAM_OFFSET(KEY2, gdp->type)); + DBGFS_DUMP(PPT, GAM_OFFSET(PPT, gdp->type)); + gdp_dbg_ppt(s, readl(gdp->regs + GAM_OFFSET(PPT, gdp->type))); + DBGFS_DUMP(CML, GAM_OFFSET(CML, gdp->type)); + if (of_device_is_compatible(np, "st,stih407-compositor")) { + DBGFS_DUMP(MST, GAM_GDP_MST_OFFSET); + gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); + } seq_puts(s, "\n\n"); if (!crtc) @@ -257,26 +280,26 @@ static int gdp_dbg_show(struct seq_file *s, void *data) return 0; } -static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node) +static void gdp_node_dump_node(struct seq_file *s, u32 *node, enum sti_gdp_type type) { seq_printf(s, "\t@:0x%p", node); - seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl); - gdp_dbg_ctl(s, node->gam_gdp_ctl); - seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc); - seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo); - gdp_dbg_vpo(s, node->gam_gdp_vpo); - seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps); - gdp_dbg_vps(s, node->gam_gdp_vps); - seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml); - seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp); - seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size); - gdp_dbg_size(s, node->gam_gdp_size); - seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn); - seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1); - seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2); - seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt); - gdp_dbg_ppt(s, node->gam_gdp_ppt); - seq_printf(s, "\n\tCML 0x%08X\n", node->gam_gdp_cml); + seq_printf(s, "\n\tCTL 0x%08X", node[GAM_OFFSET_U32(CTL, type)]); + gdp_dbg_ctl(s, node[GAM_OFFSET_U32(CTL, type)]); + seq_printf(s, "\n\tAGC 0x%08X", node[GAM_OFFSET_U32(AGC, type)]); + seq_printf(s, "\n\tVPO 0x%08X", node[GAM_OFFSET_U32(VPO, type)]); + gdp_dbg_vpo(s, node[GAM_OFFSET_U32(VPO, type)]); + seq_printf(s, "\n\tVPS 0x%08X", node[GAM_OFFSET_U32(VPS, type)]); + gdp_dbg_vps(s, node[GAM_OFFSET_U32(VPS, type)]); + seq_printf(s, "\n\tPML 0x%08X", node[GAM_OFFSET_U32(PML, type)]); + seq_printf(s, "\n\tPMP 0x%08X", node[GAM_OFFSET_U32(PMP, type)]); + seq_printf(s, "\n\tSIZE 0x%08X", node[GAM_OFFSET_U32(SIZE, type)]); + gdp_dbg_size(s, node[GAM_OFFSET_U32(SIZE, type)]); + seq_printf(s, "\n\tNVN 0x%08X", node[GAM_OFFSET_U32(NVN, type)]); + seq_printf(s, "\n\tKEY1 0x%08X", node[GAM_OFFSET_U32(KEY1, type)]); + seq_printf(s, "\n\tKEY2 0x%08X", node[GAM_OFFSET_U32(KEY2, type)]); + seq_printf(s, "\n\tPPT 0x%08X", node[GAM_OFFSET_U32(PPT, type)]); + gdp_dbg_ppt(s, node[GAM_OFFSET_U32(PPT, type)]); + seq_printf(s, "\n\tCML 0x%08X\n", node[GAM_OFFSET_U32(CML, type)]); } static int gdp_node_dbg_show(struct seq_file *s, void *arg) @@ -287,9 +310,9 @@ static int gdp_node_dbg_show(struct seq_file *s, void *arg) for (b = 0; b < GDP_NODE_NB_BANK; b++) { seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b); - gdp_node_dump_node(s, gdp->node_list[b].top_field); + gdp_node_dump_node(s, gdp->node_list[b].top_field, gdp->type); seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b); - gdp_node_dump_node(s, gdp->node_list[b].btm_field); + gdp_node_dump_node(s, gdp->node_list[b].btm_field, gdp->type); } return 0; @@ -315,6 +338,16 @@ static struct drm_info_list gdp3_debugfs_files[] = { { "gdp3_node", gdp_node_dbg_show, 0, NULL }, }; +static struct drm_info_list gdp4_debugfs_files[] = { + { "gdp4", gdp_dbg_show, 0, NULL }, + { "gdp4_node", gdp_node_dbg_show, 0, NULL }, +}; + +static struct drm_info_list gdp5_debugfs_files[] = { + { "gdp5", gdp_dbg_show, 0, NULL }, + { "gdp5_node", gdp_node_dbg_show, 0, NULL }, +}; + static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) { unsigned int i; @@ -338,6 +371,14 @@ static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) gdp_debugfs_files = gdp3_debugfs_files; nb_files = ARRAY_SIZE(gdp3_debugfs_files); break; + case STI_GDP_4: + gdp_debugfs_files = gdp4_debugfs_files; + nb_files = ARRAY_SIZE(gdp4_debugfs_files); + break; + case STI_GDP_5: + gdp_debugfs_files = gdp5_debugfs_files; + nb_files = ARRAY_SIZE(gdp5_debugfs_files); + break; default: return -EINVAL; } @@ -397,9 +438,10 @@ static int sti_gdp_get_alpharange(int format) static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) { int hw_nvn; + u32 nvn_off = GAM_OFFSET(NVN, gdp->type); unsigned int i; - hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); + hw_nvn = readl(gdp->regs + nvn_off); if (!hw_nvn) goto end; @@ -429,9 +471,10 @@ static struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) { int hw_nvn; + u32 nvn_off = GAM_OFFSET(NVN, gdp->type); unsigned int i; - hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); + hw_nvn = readl(gdp->regs + nvn_off); if (!hw_nvn) goto end; @@ -456,13 +499,14 @@ struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) static void sti_gdp_disable(struct sti_gdp *gdp) { unsigned int i; + u32 ppt_off = GAM_OFFSET_U32(PPT, gdp->type); DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); /* Set the nodes as 'to be ignored on mixer' */ for (i = 0; i < GDP_NODE_NB_BANK; i++) { - gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; - gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; + gdp->node_list[i].top_field[ppt_off] |= GAM_GDP_PPT_IGNORE; + gdp->node_list[i].btm_field[ppt_off] |= GAM_GDP_PPT_IGNORE; } if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) @@ -519,11 +563,16 @@ static void sti_gdp_init(struct sti_gdp *gdp) struct device_node *np = gdp->dev->of_node; dma_addr_t dma_addr; void *base; - unsigned int i, size; + unsigned int i, size, gdp_node_size; + + /* Check the type of GDP */ + if (gdp->type == STI_GDP_TYPE_GDP) + gdp_node_size = GAM_GDP_NODE_SIZE; + else + gdp_node_size = GAM_GDPPLUS_NODE_SIZE; /* Allocate all the nodes within a single memory page */ - size = sizeof(struct sti_gdp_node) * - GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; + size = gdp_node_size * GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL); if (!base) { @@ -541,8 +590,8 @@ static void sti_gdp_init(struct sti_gdp *gdp) gdp->node_list[i].top_field_paddr = dma_addr; DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); - base += sizeof(struct sti_gdp_node); - dma_addr += sizeof(struct sti_gdp_node); + base += gdp_node_size; + dma_addr += gdp_node_size; if (dma_addr & 0xF) { DRM_ERROR("Mem alignment failed\n"); @@ -551,8 +600,8 @@ static void sti_gdp_init(struct sti_gdp *gdp) gdp->node_list[i].btm_field = base; gdp->node_list[i].btm_field_paddr = dma_addr; DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); - base += sizeof(struct sti_gdp_node); - dma_addr += sizeof(struct sti_gdp_node); + base += gdp_node_size; + dma_addr += gdp_node_size; } if (of_device_is_compatible(np, "st,stih407-compositor")) { @@ -717,7 +766,7 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane, struct drm_gem_dma_object *dma_obj; struct sti_gdp_node_list *list; struct sti_gdp_node_list *curr_list; - struct sti_gdp_node *top_field, *btm_field; + u32 *top_field, *btm_field; u32 dma_updated_top; u32 dma_updated_btm; int format; @@ -771,12 +820,12 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane, sti_plane_to_str(plane), top_field, btm_field); /* build the top field */ - top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; - top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; + top_field[GAM_OFFSET_U32(AGC, gdp->type)] = GAM_GDP_AGC_FULL_RANGE; + top_field[GAM_OFFSET_U32(CTL, gdp->type)] = WAIT_NEXT_VSYNC; format = sti_gdp_fourcc2format(fb->format->format); - top_field->gam_gdp_ctl |= format; - top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); - top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; + top_field[GAM_OFFSET_U32(CTL, gdp->type)] |= format; + top_field[GAM_OFFSET_U32(CTL, gdp->type)] |= sti_gdp_get_alpharange(format); + top_field[GAM_OFFSET_U32(PPT, gdp->type)] &= ~GAM_GDP_PPT_IGNORE; dma_obj = drm_fb_dma_get_gem_obj(fb, 0); @@ -786,9 +835,9 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane, /* pixel memory location */ bpp = fb->format->cpp[0]; - top_field->gam_gdp_pml = (u32) dma_obj->dma_addr + fb->offsets[0]; - top_field->gam_gdp_pml += src_x * bpp; - top_field->gam_gdp_pml += src_y * fb->pitches[0]; + top_field[GAM_OFFSET_U32(PML, gdp->type)] = (u32)dma_obj->dma_addr + fb->offsets[0]; + top_field[GAM_OFFSET_U32(PML, gdp->type)] += src_x * bpp; + top_field[GAM_OFFSET_U32(PML, gdp->type)] += src_y * fb->pitches[0]; /* output parameters (clamped / cropped) */ dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); @@ -797,23 +846,25 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane, yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); xdo = sti_vtg_get_pixel_number(*mode, dst_x); xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); - top_field->gam_gdp_vpo = (ydo << 16) | xdo; - top_field->gam_gdp_vps = (yds << 16) | xds; + top_field[GAM_OFFSET_U32(VPO, gdp->type)] = (ydo << 16) | xdo; + top_field[GAM_OFFSET_U32(VPS, gdp->type)] = (yds << 16) | xds; /* input parameters */ src_w = dst_w; - top_field->gam_gdp_pmp = fb->pitches[0]; - top_field->gam_gdp_size = src_h << 16 | src_w; + top_field[GAM_OFFSET_U32(PMP, gdp->type)] = fb->pitches[0]; + top_field[GAM_OFFSET_U32(SIZE, gdp->type)] = src_h << 16 | src_w; /* Same content and chained together */ - memcpy(btm_field, top_field, sizeof(*btm_field)); - top_field->gam_gdp_nvn = list->btm_field_paddr; - btm_field->gam_gdp_nvn = list->top_field_paddr; + memcpy(btm_field, top_field, + gdp->type == STI_GDP_TYPE_GDP ? + GAM_GDP_NODE_SIZE : GAM_GDPPLUS_NODE_SIZE); + top_field[GAM_OFFSET_U32(NVN, gdp->type)] = list->btm_field_paddr; + btm_field[GAM_OFFSET_U32(NVN, gdp->type)] = list->top_field_paddr; /* Interlaced mode */ if (mode->flags & DRM_MODE_FLAG_INTERLACE) - btm_field->gam_gdp_pml = top_field->gam_gdp_pml + - fb->pitches[0]; + btm_field[GAM_OFFSET_U32(PML, gdp->type)] = + top_field[GAM_OFFSET_U32(PML, gdp->type)] + fb->pitches[0]; /* Update the NVN field of the 'right' field of the current GDP node * (being used by the HW) with the address of the updated ('free') top @@ -829,10 +880,10 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane, dma_updated_btm = list->btm_field_paddr; dev_dbg(gdp->dev, "Current NVN:0x%X\n", - readl(gdp->regs + GAM_GDP_NVN_OFFSET)); + readl(gdp->regs + GAM_OFFSET(NVN, gdp->type))); dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", (unsigned long) dma_obj->dma_addr, - readl(gdp->regs + GAM_GDP_PML_OFFSET)); + readl(gdp->regs + GAM_OFFSET(PML, gdp->type))); if (!curr_list) { /* First update or invalid node should directly write in the @@ -842,7 +893,7 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane, writel(gdp->is_curr_top ? dma_updated_btm : dma_updated_top, - gdp->regs + GAM_GDP_NVN_OFFSET); + gdp->regs + GAM_OFFSET(NVN, gdp->type)); goto end; } @@ -851,15 +902,15 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane, /* Do not update in the middle of the frame, but * postpone the update after the bottom field has * been displayed */ - curr_list->btm_field->gam_gdp_nvn = dma_updated_top; + curr_list->btm_field[GAM_OFFSET_U32(NVN, gdp->type)] = dma_updated_top; } else { /* Direct update to avoid one frame delay */ writel(dma_updated_top, - gdp->regs + GAM_GDP_NVN_OFFSET); + gdp->regs + GAM_OFFSET(NVN, gdp->type)); } } else { /* Direct update for progressive to avoid one frame delay */ - writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); + writel(dma_updated_top, gdp->regs + GAM_OFFSET(NVN, gdp->type)); } end: @@ -914,7 +965,7 @@ static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = { }; struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, - struct device *dev, int desc, + struct device *dev, enum sti_gdp_type gdp_type, int desc, void __iomem *baseaddr, unsigned int possible_crtcs, enum drm_plane_type type) @@ -932,6 +983,7 @@ struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, gdp->regs = baseaddr; gdp->plane.desc = desc; gdp->plane.status = STI_PLANE_DISABLED; + gdp->type = gdp_type; gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; diff --git a/drivers/gpu/drm/sti/sti_gdp.h b/drivers/gpu/drm/sti/sti_gdp.h index deb07e34173d..b1f06a0c5c37 100644 --- a/drivers/gpu/drm/sti/sti_gdp.h +++ b/drivers/gpu/drm/sti/sti_gdp.h @@ -16,8 +16,14 @@ struct drm_device; struct device; +enum sti_gdp_type { + STI_GDP_TYPE_GDP, + STI_GDP_TYPE_GDPPLUS, +}; + struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, - struct device *dev, int desc, + struct device *dev, enum sti_gdp_type gdp_type, + int desc, void __iomem *baseaddr, unsigned int possible_crtcs, enum drm_plane_type type); From patchwork Thu Jul 27 21:51:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 127255 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp81765vqg; Thu, 27 Jul 2023 16:53:11 -0700 (PDT) X-Google-Smtp-Source: APBJJlH6taPWcVN2QTdZHYe9gORmt5F5vkSA1fNV3LOQQCiqlcqzbFSzCQMrLRm0JOpi5Tf6fkdV X-Received: by 2002:a05:6870:4251:b0:1ba:199a:984a with SMTP id v17-20020a056870425100b001ba199a984amr1093598oac.55.1690501991034; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id fe9-20020a056a002f0900b00686d854cb0dsi1961826pfb.23.2023.07.27.16.52.49; Thu, 27 Jul 2023 16:53:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=HfaFosew; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232741AbjG0Vxs (ORCPT + 99 others); Thu, 27 Jul 2023 17:53:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232706AbjG0VxU (ORCPT ); Thu, 27 Jul 2023 17:53:20 -0400 Received: from qs51p00im-qukt01080501.me.com (qs51p00im-qukt01080501.me.com [17.57.155.22]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7468526AE for ; Thu, 27 Jul 2023 14:52:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1690494770; bh=KmnZ+NHz7PM0U1A/IX51H2Bjow4KLdppH5jj9uz/ocI=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=HfaFosewupSVW4LocN+Fh45yv/yOk7DM9vl1uPwvbMH+nnbcnyarbV9vT40J2YooV UYMrQFw1oPX8FyWjC4KfhWDMT1KtcbCydp+3dKYrphHGkml97N29HcFeTPMiZTld/X 89F2gfJZ2zapirmPqwaGu2ww6kZ5RvNlTwSRo5ll5x/T4vjkF19qNs9OHlmossenC2 R607BIJEEV44c0Qg1g2sy27AQFbd4zC1ZbNH8dzq5IQuAPlvuxFAkxIVR1Rl5xxJ0v CB1NZXHlgHphrtEdk0ICdE8UKPEYMRiQ0O0P9W3U8nVvq5bPjwbd3NNcOgirSqZxuG 0qXkjFvsyO5dQ== Received: from localhost (qs51p00im-dlb-asmtp-mailmevip.me.com [17.57.155.28]) by qs51p00im-qukt01080501.me.com (Postfix) with ESMTPSA id 0D14B1980373; Thu, 27 Jul 2023 21:52:49 +0000 (UTC) From: Alain Volmat To: Alain Volmat , David Airlie , Daniel Vetter Cc: Alain Volmat , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14] drm/sti: add compositor support for stih418 platform Date: Thu, 27 Jul 2023 21:51:34 +0000 Message-Id: <20230727215141.53910-11-avolmat@me.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727215141.53910-1-avolmat@me.com> References: <20230727215141.53910-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-GUID: caJkhSSYKcGWfwaRe3kL8KLlbXUXZNhq X-Proofpoint-ORIG-GUID: caJkhSSYKcGWfwaRe3kL8KLlbXUXZNhq X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E170-?= =?utf-8?q?22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E138=2C18=2E0?= =?utf-8?q?=2E790=2C17=2E11=2E62=2E513=2E0000000_definitions=3D2022-01-12=5F?= =?utf-8?q?02=3A2020-02-14=5F02=2C2022-01-12=5F02=2C2021-12-02=5F01_signatur?= =?utf-8?q?es=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2307270198 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772619815856291509 X-GMAIL-MSGID: 1772619815856291509 On the STiH418, a new clock (proc_mixer) must be enabled in order to have the plane mixers properly behaving. Add a new st,stih418-compositor in order to describe the planes/mixers available on this platform. Signed-off-by: Alain Volmat --- drivers/gpu/drm/sti/sti_compositor.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/sti/sti_compositor.h | 2 ++ drivers/gpu/drm/sti/sti_crtc.c | 11 +++++++++++ 3 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/sti/sti_compositor.c b/drivers/gpu/drm/sti/sti_compositor.c index 4bd7e305ab75..dfea3c1191a6 100644 --- a/drivers/gpu/drm/sti/sti_compositor.c +++ b/drivers/gpu/drm/sti/sti_compositor.c @@ -43,6 +43,23 @@ static const struct sti_compositor_data stih407_compositor_data = { }, }; +/* + * stiH418 compositor properties + */ +static const struct sti_compositor_data stih418_compositor_data = { + .nb_subdev = 8, + .subdev_desc = { + {STI_GPDPLUS_SUBDEV, (int)STI_GDP_0, 0x00000}, + {STI_GPDPLUS_SUBDEV, (int)STI_GDP_1, 0x10000}, + {STI_GPDPLUS_SUBDEV, (int)STI_GDP_2, 0x20000}, + {STI_GPDPLUS_SUBDEV, (int)STI_GDP_3, 0x30000}, + {STI_GPD_SUBDEV, (int)STI_GDP_4, 0x40000}, + {STI_GPD_SUBDEV, (int)STI_GDP_5, 0x50000}, + {STI_MIXER_MAIN_SUBDEV, STI_MIXER_MAIN, 0x100000}, + {STI_MIXER_AUX_SUBDEV, STI_MIXER_AUX, 0x110000}, + }, +}; + void sti_compositor_debugfs_init(struct sti_compositor *compo, struct drm_minor *minor) { @@ -169,6 +186,9 @@ static const struct of_device_id compositor_of_match[] = { { .compatible = "st,stih407-compositor", .data = &stih407_compositor_data, + }, { + .compatible = "st,stih418-compositor", + .data = &stih418_compositor_data, }, { /* end node */ } @@ -236,6 +256,12 @@ static int sti_compositor_probe(struct platform_device *pdev) return PTR_ERR(compo->clk_pix_aux); } + compo->clk_proc_mixer = devm_clk_get_optional(dev, "proc_mixer"); + if (IS_ERR(compo->clk_proc_mixer)) { + DRM_ERROR("Cannot get proc_mixer clock\n"); + return PTR_ERR(compo->clk_proc_mixer); + } + /* Get reset resources */ compo->rst_main = devm_reset_control_get_shared(dev, "compo-main"); /* Take compo main out of reset */ diff --git a/drivers/gpu/drm/sti/sti_compositor.h b/drivers/gpu/drm/sti/sti_compositor.h index 62545210b96d..fdc655f78579 100644 --- a/drivers/gpu/drm/sti/sti_compositor.h +++ b/drivers/gpu/drm/sti/sti_compositor.h @@ -57,6 +57,7 @@ struct sti_compositor_data { * @clk_compo_aux: clock for aux compo * @clk_pix_main: pixel clock for main path * @clk_pix_aux: pixel clock for aux path + * @clk_proc_mixer: clock for the mixers * @rst_main: reset control of the main path * @rst_aux: reset control of the aux path * @mixer: array of mixers @@ -72,6 +73,7 @@ struct sti_compositor { struct clk *clk_compo_aux; struct clk *clk_pix_main; struct clk *clk_pix_aux; + struct clk *clk_proc_mixer; struct reset_control *rst_main; struct reset_control *rst_aux; struct sti_mixer *mixer[STI_MAX_MIXER]; diff --git a/drivers/gpu/drm/sti/sti_crtc.c b/drivers/gpu/drm/sti/sti_crtc.c index 3c7154f2d5f3..d93764e99b0e 100644 --- a/drivers/gpu/drm/sti/sti_crtc.c +++ b/drivers/gpu/drm/sti/sti_crtc.c @@ -67,6 +67,12 @@ sti_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode) pix_clk = compo->clk_pix_aux; } + /* Enable the mixer processing clock (if applicable) */ + if (clk_prepare_enable(compo->clk_proc_mixer)) { + DRM_INFO("Failed to prepare/enable processing mixer clk\n"); + goto proc_mixer_error; + } + /* Prepare and enable the compo IP clock */ if (clk_prepare_enable(compo_clk)) { DRM_INFO("Failed to prepare/enable compositor clk\n"); @@ -97,6 +103,8 @@ sti_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode) pix_error: clk_disable_unprepare(compo_clk); compo_error: + clk_disable_unprepare(compo->clk_proc_mixer); +proc_mixer_error: return -EINVAL; } @@ -122,6 +130,9 @@ static void sti_crtc_disable(struct drm_crtc *crtc) clk_disable_unprepare(compo->clk_compo_aux); } + /* Disable the mixer clock (if applicable) */ + clk_disable_unprepare(compo->clk_proc_mixer); + mixer->status = STI_MIXER_DISABLED; } From patchwork Thu Jul 27 21:51:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 127220 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp42527vqg; Thu, 27 Jul 2023 15:18:41 -0700 (PDT) X-Google-Smtp-Source: APBJJlGjWzvdvOlzBbk2pUEFyG+LYaovA8954abOfO8N67NcZYrmllpCmg0merKLbEw4tVVWzCxW X-Received: by 2002:a9d:7d8c:0:b0:6b5:6b95:5876 with SMTP id j12-20020a9d7d8c000000b006b56b955876mr463549otn.25.1690496321025; Thu, 27 Jul 2023 15:18:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690496320; cv=none; d=google.com; s=arc-20160816; b=BD+z8aXQo+yALb1DMO9Ye+bls9r8uR3ysmAbGPy+jUjW4kCBYuYtbZQ5fD52H9EKBU +qFeXKiH7UlmWRfu4YLHQH+YXaolrxv2GZvXcydlVP+uUXS7s6xgpkOjHVqpdRPHSUr5 dS2NpbVOas2ENv6To+Ljv6qKzn5XyOBof8aRyg6niNDLrgycTDB14PtqEtq4WR4NqtrY aSgBdCgoLuQygrpDeSAYZtFJSh7KvCFHvii4U+QpoD9RA92LuXkH1YUTPJVkg6vzQPHO 9F/sc41Q0SYHxFDHn2OFACbFhQXppOHKxXMeIYarIzV9PAqgH4c/K6hR2YIOAjbs9xeB RmfQ== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n12-20020a63e04c000000b00563fbc0000csi1834037pgj.254.2023.07.27.15.18.27; Thu, 27 Jul 2023 15:18:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=iWSH1EJW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232517AbjG0Vxv (ORCPT + 99 others); Thu, 27 Jul 2023 17:53:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232469AbjG0Vx0 (ORCPT ); Thu, 27 Jul 2023 17:53:26 -0400 Received: from qs51p00im-qukt01080301.me.com (qs51p00im-qukt01080301.me.com [17.57.155.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB77935A3 for ; Thu, 27 Jul 2023 14:52:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1690494773; bh=HXQLqgiZg4lwSg7yuJp70xhHYQeGMquqwwsl6uxX+/s=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=iWSH1EJWwkMfSRqn9vJtLQPTLaZ45ToCmc5035Zl4yf9t6z4GcEA75Q5iEj5/fxsv rzI8ULoVds72y8jayIA8pvf0IslVNASIwoOS4/flQrYfIsh6HPC9mB4EE1FxIbNhJ9 o4lDZRViIyBF6y1Ow2ZgtiXApM3UvIKu10DYr8EePi7CreB9vLTK3XgxizKq6554GJ bYXuQxJVyhPuQu0PFc6w9wzu0epGloaMnSvrqLG2gMW3hP/CGanqPOBvITBXlA2mdQ P60FNgyU56tScM9fAEzmBNYGTDVVnzwPGCIuJx3xgpZ7xfKKsd3Cd/sonKqJBtkRLr T6Rq+voTi8D2w== Received: from localhost (qs51p00im-dlb-asmtp-mailmevip.me.com [17.57.155.28]) by qs51p00im-qukt01080301.me.com (Postfix) with ESMTPSA id EE2DA5F00408; Thu, 27 Jul 2023 21:52:52 +0000 (UTC) From: Alain Volmat To: Patrice Chotard , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Alain Volmat , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14] ARM: dts: sti: move vtg_main / vtg_aux into stih407/stih410 dtsi Date: Thu, 27 Jul 2023 21:51:35 +0000 Message-Id: <20230727215141.53910-12-avolmat@me.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727215141.53910-1-avolmat@me.com> References: <20230727215141.53910-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-GUID: H5CenQRAQ1tfGLGPSffjITEBYJ75K4oo X-Proofpoint-ORIG-GUID: H5CenQRAQ1tfGLGPSffjITEBYJ75K4oo X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E170-?= =?utf-8?q?22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E425=2C18=2E0?= =?utf-8?q?=2E572=2C17=2E0=2E605=2E474=2E0000000_definitions=3D2022-01-11=5F?= =?utf-8?q?01=3A2022-01-11=5F01=2C2020-02-14=5F11=2C2020-01-23=5F02_signatur?= =?utf-8?q?es=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 clxscore=1015 mlxlogscore=907 spamscore=0 bulkscore=0 malwarescore=0 adultscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2307270199 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772613869784084571 X-GMAIL-MSGID: 1772613869784084571 In preparation of introduction of display support in stih418, move the vtg nodes into stih407.dtsi and stih410.dtsi since vtg nodes will differ in case of the stih418 and thus cannot be kept as part of the stih407-family.dtsi. Signed-off-by: Alain Volmat --- arch/arm/boot/dts/st/stih407-family.dtsi | 13 ------------- arch/arm/boot/dts/st/stih407.dtsi | 12 ++++++++++++ arch/arm/boot/dts/st/stih410.dtsi | 12 ++++++++++++ 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/st/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi index 3f58383a7b59..6133c9934651 100644 --- a/arch/arm/boot/dts/st/stih407-family.dtsi +++ b/arch/arm/boot/dts/st/stih407-family.dtsi @@ -292,19 +292,6 @@ syscfg_lpm: lpm-syscfg@94b5100 { reg = <0x94b5100 0x1000>; }; - /* Display */ - vtg_main: sti-vtg-main@8d02800 { - compatible = "st,vtg"; - reg = <0x8d02800 0x200>; - interrupts = ; - }; - - vtg_aux: sti-vtg-aux@8d00200 { - compatible = "st,vtg"; - reg = <0x8d00200 0x100>; - interrupts = ; - }; - serial@9830000 { compatible = "st,asc"; reg = <0x9830000 0x2c>; diff --git a/arch/arm/boot/dts/st/stih407.dtsi b/arch/arm/boot/dts/st/stih407.dtsi index aca43d2bdaad..69430556edc4 100644 --- a/arch/arm/boot/dts/st/stih407.dtsi +++ b/arch/arm/boot/dts/st/stih407.dtsi @@ -8,6 +8,18 @@ #include / { soc { + vtg_main: sti-vtg-main@8d02800 { + compatible = "st,vtg"; + reg = <0x8d02800 0x200>; + interrupts = ; + }; + + vtg_aux: sti-vtg-aux@8d00200 { + compatible = "st,vtg"; + reg = <0x8d00200 0x100>; + interrupts = ; + }; + sti-display-subsystem@0 { compatible = "st,sti-display-subsystem"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/st/stih410.dtsi b/arch/arm/boot/dts/st/stih410.dtsi index 29e95e9d3229..141db3dcaf1f 100644 --- a/arch/arm/boot/dts/st/stih410.dtsi +++ b/arch/arm/boot/dts/st/stih410.dtsi @@ -99,6 +99,18 @@ ehci1: usb@9a83e00 { status = "disabled"; }; + vtg_main: sti-vtg-main@8d02800 { + compatible = "st,vtg"; + reg = <0x8d02800 0x200>; + interrupts = ; + }; + + vtg_aux: sti-vtg-aux@8d00200 { + compatible = "st,vtg"; + reg = <0x8d00200 0x100>; + interrupts = ; + }; + sti-display-subsystem@0 { compatible = "st,sti-display-subsystem"; #address-cells = <1>; From patchwork Thu Jul 27 21:51:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 127211 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp39363vqg; Thu, 27 Jul 2023 15:11:12 -0700 (PDT) X-Google-Smtp-Source: APBJJlFha/VxqbcAcS+TK34pXHw4GtnEPCe+FUR7HlLPe+MDBFmXi2FWBJYXcwbG6ApkkCW/td2h X-Received: by 2002:a17:907:75e1:b0:98d:1f6a:fd47 with SMTP id jz1-20020a17090775e100b0098d1f6afd47mr368236ejc.76.1690495872030; Thu, 27 Jul 2023 15:11:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690495872; cv=none; d=google.com; s=arc-20160816; b=sN6J7/CIp9L9dMMJi/ZwvzPvrgXe93lEd6Jaho3hBG7gkgZhp7EbjU70XhylxnrPra HWLOW53rSmrYSUYITam5dt8HqWeeG4y6+tX4jpmkyYerUSPXIsVtSTp6JSzLfx70AfDp YIEHzURixfME3xVZLDbJK2lKARB3mtCkWiBMNWYT/fcK/ZmZs0MaewjpuV1rMrGpNow4 bIHRdbHrRF6c60DZenzlQfYBizPVRNC29bZQDvdMdo33xcRASK3bVuJYQ3apWdIC1DL6 ZHdCZQMWhKkQPw0sd4SEwEQNmzlpdyBzn1l0u9zJzHGLI9y7UKs9oMbJBluRYX+OV1a1 LBag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gvNeBYQHG/KwbIMbUxyFv2rdxHKz+V5JxrelDTmwgko=; fh=arHEyEuWZlF99VKrh6xxMtrGoUvdlsvpYSYGEdDlimo=; b=0q1AefwJ6SIV2Ng2eLuoHw85c5fFx/VLI2l4qQ5KitUZn3yWNXwJqZISo4mz25c6Pw NwNBpHCxmYbive2f/E1Ppbxbqr7G4UVqiDYojteyOsxb0xAK3IgoJJvJiVC4oh71hifB 0rUwU23Kf8zjNmGIUa8zxptxaGR08MOwxGWJ0Gkm5IzstyHDd3NsTsHyddAInO7yRI4i s3EUBhrUb2y2gjsiX65RXG6FWG2GjlyfoBbtxf0bbTi46VfhecIzAFDwdHYKPAFCfjLn dnSBCdpV8ua7Fw0G4OF701yRfKZbMTLNzgmHeUmA/PXW1yIa2WihU87aikvsySGSySP3 Ynmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=UrudoX9E; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Alain Volmat --- arch/arm/boot/dts/st/stih418-clock.dtsi | 2 +- arch/arm/boot/dts/st/stih418.dtsi | 154 ++++++++++++++++++++++++ 2 files changed, 155 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stih418-clock.dtsi b/arch/arm/boot/dts/st/stih418-clock.dtsi index e1749e92a2e7..93641df58bf2 100644 --- a/arch/arm/boot/dts/st/stih418-clock.dtsi +++ b/arch/arm/boot/dts/st/stih418-clock.dtsi @@ -17,7 +17,7 @@ clk_sysin: clk-sysin { clk_tmdsout_hdmi: clk-tmdsout-hdmi { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <0>; + clock-frequency = <594000000>; }; clocks { diff --git a/arch/arm/boot/dts/st/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi index b35b9b7a7ccc..b41de235fffa 100644 --- a/arch/arm/boot/dts/st/stih418.dtsi +++ b/arch/arm/boot/dts/st/stih418.dtsi @@ -6,6 +6,7 @@ #include "stih418-clock.dtsi" #include "stih407-family.dtsi" #include "stih410-pinctrl.dtsi" +#include / { cpus { #address-cells = <1>; @@ -114,5 +115,158 @@ thermal@91a0000 { clocks = <&clk_sysin>; interrupts = ; }; + + sti-display-subsystem@0 { + compatible = "st,sti-display-subsystem"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0 0>; + assigned-clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI_DIV2>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, + <&clk_s_c0_flexgen CLK_AUX_DISP>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_PROC_MIXER>; + + assigned-clock-parents = <0>, + <0>, + <&clk_tmdsout_hdmi>, + <&clk_tmdsout_hdmi>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll0 0>, + <&clk_s_c0_pll0 0>; + + assigned-clock-rates = <297000000>, + <108000000>, + <297000000>, + <0>, + <74250000>, + <13500000>, + <400000000>, + <400000000>, + <355000000>, + <355000000>; + + ranges; + + sti_compo: sti-compositor@a600000 { + compatible = "st,stih418-compositor"; + reg = <0xa600000 0x200000>; + + clock-names = "compo_main", + "compo_aux", + "pix_main", + "pix_aux", + "proc_mixer"; + + clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_c0_flexgen CLK_PROC_MIXER>; + + reset-names = "compo-main", "compo-aux"; + resets = <&softreset STIH407_COMPO_SOFTRESET>, + <&softreset STIH407_COMPO_SOFTRESET>; + st,vtg = <&vtg_main>, <&vtg_aux>; + + status = "disabled"; + }; + + sti_tvout: sti-tvout@a900000 { + compatible = "st,stih418-tvout"; + reg = <0xa900000 0x1000>; + reg-names = "tvout-reg"; + reset-names = "tvout"; + resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; + #address-cells = <1>; + #size-cells = <1>; + assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>; + + assigned-clock-parents = <&clk_s_d2_quadfs 0>, + <&clk_tmdsout_hdmi>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d0_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>; + assigned-clock-rates = <74250000>, + <0>, + <74250000>, + <0>, + <74250000>, + <148500000>; + + status = "disabled"; + }; + + sti_dvo: sti-dvo@a800400 { + compatible = "st,stih407-dvo"; + reg = <0xa800400 0x200>; + reg-names = "dvo-reg"; + clock-names = "dvo_pix", "dvo", + "main_parent", "aux_parent"; + clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, + <&clk_s_d2_flexgen CLK_DVO>, + <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; + status = "disabled"; + }; + + sti_hdmi: sti-hdmi@a804000 { + compatible = "st,stih418-hdmi"; + reg = <0xa804000 0x1000>; + reg-names = "hdmi-reg"; + #sound-dai-cells = <0>; + interrupts = ; + interrupt-names = "irq"; + clock-names = "pix", + "tmds", + "phy", + "audio", + "main_parent", + "aux_parent"; + + clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + + hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; + reset-names = "hdmi"; + resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; + + status = "disabled"; + }; + }; + + vtg_main: sti-vtg-main@a802800 { + compatible = "st,stih418-vtg"; + reg = <0xa802800 0x200>; + interrupts = ; + + status = "disabled"; + }; + + vtg_aux: sti-vtg-aux@a800200 { + compatible = "st,stih418-vtg"; + reg = <0xa800200 0x100>; + interrupts = ; + + status = "disabled"; + }; }; }; From patchwork Thu Jul 27 21:51:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 127218 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp41880vqg; Thu, 27 Jul 2023 15:17:10 -0700 (PDT) X-Google-Smtp-Source: APBJJlGbAUH7Ujyjf/sxdF7uWkHNqH9ESKmT3bY2HcDir01M2UCZllAsNx+YShPR7rfvC9uk0zes X-Received: by 2002:a05:6a20:a127:b0:133:e3e3:dc07 with SMTP id q39-20020a056a20a12700b00133e3e3dc07mr420770pzk.49.1690496229606; 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Signed-off-by: Alain Volmat --- arch/arm/boot/dts/st/stih418.dtsi | 34 +++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/st/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi index b41de235fffa..965931da5a3f 100644 --- a/arch/arm/boot/dts/st/stih418.dtsi +++ b/arch/arm/boot/dts/st/stih418.dtsi @@ -268,5 +268,39 @@ vtg_aux: sti-vtg-aux@a800200 { status = "disabled"; }; + + gpu: gpu@9f00000 { + compatible = "arm,mali-400"; + reg = <0x9f00000 0x10000>; + /* LIMA driver needs 2 clocks, use the same for both */ + clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>, + <&clk_s_c0_flexgen CLK_ICN_GPU>; + clock-names = "bus", "core"; + assigned-clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>; + assigned-clock-rates = <400000000>; + resets = <&softreset STIH407_GPU_SOFTRESET>; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + + status = "disabled"; + }; }; }; From patchwork Thu Jul 27 21:51:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 127254 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp81253vqg; Thu, 27 Jul 2023 16:51:48 -0700 (PDT) X-Google-Smtp-Source: APBJJlGtqbFh5ektEOqB/YFQv6Ab/foJlzpT6bPZlWKU98n2gs5Y01iyvbXMts73m6NfdDLE2Dpe X-Received: by 2002:a17:902:ab0c:b0:1b3:ea47:796c with SMTP id ik12-20020a170902ab0c00b001b3ea47796cmr56051plb.29.1690501907737; Thu, 27 Jul 2023 16:51:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690501907; cv=none; d=google.com; s=arc-20160816; b=WLX2KdMHxLsbdLtu7R9ZHtdyYmBkejm7aEgUICMIb5nmZvU8B/PPeT4i5wPiK8CtbU C+JHFBvQ3LIKQZxOeqYsMS/kQtUp9RZt891uQwW2j3TcKyvjCZdyEnsh8DCBUVE53F2g 8OCPFQ3SuEBY4fbldANR8yrMacMiqx1BIBl4uuWfUS6cU92JN+8xS+/k9pnm9+c2su9L /+LF22ngzd5Y1VyAcYPCuOZxP80jCUQ0akOw2fxeyiTSpKTDwhtgEeo909xduTBxXnU+ Ew3cYyPrJCfSMpU1aa5TbXeq+fa97tuBKaMAKSzdkB26t/AWdzbZ8f8FE6RSFXMVnIBa AWMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3kWvcrRZqrEhuwXPUYQrUx6oSTk+cnm7yyjGHHndlRg=; fh=arHEyEuWZlF99VKrh6xxMtrGoUvdlsvpYSYGEdDlimo=; b=FjId7R0HqJkTi9m5DF+N8+/HPdG41Shx0Q6mffjUsd1xpqF9xdmqc/SQA6Vth06C/5 5vqwmjE48HxqNf+pyXSrIwJeDuut81lDtfcTlpTsJ34vVToWfu7B5FTmQkLOLf3lRNqD Pjvd2NYmdqJSAb3E4X/VE2Lvl6jdO8f40uc/2uVEYZ/Hd78EV2abmozcDQbMkGJg1A+A z+z9nX7TLkaVZE2EjQQdNM60TDMYYfknyeLl4xHEA9CsQ8AXPuyncoW1JTW0Fi6TmC2F 9GGfuBGjUNoScAvzd1SOAoGoR5zxrmL0nthffg4Kv2xd36zHSHaJJXn9rJeM79yFXGKj QVBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b=tXByRccH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Alain Volmat --- arch/arm/boot/dts/st/stih418-b2264.dts | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/st/stih418-b2264.dts b/arch/arm/boot/dts/st/stih418-b2264.dts index fc32a03073b6..35bf618e0783 100644 --- a/arch/arm/boot/dts/st/stih418-b2264.dts +++ b/arch/arm/boot/dts/st/stih418-b2264.dts @@ -96,6 +96,14 @@ st,pins { }; }; + hdmiddc: i2c@9541000 { + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + + status = "okay"; + }; }; }; @@ -149,3 +157,29 @@ &spifsm { &st_dwc3 { status = "okay"; }; + +&sti_compo { + status = "okay"; +}; + +&sti_tvout { + status = "okay"; +}; + +&sti_hdmi { + ddc = <&hdmiddc>; + + status = "okay"; +}; + +&vtg_main { + status = "okay"; +}; + +&vtg_aux { + status = "okay"; +}; + +&gpu { + status = "okay"; +};