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[8.43.85.97]) by mx.google.com with ESMTPS id ay3-20020a056402202300b00521a6decedfsi694120edb.245.2023.07.27.03.12.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 03:12:11 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ECE9A389BA07 for ; Thu, 27 Jul 2023 09:51:25 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by sourceware.org (Postfix) with ESMTPS id E8CE5384F8F8 for ; Thu, 27 Jul 2023 09:49:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E8CE5384F8F8 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id D4A7024E250; Thu, 27 Jul 2023 17:48:53 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 27 Jul 2023 17:48:54 +0800 Received: from damon-pc.localdomain (113.72.147.196) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 27 Jul 2023 17:48:53 +0800 From: demin.han To: CC: , Subject: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative Date: Thu, 27 Jul 2023 17:48:59 +0800 Message-ID: <20230727094859.3884298-1-demin.han@starfivetech.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Originating-IP: [113.72.147.196] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772568163185833852 X-GMAIL-MSGID: 1772568163185833852 When pass split2 starts, which_alternative is random depending on last set of certain pass. Even initialized, the generated movement is redundant. The movement can be generated by assembly output template. Signed-off-by: demin.han gcc/ChangeLog: * config/riscv/autovec.md: Delete which_alternative use in split gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/madd-split2-1.c: New test. Signed-off-by: demin.han --- gcc/config/riscv/autovec.md | 12 ------------ .../gcc.target/riscv/rvv/autovec/madd-split2-1.c | 13 +++++++++++++ 2 files changed, 13 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index d899922586a..b7ea3101f5a 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1012,8 +1012,6 @@ (define_insn_and_split "*fma" [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus (mode), riscv_vector::RVV_TERNOP, ops, operands[4]); @@ -1058,8 +1056,6 @@ (define_insn_and_split "*fnma" [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (mode), riscv_vector::RVV_TERNOP, ops, operands[4]); @@ -1102,8 +1098,6 @@ (define_insn_and_split "*fma" [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (PLUS, mode), riscv_vector::RVV_TERNOP, ops, operands[4]); @@ -1148,8 +1142,6 @@ (define_insn_and_split "*fnma" [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (PLUS, mode), riscv_vector::RVV_TERNOP, ops, operands[4]); @@ -1194,8 +1186,6 @@ (define_insn_and_split "*fms" [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (MINUS, mode), riscv_vector::RVV_TERNOP, ops, operands[4]); @@ -1242,8 +1232,6 @@ (define_insn_and_split "*fnms" [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (MINUS, mode), riscv_vector::RVV_TERNOP, ops, operands[4]); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c new file mode 100644 index 00000000000..14a9802667e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */ + +long +foo (long *__restrict a, long *__restrict b, long n) +{ + long i; + for (i = 0; i < n; ++i) + a[i] = b[i] + i * 8; + return a[1]; +} + +/* { dg-final { scan-assembler-times {\tvmv1r\.v} 1 } } */