From patchwork Thu Jul 27 00:30:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 126575 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a985:0:b0:3e4:2afc:c1 with SMTP id t5csp752070vqo; Wed, 26 Jul 2023 17:30:59 -0700 (PDT) X-Google-Smtp-Source: APBJJlEsE4LZA1XtUanKn7eDKfi5vbV7QfhE8t0WSWAUhxq5qd4wxbBPvXlpZiPZnlVcNm7uBnEx X-Received: by 2002:a17:907:9713:b0:974:fb94:8067 with SMTP id jg19-20020a170907971300b00974fb948067mr600264ejc.23.1690417859169; Wed, 26 Jul 2023 17:30:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690417859; cv=none; d=google.com; s=arc-20160816; b=VHzLKgjSqIetmZfrndpyCBBtDcXE0wEH/XojfcBXU+ykrEREqONpRLX7sE0UoWOy8Q 0/zA3EYPV/yceQtxlAOl2lhhPPKMfXwWzz1LBaNTET93mJdKYlac0Wo5NpgEqMMSRczm bEeMcD3dKFo2SZo9bYeZd1U1deLjAlYFciqInDhbvijN0egpyHExg2kTIeSA1jmX8H8B HbhJOTmTFpUv0PNXozs9ed5gSMkEd0gEjQcRd6Xot2iNTZoq5N1Jmf5r8Drqp2ZmRTEc ZnNxa44kS+CX8EMBJLkWUAJn05lw/37DLfAeaHqp0iB7NXmRqkkUaDuVkCI0yzNHHfMK +sgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=AO+9RjFIAD77IF05moTnC1fPHvNtrz3lw/7R0ev3Flg=; fh=oLBbkpKGrMjsAiDUocfN7mW0LEnMJsqDdFE8uCs7/vo=; b=FUusrKVaro6+WUeu9CfYZJmkwxCSFJ7ZAPUV8lkQduzFl9rduxFTDoZ8Pa2NTRx/OT Nyobuay0E8RQE3N8WTcopp1b56fp0IhGUzvOEkENA1VLXu1bkT4EJdQohGBHi/2Tf+GE O/fptVN2SbTGioiOj9odc+bkRMP59Ak5qT2OVGDjLkWBQgF+mWHtX5/q95YnrNwAGUSt 6ca/3Xzy4gsdnfwEqQtxY/jGc4Qp/+sSOmwIeWQHnLixrYzEefBYKLMOcB3hBy5f6vRM cgwBiB7w1t2t6WN0Zm0hG/C8VnR3cnyimESURQlAiV/xWYHdpMF8ZVJq3b8YqUakVOMt 8anw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=VFpr58fD; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id va16-20020a17090711d000b0099bc31018easi113529ejb.436.2023.07.26.17.30.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 17:30:59 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=VFpr58fD; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EF7F0385AF97 for ; Thu, 27 Jul 2023 00:30:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EF7F0385AF97 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1690417853; bh=AO+9RjFIAD77IF05moTnC1fPHvNtrz3lw/7R0ev3Flg=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=VFpr58fD5E299pPAE1wO+Dg/O8k0nuZwvldzPr9jBAZqfk2awSseSxhpbrn6T8Elb DarUjb7/CZBhhIf8+/mDeLwlnb9r5iSTzqwBefpT/3GdZNyhA8zAdMn0frs+qoJ580 YRj7uf0TNik4YDSYD9S3st1Yppv8VrKOoN55INV8= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 126133857732 for ; Thu, 27 Jul 2023 00:30:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 126133857732 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 6E1CC300089; Thu, 27 Jul 2023 00:30:40 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [RFC PATCH 1/3] RISC-V: Base for complex extension implications Date: Thu, 27 Jul 2023 00:30:19 +0000 Message-ID: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772531597352101469 X-GMAIL-MSGID: 1772531597352101469 From: Tsukasa OI Thanks to the commit 48558a5e5471 ("RISC-V: Allow nested implications for extensions"), we can write complex extension implications in theory. However, to actually do that, we need to pass more information to check_func. For example, we want to imply 'Zcf' from 'F' if and only if the 'C' extension is also enabled and XLEN is 32. Passing rps is a way to enable this. This commit prepares for such complex extension implications. bfd/ChangeLog: * elfxx-riscv.c (struct riscv_implicit_subset) Move around and change check_func function prototype. (check_implicit_always): New arguments. (check_implicit_for_i): Likewise. (riscv_implicit_subsets): Add comment for this variable. (riscv_parse_add_implicit_subsets): Call check_func with new arguments. --- bfd/elfxx-riscv.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index b43d2cfa0fab..5a2897301f9f 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1064,11 +1064,25 @@ riscv_elf_ignore_reloc (bfd *abfd ATTRIBUTE_UNUSED, return bfd_reloc_ok; } +/* Record all implicit information for the subsets. */ + +typedef struct riscv_implicit_subset +{ + const char *subset_name; + const char *implicit_name; + /* A function to determine if we need to add the implicit subset. */ + bool (*check_func) (const riscv_parse_subset_t *, + const struct riscv_implicit_subset *, + const riscv_subset_t *); +} riscv_implicit_subset_t; + /* Always add the IMPLICIT for the SUBSET. */ static bool -check_implicit_always (const char *implicit ATTRIBUTE_UNUSED, - riscv_subset_t *subset ATTRIBUTE_UNUSED) +check_implicit_always (const riscv_parse_subset_t *rps ATTRIBUTE_UNUSED, + const riscv_implicit_subset_t *implicit + ATTRIBUTE_UNUSED, + const riscv_subset_t *subset ATTRIBUTE_UNUSED) { return true; } @@ -1076,23 +1090,18 @@ check_implicit_always (const char *implicit ATTRIBUTE_UNUSED, /* Add the IMPLICIT only when the version of SUBSET less than 2.1. */ static bool -check_implicit_for_i (const char *implicit ATTRIBUTE_UNUSED, - riscv_subset_t *subset) +check_implicit_for_i (const riscv_parse_subset_t *rps ATTRIBUTE_UNUSED, + const riscv_implicit_subset_t *implicit ATTRIBUTE_UNUSED, + const riscv_subset_t *subset) { return (subset->major_version < 2 || (subset->major_version == 2 && subset->minor_version < 1)); } -/* Record all implicit information for the subsets. */ -struct riscv_implicit_subset -{ - const char *subset_name; - const char *implicit_name; - /* A function to determine if we need to add the implicit subset. */ - bool (*check_func) (const char *, riscv_subset_t *); -}; -static struct riscv_implicit_subset riscv_implicit_subsets[] = +/* All extension implications. */ + +static riscv_implicit_subset_t riscv_implicit_subsets[] = { {"e", "i", check_implicit_always}, {"i", "zicsr", check_implicit_for_i}, @@ -1897,7 +1906,7 @@ riscv_parse_extensions (riscv_parse_subset_t *rps, static void riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps) { - struct riscv_implicit_subset *t = riscv_implicit_subsets; + riscv_implicit_subset_t *t = riscv_implicit_subsets; bool finished = false; while (!finished) { @@ -1909,7 +1918,7 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps) if (riscv_lookup_subset (rps->subset_list, t->subset_name, &subset) && !riscv_lookup_subset (rps->subset_list, t->implicit_name, &implicit_subset) - && t->check_func (t->implicit_name, subset)) + && t->check_func (rps, t, subset)) { riscv_parse_add_subset (rps, t->implicit_name, RISCV_UNKNOWN_VERSION, From patchwork Thu Jul 27 00:30:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 126576 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a985:0:b0:3e4:2afc:c1 with SMTP id t5csp752352vqo; Wed, 26 Jul 2023 17:31:38 -0700 (PDT) X-Google-Smtp-Source: APBJJlE3TA5nxmOED1C2bUIpY2TTSTxb6J5So+oLohVLNPnYGdbY9wWjtSjgnSMBHqloiuKB3+YV X-Received: by 2002:aa7:d64e:0:b0:522:2aee:6832 with SMTP id v14-20020aa7d64e000000b005222aee6832mr488520edr.9.1690417898372; Wed, 26 Jul 2023 17:31:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690417898; cv=none; d=google.com; s=arc-20160816; b=a/Eslge+UqsDT6FhFN8Bg4yL5wtKQb7IcOyuzLZe3zB8Zrt7Y2nvRWDCgFg98hYRVD lev0OmgJu/VSuQKwMrGAyAKYzZOdg6cjZvH7sx6SSsPzznRfZ6LqvR8E/3iXDXHN/rRN IAZuzZ7pM8klISqI7WSrGRzn2GbsiG31EWtMb2jnm66SUVLHYpis/Pd1N30O2L6jBMvt kkgu5A1cy//M9qjHAL+3M4f0I/h6m64JtFX+V14bzdZugw6v1LeaVMc7Rr7HRjgnukRH 9i+tYIUxQ+Y0gydAeKqyeorwtJhwzzM930pFA1m3yj3q3tNfZuZ6jkqn1riudNgi0Nv+ WHsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=abEl/00vJ2m7XxC3HdJuKfymlFGYY3qwJkc+k69VR7E=; fh=oLBbkpKGrMjsAiDUocfN7mW0LEnMJsqDdFE8uCs7/vo=; b=y4hDacPv5/zKaYSEHqAmgkyLWN6Y13cVdpTryjwiq1gceHXWfClHT6QSSyxryTmw5G 6c4a9QG6qmFc9hNC5aEMR1IqmYTXJBfjvd9K/9wgIDcjJeQwNS4+frusaSNGBCUTm4nl 9Ox/rbKgngTCjCuLKvK20901TLvWo4r5/VDsfmJNdbXkaORr4fCUWop11ZobjaS278+H gjMMLX+CJKm5yccAhjpL0rRXkZ/VFL2yeMm+b/36jUuEo2xF1ycWXta8GuvLQCFEdddB OaJqEFaBT1qsK61I+z73/M7ME7EZRc+a4zq2izH6Xxf459EU0iq0XZbWxOFo53lMupJk CuGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=UESnUyoz; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id v6-20020aa7d806000000b005227da2c1d6si49334edq.429.2023.07.26.17.31.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 17:31:38 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=UESnUyoz; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A7420385DC0A for ; Thu, 27 Jul 2023 00:31:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A7420385DC0A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1690417867; bh=abEl/00vJ2m7XxC3HdJuKfymlFGYY3qwJkc+k69VR7E=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=UESnUyozb8lviOKduonhMpb05/kbZszngYzzFFa9n8gkAHssgN5D1zidRTlpQ1OvT 5HKPOKLDVJNB6tbTx4erVxMhW30DsycwRAGEQdo4Gz51hXlRh0bp9dh/Mr+XPq9B3x zbTGd1Wv6ueXPErDyWQFBlaFRxAa6HD2HT1G2xFM= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id CED303856261 for ; Thu, 27 Jul 2023 00:30:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CED303856261 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 3ED9A300089; Thu, 27 Jul 2023 00:30:51 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [RFC PATCH 2/3] RISC-V: Add complex implications from 'C'+'[DF]' Date: Thu, 27 Jul 2023 00:30:20 +0000 Message-ID: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772531638076110682 X-GMAIL-MSGID: 1772531638076110682 From: Tsukasa OI The 'C' extension and its subsets have complex relations, depending on the implemented floating point extensions. They are the expansions related in this context: 'C' == 'Zca' 'C' + 'F' == 'Zca' + 'Zcf' + 'F' (RV32) 'C' + 'F' == 'Zca' + 'F' (RV64) 'C' + 'F' + 'D' == 'Zca' + 'Zcf' + 'Zcd' + 'F' + 'D' (RV32) 'C' + 'F' + 'D' == 'Zca' + 'Zcd' + 'F' + 'D' (RV64) [they exclude dependencies from 'F' and 'D'] This commit implements those implications. Note that some test cases are modified to reflect new compressed instruction extensions: 1. Test cases that use ".option arch, -c" to turn off RVC (at least the 'Zca' extension must be also turned off). 2. Test cases that test RISC-V attributes and/or mapping symbols when the 'C' extension is enabled. bfd/ChangeLog: * elfxx-riscv.c (check_implicit_for_d_c): New. (check_implicit_for_f_c): New. (riscv_implicit_subsets): Add unconditional implication, 'C' -> 'Zca'. Add conditional implications, 'D' -> 'Zcd' and 'F' -> 'Zcf'. gas/ChangeLog: * testsuite/gas/riscv/march-imply-c.d: Test implied extensions from 'C' alone. * testsuite/gas/riscv/march-imply-c-d-32.d: New to test implied extensions from 'C' and 'D' on RV32. * testsuite/gas/riscv/march-imply-c-d-64.d: New to test implied extensions from 'C' and 'D' on RV64. * testsuite/gas/riscv/attribute-10.d: Reflect reorganization of compressed instruction extensions. * testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise. * testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise. * testsuite/gas/riscv/dis-addr-overflow.s: Likewise. * testsuite/gas/riscv/mapping-symbols.d: Likewise. * testsuite/gas/riscv/mapping.s: Likewise. * testsuite/gas/riscv/march-ok-reorder.d: Likewise. * testsuite/gas/riscv/option-arch-01.s: Likewise. * testsuite/gas/riscv/option-arch-01b.d: Likewise. * testsuite/gas/riscv/option-arch-02.d: Likewise. * testsuite/gas/riscv/option-arch-02.s: Likewise. * testsuite/gas/riscv/option-arch-03.d: Likewise. * testsuite/gas/riscv/option-arch-03.s: Likewise. --- bfd/elfxx-riscv.c | 29 +++++++++++ gas/testsuite/gas/riscv/attribute-10.d | 2 +- .../gas/riscv/dis-addr-overflow-32.d | 2 +- .../gas/riscv/dis-addr-overflow-64.d | 2 +- gas/testsuite/gas/riscv/dis-addr-overflow.s | 4 +- gas/testsuite/gas/riscv/mapping-symbols.d | 22 ++++----- gas/testsuite/gas/riscv/mapping.s | 48 +++++++++---------- gas/testsuite/gas/riscv/march-imply-c-d-32.d | 6 +++ gas/testsuite/gas/riscv/march-imply-c-d-64.d | 6 +++ gas/testsuite/gas/riscv/march-imply-c.d | 6 +++ gas/testsuite/gas/riscv/march-ok-reorder.d | 2 +- gas/testsuite/gas/riscv/option-arch-01.s | 4 +- gas/testsuite/gas/riscv/option-arch-01b.d | 2 +- gas/testsuite/gas/riscv/option-arch-02.d | 2 +- gas/testsuite/gas/riscv/option-arch-02.s | 4 +- gas/testsuite/gas/riscv/option-arch-03.d | 2 +- gas/testsuite/gas/riscv/option-arch-03.s | 4 +- 17 files changed, 97 insertions(+), 50 deletions(-) create mode 100644 gas/testsuite/gas/riscv/march-imply-c-d-32.d create mode 100644 gas/testsuite/gas/riscv/march-imply-c-d-64.d create mode 100644 gas/testsuite/gas/riscv/march-imply-c.d diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 5a2897301f9f..765c6f646743 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1099,6 +1099,30 @@ check_implicit_for_i (const riscv_parse_subset_t *rps ATTRIBUTE_UNUSED, && subset->minor_version < 1)); } +/* Add the IMPLICIT only when the 'C' extension is also available. */ + +static bool +check_implicit_for_d_c (const riscv_parse_subset_t *rps, + const riscv_implicit_subset_t *implicit + ATTRIBUTE_UNUSED, + const riscv_subset_t *subset ATTRIBUTE_UNUSED) +{ + riscv_subset_t *tmp = NULL; + return riscv_lookup_subset (rps->subset_list, "c", &tmp); +} + +/* Add the IMPLICIT only when the 'C' extension is also available + and XLEN is 32. */ + +static bool +check_implicit_for_f_c (const riscv_parse_subset_t *rps, + const riscv_implicit_subset_t *implicit + ATTRIBUTE_UNUSED, + const riscv_subset_t *subset ATTRIBUTE_UNUSED) +{ + return *rps->xlen == 32 && check_implicit_for_d_c (rps, implicit, subset); +} + /* All extension implications. */ static riscv_implicit_subset_t riscv_implicit_subsets[] = @@ -1182,6 +1206,7 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] = {"zvksg", "zvkg", check_implicit_always}, {"zvksc", "zvks", check_implicit_always}, {"zvksc", "zvbc", check_implicit_always}, + {"c", "zca", check_implicit_always}, {"zcf", "zca", check_implicit_always}, {"zcd", "zca", check_implicit_always}, {"zcb", "zca", check_implicit_always}, @@ -1192,6 +1217,10 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] = {"sscofpmf", "zicsr", check_implicit_always}, {"ssstateen", "zicsr", check_implicit_always}, {"sstc", "zicsr", check_implicit_always}, + /* Complex implications (that should be checked after others). */ + {"d", "zcd", check_implicit_for_d_c}, + {"f", "zcf", check_implicit_for_f_c}, + /* Tail of the list. */ {NULL, NULL, NULL} }; diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d index f46692275f19..d93b42a98fa4 100644 --- a/gas/testsuite/gas/riscv/attribute-10.d +++ b/gas/testsuite/gas/riscv/attribute-10.d @@ -3,4 +3,4 @@ #source: empty.s Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0" + Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zca1p0_zcd1p0_zcf1p0" diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d index 287c5ea022f3..e966a2069dfd 100644 --- a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d +++ b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d @@ -1,4 +1,4 @@ -#as: -march=rv32ic +#as: -march=rv32i_zca #source: dis-addr-overflow.s #objdump: -d diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d index 1966a5ed7437..6ef02fe1fd97 100644 --- a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d +++ b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d @@ -1,4 +1,4 @@ -#as: -march=rv64ic -defsym rv64=1 +#as: -march=rv64i_zca -defsym rv64=1 #source: dis-addr-overflow.s #objdump: -d diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow.s b/gas/testsuite/gas/riscv/dis-addr-overflow.s index 77ca39c07b66..2ce3a904c1a1 100644 --- a/gas/testsuite/gas/riscv/dis-addr-overflow.s +++ b/gas/testsuite/gas/riscv/dis-addr-overflow.s @@ -24,7 +24,7 @@ topbase = 0 target: .option push - .option arch, -c + .option arch, -zca ## Use hi_addr # Load lui t0, 0xfffff @@ -50,7 +50,7 @@ target: c.addi t6, -20 .ifdef rv64 .option push - .option arch, -c + .option arch, -zca # ADDIW (not compressed) lui s6, 0xffff8 addiw s7, s6, -24 diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d b/gas/testsuite/gas/riscv/mapping-symbols.d index 40df34097369..3008157dc049 100644 --- a/gas/testsuite/gas/riscv/mapping-symbols.d +++ b/gas/testsuite/gas/riscv/mapping-symbols.d @@ -9,44 +9,44 @@ SYMBOL TABLE: 0+00 l d .data 0+00 .data 0+00 l d .bss 0+00 .bss 0+00 l d .text.cross.section.A 0+00 .text.cross.section.A -0+00 l .text.cross.section.A 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.cross.section.A 0+00 \$xrv32i2p1_zca1p0 0+00 l d .text.corss.section.B 0+00 .text.corss.section.B -0+00 l .text.corss.section.B 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.corss.section.B 0+00 \$xrv32i2p1_zca1p0 0+02 l .text.corss.section.B 0+00 \$xrv32i2p1 0+00 l d .text.data 0+00 .text.data 0+00 l .text.data 0+00 \$d -0+08 l .text.data 0+00 \$xrv32i2p1_c2p0 +0+08 l .text.data 0+00 \$xrv32i2p1_zca1p0 0+0c l .text.data 0+00 \$d 0+00 l d .text.odd.align.start.insn 0+00 .text.odd.align.start.insn -0+00 l .text.odd.align.start.insn 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.odd.align.start.insn 0+00 \$xrv32i2p1_zca1p0 0+02 l .text.odd.align.start.insn 0+00 \$d 0+08 l .text.odd.align.start.insn 0+00 \$xrv32i2p1 0+00 l d .text.odd.align.start.data 0+00 .text.odd.align.start.data 0+00 l .text.odd.align.start.data 0+00 \$d 0+00 l d .text.zero.fill.first 0+00 .text.zero.fill.first -0+00 l .text.zero.fill.first 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.zero.fill.first 0+00 \$xrv32i2p1_zca1p0 0+00 l d .text.zero.fill.last 0+00 .text.zero.fill.last -0+00 l .text.zero.fill.last 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.zero.fill.last 0+00 \$xrv32i2p1_zca1p0 0+02 l .text.zero.fill.last 0+00 \$x 0+00 l d .text.zero.fill.align.A 0+00 .text.zero.fill.align.A -0+00 l .text.zero.fill.align.A 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.zero.fill.align.A 0+00 \$xrv32i2p1_zca1p0 0+00 l d .text.zero.fill.align.B 0+00 .text.zero.fill.align.B 0+00 l .text.zero.fill.align.B 0+00 \$xrv32i2p1 0+00 l d .text.last.section 0+00 .text.last.section 0+00 l .text.last.section 0+00 \$xrv32i2p1 0+04 l .text.last.section 0+00 \$d 0+00 l d .text.section.padding 0+00 .text.section.padding -0+00 l .text.section.padding 0+00 \$xrv32i2p1_c2p0 -0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0 +0+00 l .text.section.padding 0+00 \$xrv32i2p1_zca1p0 +0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_zca1p0 0+06 l .text.section.padding 0+00 \$d 0+00 l d .text.relax.align 0+00 .text.relax.align -0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.relax.align 0+00 \$xrv32i2p1_zca1p0 0+08 l .text.relax.align 0+00 \$xrv32i2p1 0+0a l .text.section.padding 0+00 \$x 0+03 l .text.odd.align.start.insn 0+00 \$d 0+04 l .text.odd.align.start.insn 0+00 \$x 0+01 l .text.odd.align.start.data 0+00 \$d -0+02 l .text.odd.align.start.data 0+00 \$xrv32i2p1_c2p0 +0+02 l .text.odd.align.start.data 0+00 \$xrv32i2p1_zca1p0 0+00 l d .riscv.attributes 0+00 .riscv.attributes 0+00 g .text.cross.section.A 0+00 funcA 0+00 g .text.corss.section.B 0+00 funcB diff --git a/gas/testsuite/gas/riscv/mapping.s b/gas/testsuite/gas/riscv/mapping.s index 3014a69e7920..2fbb62977c3a 100644 --- a/gas/testsuite/gas/riscv/mapping.s +++ b/gas/testsuite/gas/riscv/mapping.s @@ -1,4 +1,4 @@ -.attribute arch, "rv32ic" +.attribute arch, "rv32i_zca" .option norelax # FIXME: assembler fill the paddings after parsing everything, # so we probably won't fill anything for the norelax region when # the riscv_opts.relax is enabled at somewhere. @@ -8,13 +8,13 @@ .global funcA funcA: addi a0, zero, 1 # rv32i -.option arch, +c -j funcA # rv32ic +.option arch, +zca +j funcA # rv32i_zca .section .text.corss.section.B, "ax" .globl funcB funcB: -addi a0, zero, 2 # rv32ic, need to be added since start of section -.option arch, -c +addi a0, zero, 2 # rv32i_zca, need to be added since start of section +.option arch, -zca j funcB # rv32i .option pop @@ -22,7 +22,7 @@ j funcB # rv32i .option push .word 0 # $d .long 1 -addi a0, zero, 1 # rv32ic +addi a0, zero, 1 # rv32i_zca .data .word 2 # don't add mapping symbols for non-text section .section .text.data @@ -35,10 +35,10 @@ addi a0, zero, 2 # $x, but same as previous addi, so removed .section .text.odd.align.start.insn, "ax" .option push .option norelax -.option arch, +c -addi a0, zero, 1 # $xrv32ic +.option arch, +zca +addi a0, zero, 1 # $xrv32i_zca .byte 1 # $d -.option arch, -c +.option arch, -zca .align 3 # odd alignment, $x replaced by $d + $x addi a0, zero, 2 # $xrv32i .option pop @@ -46,9 +46,9 @@ addi a0, zero, 2 # $xrv32i .section .text.odd.align.start.data, "ax" .option push .option norelax -.option arch, +c +.option arch, +zca .byte 1 # $d -.align 2 # odd alignment, $xrv32ic replaced by $d + $xrv32ic +.align 2 # odd alignment, $xrv32i_zca replaced by $d + $xrv32i_zca addi a0, zero, 1 .option pop @@ -56,13 +56,13 @@ addi a0, zero, 1 .option push .option norelax .fill 1, 0, 0 # $d with zero size, removed in make_mapping_symbol -addi a0, zero, 1 # $xrv32ic +addi a0, zero, 1 # $xrv32i_zca .option pop .section .text.zero.fill.last, "ax" .option push .option norelax -addi a0, zero, 1 # $xrv32ic +addi a0, zero, 1 # $xrv32i_zca .fill 1, 0, 0 # $d with zero size, removed in make_mapping_symbol addi a0, zero, 2 # $x, FIXME: need find a way to remove? .option pop @@ -71,8 +71,8 @@ addi a0, zero, 2 # $x, FIXME: need find a way to remove? .section .text.zero.fill.align.A, "ax" .option push .option norelax -.align 2 # $xrv32ic, .align and .fill are in the different frag, so neither be removed -.fill 1, 0, 0 # $d with zero size, removed in make_mapping_symbol when adding $xrv32ic +.align 2 # $xrv32i_zca, .align and .fill are in the different frag, so neither be removed +.fill 1, 0, 0 # $d with zero size, removed in make_mapping_symbol when adding $xrv32i_zca addi a0, zero, 1 # $x, should be removed in riscv_check_mapping_symbols addi a0, zero, 2 .option pop @@ -81,10 +81,10 @@ addi a0, zero, 2 .section .text.zero.fill.align.B, "ax" .option push .option norelax -.align 2 # $xrv32ic, .align and .fill are in the different frag, so neither be removed, +.align 2 # $xrv32i_zca, .align and .fill are in the different frag, so neither be removed, # but will be removed in riscv_check_mapping_symbols -.fill 1, 0, 0 # $d with zero size, removed in make_mapping_symbol when adding $xrv32ic -.option arch, -c +.fill 1, 0, 0 # $d with zero size, removed in make_mapping_symbol when adding $xrv32i_zca +.option arch, -zca addi a0, zero, 1 # $xrv32i addi a0, zero, 2 .option pop @@ -92,7 +92,7 @@ addi a0, zero, 2 .section .text.last.section, "ax" .option push .option norelax -.option arch, -c +.option arch, -zca addi a0, zero, 1 # $xrv32i .word 1 # $d .align 2 # zero section padding, $x at the end of section, removed in riscv_check_mapping_symbols @@ -102,20 +102,20 @@ addi a0, zero, 1 # $xrv32i .option push .option norelax .align 2 -addi a0, zero, 1 # $rv32ic +addi a0, zero, 1 # $rv32i_zca .option arch, +a .align 2 # 2-byte padding, $x, removed -addi a0, zero, 2 # $xrv32iac +addi a0, zero, 2 # $xrv32ia_zca .word 1 # $d .option pop # 2-byte padding, $x .section .text.relax.align, "ax" .option push .option relax -.option arch, rv32ic -.balign 4 # $xrv32ic, add at the start of section +.option arch, rv32i_zca +.balign 4 # $xrv32i_zca, add at the start of section addi a0, zero, 1 # $x, won't added -.option arch, -c +.option arch, -zca .align 3 # $x, won't added addi a0, zero, 2 # $xrv32i .option pop diff --git a/gas/testsuite/gas/riscv/march-imply-c-d-32.d b/gas/testsuite/gas/riscv/march-imply-c-d-32.d new file mode 100644 index 000000000000..8d9877b63968 --- /dev/null +++ b/gas/testsuite/gas/riscv/march-imply-c-d-32.d @@ -0,0 +1,6 @@ +#as: -march=rv32idc -march-attr -misa-spec=20191213 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0_zcf1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-c-d-64.d b/gas/testsuite/gas/riscv/march-imply-c-d-64.d new file mode 100644 index 000000000000..31f8fad00dac --- /dev/null +++ b/gas/testsuite/gas/riscv/march-imply-c-d-64.d @@ -0,0 +1,6 @@ +#as: -march=rv64idc -march-attr -misa-spec=20191213 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv64i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-c.d b/gas/testsuite/gas/riscv/march-imply-c.d new file mode 100644 index 000000000000..830dd9f2acc4 --- /dev/null +++ b/gas/testsuite/gas/riscv/march-imply-c.d @@ -0,0 +1,6 @@ +#as: -march=rv32ic -march-attr -misa-spec=20191213 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p1_c2p0_zca1p0" diff --git a/gas/testsuite/gas/riscv/march-ok-reorder.d b/gas/testsuite/gas/riscv/march-ok-reorder.d index 030f8b150189..db92029e7594 100644 --- a/gas/testsuite/gas/riscv/march-ok-reorder.d +++ b/gas/testsuite/gas/riscv/march-ok-reorder.d @@ -4,4 +4,4 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zba1p0_xbar2p0_xfoo2p0" + Tag_RISCV_arch: "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_xbar2p0_xfoo2p0" diff --git a/gas/testsuite/gas/riscv/option-arch-01.s b/gas/testsuite/gas/riscv/option-arch-01.s index 50285fc8c735..1bde865d1ff2 100644 --- a/gas/testsuite/gas/riscv/option-arch-01.s +++ b/gas/testsuite/gas/riscv/option-arch-01.s @@ -1,7 +1,7 @@ -.attribute arch, "rv64ic" +.attribute arch, "rv64i_zca" add a0, a0, a1 .option push -.option arch, +d2p0, -c, +xvendor1p0 +.option arch, +d2p0, -zca, +xvendor1p0 add a0, a0, a1 frcsr a0 # Should add mapping symbol with ISA here, and then dump it to frcsr. .option push diff --git a/gas/testsuite/gas/riscv/option-arch-01b.d b/gas/testsuite/gas/riscv/option-arch-01b.d index 8f4284d5f15b..5d7176975061 100644 --- a/gas/testsuite/gas/riscv/option-arch-01b.d +++ b/gas/testsuite/gas/riscv/option-arch-01b.d @@ -4,5 +4,5 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv64i2p0_c2p0" + Tag_RISCV_arch: "rv64i2p0_zca1p0" #... diff --git a/gas/testsuite/gas/riscv/option-arch-02.d b/gas/testsuite/gas/riscv/option-arch-02.d index 3c27419f9d36..8d75b468b257 100644 --- a/gas/testsuite/gas/riscv/option-arch-02.d +++ b/gas/testsuite/gas/riscv/option-arch-02.d @@ -4,5 +4,5 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv64i2p0_m3p0_f2p0_d3p0_c2p0_zmmul1p0_xvendor32x3p0" + Tag_RISCV_arch: "rv64i2p0_m3p0_f2p0_d3p0_zmmul1p0_zca1p0_xvendor32x3p0" #... diff --git a/gas/testsuite/gas/riscv/option-arch-02.s b/gas/testsuite/gas/riscv/option-arch-02.s index e0f5de321d67..109875985f4d 100644 --- a/gas/testsuite/gas/riscv/option-arch-02.s +++ b/gas/testsuite/gas/riscv/option-arch-02.s @@ -1,7 +1,7 @@ -.attribute arch, "rv64ic" +.attribute arch, "rv64i_zca" add a0, a0, a1 .option push -.option arch, +d2p0, -c, +xvendor1p0 +.option arch, +d2p0, -zca, +xvendor1p0 add a0, a0, a1 frcsr a0 .option pop diff --git a/gas/testsuite/gas/riscv/option-arch-03.d b/gas/testsuite/gas/riscv/option-arch-03.d index 62d7f7d5ed21..06b9c6b375e4 100644 --- a/gas/testsuite/gas/riscv/option-arch-03.d +++ b/gas/testsuite/gas/riscv/option-arch-03.d @@ -4,5 +4,5 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p1_c2p0" + Tag_RISCV_arch: "rv32i2p1_c2p0_zca1p0" #... diff --git a/gas/testsuite/gas/riscv/option-arch-03.s b/gas/testsuite/gas/riscv/option-arch-03.s index ccdb1c354b0f..60da2605fe3e 100644 --- a/gas/testsuite/gas/riscv/option-arch-03.s +++ b/gas/testsuite/gas/riscv/option-arch-03.s @@ -1,3 +1,3 @@ -.attribute arch, "rv64ic" -.option arch, +d2p0, -c +.attribute arch, "rv64i_zca" +.option arch, +d2p0, -zca .option arch, rv32i2p1c2p0 From patchwork Thu Jul 27 00:30:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 126577 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a985:0:b0:3e4:2afc:c1 with SMTP id t5csp753355vqo; Wed, 26 Jul 2023 17:34:02 -0700 (PDT) X-Google-Smtp-Source: APBJJlHI/bnRvvvRpdimyuydDmfstZ4H4arhYBbdMCg0Sv/Z2vi4f1vHoBTHlMxhSL8q9nsUfdDF X-Received: by 2002:a17:906:29a:b0:99b:bd1e:b00 with SMTP id 26-20020a170906029a00b0099bbd1e0b00mr560152ejf.25.1690418042186; Wed, 26 Jul 2023 17:34:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690418042; cv=none; d=google.com; s=arc-20160816; b=vQPMoEA5qcPvXoKxZW8wfXB31M0y22b4g0TdNTC8TdiK2tyEOlPAseucs+eF6Imzjk QkY5aiKUIN7mIxuPw1hzJYwlLwrcUZ6Dqax1yyStwpEIlNhTyR39edzXFIoCS4DkeH6I dxME1lNtIZa4Z8cmYud5/1PBDTZvlwGOsmn9oc4tYQ+q+x8ETQN+ghg163AmBzvCJ0z1 +xakly5QwEIk4tNcHWetNSiTKXl1Ycuosqdbqgy1UsInmJVNEsmSTmvPtZHAHlQiNAQi ihSw09Pw+ItQxF/jU1fGbwUPSB6L5rvef3StMsPGrsCd+gZYreHFoXbVehGjd0gOu+8G Srmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=e57meKz1/Tev1THRh4Jfdn02kgU0ksjkutq7cujl0OA=; fh=oLBbkpKGrMjsAiDUocfN7mW0LEnMJsqDdFE8uCs7/vo=; b=r/aiOldPDjMdiH8A/YpSMmhtugr2KBBwi2K2M0PbroDKDdFO/IXCWsPgL6osEu4KBB G5vvofgPrAj53CgvSMS1T2ju9H3pwC5tjYqZcopWHZyWz9CEORLI725Ac11+AxQ4x+mO 6fvFzAe6/Mu1qtXdODf211lzsqEjAUKNjvbuCA8vVc4LO/qUfPsBA6XCDUUdCAQOxqTJ VuKgHd9MOh5OBR4JHAp7g1OcblF6HS3N9n2eP97ucpsAK5QigVdUHwiJiTVtrpYr9vj/ xt+76cnJm56xm88mshcZHby8UQenK6MiyapiqzEgr3T18Wkgf1h2CcWREZU3V0WvvRY0 OGXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=bWWBnORN; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id l12-20020a1709065a8c00b00992ae4dfc05si91566ejq.1021.2023.07.26.17.34.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 17:34:02 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=bWWBnORN; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AC32D3870C3F for ; Thu, 27 Jul 2023 00:32:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AC32D3870C3F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1690417931; bh=e57meKz1/Tev1THRh4Jfdn02kgU0ksjkutq7cujl0OA=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=bWWBnORNaovIr7Plmzv6+Atv3Zo/LRPIyWPS9hehUW24dVM/LrHA9O30tvjrqmVNO Z6OS7uq2HFVRyPVpxSXMMNvsXc+kkQUaWWvQjXboyzeOz1fVxXt0O2aHtd60YwUfL+ 3/m+sptcHB1m7MqoCybqFKdyHjLYIl9dcWbTyFLE= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 639AF385C6D9 for ; Thu, 27 Jul 2023 00:31:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 639AF385C6D9 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 1245B300089; Thu, 27 Jul 2023 00:31:02 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [RFC PATCH 3/3] RISC-V: ".option norvc" to disable 'C' and subsets Date: Thu, 27 Jul 2023 00:30:21 +0000 Message-ID: <8aaf145c772b2d3752b0ae08ce93de34494b7020.1690417818.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772531789003450355 X-GMAIL-MSGID: 1772531789003450355 From: Tsukasa OI Despite its deprecation, ".option norvc" may used to turn off the 'C' extension. This commit also disables its subsets, 'Zca', 'Zcf' and 'Zcd' and clarifies that it won't completely do the job if other enabled extensions depend on 'C' or 'Zc*'. Note that, even if it does not "completely" work, we cannot emit any compressed instructions after the ".option norvc" directive since it disables RVC and prevents any 2-byte instructions from assembling. gas/ChangeLog: * config/tc-riscv.c (s_riscv_option): Also turn off 'Zca', 'Zcf' and 'Zcd'. Clarify the limitation of this directive. --- gas/config/tc-riscv.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index aaf8b9be64fd..4c582e7813b0 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -4351,7 +4351,11 @@ s_riscv_option (int x ATTRIBUTE_UNUSED) } else if (strcmp (name, "norvc") == 0) { - riscv_update_subset (&riscv_rps_as, "-c"); + /* Compatibility: + Disable classic 'C' extension and its subsets. + It won't completely disable them if other enabled extensions + depend on 'C' or 'Zc*'. */ + riscv_update_subset (&riscv_rps_as, "-c,-zca,-zcf,-zcd"); riscv_reset_subsets_list_arch_str (); riscv_set_rvc (false); }