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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d21-20020a056402517500b005223814710csi3835967ede.3.2023.07.26.02.07.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 02:07:30 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B10153857723 for ; Wed, 26 Jul 2023 09:07:26 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) by sourceware.org (Postfix) with ESMTPS id 5514B3858426 for ; Wed, 26 Jul 2023 09:07:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5514B3858426 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-03 (Coremail) with SMTP id rQCowAD3_WUj4sBkbOYgDg--.8116S2; Wed, 26 Jul 2023 17:06:44 +0800 (CST) From: Jiawei To: binutils@sourceware.org Cc: nelson@rivosinc.com, kito.cheng@sifive.com, palmer@dabbelt.com, jbeulich@suse.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, nandni.jamnadas@embecosm.com, mary.bennett@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, sinan.lin@linux.alibaba.com, gaofei@eswincomputing.com, fujin.zhao@foxmail.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Jiawei Subject: [v2 PATCH 1/2] RISC-V: Support Zcmp push/pop instructions Date: Wed, 26 Jul 2023 17:06:21 +0800 Message-Id: <20230726090622.630672-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: rQCowAD3_WUj4sBkbOYgDg--.8116S2 X-Coremail-Antispam: 1UD129KBjvAXoWfur1fKrW5XF1UJF1fuFy7Awb_yoW5Kr1UWo W8Xa1rKFs0gw12krn5tr1fGa1kua4rGr97Xwn8Cw1UAFWDC3y3GryYqa1xua4UKr4Sqr1D Za4kWrW8XFWvqr47n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYf7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2 x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWx JVW8Jr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxV WxJr0_GcWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2Wl Yx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbV WUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7Cj xVA2Y2ka0xkIwI1lc2xSY4AK67A8MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r 1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CE b7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0x vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAI cVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2Kf nxnUUI43ZEXa7VUU5fHUUUUUU== X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCQoEAGTAnAP73wAAsY X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772473497256690949 X-GMAIL-MSGID: 1772473497256690949 Support zcmp extension push/pop/popret and popret zero instructions. `reg_list` is a list containing 1 to 13 registers, we can use: "{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2}, …, {ra, s0-sN}" to present this feature. `stack_adj` is the total size of the stack frame, use `riscv_get_sp_base` function to calculate it. Most work was finished by Sinan Lin. V2 changes: Add missing insn declarations, adjust op operands to Zc fields, fix format. Co-Authored by: Charlie Keaney Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Sinan Lin Co-Authored by: Simon Cook Co-Authored by: Shihua Liao Co-Authored by: Yulong Shi bfd/ChangeLog: * elfxx-riscv.c (riscv_get_sp_base): New function. (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. * elfxx-riscv.h (SP_ALIGNMENT): New macro. (riscv_get_sp_base): New function prototype. gas/ChangeLog: * config/tc-riscv.c (regno_to_rlist): New regs mapping. (reglist_lookup): New function. (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-push-pop-fail.d: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.l: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.s: New test. * testsuite/gas/riscv/zcmp-push-pop.d: New test. * testsuite/gas/riscv/zcmp-push-pop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_PUSH): New opcode. (MASK_CM_PUSH): New mask. (MATCH_CM_POP): New opcode. (MASK_CM_POP): New mask. (MATCH_CM_POPRET): New opcode. (MASK_CM_POPRET): New mask. (MATCH_CM_POPRETZ): New opcode. (MASK_CM_POPRETZ): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (EXTRACT_ZCMP_SPIMM): New inline function. (ENCODE_ZCMP_SPIMM): Ditto. (VALID_ZCMP_SPIMM): Ditto. (OP_MASK_RLIST): New mask. (OP_SH_RLIST): New operand code. (X_S0): New reg number. (X_S1): Ditto. (X_S2): Ditto. (X_S10): Ditto. (X_S11): Ditto. (enum riscv_insn_class): New extension class. opcodes/ChangeLog: * riscv-dis.c (set_default_riscv_dis_options): New var. (parse_riscv_dis_option_without_args): Ditto. (print_rlist): New print function. (riscv_get_spimm): New function. (print_insn_args): New operators. * riscv-opc.c: New instructions. --- bfd/elfxx-riscv.c | 19 ++ bfd/elfxx-riscv.h | 4 + gas/config/tc-riscv.c | 180 ++++++++++++++++- gas/testsuite/gas/riscv/zcmp-push-pop-fail.d | 3 + gas/testsuite/gas/riscv/zcmp-push-pop-fail.l | 9 + gas/testsuite/gas/riscv/zcmp-push-pop-fail.s | 13 ++ gas/testsuite/gas/riscv/zcmp-push-pop.d | 154 +++++++++++++++ gas/testsuite/gas/riscv/zcmp-push-pop.s | 197 +++++++++++++++++++ include/opcode/riscv-opc.h | 14 ++ include/opcode/riscv.h | 15 ++ opcodes/riscv-dis.c | 57 ++++++ opcodes/riscv-opc.c | 6 + 12 files changed, 670 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/zcmp-push-pop-fail.d create mode 100644 gas/testsuite/gas/riscv/zcmp-push-pop-fail.l create mode 100644 gas/testsuite/gas/riscv/zcmp-push-pop-fail.s create mode 100644 gas/testsuite/gas/riscv/zcmp-push-pop.d create mode 100644 gas/testsuite/gas/riscv/zcmp-push-pop.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index b43d2cfa0fa..e68de65fac1 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1084,6 +1084,19 @@ check_implicit_for_i (const char *implicit ATTRIBUTE_UNUSED, && subset->minor_version < 1)); } +/* get sp base adjustment */ + +int +riscv_get_sp_base (insn_t opcode, riscv_parse_subset_t *rps) +{ + unsigned reg_size = *(rps->xlen) / 8; + unsigned rlist = EXTRACT_BITS (opcode, OP_MASK_RLIST, OP_SH_RLIST); + + unsigned min_sp_adj = (rlist - 3) * reg_size + (rlist == 15 ? reg_size : 0); + return ((min_sp_adj / SP_ALIGNMENT) + (min_sp_adj % SP_ALIGNMENT != 0)) + * SP_ALIGNMENT; +} + /* Record all implicit information for the subsets. */ struct riscv_implicit_subset { @@ -1176,6 +1189,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zcf", "zca", check_implicit_always}, {"zcd", "zca", check_implicit_always}, {"zcb", "zca", check_implicit_always}, + {"zcmp", "zca", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, @@ -1313,6 +1327,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2516,6 +2531,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_ZCB_AND_ZMMUL: return (riscv_subset_supports (rps, "zcb") && riscv_subset_supports (rps, "zmmul")); + case INSN_CLASS_ZCMP: + return riscv_subset_supports (rps, "zcmp"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2732,6 +2749,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zcb' and `zbb"); case INSN_CLASS_ZCB_AND_ZMMUL: return _("zcb' and `zmmul', or `zcb' and `m"); + case INSN_CLASS_ZCMP: + return "zcmp"; case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h index abcb409bd78..ae144567116 100644 --- a/bfd/elfxx-riscv.h +++ b/bfd/elfxx-riscv.h @@ -26,6 +26,7 @@ #include "cpu-riscv.h" #define RISCV_UNKNOWN_VERSION -1 +#define SP_ALIGNMENT 16 struct riscv_elf_params { @@ -123,3 +124,6 @@ extern void bfd_elf32_riscv_set_data_segment_info (struct bfd_link_info *, int *); extern void bfd_elf64_riscv_set_data_segment_info (struct bfd_link_info *, int *); + +extern int +riscv_get_sp_base (insn_t, riscv_parse_subset_t *); \ No newline at end of file diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index aaf8b9be64f..266a91451b7 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1237,6 +1237,152 @@ flt_lookup (float f, const float *array, size_t size, unsigned *regnop) return false; } +/* Map ra and s-register to [4,15], so that we can check if the + reg2 in register list reg1-reg2 or single reg2 is valid or not, + and obtain the corresponding rlist value. + + ra - 4 + s0 - 5 + s1 - 6 + .... + s10 - 0 (invalid) + s11 - 15 +*/ + +static int +regno_to_rlist (unsigned regno) +{ + if (regno == X_RA) + return 4; + else if (regno == X_S0 || regno == X_S1) + return 5 + regno - X_S0; + else if (regno >= X_S2 && regno < X_S10) + return 7 + regno - X_S2; + else if (regno == X_S11) + return 15; + + return 0; /* invalid symbol */ +} + +/* Parse register list, and the parsed rlist value is stored in rlist + argument. + + If ABI register names are used (e.g. ra and s0), the register + list could be "{ra}", "{ra, s0}", "{ra, s0-sN}", where 0 < N < 10 or + N == 11. + + If numeric register names are used (e.g. x1 and x8), the register list + could be "{x1}", "{x1,x8}", "{x1,x8-x9}", "{x1,x8-x9, x18}" and + "{x1,x8-x9,x18-xN}", where 19 < N < 25 or N == 27. + + It will fail if numeric register names and ABI register names are used + at the same time. + */ + +static bool +reglist_lookup (char **s, unsigned *rlist) +{ + unsigned regno; + /* Use to check if the register format is xreg. */ + bool use_xreg = **s == 'x'; + + /* The first register in register list should be ra. */ + if (!reg_lookup (s, RCLASS_GPR, ®no) + || !(*rlist = regno_to_rlist (regno)) /* update rlist */ + || regno != X_RA) + return FALSE; + + /* Skip "whitespace, whitespace" pattern. */ + while (ISSPACE (**s)) + ++ *s; + if (**s == '}') + return TRUE; + else if (**s != ',') + return FALSE; + while (ISSPACE (*++*s)) + ++ *s; + + /* Do not use numeric and abi names at the same time. */ + if (use_xreg && **s != 'x') + return FALSE; + + /* Reg1 should be s0 or its numeric names x8. */ + if (!reg_lookup (s, RCLASS_GPR, ®no) + || !(*rlist = regno_to_rlist (regno)) + || regno != X_S0) + return FALSE; + + /* Skip "whitespace - whitespace" pattern. */ + while (ISSPACE (**s)) + ++ *s; + if (**s == '}') + return TRUE; + else if (**s != '-') + return FALSE; + while (ISSPACE (*++*s)) + ++ *s; + + if (use_xreg && **s != 'x') + return FALSE; + + /* Reg2 is x9 if the numeric name is used, otherwise, + it could be any other sN register, where N > 0. */ + if (!reg_lookup (s, RCLASS_GPR, ®no) + || !(*rlist = regno_to_rlist (regno)) + || regno <= X_S0 + || (use_xreg && regno != X_S1)) + return FALSE; + + /* Skip whitespace */ + while (ISSPACE (**s)) + ++ *s; + + /* Check if it is the end of register list. */ + if (**s == '}') + return TRUE; + else if (!use_xreg) + return FALSE; + + /* Here is not reachable if the abi name is used. */ + gas_assert (use_xreg); + + /* If the numeric name is used, we need to parse extra + register list, reg3 or reg3-reg4. */ + + /* Skip ", white space" pattern. */ + if (**s != ',') + return FALSE; + while (ISSPACE (*++*s)) + ++ *s; + + if (use_xreg && **s != 'x') + return FALSE; + + /* Reg3 should be s2. */ + if (!reg_lookup (s, RCLASS_GPR, ®no) + || !(*rlist = regno_to_rlist (regno)) + || regno != X_S2) + return FALSE; + + /* skip "whitespace - whitespace" pattern. */ + while (ISSPACE (**s)) + ++ *s; + if (**s == '}') + return TRUE; + else if (**s != '-') + return FALSE; + while (ISSPACE (*++*s)) + ++ *s; + + /* Reg4 could be any other sN register, where N > 1. */ + if (!reg_lookup (s, RCLASS_GPR, ®no) + || !(*rlist = regno_to_rlist (regno)) + || regno <= X_S2) + return FALSE; + + return TRUE; +} + #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) #define USE_IMM(n, s) \ (used_bits |= ((insn_t)((1ull<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case 'A': break; /* Macro operand, must be symbol. */ @@ -1433,6 +1582,10 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'h': used_bits |= ENCODE_ZCB_HALFWORD_UIMM (-1U); break; /* halfword immediate operators, load/store halfword insns. */ case 'b': used_bits |= ENCODE_ZCB_BYTE_UIMM (-1U); break; + /* immediate offset operand for cm.push and cm.pop. */ + case 'p': used_bits |= ENCODE_ZCMP_SPIMM (-1U); break; + /* register list operand for cm.push and cm.pop. */ + case 'r': USE_BITS (OP_MASK_RLIST, OP_SH_RLIST); break; case 'f': break; default: goto unknown_validate_operand; @@ -3141,6 +3294,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, case ')': case '[': case ']': + case '{': + case '}': if (*asarg++ == *oparg) continue; break; @@ -3597,7 +3752,30 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, ip->insn_opcode |= ENCODE_ZCB_BYTE_UIMM (imm_expr->X_add_number); goto rvc_imm_done; - case 'f': /* Operand for matching immediate 255. */ + case 'r': + /* we use regno to store reglist value here. */ + if (!reglist_lookup (&asarg, ®no)) + break; + INSERT_OPERAND (RLIST, *ip, regno); + continue; + + case 'p': + if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) + || imm_expr->X_op != O_constant) + break; + /* convert stack adjust of cm.push to a positive offset. */ + if (ip->insn_mo->match == MATCH_CM_PUSH) + imm_expr->X_add_number *= -1; + /* subtract base stack adjust and get spimm. */ + imm_expr->X_add_number -= + riscv_get_sp_base (ip->insn_opcode, &riscv_rps_as); + if (!VALID_ZCMP_SPIMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= + ENCODE_ZCMP_SPIMM (imm_expr->X_add_number); + goto rvc_imm_done; + + case 'f': /* operand for matching immediate 255. */ if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) || imm_expr->X_op != O_constant || imm_expr->X_add_number != 255) diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d new file mode 100644 index 00000000000..ca1d88e6299 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_zcmp +#source: zcmp-push-pop-fail.s +#error_output: zcmp-push-pop-fail.l \ No newline at end of file diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l new file mode 100644 index 00000000000..955e495d5bb --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l @@ -0,0 +1,9 @@ +.*: Assembler messages: +.*: Error: illegal operands `cm.push \{a0\},-64' +.*: Error: illegal operands `cm.pop \{ra,s1\},-64' +.*: Error: illegal operands `cm.popret \{ra,s2-s3\},-64' +.*: Error: illegal operands `cm.popretz \{ra,s0-s10\},-112' +.*: Error: illegal operands `cm.push \{ra\},0' +.*: Error: illegal operands `cm.pop \{ra,s0\},-80' +.*: Error: illegal operands `cm.popret \{ra,s0-s1\},-15' +.*: Error: illegal operands `cm.popretz \{ra,s0-s11\},-165' diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s new file mode 100644 index 00000000000..a82f9399787 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s @@ -0,0 +1,13 @@ +target: + + # rlist + cm.push {a0}, -64 + cm.pop {ra, s1}, -64 + cm.popret {ra, s2-s3}, -64 + cm.popretz {ra, s0-s10}, -112 + + # spimm + cm.push {ra}, 0 + cm.pop {ra, s0}, -80 + cm.popret {ra, s0-s1}, -15 + cm.popretz {ra, s0-s11}, -165 diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop.d b/gas/testsuite/gas/riscv/zcmp-push-pop.d new file mode 100644 index 00000000000..e21295051ec --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop.d @@ -0,0 +1,154 @@ +#as: -march=rv64i_zcmp +#source: zcmp-push-pop.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+b84e[ ]+cm.push[ ]+\{ra\},-64 +[ ]*[0-9a-f]+:[ ]+b85e[ ]+cm.push[ ]+\{ra,s0\},-64 +[ ]*[0-9a-f]+:[ ]+b86a[ ]+cm.push[ ]+\{ra,s0-s1\},-64 +[ ]*[0-9a-f]+:[ ]+b87a[ ]+cm.push[ ]+\{ra,s0-s2\},-64 +[ ]*[0-9a-f]+:[ ]+b8da[ ]+cm.push[ ]+\{ra,s0-s8\},-112 +[ ]*[0-9a-f]+:[ ]+b8e6[ ]+cm.push[ ]+\{ra,s0-s9\},-112 +[ ]*[0-9a-f]+:[ ]+b8f2[ ]+cm.push[ ]+\{ra,s0-s11\},-112 +[ ]*[0-9a-f]+:[ ]+b84e[ ]+cm.push[ ]+\{ra\},-64 +[ ]*[0-9a-f]+:[ ]+b85e[ ]+cm.push[ ]+\{ra,s0\},-64 +[ ]*[0-9a-f]+:[ ]+b86a[ ]+cm.push[ ]+\{ra,s0-s1\},-64 +[ ]*[0-9a-f]+:[ ]+b87a[ ]+cm.push[ ]+\{ra,s0-s2\},-64 +[ ]*[0-9a-f]+:[ ]+b8da[ ]+cm.push[ ]+\{ra,s0-s8\},-112 +[ ]*[0-9a-f]+:[ ]+b8e6[ ]+cm.push[ ]+\{ra,s0-s9\},-112 +[ ]*[0-9a-f]+:[ ]+b8f2[ ]+cm.push[ ]+\{ra,s0-s11},-112 +[ ]*[0-9a-f]+:[ ]+b842[ ]+cm.push[ ]+\{ra\},-16 +[ ]*[0-9a-f]+:[ ]+b846[ ]+cm.push[ ]+\{ra\},-32 +[ ]*[0-9a-f]+:[ ]+b84e[ ]+cm.push[ ]+\{ra\},-64 +[ ]*[0-9a-f]+:[ ]+b872[ ]+cm.push[ ]+\{ra,s0-s2\},-32 +[ ]*[0-9a-f]+:[ ]+b87a[ ]+cm.push[ ]+\{ra,s0-s2\},-64 +[ ]*[0-9a-f]+:[ ]+b87e[ ]+cm.push[ ]+\{ra,s0-s2\},-80 +[ ]*[0-9a-f]+:[ ]+b882[ ]+cm.push[ ]+\{ra,s0-s3\},-48 +[ ]*[0-9a-f]+:[ ]+b886[ ]+cm.push[ ]+\{ra,s0-s3\},-64 +[ ]*[0-9a-f]+:[ ]+b88e[ ]+cm.push[ ]+\{ra,s0-s3\},-96 +[ ]*[0-9a-f]+:[ ]+b8b2[ ]+cm.push[ ]+\{ra,s0-s6\},-64 +[ ]*[0-9a-f]+:[ ]+b8b6[ ]+cm.push[ ]+\{ra,s0-s6\},-80 +[ ]*[0-9a-f]+:[ ]+b8be[ ]+cm.push[ ]+\{ra,s0-s6\},-112 +[ ]*[0-9a-f]+:[ ]+b8c2[ ]+cm.push[ ]+\{ra,s0-s7\},-80 +[ ]*[0-9a-f]+:[ ]+b8c6[ ]+cm.push[ ]+\{ra,s0-s7\},-96 +[ ]*[0-9a-f]+:[ ]+b8ce[ ]+cm.push[ ]+\{ra,s0-s7\},-128 +[ ]*[0-9a-f]+:[ ]+b8e2[ ]+cm.push[ ]+\{ra,s0-s9\},-96 +[ ]*[0-9a-f]+:[ ]+b8e6[ ]+cm.push[ ]+\{ra,s0-s9\},-112 +[ ]*[0-9a-f]+:[ ]+b8ee[ ]+cm.push[ ]+\{ra,s0-s9\},-144 +[ ]*[0-9a-f]+:[ ]+b8f2[ ]+cm.push[ ]+\{ra,s0-s11\},-112 +[ ]*[0-9a-f]+:[ ]+b8f6[ ]+cm.push[ ]+\{ra,s0-s11\},-128 +[ ]*[0-9a-f]+:[ ]+b8fa[ ]+cm.push[ ]+\{ra,s0-s11\},-144 +[ ]*[0-9a-f]+:[ ]+b8fe[ ]+cm.push[ ]+\{ra,s0-s11\},-160 +[ ]*[0-9a-f]+:[ ]+ba4e[ ]+cm.pop[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+ba5e[ ]+cm.pop[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+ba6a[ ]+cm.pop[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+ba7a[ ]+cm.pop[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bada[ ]+cm.pop[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bae6[ ]+cm.pop[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+baf2[ ]+cm.pop[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+ba4e[ ]+cm.pop[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+ba5e[ ]+cm.pop[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+ba6a[ ]+cm.pop[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+ba7a[ ]+cm.pop[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bada[ ]+cm.pop[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bae6[ ]+cm.pop[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+baf2[ ]+cm.pop[ ]+\{ra,s0-s11},112 +[ ]*[0-9a-f]+:[ ]+ba42[ ]+cm.pop[ ]+\{ra\},16 +[ ]*[0-9a-f]+:[ ]+ba46[ ]+cm.pop[ ]+\{ra\},32 +[ ]*[0-9a-f]+:[ ]+ba4e[ ]+cm.pop[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+ba72[ ]+cm.pop[ ]+\{ra,s0-s2\},32 +[ ]*[0-9a-f]+:[ ]+ba7a[ ]+cm.pop[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+ba7e[ ]+cm.pop[ ]+\{ra,s0-s2\},80 +[ ]*[0-9a-f]+:[ ]+ba82[ ]+cm.pop[ ]+\{ra,s0-s3\},48 +[ ]*[0-9a-f]+:[ ]+ba86[ ]+cm.pop[ ]+\{ra,s0-s3\},64 +[ ]*[0-9a-f]+:[ ]+ba8e[ ]+cm.pop[ ]+\{ra,s0-s3\},96 +[ ]*[0-9a-f]+:[ ]+bab2[ ]+cm.pop[ ]+\{ra,s0-s6\},64 +[ ]*[0-9a-f]+:[ ]+bab6[ ]+cm.pop[ ]+\{ra,s0-s6\},80 +[ ]*[0-9a-f]+:[ ]+babe[ ]+cm.pop[ ]+\{ra,s0-s6\},112 +[ ]*[0-9a-f]+:[ ]+bac2[ ]+cm.pop[ ]+\{ra,s0-s7\},80 +[ ]*[0-9a-f]+:[ ]+bac6[ ]+cm.pop[ ]+\{ra,s0-s7\},96 +[ ]*[0-9a-f]+:[ ]+bace[ ]+cm.pop[ ]+\{ra,s0-s7\},128 +[ ]*[0-9a-f]+:[ ]+bae2[ ]+cm.pop[ ]+\{ra,s0-s9\},96 +[ ]*[0-9a-f]+:[ ]+bae6[ ]+cm.pop[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+baee[ ]+cm.pop[ ]+\{ra,s0-s9\},144 +[ ]*[0-9a-f]+:[ ]+baf2[ ]+cm.pop[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+baf6[ ]+cm.pop[ ]+\{ra,s0-s11\},128 +[ ]*[0-9a-f]+:[ ]+bafa[ ]+cm.pop[ ]+\{ra,s0-s11\},144 +[ ]*[0-9a-f]+:[ ]+bafe[ ]+cm.pop[ ]+\{ra,s0-s11\},160 +[ ]*[0-9a-f]+:[ ]+be4e[ ]+cm.popret[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+be5e[ ]+cm.popret[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+be6a[ ]+cm.popret[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+be7a[ ]+cm.popret[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+beda[ ]+cm.popret[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bee6[ ]+cm.popret[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bef2[ ]+cm.popret[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+be4e[ ]+cm.popret[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+be5e[ ]+cm.popret[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+be6a[ ]+cm.popret[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+be7a[ ]+cm.popret[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+beda[ ]+cm.popret[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bee6[ ]+cm.popret[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bef2[ ]+cm.popret[ ]+\{ra,s0-s11},112 +[ ]*[0-9a-f]+:[ ]+be42[ ]+cm.popret[ ]+\{ra\},16 +[ ]*[0-9a-f]+:[ ]+be46[ ]+cm.popret[ ]+\{ra\},32 +[ ]*[0-9a-f]+:[ ]+be4e[ ]+cm.popret[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+be72[ ]+cm.popret[ ]+\{ra,s0-s2\},32 +[ ]*[0-9a-f]+:[ ]+be7a[ ]+cm.popret[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+be7e[ ]+cm.popret[ ]+\{ra,s0-s2\},80 +[ ]*[0-9a-f]+:[ ]+be82[ ]+cm.popret[ ]+\{ra,s0-s3\},48 +[ ]*[0-9a-f]+:[ ]+be86[ ]+cm.popret[ ]+\{ra,s0-s3\},64 +[ ]*[0-9a-f]+:[ ]+be8e[ ]+cm.popret[ ]+\{ra,s0-s3\},96 +[ ]*[0-9a-f]+:[ ]+beb2[ ]+cm.popret[ ]+\{ra,s0-s6\},64 +[ ]*[0-9a-f]+:[ ]+beb6[ ]+cm.popret[ ]+\{ra,s0-s6\},80 +[ ]*[0-9a-f]+:[ ]+bebe[ ]+cm.popret[ ]+\{ra,s0-s6\},112 +[ ]*[0-9a-f]+:[ ]+bec2[ ]+cm.popret[ ]+\{ra,s0-s7\},80 +[ ]*[0-9a-f]+:[ ]+bec6[ ]+cm.popret[ ]+\{ra,s0-s7\},96 +[ ]*[0-9a-f]+:[ ]+bece[ ]+cm.popret[ ]+\{ra,s0-s7\},128 +[ ]*[0-9a-f]+:[ ]+bee2[ ]+cm.popret[ ]+\{ra,s0-s9\},96 +[ ]*[0-9a-f]+:[ ]+bee6[ ]+cm.popret[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+beee[ ]+cm.popret[ ]+\{ra,s0-s9\},144 +[ ]*[0-9a-f]+:[ ]+bef2[ ]+cm.popret[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+bef6[ ]+cm.popret[ ]+\{ra,s0-s11\},128 +[ ]*[0-9a-f]+:[ ]+befa[ ]+cm.popret[ ]+\{ra,s0-s11\},144 +[ ]*[0-9a-f]+:[ ]+befe[ ]+cm.popret[ ]+\{ra,s0-s11\},160 +[ ]*[0-9a-f]+:[ ]+bc4e[ ]+cm.popretz[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+bc5e[ ]+cm.popretz[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+bc6a[ ]+cm.popretz[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+bc7a[ ]+cm.popretz[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bcda[ ]+cm.popretz[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bce6[ ]+cm.popretz[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bcf2[ ]+cm.popretz[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+bc4e[ ]+cm.popretz[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+bc5e[ ]+cm.popretz[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+bc6a[ ]+cm.popretz[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+bc7a[ ]+cm.popretz[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bcda[ ]+cm.popretz[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bce6[ ]+cm.popretz[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bcf2[ ]+cm.popretz[ ]+\{ra,s0-s11},112 +[ ]*[0-9a-f]+:[ ]+bc42[ ]+cm.popretz[ ]+\{ra\},16 +[ ]*[0-9a-f]+:[ ]+bc46[ ]+cm.popretz[ ]+\{ra\},32 +[ ]*[0-9a-f]+:[ ]+bc4e[ ]+cm.popretz[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+bc72[ ]+cm.popretz[ ]+\{ra,s0-s2\},32 +[ ]*[0-9a-f]+:[ ]+bc7a[ ]+cm.popretz[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bc7e[ ]+cm.popretz[ ]+\{ra,s0-s2\},80 +[ ]*[0-9a-f]+:[ ]+bc82[ ]+cm.popretz[ ]+\{ra,s0-s3\},48 +[ ]*[0-9a-f]+:[ ]+bc86[ ]+cm.popretz[ ]+\{ra,s0-s3\},64 +[ ]*[0-9a-f]+:[ ]+bc8e[ ]+cm.popretz[ ]+\{ra,s0-s3\},96 +[ ]*[0-9a-f]+:[ ]+bcb2[ ]+cm.popretz[ ]+\{ra,s0-s6\},64 +[ ]*[0-9a-f]+:[ ]+bcb6[ ]+cm.popretz[ ]+\{ra,s0-s6\},80 +[ ]*[0-9a-f]+:[ ]+bcbe[ ]+cm.popretz[ ]+\{ra,s0-s6\},112 +[ ]*[0-9a-f]+:[ ]+bcc2[ ]+cm.popretz[ ]+\{ra,s0-s7\},80 +[ ]*[0-9a-f]+:[ ]+bcc6[ ]+cm.popretz[ ]+\{ra,s0-s7\},96 +[ ]*[0-9a-f]+:[ ]+bcce[ ]+cm.popretz[ ]+\{ra,s0-s7\},128 +[ ]*[0-9a-f]+:[ ]+bce2[ ]+cm.popretz[ ]+\{ra,s0-s9\},96 +[ ]*[0-9a-f]+:[ ]+bce6[ ]+cm.popretz[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bcee[ ]+cm.popretz[ ]+\{ra,s0-s9\},144 +[ ]*[0-9a-f]+:[ ]+bcf2[ ]+cm.popretz[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+bcf6[ ]+cm.popretz[ ]+\{ra,s0-s11\},128 +[ ]*[0-9a-f]+:[ ]+bcfa[ ]+cm.popretz[ ]+\{ra,s0-s11\},144 +[ ]*[0-9a-f]+:[ ]+bcfe[ ]+cm.popretz[ ]+\{ra,s0-s11\},160 diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop.s b/gas/testsuite/gas/riscv/zcmp-push-pop.s new file mode 100644 index 00000000000..bec40ebbcbc --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop.s @@ -0,0 +1,197 @@ +target: + + # push + # abi names + cm.push {ra}, -64 + cm.push {ra, s0}, -64 + cm.push {ra, s0-s1}, -64 + cm.push {ra, s0-s2}, -64 + cm.push {ra, s0-s8}, -112 + cm.push {ra, s0-s9}, -112 + cm.push {ra, s0-s11}, -112 + + # numeric names + cm.push {x1}, -64 + cm.push {x1, x8}, -64 + cm.push {x1, x8-x9}, -64 + cm.push {x1, x8-x9, x18}, -64 + cm.push {x1, x8-x9, x18-x24}, -112 + cm.push {x1, x8-x9, x18-x25}, -112 + cm.push {x1, x8-x9, x18-x27}, -112 + + # spimm + cm.push {ra}, -16 + cm.push {ra}, -32 + cm.push {ra}, -64 + + cm.push {ra, s0-s2}, -32 + cm.push {ra, s0-s2}, -64 + cm.push {ra, s0-s2}, -80 + + cm.push {ra, s0-s3}, -48 + cm.push {ra, s0-s3}, -64 + cm.push {ra, s0-s3}, -96 + + cm.push {ra, s0-s6}, -64 + cm.push {ra, s0-s6}, -80 + cm.push {ra, s0-s6}, -112 + + cm.push {ra, s0-s7}, -80 + cm.push {ra, s0-s7}, -96 + cm.push {ra, s0-s7}, -128 + + cm.push {ra, s0-s9}, -96 + cm.push {ra, s0-s9}, -112 + cm.push {ra, s0-s9}, -144 + + cm.push {ra, s0-s11}, -112 + cm.push {ra, s0-s11}, -128 + cm.push {ra, s0-s11}, -144 + cm.push {ra, s0-s11}, -160 + + # pop + # abi names + cm.pop {ra}, 64 + cm.pop {ra, s0}, 64 + cm.pop {ra, s0-s1}, 64 + cm.pop {ra, s0-s2}, 64 + cm.pop {ra, s0-s8}, 112 + cm.pop {ra, s0-s9}, 112 + cm.pop {ra, s0-s11}, 112 + + # numeric names + cm.pop {x1}, 64 + cm.pop {x1, x8}, 64 + cm.pop {x1, x8-x9}, 64 + cm.pop {x1, x8-x9, x18}, 64 + cm.pop {x1, x8-x9, x18-x24}, 112 + cm.pop {x1, x8-x9, x18-x25}, 112 + cm.pop {x1, x8-x9, x18-x27}, 112 + + # spimm + cm.pop {ra}, 16 + cm.pop {ra}, 32 + cm.pop {ra}, 64 + + cm.pop {ra, s0-s2}, 32 + cm.pop {ra, s0-s2}, 64 + cm.pop {ra, s0-s2}, 80 + + cm.pop {ra, s0-s3}, 48 + cm.pop {ra, s0-s3}, 64 + cm.pop {ra, s0-s3}, 96 + + cm.pop {ra, s0-s6}, 64 + cm.pop {ra, s0-s6}, 80 + cm.pop {ra, s0-s6}, 112 + + cm.pop {ra, s0-s7}, 80 + cm.pop {ra, s0-s7}, 96 + cm.pop {ra, s0-s7}, 128 + + cm.pop {ra, s0-s9}, 96 + cm.pop {ra, s0-s9}, 112 + cm.pop {ra, s0-s9}, 144 + + cm.pop {ra, s0-s11}, 112 + cm.pop {ra, s0-s11}, 128 + cm.pop {ra, s0-s11}, 144 + cm.pop {ra, s0-s11}, 160 + + # popret + # abi names + cm.popret {ra}, 64 + cm.popret {ra, s0}, 64 + cm.popret {ra, s0-s1}, 64 + cm.popret {ra, s0-s2}, 64 + cm.popret {ra, s0-s8}, 112 + cm.popret {ra, s0-s9}, 112 + cm.popret {ra, s0-s11}, 112 + + # numeric names + cm.popret {x1}, 64 + cm.popret {x1, x8}, 64 + cm.popret {x1, x8-x9}, 64 + cm.popret {x1, x8-x9, x18}, 64 + cm.popret {x1, x8-x9, x18-x24}, 112 + cm.popret {x1, x8-x9, x18-x25}, 112 + cm.popret {x1, x8-x9, x18-x27}, 112 + + # spimm + cm.popret {ra}, 16 + cm.popret {ra}, 32 + cm.popret {ra}, 64 + + cm.popret {ra, s0-s2}, 32 + cm.popret {ra, s0-s2}, 64 + cm.popret {ra, s0-s2}, 80 + + cm.popret {ra, s0-s3}, 48 + cm.popret {ra, s0-s3}, 64 + cm.popret {ra, s0-s3}, 96 + + cm.popret {ra, s0-s6}, 64 + cm.popret {ra, s0-s6}, 80 + cm.popret {ra, s0-s6}, 112 + + cm.popret {ra, s0-s7}, 80 + cm.popret {ra, s0-s7}, 96 + cm.popret {ra, s0-s7}, 128 + + cm.popret {ra, s0-s9}, 96 + cm.popret {ra, s0-s9}, 112 + cm.popret {ra, s0-s9}, 144 + + cm.popret {ra, s0-s11}, 112 + cm.popret {ra, s0-s11}, 128 + cm.popret {ra, s0-s11}, 144 + cm.popret {ra, s0-s11}, 160 + + # popretz + # abi names + cm.popretz {ra}, 64 + cm.popretz {ra, s0}, 64 + cm.popretz {ra, s0-s1}, 64 + cm.popretz {ra, s0-s2}, 64 + cm.popretz {ra, s0-s8}, 112 + cm.popretz {ra, s0-s9}, 112 + cm.popretz {ra, s0-s11}, 112 + + # numeric names + cm.popretz {x1}, 64 + cm.popretz {x1, x8}, 64 + cm.popretz {x1, x8-x9}, 64 + cm.popretz {x1, x8-x9, x18}, 64 + cm.popretz {x1, x8-x9, x18-x24}, 112 + cm.popretz {x1, x8-x9, x18-x25}, 112 + cm.popretz {x1, x8-x9, x18-x27}, 112 + + # spimm + cm.popretz {ra}, 16 + cm.popretz {ra}, 32 + cm.popretz {ra}, 64 + + cm.popretz {ra, s0-s2}, 32 + cm.popretz {ra, s0-s2}, 64 + cm.popretz {ra, s0-s2}, 80 + + cm.popretz {ra, s0-s3}, 48 + cm.popretz {ra, s0-s3}, 64 + cm.popretz {ra, s0-s3}, 96 + + cm.popretz {ra, s0-s6}, 64 + cm.popretz {ra, s0-s6}, 80 + cm.popretz {ra, s0-s6}, 112 + + cm.popretz {ra, s0-s7}, 80 + cm.popretz {ra, s0-s7}, 96 + cm.popretz {ra, s0-s7}, 128 + + cm.popretz {ra, s0-s9}, 96 + cm.popretz {ra, s0-s9}, 112 + cm.popretz {ra, s0-s9}, 144 + + cm.popretz {ra, s0-s11}, 112 + cm.popretz {ra, s0-s11}, 128 + cm.popretz {ra, s0-s11}, 144 + cm.popretz {ra, s0-s11}, 160 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 53f5f200508..f8054f54f15 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2235,6 +2235,15 @@ #define MASK_C_NOT 0xfc7f #define MATCH_C_MUL 0x9c41 #define MASK_C_MUL 0xfc63 +/* ZCMP instructions. */ +#define MATCH_CM_PUSH 0xb802 +#define MASK_CM_PUSH 0xff03 +#define MATCH_CM_POP 0xba02 +#define MASK_CM_POP 0xff03 +#define MATCH_CM_POPRET 0xbe02 +#define MASK_CM_POPRET 0xff03 +#define MATCH_CM_POPRETZ 0xbc02 +#define MASK_CM_POPRETZ 0xff03 /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3405,6 +3414,11 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) +/* Zcmp instructions. */ +DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) +DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) +DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) +DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 808f3657303..f9bfb19bd5e 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -112,6 +112,8 @@ static inline unsigned int riscv_insn_length (insn_t insn) (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1)) #define EXTRACT_ZCB_HALFWORD_UIMM(x) \ (RV_X(x, 5, 1) << 1) +#define EXTRACT_ZCMP_SPIMM(x) \ + (RV_X(x, 2, 2) << 4) #define ENCODE_ITYPE_IMM(x) \ (RV_X(x, 0, 12) << 20) @@ -163,6 +165,8 @@ static inline unsigned int riscv_insn_length (insn_t insn) ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5)) #define ENCODE_ZCB_HALFWORD_UIMM(x) \ (RV_X(x, 1, 1) << 5) +#define ENCODE_ZCMP_SPIMM(x) \ + (RV_X(x, 4, 2) << 2) #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) @@ -190,6 +194,7 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x)) #define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x)) #define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x)) +#define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) == (x)) #define RISCV_RTYPE(insn, rd, rs1, rs2) \ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) @@ -318,6 +323,10 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define OP_MASK_VWD 0x1 #define OP_SH_VWD 26 +/* Zc fields. */ +#define OP_MASK_RLIST 0xf +#define OP_SH_RLIST 4 + #define NVECR 32 #define NVECM 1 @@ -330,6 +339,11 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define X_T0 5 #define X_T1 6 #define X_T2 7 +#define X_S0 8 +#define X_S1 9 +#define X_S2 18 +#define X_S10 26 +#define X_S11 27 #define X_T3 28 #define NGPR 32 @@ -435,6 +449,7 @@ enum riscv_insn_class INSN_CLASS_ZCB_AND_ZBA, INSN_CLASS_ZCB_AND_ZBB, INSN_CLASS_ZCB_AND_ZMMUL, + INSN_CLASS_ZCMP, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 2826248f8af..d938c9cb2ed 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -75,6 +75,8 @@ static const char * const *riscv_fpr_names; /* If set, disassemble as most general instruction. */ static bool no_aliases = false; +/* If set, disassemble numeric register names instead of ABI names. */ +static int numeric = 0; /* Set default RISC-V disassembler options. */ @@ -84,6 +86,7 @@ set_default_riscv_dis_options (void) riscv_gpr_names = riscv_gpr_names_abi; riscv_fpr_names = riscv_fpr_names_abi; no_aliases = false; + numeric = 0; } /* Parse RISC-V disassembler option (without arguments). */ @@ -97,6 +100,7 @@ parse_riscv_dis_option_without_args (const char *option) { riscv_gpr_names = riscv_gpr_names_numeric; riscv_fpr_names = riscv_fpr_names_numeric; + numeric = 1; } else return false; @@ -215,6 +219,50 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset, pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr; } +/* Get ZCMP rlist field. */ + +static void +print_rlist (disassemble_info *info, insn_t l) +{ + unsigned rlist = (int)EXTRACT_OPERAND (RLIST, l); + unsigned r_start = numeric ? X_S2 : X_S0; + info->fprintf_func (info->stream, "%s", riscv_gpr_names[X_RA]); + + if (rlist == 5) + info->fprintf_func (info->stream, ",%s", riscv_gpr_names[X_S0]); + else if (rlist == 6 || (numeric && rlist > 6)) + info->fprintf_func (info->stream, ",%s-%s", + riscv_gpr_names[X_S0], + riscv_gpr_names[X_S1]); + + if (rlist == 15) + info->fprintf_func (info->stream, ",%s-%s", + riscv_gpr_names[r_start], + riscv_gpr_names[X_S11]); + else if (rlist == 7 && numeric) + info->fprintf_func (info->stream, ",%s", + riscv_gpr_names[X_S2]); + else if (rlist > 6) + info->fprintf_func (info->stream, ",%s-%s", + riscv_gpr_names[r_start], + riscv_gpr_names[rlist + 11]); +} + +/* Get ZCMP sp adjustment immediate. */ + +static int +riscv_get_spimm (insn_t l) +{ + int spimm = riscv_get_sp_base(l, &riscv_rps_dis); + + spimm += EXTRACT_ZCMP_SPIMM (l); + + if (((l ^ MATCH_CM_PUSH) & MASK_CM_PUSH) == 0) + spimm *= -1; + + return spimm; +} + /* Print insn arguments for 32/64-bit code. */ static void @@ -420,6 +468,8 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case ')': case '[': case ']': + case '{': + case '}': print (info->stream, dis_style_text, "%c", *oparg); break; @@ -625,6 +675,13 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info print (info->stream, dis_style_immediate, "%d", (int)EXTRACT_ZCB_HALFWORD_UIMM (l)); break; + case 'r': + print_rlist (info, l); + break; + case 'p': + print (info->stream, dis_style_immediate, "%d", + riscv_get_spimm (l)); + break; default: break; } break; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6a854736fec..7d2f92e736b 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1967,6 +1967,12 @@ const struct riscv_opcode riscv_opcodes[] = {"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 }, {"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +/* Zcmp instructions. */ +{"cm.push", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_PUSH, MASK_CM_PUSH, match_opcode, 0 }, +{"cm.pop", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 }, +{"cm.popret", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRET, MASK_CM_POPRET, match_opcode, 0 }, +{"cm.popretz", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRETZ, MASK_CM_POPRETZ, match_opcode, 0 }, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS }, From patchwork Wed Jul 26 09:06:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 126207 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a985:0:b0:3e4:2afc:c1 with SMTP id t5csp269563vqo; Wed, 26 Jul 2023 02:07:17 -0700 (PDT) X-Google-Smtp-Source: APBJJlEx83yD7z4YOWqybGMT8y3sfF7MZhgnROl90A6Juhauu5gmqVA24RDa3SM/ZTvgaXmFn1p0 X-Received: by 2002:a17:907:78c9:b0:992:a618:c3c4 with SMTP id kv9-20020a17090778c900b00992a618c3c4mr1356018ejc.66.1690362437294; Wed, 26 Jul 2023 02:07:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690362437; cv=none; d=google.com; s=arc-20160816; b=OAMMyyx4AsS4PGrI7ZdbJurFOphZZumVeWbsbhYlqMFep5n34B32pIshXl1nYl3hDk mvAsi5xJo/p6W9fItR2bmwkYpTII/GQuhD7oKBDkmGdGjO4kDvWmQjk87Etl7Qpkau6E QbIw3Kn11mO7Y8exQ9QXX8NEAm42LmkAgrDoInJ1G4d0BKtv9aSyx5+YkJtVvNl+NfHe IQ0d+s9v/NoHXKlDtVjtHieo3Ajv9RMcCsXtxkKGQNBckQxwBo9lu2Wav6UHBaTL4vEx rxcDXSAwj2vJGntz3WxBYHeOsyMzap6VCmph8XanhgMWjmc4i9a9SAtn6DuTR30wIcsv tKtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dmarc-filter:delivered-to; bh=krkXZ2Y9YyhWphQ/ynE+2+PmTFCgVRn88Xi18/eX4V8=; fh=uVQyGh8W76dTTsmixLnhYJTyh7pAWMX+LbNseZLixk8=; b=oDvil4e4xQcB6hj5ywB7xcuXxxSuylcVWi1wIu5Uqxw3TMoGEzwlZmud5smgz5+ECv 9v22VS3kdEGP6zBP0JbxGf321bo0Qlq2MUOzzcVgGCN62YQQIjjmZwgxbJU8as3NziI8 tpo6d2KQpDdLV1J4f1vRpDUznY2oqD4WNE1ZAEcExrIwwg1IpK62lTlSiM63z58M2Ghk ED15QP0sKjtSlXhkFJ3Vu8TQ8JMyV5J0h9/oyPe9qSA3U3nt8eQAdR6Bb55enJpQ8Hw5 HwfDCdEvP2bNVzQg6tfAnRSyqxBz4CYHZKDdoidzpCAAQnxpJ9pAJN4pUn9NhklAgl1g IJVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id rp16-20020a170906d97000b0098e15543465si8342810ejb.280.2023.07.26.02.07.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 02:07:17 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 809DA385772A for ; Wed, 26 Jul 2023 09:07:15 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) by sourceware.org (Postfix) with ESMTPS id 7C4103858C33 for ; Wed, 26 Jul 2023 09:06:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7C4103858C33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-03 (Coremail) with SMTP id rQCowAD3_WUj4sBkbOYgDg--.8116S3; Wed, 26 Jul 2023 17:06:48 +0800 (CST) From: Jiawei To: binutils@sourceware.org Cc: nelson@rivosinc.com, kito.cheng@sifive.com, palmer@dabbelt.com, jbeulich@suse.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, nandni.jamnadas@embecosm.com, mary.bennett@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, sinan.lin@linux.alibaba.com, gaofei@eswincomputing.com, fujin.zhao@foxmail.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Jiawei Subject: [PATCH 2/2] RISC-V: Support Zcmp cm.mv instructions Date: Wed, 26 Jul 2023 17:06:22 +0800 Message-Id: <20230726090622.630672-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230726090622.630672-1-jiawei@iscas.ac.cn> References: <20230726090622.630672-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: rQCowAD3_WUj4sBkbOYgDg--.8116S3 X-Coremail-Antispam: 1UD129KBjvJXoW3Xry8AFW3Ww1xGF4UZw48tFb_yoWftF43pr 45Cr4Y9an5Ja97Cr4SgFy8ur43J397G34Yyw12ga17Z34xXrWfXFZ5tw1ftFZ5WF4a9r13 uw4a9r109F1UJFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lc2xSY4AK67A8MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I 3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxV W8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8I cVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aV AFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZE Xa7sREVyxtUUUUU== X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiAw0EAGTAnlbZvQABsD X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772473483014739561 X-GMAIL-MSGID: 1772473483014739561 This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'. All disassemble instructions use the sreg format. Co-Authored by: Charlie Keaney Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Sinan Lin Co-Authored by: Simon Cook Co-Authored by: Shihua Liao Co-Authored by: Yulong Shi gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-mv.d: New test. * testsuite/gas/riscv/zcmp-mv.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode. (MASK_CM_MVA01S): New mask. (MATCH_CM_MVSA01): New opcode. (MASK_CM_MVSA01): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (OP_MASK_SREG1): New mask. (OP_SH_SREG1): New operand code. (OP_MASK_SREG2): New mask. (OP_SH_SREG2): New operand code. (X_A0): New reg number. (X_A1): Ditto. (X_S7): Ditto. (RISCV_SREG_0_7): New macro function. opcodes/ChangeLog: * riscv-dis.c (riscv_get_sregno): (print_insn_args): * riscv-opc.c (match_sreg1_not_eq_sreg2): --- gas/config/tc-riscv.c | 17 +++++++++++++++++ gas/testsuite/gas/riscv/zcmp-mv.d | 26 ++++++++++++++++++++++++++ gas/testsuite/gas/riscv/zcmp-mv.s | 21 +++++++++++++++++++++ include/opcode/riscv-opc.h | 6 ++++++ include/opcode/riscv.h | 12 ++++++++++++ opcodes/riscv-dis.c | 19 +++++++++++++++++++ opcodes/riscv-opc.c | 8 ++++++++ 7 files changed, 109 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zcmp-mv.d create mode 100644 gas/testsuite/gas/riscv/zcmp-mv.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 266a91451b7..c5be308aa08 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1578,6 +1578,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'c': switch (*++oparg) { + /* sreg operators in cm.mvsa01 and cm.mva01s. */ + case '1': USE_BITS (OP_MASK_SREG1, OP_SH_SREG1); break; + case '2': USE_BITS (OP_MASK_SREG2, OP_SH_SREG2); break; /* byte immediate operators, load/store byte insns. */ case 'h': used_bits |= ENCODE_ZCB_HALFWORD_UIMM (-1U); break; /* halfword immediate operators, load/store halfword insns. */ @@ -3785,6 +3788,20 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, asarg = expr_parse_end; imm_expr->X_op = O_absent; continue; + + case '1': + if (!reg_lookup (&asarg, RCLASS_GPR, ®no) + || !RISCV_SREG_0_7 (regno)) + break; + INSERT_OPERAND (SREG1, *ip, regno % 8); + continue; + + case '2': + if (!reg_lookup (&asarg, RCLASS_GPR, ®no) + || !RISCV_SREG_0_7 (regno)) + break; + INSERT_OPERAND (SREG2, *ip, regno % 8); + continue; default: goto unknown_riscv_ip_operand; diff --git a/gas/testsuite/gas/riscv/zcmp-mv.d b/gas/testsuite/gas/riscv/zcmp-mv.d new file mode 100644 index 00000000000..351d301dd3f --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-mv.d @@ -0,0 +1,26 @@ +#as: -march=rv64i_zcmp +#source: zcmp-mv.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+ac7e[ ]+cm.mva01s[ ]+s0,s7 +[ ]*[0-9a-f]+:[ ]+ac7a[ ]+cm.mva01s[ ]+s0,s6 +[ ]*[0-9a-f]+:[ ]+acfe[ ]+cm.mva01s[ ]+s1,s7 +[ ]*[0-9a-f]+:[ ]+acfa[ ]+cm.mva01s[ ]+s1,s6 +[ ]*[0-9a-f]+:[ ]+afee[ ]+cm.mva01s[ ]+s7,s3 +[ ]*[0-9a-f]+:[ ]+ade2[ ]+cm.mva01s[ ]+s3,s0 +[ ]*[0-9a-f]+:[ ]+aef2[ ]+cm.mva01s[ ]+s5,s4 +[ ]*[0-9a-f]+:[ ]+aefa[ ]+cm.mva01s[ ]+s5,s6 +[ ]*[0-9a-f]+:[ ]+afa2[ ]+cm.mvsa01[ ]+s7,s0 +[ ]*[0-9a-f]+:[ ]+af22[ ]+cm.mvsa01[ ]+s6,s0 +[ ]*[0-9a-f]+:[ ]+afa6[ ]+cm.mvsa01[ ]+s7,s1 +[ ]*[0-9a-f]+:[ ]+af26[ ]+cm.mvsa01[ ]+s6,s1 +[ ]*[0-9a-f]+:[ ]+adbe[ ]+cm.mvsa01[ ]+s3,s7 +[ ]*[0-9a-f]+:[ ]+ada2[ ]+cm.mvsa01[ ]+s3,s0 +[ ]*[0-9a-f]+:[ ]+aeb2[ ]+cm.mvsa01[ ]+s5,s4 +[ ]*[0-9a-f]+:[ ]+aeba[ ]+cm.mvsa01[ ]+s5,s6 diff --git a/gas/testsuite/gas/riscv/zcmp-mv.s b/gas/testsuite/gas/riscv/zcmp-mv.s new file mode 100644 index 00000000000..0bcf2a6cd98 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-mv.s @@ -0,0 +1,21 @@ +target: + + # cm.mva01s + cm.mva01s s0,s7 + cm.mva01s s0,s6 + cm.mva01s s1,s7 + cm.mva01s s1,s6 + cm.mva01s s7,s3 + cm.mva01s x19,s0 + cm.mva01s s5,x20 + cm.mva01s x21,x22 + + # cm.mvsa01 + cm.mvsa01 s7,s0 + cm.mvsa01 s6,s0 + cm.mvsa01 s7,s1 + cm.mvsa01 s6,s1 + cm.mvsa01 s3,s7 + cm.mvsa01 x19,s0 + cm.mvsa01 s5,x20 + cm.mvsa01 x21,x22 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index f8054f54f15..11e9c0b99d0 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2244,6 +2244,10 @@ #define MASK_CM_POPRET 0xff03 #define MATCH_CM_POPRETZ 0xbc02 #define MASK_CM_POPRETZ 0xff03 +#define MATCH_CM_MVA01S 0xac62 +#define MASK_CM_MVA01S 0xfc63 +#define MATCH_CM_MVSA01 0xac22 +#define MASK_CM_MVSA01 0xfc63 /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3419,6 +3423,8 @@ DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) +DECLARE_INSN(cm_mvsa01, MATCH_CM_MVSA01, MASK_CM_MVSA01) +DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f9bfb19bd5e..44576fa9241 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -326,6 +326,10 @@ static inline unsigned int riscv_insn_length (insn_t insn) /* Zc fields. */ #define OP_MASK_RLIST 0xf #define OP_SH_RLIST 4 +#define OP_MASK_SREG1 0x7 +#define OP_SH_SREG1 7 +#define OP_MASK_SREG2 0x7 +#define OP_SH_SREG2 2 #define NVECR 32 #define NVECM 1 @@ -341,7 +345,10 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define X_T2 7 #define X_S0 8 #define X_S1 9 +#define X_A0 10 +#define X_A1 11 #define X_S2 18 +#define X_S7 23 #define X_S10 26 #define X_S11 27 #define X_T3 28 @@ -389,6 +396,11 @@ static inline unsigned int riscv_insn_length (insn_t insn) /* The maximal number of subset can be required. */ #define MAX_SUBSET_NUM 4 +/* The range of sregs. */ +#define RISCV_SREG_0_7(REGNO) \ + ((REGNO == X_S0 || REGNO == X_S1) \ + || (REGNO >= X_S2 && REGNO <= X_S7)) + /* All RISC-V instructions belong to at least one of these classes. */ enum riscv_insn_class { diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index d938c9cb2ed..058698c0c0a 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -263,6 +263,17 @@ riscv_get_spimm (insn_t l) return spimm; } +/* Get s-register regno by using sreg number. + e.g. the regno of s0 is 8, so + riscv_get_sregno (0) equals 8. */ + +static unsigned +riscv_get_sregno (unsigned sreg_idx) +{ + return sreg_idx > 1 ? + sreg_idx + 16 : sreg_idx + 8; +} + /* Print insn arguments for 32/64-bit code. */ static void @@ -667,6 +678,14 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case 'c': /* Zcb extension 16 bits length instruction fields. */ switch (*++oparg) { + case '1': + print (info->stream, dis_style_register, "%s", + riscv_gpr_names[riscv_get_sregno (EXTRACT_OPERAND (SREG1, l))]); + break; + case '2': + print (info->stream, dis_style_register, "%s", + riscv_gpr_names[riscv_get_sregno (EXTRACT_OPERAND (SREG2, l))]); + break; case 'b': print (info->stream, dis_style_immediate, "%d", (int)EXTRACT_ZCB_BYTE_UIMM (l)); diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 7d2f92e736b..b0a69efed49 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -329,6 +329,12 @@ match_th_load_pair(const struct riscv_opcode *op, return rd1 != rd2 && rd1 != rs && rd2 != rs && match_opcode (op, insn); } +match_sreg1_not_eq_sreg2 (const struct riscv_opcode *op, insn_t insn) +{ + return match_opcode (op, insn) + && (EXTRACT_OPERAND (SREG1, insn) != EXTRACT_OPERAND (SREG2, insn)); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -1972,6 +1978,8 @@ const struct riscv_opcode riscv_opcodes[] = {"cm.pop", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 }, {"cm.popret", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRET, MASK_CM_POPRET, match_opcode, 0 }, {"cm.popretz", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRETZ, MASK_CM_POPRETZ, match_opcode, 0 }, +{"cm.mva01s", 0, INSN_CLASS_ZCMP, "Wc1,Wc2", MATCH_CM_MVA01S, MASK_CM_MVA01S, match_opcode, 0 }, +{"cm.mvsa01", 0, INSN_CLASS_ZCMP, "Wc1,Wc2", MATCH_CM_MVSA01, MASK_CM_MVSA01, match_sreg1_not_eq_sreg2, 0 }, /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },