From patchwork Tue Jul 25 22:08:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Faust X-Patchwork-Id: 125839 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a985:0:b0:3e4:2afc:c1 with SMTP id t5csp37745vqo; Tue, 25 Jul 2023 15:10:23 -0700 (PDT) X-Google-Smtp-Source: APBJJlHn2qhJgRVdALdAJG/zbyOEulniDPNQIC2Kv0B6WEGmunCSFUs3tm0YsnjyLGfbrn0C8Bnf X-Received: by 2002:aa7:d813:0:b0:522:2dcc:afb6 with SMTP id v19-20020aa7d813000000b005222dccafb6mr167440edq.7.1690323023501; Tue, 25 Jul 2023 15:10:23 -0700 (PDT) Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id i17-20020a50fc11000000b005222b2ccdd7si4052906edr.433.2023.07.25.15.10.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 15:10:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=DZUSS8X+; arc=fail (signature failed); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E32E53855583 for ; Tue, 25 Jul 2023 22:10:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E32E53855583 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690323007; bh=MyeKDVBXwxFkvHPx372ta3l5c7r6w/0Mfq3H4wLazUQ=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=DZUSS8X+yP69UZP4tiESNN3JrOg18Rd0funTPTCiP5wvnDm09wPP9+RE2t1LwkkMt JH1TU99rUzP7C7re2bOCZ0ngk2vhFc0Ucj/ZN7VQ7ji/+mu9h3bcrCRCKJrEYo2Eab 0gfJLEwpriw0tgYRgDX8igltGjzLQ05CaOt/o44g= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com [205.220.165.32]) by sourceware.org (Postfix) with ESMTPS id 1561B3858C33 for ; Tue, 25 Jul 2023 22:09:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1561B3858C33 Received: from pps.filterd (m0246629.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36PJIqf3019154 for ; Tue, 25 Jul 2023 22:09:16 GMT Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.appoci.oracle.com [138.1.37.129]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3s070ax6sj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 25 Jul 2023 22:09:16 +0000 Received: from pps.filterd (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (8.17.1.19/8.17.1.19) with ESMTP id 36PLs3ZA025472 for ; Tue, 25 Jul 2023 22:09:16 GMT Received: from nam11-bn8-obe.outbound.protection.outlook.com (mail-bn8nam11lp2168.outbound.protection.outlook.com [104.47.58.168]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id 3s05j5vxgd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 25 Jul 2023 22:09:15 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Dm0ceSEzVf1v4GgbGdyN4Bcu9SATYpg/BM3KXjewUoaZQAmHtCARRc6bDuVFwPCkHoyARjfcJ/FiH4hprp+TvdGhIjn5yxJE5Wu3lmwC3ozGlHP4oEvs4JdLfg0/noz+rG3zH6S8z2zy8JJqcTRf7VMKOQH5jM27cJapGRnz/t9Yzitw7FZErRYwN6x6F3xCIMVKOIqduwh+mhb2pV83yNaw62MT1vKw0GliqAZfRdAzJjS7lNgMo8HfnsEgMZl1WbDJsHQbPMU5BK7/JDzQTWjnGfHQ5eJcnhxeRTzCC28u1T92Y/hcIyHIU5bHIRNXGix4WzU6UGTBfoMH/776zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MyeKDVBXwxFkvHPx372ta3l5c7r6w/0Mfq3H4wLazUQ=; b=FUCkkyMe89IumPoWE3i0m9GiqRHoB5m5VXzG0A7L7Apv4HoBOAuHTPWmqZH4tJI9zIMAPlvYBQKC+4zj3kHMgMeNb0lE/RynNiXYioE7Y2kZoLPYZl33PzlQDOnkKphTuu1fh4YypbnAM14Jk1lnhYDXeVzgy3H6fN1jTgb1uj7fvFrEVvrpx3Fp5RHAx2a5sGnY/0T+28bEU08IimqmdesmAAlh+7we7X+g0p8xpvoQZX6kGpvLH0v/FbJPC2+2cxMeaXwX7imv98iflL2t7HyBbXPRo+XPwwzblPIQdWoR/Mxrltinnkp42T1QUaa8BOhBPjhPfDSlzzfFgS4aAA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oracle.com; dmarc=pass action=none header.from=oracle.com; dkim=pass header.d=oracle.com; arc=none Received: from MN2PR10MB3213.namprd10.prod.outlook.com (2603:10b6:208:131::33) by SJ0PR10MB4512.namprd10.prod.outlook.com (2603:10b6:a03:2dc::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.32; Tue, 25 Jul 2023 22:09:13 +0000 Received: from MN2PR10MB3213.namprd10.prod.outlook.com ([fe80::827f:8665:2052:16c5]) by MN2PR10MB3213.namprd10.prod.outlook.com ([fe80::827f:8665:2052:16c5%4]) with mapi id 15.20.6609.032; Tue, 25 Jul 2023 22:09:13 +0000 To: gcc-patches@gcc.gnu.org Cc: jose.marchesi@oracle.com Subject: [PATCH 1/2] bpf: don't print () in bpf_print_operand_address Date: Tue, 25 Jul 2023 15:08:20 -0700 Message-Id: <20230725220821.11431-1-david.faust@oracle.com> X-Mailer: git-send-email 2.39.1 X-ClientProxiedBy: SJ0PR03CA0196.namprd03.prod.outlook.com (2603:10b6:a03:2ef::21) To MN2PR10MB3213.namprd10.prod.outlook.com (2603:10b6:208:131::33) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN2PR10MB3213:EE_|SJ0PR10MB4512:EE_ X-MS-Office365-Filtering-Correlation-Id: e5b6dd15-c7f1-4ea2-8e5a-08db8d5bc74a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: If+eP0y5/PFIObxqgeOGU3PJgfhGuGFYuJGyKcgC14kl12XkWywT1yq6GgTNxp34ikA2R/4EfGWXIRyjhHDJsQSNPCsFc0AoH3I1xPqA/Ogccv4B2ZkFSG99UD6hwl9k8fLK0xxC6oDTvIAbBqm/geqSxJFEkrZqABmUf1DNNV/Y5t7A2Qa2oGYX3Ny3uP8zu26QEr0foGCfBglUEGXOz0ErjRZKONanOkHfzzDZ5ytP0xf9gWrEQr7MU9dJ68lYvMnOprqH0ek+WHcdhhOYHIg/auhq8QuujmkT76YJqzfRYlK9ICh4D/wGitrnT6CdXOOySfypjrBmcQMwrycc03KLHCL3szHy8gCOraIHSYv7N+N25NIRd6td+a4EluI2GCMMSS7XQUhBe2r+pyrYG9BIv50poayNHdmXbZwK/jBfRuocou062v0E2HkIviysw4ClWEZh3Idvymm3EnDLKCH79qY3Upi3FCeYvUmH0ZXTHAqmP18byKNGDCHs/If22Kb3ZZlHT4elfD7XfOdhcGWe2GnjVLKNDpFZgj26yfvWnT5Vg8Sd3E4zmb/NcbTi X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MN2PR10MB3213.namprd10.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230028)(346002)(396003)(366004)(376002)(136003)(39860400002)(451199021)(5660300002)(83380400001)(2616005)(2906002)(8676002)(8936002)(38100700002)(6486002)(44832011)(6506007)(478600001)(1076003)(26005)(186003)(107886003)(41300700001)(6666004)(6512007)(66556008)(86362001)(6916009)(4326008)(316002)(66476007)(66946007)(36756003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Bc5VzfBzA/CPkhAoC1esWRfp8QpobwMDee/P902WaZdExBhc6M3HmakcQRCTC7OFazl9QGRO0fq0+5eX61VJ4ukYJRh748tmXMa2P/bhWb6AhETJCfPVXE9teyFBUsZxIqFNennDLDcXelGFQfyiOQ8I27QUcgvkQlmqzywXxZbviOTJSsh3YIK3vGqn6V32yj89BaSV5QNORBFTMyW1v9k/O2fnhRSLFuofelgLezOLHWC4UshcvzdQEK921qpQxcXOV1Rv7qvhyB26i0CKozxo81kObynNcRS4BnE0QU1nCOKLuBKCQ/NlEHlVdbWPMrYBlin5PhSAxpypwdQmjYOfA4N2YbBD/edrOwwXtEkRBkWcLQAn4pOBuKCIOZ2t/nE2MOJ8IE2sgJ1GBZ/CGdF2ALZT/38lTfVdHntLe3U/8VQinIzxtImy0NByuaDXwgMilX4QEdUQ7WosI36MVO8HYWgdZZT9b5ALPFdxew7mKUife0HZ+Ki6KBwmS4MoVwgnKDu6SiTpJEF6Aub1rBNzizqF9sAj4RWobOsrbjr7p84yShAHwcrHwL5OCFVZ5DlcUm6Hr40XDN/frcKE5AGy/WOzsTgXb+YPnJAzFqAsaP3X4jI/tqaMiA8ziYP3snnFv5KPIy7sMegtKvwSl5R4+zAh47jZ4YdJTPUwDaKZ+g4lNVCBzAC3BKoTjQqTgind3M0tteeuvffq1uKK+ZtU23cWxM+D1KeTWbiQyGVWJSZrO+d4GeTED2QPN67pm/My6u4dOoV6kJ5gP8ehNs860iVRw5lq4+9a0h9YEo79+63634tAD1hs3nJdKVCmIh/3a6L09sSnyFQ3uxRt2s6RPP2XXSwZfU27sy7JiE1b0NAtlWJ6CC5kd+hWsn76Xe5Xv9HVF28kHpmbn9OHDikKeqogPHXaEMEzmd6vPBXnk9ZaUyaTAAYlRsP9xf0WyLSup5g+xkHJLO88TVYTzeUdbOOLmR9jwmO04eJjtdpGPAfDGWZxPrszdr3UTX/TB1NSYiAVVkErb8IAuffuTxgpERIgIu8dfMgMGfAnXOBoY09Hjf2Sp+E60iqs8RZ2ORzjZhkv9ZFGfyTSD7z00aR7gFcP3ogHhjhqcjW6AePu/wS+Y8DOYBoLdLFO1t5a/Ue/XB/rlY5onr8a8xH1PibTFCFF4GM8CETeNvG6ypF4wqYamrGxU4UGnCJmiVXtaQqL5MIqBJuzYLFZIL/KeqDv+NiIA8Lr1WCQhGCtE1JFT9Agv8XOey/lgTVSWOG8ty2POrBmMUYYj/KIPnLDHuLtCo9L37ZC4NepSATlCREVixeRMll/bOoxekCeAVkEgoxObCceZPxrtEpsxBigEl+mYOx30Qn4T6EgiiTvB+fHAEqR0kH+Lbu6tjkDRrjEVAlWSy5mr90WZeHZPKXI4y4DWkGUShMbEVChiJDi79x5Ix4VzMrb3dhLL0TaDM2E9vWTaIE7bEiVKCmp5nCUPA5L3jlFV8jshZQ1bEKzJVAy2jGyWSwXgCLPVXFJBUXC8PPhyMITZsmEpdj9g46VJXbWotKMrGd+6H215G8Ul9dXLBTTiKHydKYE/ZgewtAy X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: sRMAdVUuyML4D6R3AxnOw3CyS4fBw4vkP5dX0/HivDzjYfQWNsQvqaA5FlhANowfWWEh84d6h5xH9ln05fls7M9J/9n/jz5PlpcNzV8zxdoRdw+qYVqAe0EK6bLd2RKsrWFpqzF+bZSJ8zBh/0CpG08yb7MeedV3wiIBd8nZW4BLK+zw0kGNHoETNu9tHZTW4TLLRR3i7BYYk7bPy/vUOaJbDksUbbRhalnTBVr45hfTBK2+VBNwk6PMoSpauxapmDPizgcdrj7BpZIEvwLEyx0X8tjJQ3/wvQI8hQFIyhy1nF6c2E9O0n7e486iKPLIkqmA91K5B8wbdXy3xOB/cn/JZe5CpM1lPwfQ4fj2lvSveCwzgl4pSnzci+pje1RUwHpEdSBMl5r7eO1GKA8JRCP0251HUHikHyqDikOMgVz+KEEBYvmnIpevjiNPcQqiOooW79BeJPpxmMixMYGgupGcBmYry/P9xUbT/e7SVUUxTUtfgBKp3CbyQw9qN3EzxETSOMlt1FE7JeKiD7GTviDddyU4ppd7dwnaIWO+v46WdJ6kW6Bi1ruH/KAVESp+ZjyEJyfDhSTn1QdeOPfaDKRo+U7lDLmASo3WnG3iyIhoZ+LpglujAsEZvc1/XJ+/r0HEBJ/2mCgryCTPRqA05nQOB1idToWIU97eFmrLmMcTtOiqrRPGSYt7VOoJ8C8Bj9Jb37lm11A3Pl9lIS8Jw36tBCBTWWTwngBNzpe7puxTlU8nj8YoIwQ9nT9axpnV X-OriginatorOrg: oracle.com X-MS-Exchange-CrossTenant-Network-Message-Id: e5b6dd15-c7f1-4ea2-8e5a-08db8d5bc74a X-MS-Exchange-CrossTenant-AuthSource: MN2PR10MB3213.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jul 2023 22:09:13.0683 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: u4TbPrewTbK5jMGMajCs0l8/LnPcqvKZZwwOAogRySyD6t5ToR8b87ffbe0KJSLnzTHH5+k1Fb8wVfyzO5E65A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR10MB4512 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_12,2023-07-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 mlxlogscore=999 adultscore=0 mlxscore=0 phishscore=0 suspectscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250189 X-Proofpoint-GUID: 1WS9WpwDxn6IVk1wlfndHBcRmG63U33H X-Proofpoint-ORIG-GUID: 1WS9WpwDxn6IVk1wlfndHBcRmG63U33H X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: David Faust via Gcc-patches From: David Faust Reply-To: David Faust Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772432154892742261 X-GMAIL-MSGID: 1772432154892742261 Unfortunately, the pseudo-C dialect syntax used for some of the v3 atomic instructions clashes with unconditionally printing the surrounding parentheses in bpf_print_operand_address. Instead, place the parentheses in the output templates where needed. Tested in bpf-unknown-none. OK? gcc/ * config/bpf/bpf.cc (bpf_print_operand_address): Don't print enclosing parentheses for pseudo-C dialect. * config/bpf/bpf.md (zero_exdendhidi2): Add parentheses around operands of pseudo-C dialect output templates where needed. (zero_extendqidi2): Likewise. (zero_extendsidi2): Likewise. (*mov): Likewise. --- gcc/config/bpf/bpf.cc | 8 ++++---- gcc/config/bpf/bpf.md | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc index 55b6927a62f..2c077ea834e 100644 --- a/gcc/config/bpf/bpf.cc +++ b/gcc/config/bpf/bpf.cc @@ -933,9 +933,9 @@ bpf_print_operand_address (FILE *file, rtx addr) switch (GET_CODE (addr)) { case REG: - fprintf (file, asm_dialect == ASM_NORMAL ? "[" : "("); + fprintf (file, asm_dialect == ASM_NORMAL ? "[" : ""); bpf_print_register (file, addr, 0); - fprintf (file, asm_dialect == ASM_NORMAL ? "+0]" : "+0)"); + fprintf (file, asm_dialect == ASM_NORMAL ? "+0]" : "+0"); break; case PLUS: { @@ -944,11 +944,11 @@ bpf_print_operand_address (FILE *file, rtx addr) if (GET_CODE (op0) == REG && GET_CODE (op1) == CONST_INT) { - fprintf (file, asm_dialect == ASM_NORMAL ? "[" : "("); + fprintf (file, asm_dialect == ASM_NORMAL ? "[" : ""); bpf_print_register (file, op0, 0); fprintf (file, "+"); output_addr_const (file, op1); - fprintf (file, asm_dialect == ASM_NORMAL ? "]" : ")"); + fprintf (file, asm_dialect == ASM_NORMAL ? "]" : ""); } else fatal_insn ("invalid address in operand", addr); diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md index 64342ea1de2..579a8213b09 100644 --- a/gcc/config/bpf/bpf.md +++ b/gcc/config/bpf/bpf.md @@ -260,7 +260,7 @@ (define_insn "zero_extendhidi2" "@ {and\t%0,0xffff|%0 &= 0xffff} {mov\t%0,%1\;and\t%0,0xffff|%0 = %1;%0 &= 0xffff} - {ldxh\t%0,%1|%0 = *(u16 *) %1}" + {ldxh\t%0,%1|%0 = *(u16 *) (%1)}" [(set_attr "type" "alu,alu,ldx")]) (define_insn "zero_extendqidi2" @@ -270,7 +270,7 @@ (define_insn "zero_extendqidi2" "@ {and\t%0,0xff|%0 &= 0xff} {mov\t%0,%1\;and\t%0,0xff|%0 = %1;%0 &= 0xff} - {ldxh\t%0,%1|%0 = *(u8 *) %1}" + {ldxh\t%0,%1|%0 = *(u8 *) (%1)}" [(set_attr "type" "alu,alu,ldx")]) (define_insn "zero_extendsidi2" @@ -280,7 +280,7 @@ (define_insn "zero_extendsidi2" "" "@ * return bpf_has_alu32 ? \"{mov32\t%0,%1|%0 = %1}\" : \"{mov\t%0,%1\;and\t%0,0xffffffff|%0 = %1;%0 &= 0xffffffff}\"; - {ldxw\t%0,%1|%0 = *(u32 *) %1}" + {ldxw\t%0,%1|%0 = *(u32 *) (%1)}" [(set_attr "type" "alu,ldx")]) ;;; Sign-extension @@ -319,11 +319,11 @@ (define_insn "*mov" (match_operand:MM 1 "mov_src_operand" " q,rI,B,r,I"))] "" "@ - {ldx\t%0,%1|%0 = *( *) %1} + {ldx\t%0,%1|%0 = *( *) (%1)} {mov\t%0,%1|%0 = %1} {lddw\t%0,%1|%0 = %1 ll} - {stx\t%0,%1|*( *) %0 = %1} - {st\t%0,%1|*( *) %0 = %1}" + {stx\t%0,%1|*( *) (%0) = %1} + {st\t%0,%1|*( *) (%0) = %1}" [(set_attr "type" "ldx,alu,alu,stx,st")]) ;;;; Shifts From patchwork Tue Jul 25 22:08:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Faust X-Patchwork-Id: 125840 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a985:0:b0:3e4:2afc:c1 with SMTP id t5csp37859vqo; Tue, 25 Jul 2023 15:10:37 -0700 (PDT) X-Google-Smtp-Source: APBJJlG4YRhybo77l1vwO1LtB2zindCzOaGyWxq6vpCBpyneGxKuL276+whJlGQ49eCfSce9ggi5 X-Received: by 2002:a05:6402:8d6:b0:51e:227c:9492 with SMTP id d22-20020a05640208d600b0051e227c9492mr481277edz.20.1690323037604; Tue, 25 Jul 2023 15:10:37 -0700 (PDT) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id c2-20020a056402120200b00521d18821aasi1795325edw.109.2023.07.25.15.10.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 15:10:37 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=rFiextlZ; arc=fail (signature failed); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BAF5A385DC13 for ; Tue, 25 Jul 2023 22:10:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BAF5A385DC13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690323017; bh=EtaMXYUZAx19/5i+b4ZBpOVhggSCm9nw3oiSAE+i3V0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=rFiextlZD3BaoOIfHff1DKqfIBrcbX8wuQgX6eUXvS1ecISYhhXQugWiWvMZ/swkz Op8PA3RGxZHlpagOhHORNaXSdjc+x/7bZAZvGqvNbeLB/BGbLDL8cG4MMNnjEHgGWV a7BfsZBHHK3OJ82gGyjv/YbKqGKeSehUhr3X3/Q8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-00069f02.pphosted.com (mx0b-00069f02.pphosted.com [205.220.177.32]) by sourceware.org (Postfix) with ESMTPS id AC4D43856262 for ; Tue, 25 Jul 2023 22:09:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AC4D43856262 Received: from pps.filterd (m0246632.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36PJImgc028635 for ; Tue, 25 Jul 2023 22:09:25 GMT Received: from iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (iadpaimrmta01.appoci.oracle.com [130.35.100.223]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3s06qtx6sw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 25 Jul 2023 22:09:24 +0000 Received: from pps.filterd (iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com [127.0.0.1]) by iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (8.17.1.19/8.17.1.19) with ESMTP id 36PLjZS9030483 for ; Tue, 25 Jul 2023 22:09:24 GMT Received: from nam11-bn8-obe.outbound.protection.outlook.com (mail-bn8nam11lp2168.outbound.protection.outlook.com [104.47.58.168]) by iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTPS id 3s05jbnty1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 25 Jul 2023 22:09:24 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eaQhYMfEA5Mp3UouCB6HQcZg6fgK2aU2jMUNrnSNbFr3Y7eCBz42PfDQhdnI2raC/2qyq5pvFPUzfI0hAwul0OCcT6N5rXzn9fgAkiIN7Y7Vcw0gs6XHfwU+Vu48NrpQBc1fT6wMo/3GhMLgX3yqpAEW88TiRG+fVkEjccBV9O7b9ywj9p41V+yMawkEeDXL3e+KekniM+68pJVhEYRYHI7ELpwLyuQOPhQ4ogTAI67vVWSOAFXCto/DQ1tZuMbnKw4qq47PCi8bQCqTbGZOWAbMWWsFheMGs7fghdC+J4/lnTqDoiYEkc481kRRnlVGRsWhRAh6ck14Mjlc91+VFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=EtaMXYUZAx19/5i+b4ZBpOVhggSCm9nw3oiSAE+i3V0=; b=QDB6SMmNfQxkgY5IGKDCGlCs46+BSPNbOlvZmU6IVvppzttCSx0+/aOQt450k2whooGks7OrpFMi4GEYKV+RBAExoUsbhwL5u/rccgcDh585wvRWkdmUa9YfpNP/kEZk0OJ2sL/jlgDu4iRw4cUPLWVAg11F6NuEs75FagzNqkAI/C6Icw+2iUjvlXfcioCcUdH0dBh/AnAgiRbMnBBAqp+2KCGy8QuEEZ1YsWa6+2WK+Cx2vBF/UBhpRb0b26u4s1quZaraolzyZ6zbY3AQDv1j8lagZABKgV+nI++uscklzSoluvSkDxMcjyZiIOEgZQbomA0SvCyRguWwHcnGuQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oracle.com; dmarc=pass action=none header.from=oracle.com; dkim=pass header.d=oracle.com; arc=none Received: from MN2PR10MB3213.namprd10.prod.outlook.com (2603:10b6:208:131::33) by SJ0PR10MB4512.namprd10.prod.outlook.com (2603:10b6:a03:2dc::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.32; Tue, 25 Jul 2023 22:09:21 +0000 Received: from MN2PR10MB3213.namprd10.prod.outlook.com ([fe80::827f:8665:2052:16c5]) by MN2PR10MB3213.namprd10.prod.outlook.com ([fe80::827f:8665:2052:16c5%4]) with mapi id 15.20.6609.032; Tue, 25 Jul 2023 22:09:21 +0000 To: gcc-patches@gcc.gnu.org Cc: jose.marchesi@oracle.com Subject: [PATCH 2/2] bpf: add v3 atomic instructions Date: Tue, 25 Jul 2023 15:08:21 -0700 Message-Id: <20230725220821.11431-2-david.faust@oracle.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230725220821.11431-1-david.faust@oracle.com> References: <20230725220821.11431-1-david.faust@oracle.com> X-ClientProxiedBy: BY5PR04CA0023.namprd04.prod.outlook.com (2603:10b6:a03:1d0::33) To MN2PR10MB3213.namprd10.prod.outlook.com (2603:10b6:208:131::33) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN2PR10MB3213:EE_|SJ0PR10MB4512:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ba334de-6a04-40cb-da96-08db8d5bcc3e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: n4xI+DTmS3kCh49G7DV2qJM4S+FKN2kDWhv3Ju1IFFcJx2Kxl+8BFzqEsp4wHA1yDiNhA8cg3u8T79hkZXg6roU6TkAKgZSm96xYDSt2hACY/aX9ErMiZNi41HEoQtWLsOkqgWkjz3Umx2BRijPqJVJ73B37sDrI+J1OopMLStAX6J/vAHqO6y/TtGMR6DzDbEEiPCE5FM/kF1Tgqetc374tkhzVUHrNr3dVUcMoUAWkTQiIxaXstOdF9q143XySra7IU31Ca8CMZimvJHi+5zpeeoh55ZV1qtjMDFFhQc5CsQ3jmWTpkl4jFOiMJRyvPg3cg9WB8NlQ/+63gMfyuXG6bE96f5rZ8xaXAYJv8O2nRtr21fEGm74cgWRVbBusNxnwAmk0hBElyI2DCJSn+6yC749Fp85GlIzCVSHkC766h4Rx5LXwCPnp+B7Z2D09ENnZbCws25m0zd2CFK+BDSXbKdNcEk8jzXxbEqaQgjCcoYKNimlPNQe0kOyf149cIbMop+btmWSuSwQCMwGQUps3qtdEbtrhXz67X/lk7jgIq7AT0252hqvZX9Ckhp3wz7pc9gmDirGqkgjee4ulXg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MN2PR10MB3213.namprd10.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230028)(346002)(396003)(366004)(376002)(136003)(39860400002)(451199021)(30864003)(5660300002)(83380400001)(2616005)(2906002)(8676002)(8936002)(38100700002)(6486002)(84970400001)(44832011)(6506007)(478600001)(1076003)(26005)(186003)(107886003)(41300700001)(6512007)(66556008)(86362001)(6916009)(4326008)(316002)(66476007)(66946007)(36756003)(2004002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KnEoX3Fm/ptJTaSHuAxMKDLkXUNN2Awvh+LdjIFvtC9itqG7l5o/4OGibQaF2dSi4XpfC2xXmV0kwf+gD1TZtVKtXmri8vTUfaRqxYBIuW+D4Q00Y9LHnwt2BCVelmrfkcrRX9H9xIiNMVHVzTfrS4ZT2hKaMUGPPlGVVzKn0lUwScf8HKaD52kaU8w/uPSRcLbseWEUYSxVd4uHY429D6FvK1sWT3KwbxizXBfIJt5s26KV2/EBTyAnuBdJyF3ig2DbtrQB2RlcrztjyQfNMXg8KRhF9Czn4GWyBHXxjiIZW/eAFRwZl4bMue2ByD6cvD7uHm4YYKCM0igr3Dp9V7PhnnUryPJcdyrZW5Sqoo4WuMGKXzMt4iOyELxvInOV/3cgrTQZnhZYRSvGkG9Ghd5674RI6phzUvF5Jcv0UjRtnd3QqFfg8YAZP71U/Thz4PxwJqe0rhIi1t4fz/lZJdXxq/2T2i2OLWbGe9hwJm+nozGLmSXsA50LAxIdvJeO3n26996c6sWTFJVP0MXk9liYXrhkiOndunnHTD3C5XDpQhyJp3jbEUa6ewEvztev9onhURfT+vP+Z++rJdbF1jq+O6raulHFyTjqBPF51k1NXwZGIQe5YQwJlUoTpSMhm1tp/GjEEKF2U1NyCylBc0bxFv3zg6kKZRwrX8pfF3ZdEPVmiy0Wjs998Y8SmDPXT/1M54pxoeSEfG4eh4TPvLrKZv3QGzoPCbatLWwgynb+nnRXfnA71WQmhajMXol/IloSNjG+Tip0NiDHgWLP9T6ixDaB0DQghDZUJob4OGehZt9PKvUKTO3b6FM5WLLh/DbIxGnxjjzbTm/d5SyZBtfHwkWrBjwluwEnQ+l78uwxXYit1zZ2wy4ChGrWfHvNWgefttnoEDbdu8fD29NCLX9jNyCVi5Qc1wCtiRIHSvyAIFnkYjBDpubLIPYcv7sCrnegdgUIYCiOcQ+ReByLLYrQfBnQZqd3TH2Is0IIwTT35wXePl1pWhG5eq4FHlgXYo0mXRqLkkxw9FEYfAX7K3waCkILC2tTz6MWBPxEMQTfr4/bzojd1poLPf7vcVTg5K/8tCLWE4D/KIsyDTtAXfCAVmFGBPdI3CXqo7+odYuO1IA9qxBy17tKyETu5twW0KjXSZd32+7KEbpiIZG6Tva0bkoa/hG5W+/ZjX9I1V0FH+GPpCOiyUd+n+gYg6BavPfE7ScNoroQU+Mlm5ugVBe6WlKVDzdJxZXdpZt89VNoGTkqBh6mwLnMJKqgQBGrmuW+0qh0BQ7WGedp1t15Yjj88t6BKhP95uEaz6WfztkRlnd4T9NCrO4E5D+xdeyDJ63IMGoFl8Zw1wXfOE3oZ+24/XZdnhdy3TjY220sG/AF0hNHTKICV9KDzeaXM7op4/EANL7w3FWjzu1lm2FsB7tk4l0AQPAlRqEnafanyoWvLHbjrzq9/9hB21olgS3CXgv8biQEcgZ+RArT3kkCX4tCD7wNsFF6PCZ5jyR0uQIjT/IzM1cwhAcUUgm5JifaS0Bwd+JjOj7dYVLVIHNHx1ZFZBLQ5I2Z7NXZHQSzinf4NaJCbD7NA+uPg19zJlAQ X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: Fuw/auu2YRulBtf9AEOa1YRaW/8sNugASi3n6ilOq1uA7KhPVIcUpayC2mVCW8xDIvesgaxw44c9LPaALS4NB9hrlSYah5XlDpIlD4Wq/QPq8yah+q3eDMfl2xt+37RY/A3Na2DfYjtoBQ8V+YF1ocjvZ63xVbSYwhfnDn49Rw2SYk3JxYdawWMeEwVjj7ESW37Zfznz2OBO7ZsQeQfU0Cm8xOzbfSnSddY4aip33/qHgMP8xMGvUKWziLVBMJtRkKtpYkKvuOjE9gSStKT4YOItf+aMP8/p+XqUUqoqmWUubJW+k6tJFgsY0tSzGt7E1NNgU+K6ppttt+dG+TU/oPdzt0FXFDulSSaqMpPpDbTv9u7VTt1ZPyoxj7PNeb7XrDWq8FL2YFnszIav8lo0VhCYcQh/pb0LChcn2nY96M6s+Jp3RRyC/1AOv7s/3RWbK3LYoPmS5l1WqWWVrfmFXCpDad7322E4SgugRQaHkove156TQVD4ZToLfjrHbhbgTEzMW8fCfcLdzEQqY9TUBpJj0LVRwtgT5kDbSYOhZxC2VFKV8n0O3Qu5SHQeWKX3Yu+8ID1OKsbet3weWPKXa/Gorvf1xTLY1hbP8hrpsXBWf48WhPbj5kARi5Jmq5Zmllug4W+SFhlo0ah3feRUvzEletGHU4Mh8Ep4fMvkeY5sNkEPBsieaaCnWKIT4KkYxUperHibSNznb4brVxRXt9bNtnyTkSVeJMcXe3f2/2ydXl2aXBQa0w8osFagrS+C X-OriginatorOrg: oracle.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1ba334de-6a04-40cb-da96-08db8d5bcc3e X-MS-Exchange-CrossTenant-AuthSource: MN2PR10MB3213.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jul 2023 22:09:21.4639 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Gkr8xx3YGYR0zaO5xnEe0qo+AzrL682M5yc9C5FtarrIhArNr1TZWCLQP5bxgP8bAdM3XSU7NryDXadHznW3yQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR10MB4512 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_12,2023-07-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 spamscore=0 adultscore=0 suspectscore=0 phishscore=0 malwarescore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250189 X-Proofpoint-ORIG-GUID: SbOS8qiZtFKLUlHo3xmJ_HfuMzxyjw5m X-Proofpoint-GUID: SbOS8qiZtFKLUlHo3xmJ_HfuMzxyjw5m X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: David Faust via Gcc-patches From: David Faust Reply-To: David Faust Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772432169048026465 X-GMAIL-MSGID: 1772432169048026465 This patch adds support for the general atomic operations introduced in eBPF v3. In addition to the existing atomic add instruction, this adds: - Atomic and, or, xor - Fetching versions of these operations (including add) - Atomic exchange - Atomic compare-and-exchange To control emission of these instructions, a new target option -m[no-]v3-atomics is added. This option is enabled by -mcpu=v3 and above. Support for these instructions was recently added in binutils. Tested in bpf-unknown-none. OK? gcc/ * config/bpf/bpf.opt (mv3-atomics): New option. * config/bpf/bpf.cc (bpf_option_override): Handle it here. * config/bpf/bpf.h (enum_reg_class): Add R0 class. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Likewise. (REGNO_REG_CLASS): Handle R0. * config/bpf/bpf.md (UNSPEC_XADD): Rename to UNSPEC_AADD. (UNSPEC_AAND): New unspec. (UNSPEC_AOR): Likewise. (UNSPEC_AXOR): Likewise. (UNSPEC_AFADD): Likewise. (UNSPEC_AFAND): Likewise. (UNSPEC_AFOR): Likewise. (UNSPEC_AFXOR): Likewise. (UNSPEC_AXCHG): Likewise. (UNSPEC_ACMPX): Likewise. (atomic_add): Use UNSPEC_AADD and atomic type attribute. Move to... * config/bpf/atomic.md: ...Here. New file. * config/bpf/constraints.md (t): New constraint for R0. * doc/invoke.texi (eBPF Options): Document -mv3-atomics. gcc/testsuite/ * gcc.target/bpf/atomic-cmpxchg-1.c: New test. * gcc.target/bpf/atomic-cmpxchg-2.c: New test. * gcc.target/bpf/atomic-fetch-op-1.c: New test. * gcc.target/bpf/atomic-fetch-op-2.c: New test. * gcc.target/bpf/atomic-fetch-op-3.c: New test. * gcc.target/bpf/atomic-op-1.c: New test. * gcc.target/bpf/atomic-op-2.c: New test. * gcc.target/bpf/atomic-op-3.c: New test. * gcc.target/bpf/atomic-xchg-1.c: New test. * gcc.target/bpf/atomic-xchg-2.c: New test. --- gcc/config/bpf/atomic.md | 185 ++++++++++++++++++ gcc/config/bpf/bpf.cc | 3 + gcc/config/bpf/bpf.h | 6 +- gcc/config/bpf/bpf.md | 29 ++- gcc/config/bpf/bpf.opt | 4 + gcc/config/bpf/constraints.md | 3 + gcc/doc/invoke.texi | 10 +- .../gcc.target/bpf/atomic-cmpxchg-1.c | 19 ++ .../gcc.target/bpf/atomic-cmpxchg-2.c | 19 ++ .../gcc.target/bpf/atomic-fetch-op-1.c | 50 +++++ .../gcc.target/bpf/atomic-fetch-op-2.c | 50 +++++ .../gcc.target/bpf/atomic-fetch-op-3.c | 49 +++++ gcc/testsuite/gcc.target/bpf/atomic-op-1.c | 49 +++++ gcc/testsuite/gcc.target/bpf/atomic-op-2.c | 49 +++++ gcc/testsuite/gcc.target/bpf/atomic-op-3.c | 49 +++++ gcc/testsuite/gcc.target/bpf/atomic-xchg-1.c | 20 ++ gcc/testsuite/gcc.target/bpf/atomic-xchg-2.c | 20 ++ 17 files changed, 595 insertions(+), 19 deletions(-) create mode 100644 gcc/config/bpf/atomic.md create mode 100644 gcc/testsuite/gcc.target/bpf/atomic-cmpxchg-1.c create mode 100644 gcc/testsuite/gcc.target/bpf/atomic-cmpxchg-2.c create mode 100644 gcc/testsuite/gcc.target/bpf/atomic-fetch-op-1.c create mode 100644 gcc/testsuite/gcc.target/bpf/atomic-fetch-op-2.c create mode 100644 gcc/testsuite/gcc.target/bpf/atomic-fetch-op-3.c create mode 100644 gcc/testsuite/gcc.target/bpf/atomic-op-1.c create mode 100644 gcc/testsuite/gcc.target/bpf/atomic-op-2.c create mode 100644 gcc/testsuite/gcc.target/bpf/atomic-op-3.c create mode 100644 gcc/testsuite/gcc.target/bpf/atomic-xchg-1.c create mode 100644 gcc/testsuite/gcc.target/bpf/atomic-xchg-2.c diff --git a/gcc/config/bpf/atomic.md b/gcc/config/bpf/atomic.md new file mode 100644 index 00000000000..caf8cc15cd4 --- /dev/null +++ b/gcc/config/bpf/atomic.md @@ -0,0 +1,185 @@ +;; Machine description for eBPF. +;; Copyright (C) 2023 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + + +(define_mode_iterator AMO [SI DI]) + +;;; Plain atomic modify operations. + +;; Non-fetching atomic add predates all other BPF atomic insns. +;; Use xadd{w,dw} for compatibility with older GAS without support +;; for v3 atomics. Newer GAS supports "aadd[32]" in line with the +;; other atomic operations. +(define_insn "atomic_add" + [(set (match_operand:AMO 0 "memory_operand" "+m") + (unspec_volatile:AMO + [(plus:AMO (match_dup 0) + (match_operand:AMO 1 "register_operand" "r")) + (match_operand:SI 2 "const_int_operand")] ;; Memory model. + UNSPEC_AADD))] + "" + "{xadd\t%0,%1|lock *( *)(%w0) += %w1}" + [(set_attr "type" "atomic")]) + +(define_insn "atomic_and" + [(set (match_operand:AMO 0 "memory_operand" "+m") + (unspec_volatile:AMO + [(and:AMO (match_dup 0) + (match_operand:AMO 1 "register_operand" "r")) + (match_operand:SI 2 "const_int_operand")] ;; Memory model. + UNSPEC_AAND))] + "bpf_has_v3_atomics" + "{aand\t%0,%1|lock *( *)(%w0) &= %w1}") + +(define_insn "atomic_or" + [(set (match_operand:AMO 0 "memory_operand" "+m") + (unspec_volatile:AMO + [(ior:AMO (match_dup 0) + (match_operand:AMO 1 "register_operand" "r")) + (match_operand:SI 2 "const_int_operand")] ;; Memory model. + UNSPEC_AOR))] + "bpf_has_v3_atomics" + "{aor\t%0,%1|lock *( *)(%w0) %|= %w1}") + +(define_insn "atomic_xor" + [(set (match_operand:AMO 0 "memory_operand" "+m") + (unspec_volatile:AMO + [(xor:AMO (match_dup 0) + (match_operand:AMO 1 "register_operand" "r")) + (match_operand:SI 2 "const_int_operand")] ;; Memory model. + UNSPEC_AXOR))] + "bpf_has_v3_atomics" + "{axor\t%0,%1|lock *( *)(%w0) ^= %w1}") + +;;; Feching (read-modify-store) versions of atomic operations. + +(define_insn "atomic_fetch_add" + [(set (match_operand:AMO 0 "register_operand" "=r") ; output + (match_operand:AMO 1 "memory_operand" "+m")) + (set (match_dup 1) + (unspec_volatile:AMO + [(plus:AMO (match_dup 1) + (match_operand:AMO 2 "nonmemory_operand" "0")) ; second operand to op + (match_operand:AMO 3 "const_int_operand")] ;; Memory model + UNSPEC_AFADD))] + "bpf_has_v3_atomics" + "{afadd\t%1,%0|%w0 = atomic_fetch_add(( *)(%1), %w0)}") + +(define_insn "atomic_fetch_and" + [(set (match_operand:AMO 0 "register_operand" "=r") + (match_operand:AMO 1 "memory_operand" "+m")) + (set (match_dup 1) + (unspec_volatile:AMO + [(and:AMO (match_dup 1) + (match_operand:AMO 2 "nonmemory_operand" "0")) + (match_operand:AMO 3 "const_int_operand")] + UNSPEC_AFAND))] + "bpf_has_v3_atomics" + "{afand\t%1,%0|%w0 = atomic_fetch_and(( *)(%1), %w0)}") + +(define_insn "atomic_fetch_or" + [(set (match_operand:AMO 0 "register_operand" "=r") + (match_operand:AMO 1 "memory_operand" "+m")) + (set (match_dup 1) + (unspec_volatile:AMO + [(ior:AMO (match_dup 1) + (match_operand:AMO 2 "nonmemory_operand" "0")) + (match_operand:AMO 3 "const_int_operand")] + UNSPEC_AFOR))] + "bpf_has_v3_atomics" + "{afor\t%1,%0|%w0 = atomic_fetch_or(( *)(%1), %w0)}") + +(define_insn "atomic_fetch_xor" + [(set (match_operand:AMO 0 "register_operand" "=r") + (match_operand:AMO 1 "memory_operand" "+m")) + (set (match_dup 1) + (unspec_volatile:AMO + [(xor:AMO (match_dup 1) + (match_operand:AMO 2 "nonmemory_operand" "0")) + (match_operand:AMO 3 "const_int_operand")] + UNSPEC_AFXOR))] + "bpf_has_v3_atomics" + "{afxor\t%1,%0|%w0 = atomic_fetch_xor(( *)(%1), %w0)}") + +;; Weird suffixes used in pseudo-c atomic compare-exchange insns. +(define_mode_attr pcaxsuffix [(SI "32_32") (DI "_64")]) + +(define_insn "atomic_exchange" + [(set (match_operand:AMO 0 "register_operand" "=r") + (unspec_volatile:AMO + [(match_operand:AMO 1 "memory_operand" "+m") + (match_operand:AMO 3 "const_int_operand")] + UNSPEC_AXCHG)) + (set (match_dup 1) + (match_operand:AMO 2 "nonmemory_operand" "0"))] + "bpf_has_v3_atomics" + "{axchg\t%1,%0|%w0 = xchg(%1, %w0)}") + +;; The eBPF atomic-compare-and-exchange instruction has the form +;; acmp [%dst+offset], %src +;; The instruction atomically compares the value addressed by %dst+offset +;; with register R0. If they match, the value at %dst+offset is overwritten +;; with the value of %src. Otherwise, no write occurs. In either case, the +;; original value of %dst+offset is zero-extended and loaded back into R0. + +(define_expand "atomic_compare_and_swap" + [(match_operand:SI 0 "register_operand" "=r") ;; bool success + (match_operand:AMO 1 "register_operand" "=r") ;; old value + (match_operand:AMO 2 "memory_operand" "+m") ;; memory + (match_operand:AMO 3 "register_operand") ;; expected + (match_operand:AMO 4 "register_operand") ;; desired + (match_operand:SI 5 "const_int_operand") ;; is_weak (unused) + (match_operand:SI 6 "const_int_operand") ;; success model (unused) + (match_operand:SI 7 "const_int_operand")] ;; failure model (unused) + "bpf_has_v3_atomics" +{ + /* Load the expected value (into R0 by constraint of below). */ + emit_move_insn (operands[1], operands[3]); + + /* Emit the acmp. */ + emit_insn (gen_atomic_compare_and_swap_1 (operands[1], operands[2], operands[3], operands[4])); + + /* Assume that the operation was successful. */ + emit_move_insn (operands[0], const1_rtx); + rtx_code_label *success_label = gen_label_rtx (); + + /* Compare value that was in memory (now in R0/op[1]) to expected value. + If they are equal, then the write occurred. Otherwise, indicate fail in output. */ + emit_cmp_and_jump_insns (operands[1], operands[3], EQ, 0, + GET_MODE (operands[1]), 1, success_label); + emit_move_insn (operands[0], const0_rtx); + + if (success_label) + { + emit_label (success_label); + LABEL_NUSES (success_label) = 1; + } + DONE; +}) + +(define_insn "atomic_compare_and_swap_1" + [(set (match_operand:AMO 0 "register_operand" "+t") ;; R0 is both input (expected value) + (unspec_volatile:AMO ;; and output (original value) + [(match_dup 0) ;; result depends on R0 + (match_operand:AMO 1 "memory_operand") ;; memory + (match_operand:AMO 2 "register_operand") ;; expected + (match_operand:AMO 3 "register_operand")] ;; desired + UNSPEC_ACMP))] + "bpf_has_v3_atomics" + "{acmp\t%1,%3|%w0 = cmpxchg(%1, %w0, %w3)}") diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc index 2c077ea834e..315c6606869 100644 --- a/gcc/config/bpf/bpf.cc +++ b/gcc/config/bpf/bpf.cc @@ -253,6 +253,9 @@ bpf_option_override (void) if (bpf_has_jmp32 == -1) bpf_has_jmp32 = (bpf_isa >= ISA_V3); + if (bpf_has_v3_atomics == -1) + bpf_has_v3_atomics = (bpf_isa >= ISA_V3); + if (bpf_has_bswap == -1) bpf_has_bswap = (bpf_isa >= ISA_V4); diff --git a/gcc/config/bpf/bpf.h b/gcc/config/bpf/bpf.h index 9561bf59b80..ccba7f8b333 100644 --- a/gcc/config/bpf/bpf.h +++ b/gcc/config/bpf/bpf.h @@ -177,6 +177,7 @@ enum reg_class { NO_REGS, /* no registers in set. */ + R0, /* register r0. */ ALL_REGS, /* all registers. */ LIM_REG_CLASSES /* max value + 1. */ }; @@ -190,6 +191,7 @@ enum reg_class #define REG_CLASS_NAMES \ { \ "NO_REGS", \ + "R0", \ "ALL_REGS" \ } @@ -203,6 +205,7 @@ enum reg_class #define REG_CLASS_CONTENTS \ { \ 0x00000000, /* NO_REGS */ \ + 0x00000001, /* R0 */ \ 0x00000fff, /* ALL_REGS */ \ } @@ -210,7 +213,8 @@ enum reg_class register REGNO. In general there is more that one such class; choose a class which is "minimal", meaning that no smaller class also contains the register. */ -#define REGNO_REG_CLASS(REGNO) ((void)(REGNO), GENERAL_REGS) +#define REGNO_REG_CLASS(REGNO) \ + ((REGNO) == 0 ? R0 : GENERAL_REGS) /* A macro whose definition is the name of the class to which a valid base register must belong. A base register is one used in diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md index 579a8213b09..c782e545294 100644 --- a/gcc/config/bpf/bpf.md +++ b/gcc/config/bpf/bpf.md @@ -35,7 +35,16 @@ (define_insn_reservation "frobnicator" 814 (define_c_enum "unspec" [ UNSPEC_LDINDABS - UNSPEC_XADD + UNSPEC_AADD + UNSPEC_AAND + UNSPEC_AOR + UNSPEC_AXOR + UNSPEC_AFADD + UNSPEC_AFAND + UNSPEC_AFOR + UNSPEC_AFXOR + UNSPEC_AXCHG + UNSPEC_ACMP ]) ;;;; Constants @@ -67,11 +76,10 @@ (define_constants ;; st generic store instructions for immediates. ;; stx generic store instructions. ;; jmp jump instructions. -;; xadd atomic exchange-and-add instructions. ;; multi multiword sequence (or user asm statements). (define_attr "type" - "unknown,alu,alu32,end,ld,lddw,ldx,st,stx,jmp,xadd,multi" + "unknown,alu,alu32,end,ld,lddw,ldx,st,stx,jmp,multi,atomic" (const_string "unknown")) ;; Length of instruction in bytes. @@ -548,17 +556,4 @@ (define_insn "ldabs" "{ldabs\t%0|r0 = *( *) skb[%0]}" [(set_attr "type" "ld")]) -;;;; Atomic increments - -(define_mode_iterator AMO [SI DI]) - -(define_insn "atomic_add" - [(set (match_operand:AMO 0 "memory_operand" "+m") - (unspec_volatile:AMO - [(plus:AMO (match_dup 0) - (match_operand:AMO 1 "register_operand" "r")) - (match_operand:SI 2 "const_int_operand")] ;; Memory model. - UNSPEC_XADD))] - "" - "{xadd\t%0,%1|*( *) %0 += %1}" - [(set_attr "type" "xadd")]) +(include "atomic.md") diff --git a/gcc/config/bpf/bpf.opt b/gcc/config/bpf/bpf.opt index bd35f8dbd0c..b21cfcab9ea 100644 --- a/gcc/config/bpf/bpf.opt +++ b/gcc/config/bpf/bpf.opt @@ -59,6 +59,10 @@ mjmp32 Target Var(bpf_has_jmp32) Init(-1) Enable 32-bit jump instructions. +mv3-atomics +Target Var(bpf_has_v3_atomics) Init(-1) +Enable general atomic operations introduced in v3 ISA. + mbswap Target Var(bpf_has_bswap) Init(-1) Enable byte swap instructions. diff --git a/gcc/config/bpf/constraints.md b/gcc/config/bpf/constraints.md index 33f9177b8eb..199dd00c0cb 100644 --- a/gcc/config/bpf/constraints.md +++ b/gcc/config/bpf/constraints.md @@ -30,6 +30,9 @@ (define_constraint "S" "A constant call address." (match_code "const,symbol_ref,label_ref,const_int")) +(define_register_constraint "t" "R0" + "Register r0") + ;; ;; Memory constraints. ;; diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index fa765d5a0dd..9a8057417a3 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -947,7 +947,7 @@ Objective-C and Objective-C++ Dialects}. @emph{eBPF Options} @gccoptlist{-mbig-endian -mlittle-endian -mkernel=@var{version} -mframe-limit=@var{bytes} -mxbpf -mco-re -mno-co-re -mjmpext --mjmp32 -malu32 -mcpu=@var{version} -masm=@var{dialect}} +-mjmp32 -malu32 -mv3-atomics -mcpu=@var{version} -masm=@var{dialect}} @emph{FR30 Options} @gccoptlist{-msmall-model -mno-lsim} @@ -24707,6 +24707,7 @@ Enable 32-bit jump instructions. Enabled for CPU v3 and above. @item -malu32 Enable 32-bit ALU instructions. Enabled for CPU v3 and above. +<<<<<<< HEAD @opindex mbswap @item -mbswap Enable byte swap instructions. Enabled for CPU v4 and above. @@ -24715,6 +24716,12 @@ Enable byte swap instructions. Enabled for CPU v4 and above. @item -msdiv Enable signed division and modulus instructions. Enabled for CPU v4 and above. +======= +@opindex mv3-atomics +@item -mv3-atomics +Enable instructions for general atomic operations introduced in CPU v3. +Enabled for CPU v3 and above. +>>>>>>> 6de76bd11b6 (bpf: add v3 atomic instructions) @opindex mcpu @item -mcpu=@var{version} @@ -24735,6 +24742,7 @@ All features of v2, plus: @itemize @minus @item 32-bit jump operations, as in @option{-mjmp32} @item 32-bit ALU operations, as in @option{-malu32} +@item general atomic operations, as in @option{-mv3-atomics} @end itemize @item v4 diff --git a/gcc/testsuite/gcc.target/bpf/atomic-cmpxchg-1.c b/gcc/testsuite/gcc.target/bpf/atomic-cmpxchg-1.c new file mode 100644 index 00000000000..4bb6a7dba29 --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/atomic-cmpxchg-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-mv3-atomics -O2" } */ + +int +foo (int *p, int *expected, int desired) +{ + return __atomic_compare_exchange (p, expected, &desired, 0, + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); +} + +int +foo64 (long *p, long *expected, long desired) +{ + return __atomic_compare_exchange (p, expected, &desired, 0, + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); +} + +/* { dg-final { scan-assembler "acmp\t.*" } } */ +/* { dg-final { scan-assembler "acmp32\t.*" } } */ diff --git a/gcc/testsuite/gcc.target/bpf/atomic-cmpxchg-2.c b/gcc/testsuite/gcc.target/bpf/atomic-cmpxchg-2.c new file mode 100644 index 00000000000..4036570ac60 --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/atomic-cmpxchg-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-v3-atomics -O2" } */ + +int +foo (int *p, int *expected, int desired) +{ + return __atomic_compare_exchange (p, expected, &desired, 0, + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); +} + +int +foo64 (long *p, long *expected, long desired) +{ + return __atomic_compare_exchange (p, expected, &desired, 0, + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); +} + +/* { dg-final { scan-assembler-not "acmp\t.*" } } */ +/* { dg-final { scan-assembler-not "acmp32\t.*" } } */ diff --git a/gcc/testsuite/gcc.target/bpf/atomic-fetch-op-1.c b/gcc/testsuite/gcc.target/bpf/atomic-fetch-op-1.c new file mode 100644 index 00000000000..533e955fe88 --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/atomic-fetch-op-1.c @@ -0,0 +1,50 @@ +/* Test 64-bit atomic-fetch-op instructions. */ + +/* { dg-do compile } */ +/* { dg-options "-mv3-atomics -O2" } */ + +long val; + +long +test_atomic_fetch_add (long x) +{ + return __atomic_fetch_add (&val, x, __ATOMIC_ACQUIRE); +} + +long +test_atomic_fetch_sub (long x) +{ + return __atomic_fetch_sub (&val, x, __ATOMIC_RELEASE); +} + +long +test_atomic_fetch_and (long x) +{ + return __atomic_fetch_and (&val, x, __ATOMIC_ACQUIRE); +} + +long +test_atomic_fetch_nand (long x) +{ + return __atomic_fetch_nand (&val, x, __ATOMIC_ACQUIRE); +} + +long +test_atomic_fetch_or (long x) +{ + return __atomic_fetch_or (&val, x, __ATOMIC_ACQUIRE); +} + +long +test_atomic_fetch_xor (long x) +{ + return __atomic_fetch_xor (&val, x, __ATOMIC_ACQUIRE); +} + +/* sub implemented in terms of add */ +/* { dg-final { scan-assembler-times "afadd\t" 2 } } */ +/* { dg-final { scan-assembler-times "afand\t" 1 } } */ +/* nand must use a compare-exchange loop */ +/* { dg-final { scan-assembler "acmp\t" } } */ +/* { dg-final { scan-assembler-times "afor\t" 1 } } */ +/* { dg-final { scan-assembler-times "afxor\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/atomic-fetch-op-2.c b/gcc/testsuite/gcc.target/bpf/atomic-fetch-op-2.c new file mode 100644 index 00000000000..6b9ee6348b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/atomic-fetch-op-2.c @@ -0,0 +1,50 @@ +/* Test 32-bit atomic-fetch-op instructions. */ + +/* { dg-do compile } */ +/* { dg-options "-mv3-atomics -O2" } */ + +int val; + +int +test_atomic_fetch_add (int x) +{ + return __atomic_fetch_add (&val, x, __ATOMIC_ACQUIRE); +} + +int +test_atomic_fetch_sub (int x) +{ + return __atomic_fetch_sub (&val, x, __ATOMIC_RELEASE); +} + +int +test_atomic_fetch_and (int x) +{ + return __atomic_fetch_and (&val, x, __ATOMIC_ACQUIRE); +} + +int +test_atomic_fetch_nand (int x) +{ + return __atomic_fetch_nand (&val, x, __ATOMIC_ACQUIRE); +} + +int +test_atomic_fetch_or (int x) +{ + return __atomic_fetch_or (&val, x, __ATOMIC_ACQUIRE); +} + +int +test_atomic_fetch_xor (int x) +{ + return __atomic_fetch_xor (&val, x, __ATOMIC_ACQUIRE); +} + +/* sub implemented in terms of add */ +/* { dg-final { scan-assembler-times "afadd32\t" 2 } } */ +/* { dg-final { scan-assembler-times "afand32\t" 1 } } */ +/* nand must use a compare-exchange loop */ +/* { dg-final { scan-assembler "acmp32\t" } } */ +/* { dg-final { scan-assembler-times "afor32\t" 1 } } */ +/* { dg-final { scan-assembler-times "afxor32\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/atomic-fetch-op-3.c b/gcc/testsuite/gcc.target/bpf/atomic-fetch-op-3.c new file mode 100644 index 00000000000..044a2f76474 --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/atomic-fetch-op-3.c @@ -0,0 +1,49 @@ +/* Test atomic-fetch-op instructions are disabled with -mno-v3-atomics. */ + +/* { dg-do compile } */ +/* { dg-options "-mno-v3-atomics -O2" } */ + +long val; + +long +test_atomic_fetch_add (long x) +{ + return __atomic_fetch_add (&val, x, __ATOMIC_ACQUIRE); +} + +long +test_atomic_fetch_sub (long x) +{ + return __atomic_fetch_sub (&val, x, __ATOMIC_RELEASE); +} + +long +test_atomic_fetch_and (long x) +{ + return __atomic_fetch_and (&val, x, __ATOMIC_ACQUIRE); +} + +long +test_atomic_fetch_nand (long x) +{ + return __atomic_fetch_nand (&val, x, __ATOMIC_ACQUIRE); +} + +long +test_atomic_fetch_or (long x) +{ + return __atomic_fetch_or (&val, x, __ATOMIC_ACQUIRE); +} + +long +test_atomic_fetch_xor (long x) +{ + return __atomic_fetch_xor (&val, x, __ATOMIC_ACQUIRE); +} + +/* { dg-final { scan-assembler-not "afadd\t" } } */ +/* { dg-final { scan-assembler-not "afand\t" } } */ +/* { dg-final { scan-assembler-not "afor\t" } } */ +/* { dg-final { scan-assembler-not "afxor\t" } } */ +/* { dg-final { scan-assembler-not "acmp\t" } } */ +/* { dg-final { scan-assembler-not "axchg\t" } } */ diff --git a/gcc/testsuite/gcc.target/bpf/atomic-op-1.c b/gcc/testsuite/gcc.target/bpf/atomic-op-1.c new file mode 100644 index 00000000000..453c0ed47ce --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/atomic-op-1.c @@ -0,0 +1,49 @@ +/* Test 64-bit non-fetch atomic operations. */ +/* { dg-do compile } */ +/* { dg-options "-mv3-atomics -O2" } */ + +long val; + +void +test_atomic_add (long x) +{ + __atomic_add_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_sub (long x) +{ + __atomic_add_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_and (long x) +{ + __atomic_and_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_nand (long x) +{ + __atomic_nand_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_or (long x) +{ + __atomic_or_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_xor (long x) +{ + __atomic_xor_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +/* sub implemented in terms of add, and we output xadd to support older GAS. */ +/* { dg-final { scan-assembler-times "xadddw\t" 2 } } */ +/* { dg-final { scan-assembler-times "aand\t" 1 } } */ +/* nand must use an exchange loop */ +/* { dg-final { scan-assembler "acmp\t" } } */ +/* { dg-final { scan-assembler-times "aor\t" 1 } } */ +/* { dg-final { scan-assembler-times "axor\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/atomic-op-2.c b/gcc/testsuite/gcc.target/bpf/atomic-op-2.c new file mode 100644 index 00000000000..daacf42c00b --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/atomic-op-2.c @@ -0,0 +1,49 @@ +/* Test 32-bit non-fetch atomic operations. */ +/* { dg-do compile } */ +/* { dg-options "-mv3-atomics -O2" } */ + +int val; + +void +test_atomic_add (int x) +{ + __atomic_add_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_sub (int x) +{ + __atomic_add_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_and (int x) +{ + __atomic_and_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_nand (int x) +{ + __atomic_nand_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_or (int x) +{ + __atomic_or_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_xor (int x) +{ + __atomic_xor_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +/* sub implemented in terms of add, and we output xadd to support older GAS. */ +/* { dg-final { scan-assembler-times "xaddw\t" 2 } } */ +/* { dg-final { scan-assembler-times "aand32\t" 1 } } */ +/* nand must use an exchange loop */ +/* { dg-final { scan-assembler "acmp32\t" } } */ +/* { dg-final { scan-assembler-times "aor32\t" 1 } } */ +/* { dg-final { scan-assembler-times "axor32\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/atomic-op-3.c b/gcc/testsuite/gcc.target/bpf/atomic-op-3.c new file mode 100644 index 00000000000..b2ce2892634 --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/atomic-op-3.c @@ -0,0 +1,49 @@ +/* Test that atomic insns are properly disabled with -mno-v3-atomics. */ +/* { dg-do compile } */ +/* { dg-options "-mno-v3-atomics -O2" } */ + +int val; + +void +test_atomic_add (int x) +{ + __atomic_add_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_sub (int x) +{ + __atomic_add_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_and (int x) +{ + __atomic_and_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_nand (int x) +{ + __atomic_nand_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_or (int x) +{ + __atomic_or_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +void +test_atomic_xor (int x) +{ + __atomic_xor_fetch (&val, x, __ATOMIC_ACQUIRE); +} + +/* Without v3 atomics, only xadd{w,dw} is available. */ +/* { dg-final { scan-assembler-not "aadd" } } */ +/* { dg-final { scan-assembler-not "aand" } } */ +/* { dg-final { scan-assembler-not "aor" } } */ +/* { dg-final { scan-assembler-not "axor" } } */ +/* { dg-final { scan-assembler-not "axchg" } } */ +/* { dg-final { scan-assembler-not "acmp" } } */ diff --git a/gcc/testsuite/gcc.target/bpf/atomic-xchg-1.c b/gcc/testsuite/gcc.target/bpf/atomic-xchg-1.c new file mode 100644 index 00000000000..bab806393df --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/atomic-xchg-1.c @@ -0,0 +1,20 @@ +/* Test atomic exchange instruction. */ +/* { dg-do compile } */ +/* { dg-options "-mv3-atomics -O2" } */ + +int foo (int *p, int *new) +{ + int old; + __atomic_exchange (p, new, &old, __ATOMIC_RELAXED); + return old; +} + +int foo64 (long *p, long *new) +{ + long old; + __atomic_exchange (p, new, &old, __ATOMIC_SEQ_CST); + return old; +} + +/* { dg-final { scan-assembler-times "axchg\t.*" 1 } } */ +/* { dg-final { scan-assembler-times "axchg32\t.*" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/atomic-xchg-2.c b/gcc/testsuite/gcc.target/bpf/atomic-xchg-2.c new file mode 100644 index 00000000000..3b6324e966b --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/atomic-xchg-2.c @@ -0,0 +1,20 @@ +/* Test atomic exchange instruction is disabled with -mno-v3-atomics. */ +/* { dg-do compile } */ +/* { dg-options "-mno-v3-atomics -O2" } */ + +int foo (int *p, int *new) +{ + int old; + __atomic_exchange (p, new, &old, __ATOMIC_RELAXED); + return old; +} + +int foo64 (long *p, long *new) +{ + long old; + __atomic_exchange (p, new, &old, __ATOMIC_SEQ_CST); + return old; +} + +/* { dg-final { scan-assembler-not "axchg\t.*" } } */ +/* { dg-final { scan-assembler-not "axchg32\t.*" } } */