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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id l24-20020a62be18000000b0064f7c56d8b7sm9121132pff.219.2023.07.25.02.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 02:40:40 -0700 (PDT) From: Jacky Huang To: a.zummo@towertech.it, alexandre.belloni@bootlin.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, soc@kernel.org, mjchen@nuvoton.com, schung@nuvoton.com, Jacky Huang Subject: [PATCH v2 1/3] dt-bindings: rtc: Add Nuvoton ma35d1 rtc Date: Tue, 25 Jul 2023 09:40:28 +0000 Message-Id: <20230725094030.32877-2-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230725094030.32877-1-ychuang570808@gmail.com> References: <20230725094030.32877-1-ychuang570808@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772386343811387772 X-GMAIL-MSGID: 1772386343811387772 From: Jacky Huang Add documentation describing the Nuvoton ma35d1 rtc controller. Signed-off-by: Jacky Huang Reviewed-by: Krzysztof Kozlowski --- .../bindings/rtc/nuvoton,ma35d1-rtc.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/nuvoton,ma35d1-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/nuvoton,ma35d1-rtc.yaml b/Documentation/devicetree/bindings/rtc/nuvoton,ma35d1-rtc.yaml new file mode 100644 index 000000000000..5e4ade803eed --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nuvoton,ma35d1-rtc.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nuvoton,ma35d1-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Real Time Clock + +maintainers: + - Min-Jen Chen + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + enum: + - nuvoton,ma35d1-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + rtc@40410000 { + compatible = "nuvoton,ma35d1-rtc"; + reg = <0x40410000 0x200>; + interrupts = ; + clocks = <&clk RTC_GATE>; + }; + +... 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id l24-20020a62be18000000b0064f7c56d8b7sm9121132pff.219.2023.07.25.02.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 02:40:42 -0700 (PDT) From: Jacky Huang To: a.zummo@towertech.it, alexandre.belloni@bootlin.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, soc@kernel.org, mjchen@nuvoton.com, schung@nuvoton.com, Jacky Huang Subject: [PATCH v2 2/3] arm64: dts: nuvoton: Add rtc for ma35d1 Date: Tue, 25 Jul 2023 09:40:29 +0000 Message-Id: <20230725094030.32877-3-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230725094030.32877-1-ychuang570808@gmail.com> References: <20230725094030.32877-1-ychuang570808@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772389455478369222 X-GMAIL-MSGID: 1772389455478369222 From: Jacky Huang Add rtc controller support to the dtsi of ma35d1 SoC and enable rtc on SOM and IoT boards. Signed-off-by: Jacky Huang --- arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts | 4 ++++ arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts | 4 ++++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 8 ++++++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts index b89e2be6abae..b3be4331abcf 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -54,3 +54,7 @@ &clk { "integer", "integer"; }; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts index a1ebddecb7f8..9858788a589c 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -54,3 +54,7 @@ &clk { "integer", "integer"; }; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi index 781cdae566a0..394395bfd3ae 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -95,6 +95,14 @@ clk: clock-controller@40460200 { clocks = <&clk_hxt>; }; + rtc: rtc@40410000 { + compatible = "nuvoton,ma35d1-rtc"; + reg = <0x0 0x40410000 0x0 0x200>; + interrupts = ; + clocks = <&clk RTC_GATE>; + status = "disabled"; + }; + uart0: serial@40700000 { compatible = "nuvoton,ma35d1-uart"; reg = <0x0 0x40700000 0x0 0x100>; From patchwork Tue Jul 25 09:40:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 125510 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2382093vqg; Tue, 25 Jul 2023 03:52:24 -0700 (PDT) X-Google-Smtp-Source: APBJJlG9JMljINwPsAErMC7jsTe89cSAH940X37ZLB6aM0TvnLrbac7yO9w1wA1BMsMTYccITMpe X-Received: by 2002:a17:902:e5c5:b0:1b9:c205:a876 with SMTP id u5-20020a170902e5c500b001b9c205a876mr14929922plf.29.1690282344292; Tue, 25 Jul 2023 03:52:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690282344; cv=none; d=google.com; s=arc-20160816; b=cvDcqoxTmoWtO4KgA67REZrLkkqGyP5T83ZUlLRkFSP1oV8uMN3o0wXmDp5G0cqBtG CBZr0Cy8pBONiGzW87JLrEx5Cs7tvdYoxY1CzZv5KPCsbAAJhdEhsUvVUJW0eB2JBF43 iErwkdSwLrFt5HbA5KlS4IQ82KRrU7Hpun9BC0me6YRkhF2t5ae9aIUQIF5hBdjeB9RB ielRe1rUn7BY1R8cj+PMyGAM0Eu3Vaqr4/a/uE4TKPfbSFOT3Z/9ba8JFUczNcwlrZgG Bo2XdloHtxFHvBKz/bu3Gu8JqlIuznobHzP5Os7UBmVNOm6pruwrkG7kvbR5kkGMWc3z dXMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nPNCweX+5ma/GkGVGkz+d+I063Vnz2ba+24+RFVQOm8=; fh=CuOU2zHMRvKBIxU3VBdQp/xZQgB1IU6H7AgQjHd0CZ4=; b=snh6leM/Y4yb5gIcwlvmi41f0haRAq+k0+mSU37f4IvNRDZAsrHreAkBp9kN3hHGxX F7biBaljGH12YW2GvMgbWIUZAKuFGGjqjtLCV4VF8gWqQbEJqVdhWUKQkclHtx5X57NW UQDaiH7RWEoqo1eHqPKZalXtpvhVcO4E7EqwOemd2pPWbfWHfJEvNvaovPYRLJ1w73oe 3ObBSquHgCBq8Y5Bt1R4+K0SaOKxTnUyVv25iz1urVr/ozkNndu/rcvQDgKq7EX7a9+N p5GF2YHO6ZHisT2HmzhQAloMUGV5J3Qm2dulD/SnpbIKjFDTAJ2I2BRCYUxSAweMG9uu XwLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b="gsjUAjA/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id l24-20020a62be18000000b0064f7c56d8b7sm9121132pff.219.2023.07.25.02.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 02:40:44 -0700 (PDT) From: Jacky Huang To: a.zummo@towertech.it, alexandre.belloni@bootlin.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, soc@kernel.org, mjchen@nuvoton.com, schung@nuvoton.com, Jacky Huang Subject: [PATCH v2 3/3] rtc: Add driver for Nuvoton ma35d1 rtc controller Date: Tue, 25 Jul 2023 09:40:30 +0000 Message-Id: <20230725094030.32877-4-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230725094030.32877-1-ychuang570808@gmail.com> References: <20230725094030.32877-1-ychuang570808@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772389499602007985 X-GMAIL-MSGID: 1772389499602007985 From: Jacky Huang The ma35d1 rtc controller provides real-time and calendar messaging capabilities. It supports programmable time tick and alarm match interrupts. The time and calendar messages are expressed in BCD format. This driver supports the built-in rtc controller of the ma35d1. It enables setting and reading the rtc time and configuring and reading the rtc alarm. Signed-off-by: Jacky Huang --- drivers/rtc/Kconfig | 11 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-ma35d1.c | 355 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 367 insertions(+) create mode 100644 drivers/rtc/rtc-ma35d1.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 05f4b2d66290..95ddd8f616f4 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1929,6 +1929,17 @@ config RTC_DRV_TI_K3 This driver can also be built as a module, if so, the module will be called "rtc-ti-k3". +config RTC_DRV_MA35D1 + tristate "Nuvoton MA35D1 RTC" + depends on ARCH_MA35 || COMPILE_TEST + select REGMAP_MMIO + help + If you say yes here you get support for the Nuvoton MA35D1 + On-Chip Real Time Clock. + + This driver can also be built as a module, if so, the module + will be called "rtc-ma35d1". + comment "HID Sensor RTC drivers" config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index fd209883ee2e..763c9cb5dde1 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -88,6 +88,7 @@ obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o +obj-$(CONFIG_RTC_DRV_MA35D1) += rtc-ma35d1.o obj-$(CONFIG_RTC_DRV_MAX6900) += rtc-max6900.o obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o obj-$(CONFIG_RTC_DRV_MAX6916) += rtc-max6916.o diff --git a/drivers/rtc/rtc-ma35d1.c b/drivers/rtc/rtc-ma35d1.c new file mode 100644 index 000000000000..f63b484ee37f --- /dev/null +++ b/drivers/rtc/rtc-ma35d1.c @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RTC driver for Nuvoton MA35D1 + * + * Copyright (C) 2023 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* MA35D1 RTC Control Registers */ +#define MA35_REG_RTC_INIT 0x00 +#define MA35_REG_RTC_SINFASTS 0x04 +#define MA35_REG_RTC_FREQADJ 0x08 +#define MA35_REG_RTC_TIME 0x0c +#define MA35_REG_RTC_CAL 0x10 +#define MA35_REG_RTC_CLKFMT 0x14 +#define MA35_REG_RTC_WEEKDAY 0x18 +#define MA35_REG_RTC_TALM 0x1c +#define MA35_REG_RTC_CALM 0x20 +#define MA35_REG_RTC_LEAPYEAR 0x24 +#define MA35_REG_RTC_INTEN 0x28 +#define MA35_REG_RTC_INTSTS 0x2c +#define MA35_REG_RTC_TICK 0x30 + +/* register MA35_REG_RTC_INIT */ +#define RTC_INIT_ACTIVE BIT(0) +#define RTC_INIT_MAGIC_CODE 0xa5eb1357 + +/* register MA35_REG_RTC_CLKFMT */ +#define RTC_CLKFMT_24HEN BIT(0) +#define RTC_CLKFMT_DCOMPEN BIT(16) + +/* register MA35_REG_RTC_INTEN */ +#define RTC_INTEN_ALMIEN BIT(0) +#define RTC_INTEN_TICKIEN BIT(1) +#define RTC_INTEN_CLKFIEN BIT(24) +#define RTC_INTEN_CLKSTIEN BIT(25) + +/* register MA35_REG_RTC_INTSTS */ +#define RTC_INTSTS_ALMIF BIT(0) +#define RTC_INTSTS_TICKIF BIT(1) +#define RTC_INTSTS_CLKFIF BIT(24) +#define RTC_INTSTS_CLKSTIF BIT(25) + +#define RTC_INIT_TIMEOUT 250 + +struct ma35_rtc { + int irq_num; + void __iomem *rtc_reg; + struct rtc_device *rtcdev; +}; + +struct ma35_bcd_time { + int bcd_sec; + int bcd_min; + int bcd_hour; + int bcd_mday; + int bcd_mon; + int bcd_year; +}; + +static u32 rtc_reg_read(struct ma35_rtc *p, u32 offset) +{ + return __raw_readl(p->rtc_reg + offset); +} + +static inline void rtc_reg_write(struct ma35_rtc *p, u32 offset, u32 value) +{ + __raw_writel(value, p->rtc_reg + offset); +} + +static irqreturn_t ma35d1_rtc_interrupt(int irq, void *data) +{ + struct ma35_rtc *rtc = (struct ma35_rtc *)data; + unsigned long events = 0, rtc_irq; + + rtc_irq = rtc_reg_read(rtc, MA35_REG_RTC_INTSTS); + + if (rtc_irq & RTC_INTSTS_ALMIF) { + rtc_reg_write(rtc, MA35_REG_RTC_INTSTS, RTC_INTSTS_ALMIF); + events |= RTC_AF | RTC_IRQF; + } + + if (rtc_irq & RTC_INTSTS_TICKIF) { + rtc_reg_write(rtc, MA35_REG_RTC_INTSTS, RTC_INTSTS_TICKIF); + events |= RTC_UF | RTC_IRQF; + } + + rtc_update_irq(rtc->rtcdev, 1, events); + + return IRQ_HANDLED; +} + +static int ma35d1_rtc_init(struct ma35_rtc *rtc, u32 ms_timeout) +{ + const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); + + do { + if (rtc_reg_read(rtc, MA35_REG_RTC_INIT) & RTC_INIT_ACTIVE) + return 0; + + rtc_reg_write(rtc, MA35_REG_RTC_INIT, RTC_INIT_MAGIC_CODE); + + mdelay(1); + + } while (time_before(jiffies, timeout)); + + return -ETIMEDOUT; +} + +static int ma35d1_rtc_bcd2bin(u32 time, u32 cal, u32 wday, struct rtc_time *tm) +{ + tm->tm_mday = bcd2bin(cal >> 0); + tm->tm_mon = bcd2bin(cal >> 8); + tm->tm_mon = tm->tm_mon - 1; + tm->tm_year = bcd2bin(cal >> 16) + 100; + + tm->tm_sec = bcd2bin(time >> 0); + tm->tm_min = bcd2bin(time >> 8); + tm->tm_hour = bcd2bin(time >> 16); + + tm->tm_wday = wday; + + return rtc_valid_tm(tm); +} + +static int ma35d1_rtc_alarm_bcd2bin(u32 talm, u32 calm, struct rtc_time *tm) +{ + tm->tm_mday = bcd2bin(calm >> 0); + tm->tm_mon = bcd2bin(calm >> 8); + tm->tm_mon = tm->tm_mon - 1; + tm->tm_year = bcd2bin(calm >> 16) + 100; + + tm->tm_sec = bcd2bin(talm >> 0); + tm->tm_min = bcd2bin(talm >> 8); + tm->tm_hour = bcd2bin(talm >> 16); + + return rtc_valid_tm(tm); +} + +static void ma35d1_rtc_bin2bcd(struct device *dev, struct rtc_time *settm, + struct ma35_bcd_time *gettm) +{ + gettm->bcd_mday = bin2bcd(settm->tm_mday) << 0; + gettm->bcd_mon = bin2bcd((settm->tm_mon + 1)) << 8; + + if (settm->tm_year < 100) { + dev_warn(dev, "The year will be between 1970-1999, right?\n"); + gettm->bcd_year = bin2bcd(settm->tm_year) << 16; + } else { + gettm->bcd_year = bin2bcd(settm->tm_year - 100) << 16; + } + + gettm->bcd_sec = bin2bcd(settm->tm_sec) << 0; + gettm->bcd_min = bin2bcd(settm->tm_min) << 8; + gettm->bcd_hour = bin2bcd(settm->tm_hour) << 16; +} + +static int ma35d1_alarm_irq_enable(struct device *dev, u32 enabled) +{ + struct ma35_rtc *rtc = dev_get_drvdata(dev); + u32 reg_ien; + + reg_ien = rtc_reg_read(rtc, MA35_REG_RTC_INTEN); + + if (enabled) + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, reg_ien | RTC_INTEN_ALMIEN); + else + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, reg_ien & ~RTC_INTEN_ALMIEN); + + return 0; +} + +static int ma35d1_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct ma35_rtc *rtc = dev_get_drvdata(dev); + u32 time, cal, wday; + + time = rtc_reg_read(rtc, MA35_REG_RTC_TIME); + cal = rtc_reg_read(rtc, MA35_REG_RTC_CAL); + wday = rtc_reg_read(rtc, MA35_REG_RTC_WEEKDAY); + + return ma35d1_rtc_bcd2bin(time, cal, wday, tm); +} + +static int ma35d1_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct ma35_rtc *rtc = dev_get_drvdata(dev); + struct ma35_bcd_time gettm; + u32 val; + + ma35d1_rtc_bin2bcd(dev, tm, &gettm); + + val = gettm.bcd_mday | gettm.bcd_mon | gettm.bcd_year; + rtc_reg_write(rtc, MA35_REG_RTC_CAL, val); + + val = gettm.bcd_sec | gettm.bcd_min | gettm.bcd_hour; + rtc_reg_write(rtc, MA35_REG_RTC_TIME, val); + + val = tm->tm_wday; + rtc_reg_write(rtc, MA35_REG_RTC_WEEKDAY, val); + + return 0; +} + +static int ma35d1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct ma35_rtc *rtc = dev_get_drvdata(dev); + u32 talm, calm; + + talm = rtc_reg_read(rtc, MA35_REG_RTC_TALM); + calm = rtc_reg_read(rtc, MA35_REG_RTC_CALM); + + return ma35d1_rtc_alarm_bcd2bin(talm, calm, &alrm->time); +} + +static int ma35d1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct ma35_rtc *rtc = dev_get_drvdata(dev); + struct ma35_bcd_time tm; + unsigned long val; + + ma35d1_rtc_bin2bcd(dev, &alrm->time, &tm); + + val = tm.bcd_mday | tm.bcd_mon | tm.bcd_year; + rtc_reg_write(rtc, MA35_REG_RTC_CALM, val); + + val = tm.bcd_sec | tm.bcd_min | tm.bcd_hour; + rtc_reg_write(rtc, MA35_REG_RTC_TALM, val); + + return 0; +} + +static const struct rtc_class_ops ma35d1_rtc_ops = { + .read_time = ma35d1_rtc_read_time, + .set_time = ma35d1_rtc_set_time, + .read_alarm = ma35d1_rtc_read_alarm, + .set_alarm = ma35d1_rtc_set_alarm, + .alarm_irq_enable = ma35d1_alarm_irq_enable, +}; + +static int ma35d1_rtc_probe(struct platform_device *pdev) +{ + struct ma35_rtc *rtc; + struct clk *clk; + u32 regval; + int err; + + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + + rtc->rtc_reg = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rtc->rtc_reg)) + return PTR_ERR(rtc->rtc_reg); + + clk = of_clk_get(pdev->dev.of_node, 0); + if (IS_ERR(clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk), "failed to find rtc clock\n"); + + err = clk_prepare_enable(clk); + if (err) + return -ENOENT; + + platform_set_drvdata(pdev, rtc); + + rtc->rtcdev = devm_rtc_device_register(&pdev->dev, pdev->name, + &ma35d1_rtc_ops, THIS_MODULE); + if (IS_ERR(rtc->rtcdev)) + return dev_err_probe(&pdev->dev, PTR_ERR(rtc->rtcdev), + "failed to register rtc device\n"); + + err = ma35d1_rtc_init(rtc, RTC_INIT_TIMEOUT); + if (err) + return err; + + regval = rtc_reg_read(rtc, MA35_REG_RTC_CLKFMT); + regval |= RTC_CLKFMT_24HEN; + rtc_reg_write(rtc, MA35_REG_RTC_CLKFMT, regval); + + rtc->irq_num = platform_get_irq(pdev, 0); + + err = devm_request_irq(&pdev->dev, rtc->irq_num, ma35d1_rtc_interrupt, + IRQF_NO_SUSPEND, "ma35d1rtc", rtc); + if (err) + return dev_err_probe(&pdev->dev, err, "Failed to request rtc irq\n"); + + regval = rtc_reg_read(rtc, MA35_REG_RTC_INTEN); + regval |= RTC_INTEN_TICKIEN; + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, regval); + + device_init_wakeup(&pdev->dev, true); + + return 0; +} + +static int ma35d1_rtc_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct ma35_rtc *rtc = platform_get_drvdata(pdev); + u32 regval; + + if (device_may_wakeup(&pdev->dev)) + enable_irq_wake(rtc->irq_num); + + regval = rtc_reg_read(rtc, MA35_REG_RTC_INTEN); + regval &= ~RTC_INTEN_TICKIEN; + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, regval); + + return 0; +} + +static int ma35d1_rtc_resume(struct platform_device *pdev) +{ + struct ma35_rtc *rtc = platform_get_drvdata(pdev); + u32 regval; + + if (device_may_wakeup(&pdev->dev)) + disable_irq_wake(rtc->irq_num); + + regval = rtc_reg_read(rtc, MA35_REG_RTC_INTEN); + regval |= RTC_INTEN_TICKIEN; + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, regval); + + return 0; +} + +static const struct of_device_id ma35d1_rtc_of_match[] = { + { .compatible = "nuvoton,ma35d1-rtc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ma35d1_rtc_of_match); + +static struct platform_driver ma35d1_rtc_driver = { + .suspend = ma35d1_rtc_suspend, + .resume = ma35d1_rtc_resume, + .probe = ma35d1_rtc_probe, + .driver = { + .name = "rtc-ma35d1", + .of_match_table = ma35d1_rtc_of_match, + }, +}; + +module_platform_driver(ma35d1_rtc_driver); + +MODULE_AUTHOR("Min-Jen Chen "); +MODULE_DESCRIPTION("MA35D1 RTC driver"); +MODULE_LICENSE("GPL");