From patchwork Tue Jul 25 07:15:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125369 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2296374vqg; Tue, 25 Jul 2023 00:29:53 -0700 (PDT) X-Google-Smtp-Source: APBJJlGJiNt2Z3odibKm6A9nUM7vmfQAtgh3KvBjdz+Pe6s/1FjucIBNGVy/440FlvH6lm597Ysa X-Received: by 2002:a05:6512:31d4:b0:4fb:f2d5:467f with SMTP id j20-20020a05651231d400b004fbf2d5467fmr7750696lfe.13.1690270192884; Tue, 25 Jul 2023 00:29:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690270192; cv=none; d=google.com; s=arc-20160816; b=jS9MP+Sgm4xlqiFBBzLIstTJKo7PNueCwAewFX2NvA9fST0iZwjm43b6hHWGDnZ5hU /fY5v6RpIzU4RtFJjJ5Xw5uGAPTOH+FdN1DVR18Crji7rlHb6NaeNPHaxHdVog32gB1a V+Sk1JYRqS4e5sSEyn9I+cSE/yoXSpxByhx3Wk4TSCaJcdUXralyFfqA59+PUzB9u6+F ZstH9ncTMRU3PFUQ0TX1F1JLlCMmDWZoFNgptRvpkgTgNUGMsB12vcmLQ6U48XfbqtZa HNNOtd1GEcazj58WjHQKvfyJsGlBQQm1Fdfp+ZQkoo7XG6tsSytVPQrqzKPML2uHSaUY gvDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=2+FYJqvd8KPGLBxHJyZuzJMgY6Vqc6U1VDQqXT1I4S0=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=FiIwjJx6nmitgxsVA6iFnq9AYwad3HwaQr2g5xk/KzaGNw1zWIjnBOi4YTW/RAXZYl 93DTx8njjZdZp1slusZJtor9jMH+vI6z6zO1O0TC9MIYBnOjb58eCnY76d5t51ijvARy exANIKnqTPXr4T3CWeU1Z1+yX7nJ0dRsxSYZEDWP44gh3FMoZ4o9U36GqSrnQoDTdCsh cm9MM531fzCJywWxtZq/vINLN1q3AVbF0k66kUGj85QCy9UGPj/KmuNknzg6TtAe0iYc 43hcnyLqHqpeVxCSN7HKNP85nw9QlInWk4goKuh1qHui5MPwl+UXUTsuGDazH5GDHPnn uwfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kN0t4tz0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m17-20020a056402051100b0051e02696179si7683667edv.388.2023.07.25.00.29.26; Tue, 25 Jul 2023 00:29:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kN0t4tz0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232359AbjGYHQm (ORCPT + 99 others); Tue, 25 Jul 2023 03:16:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232298AbjGYHQh (ORCPT ); Tue, 25 Jul 2023 03:16:37 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30D0B10C8; Tue, 25 Jul 2023 00:16:33 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P1RqKu020562; Tue, 25 Jul 2023 07:16:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=2+FYJqvd8KPGLBxHJyZuzJMgY6Vqc6U1VDQqXT1I4S0=; b=kN0t4tz0f06Movn8p08l+EPygFNk4MKdKJjflGK2NM1C+rQ7ZoPieA2tZnDLneLyjSUb MPxUG20izW71iMMe9wBez6+ilecfY+Od2Mn9B4RlrUwrnxpDPcgIuMGHHxVUo80/8s54 eXeYxRsHAOOuhlnTjT8j188l1qorUpFr2yOQCf6IaYQgEx5s+e51kxmMFdx7n7SSRitp jBfAmrcscWRk9Tqm4WzorQGEVPixhFADE7vThAcKUFPq70GOF8iN/jJxF7yb4r57+W6s YOyMH/nMX1h0A1huwdzXsnkXDLYDAiEbbljDMrC5v8x/LzkPUPsC44Q7p/A4haTs7Jzv 1w== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1y6m14cw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:21 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7GJfD028958 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:19 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:16:14 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 01/13] coresight-tpdm: Remove the unnecessary lock Date: Tue, 25 Jul 2023 15:15:41 +0800 Message-ID: <1690269353-10829-2-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fiZYnpDHU25wf9xyX6sfq_aXB4TpL58b X-Proofpoint-ORIG-GUID: fiZYnpDHU25wf9xyX6sfq_aXB4TpL58b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 mlxlogscore=999 bulkscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772376757964505834 X-GMAIL-MSGID: 1772376757964505834 Remove the unnecessary lock "CS_{UN,}LOCK" in TPDM driver. This lock is only needed while writing the data to Coresight registers. Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-tpdm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index f4854af..b645612 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -114,11 +114,9 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) { u32 pidr; - CS_UNLOCK(drvdata->base); /* Get the datasets present on the TPDM. */ pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0); - CS_LOCK(drvdata->base); } /* From patchwork Tue Jul 25 07:15:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125389 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2303085vqg; Tue, 25 Jul 2023 00:46:44 -0700 (PDT) X-Google-Smtp-Source: APBJJlFW4+LJHiN33YSqb0WI7qnUPIuF9ikmWt2TpjIQOFSSM+jx4sVb2k4LxhcvTpDKQzcW5bx7 X-Received: by 2002:a05:6a00:1398:b0:662:f0d0:a77d with SMTP id t24-20020a056a00139800b00662f0d0a77dmr8493537pfg.30.1690271204129; Tue, 25 Jul 2023 00:46:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690271204; cv=none; d=google.com; s=arc-20160816; b=lUITgGXVprNFn6mLi59WMNYGh2amg/XF6lqT396PaFRLa4iFzP6zC2nGW1sZgu1CLH Kb6X3r26wroUm2D9I0/EugSWGxrDP/Sih/nhVAbMbZVJyAllsn4dxJnkExPprxnRoONU WiaINCn9PDwEYmk7Z7QZnDgaC5bi4D60PUm6CRthmn4P78EFYpr1iGONFLji3s7F/Z+S qkqXr3fVtPZGnt8smepN8rvwhTah/q7IU8gEnh/eaTXLNj54xTIBp+faCmfs3snwUoLu H9VsKUo47npwjj8rgQ6c3D1GIOtpLqFDjB2Rhz87o2v5+PwaBnjWRXVASwGK3cHGERnM vCPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=8/LtmSNb13yMzYwKyLuH7zr+LVetrEKVS5tC1j6X0xU=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=LgjVUo/TApgaH/Eq/8A2jy32PuCfCAC0JB6sUKt513ph3+epQ5OfTbAbM9Q29i9MM/ D1z5MgOurlfI0GOCp3voTam/Rt1jibg0nN9xImfptmgn2JzS3RX32QCX/Q5KZwzDCdLT bcTEyC8aqUwwG0Q6s0AOpWnVM9YU7+QuVLfYn1aqiCVZbkcqgT6WweAsy/r9A+Eox6g5 ym5v7gtXRbv3+DrP1DW8gELck0uYFvtzn3IeQWbg37TCAcCUXIWYWazTRkJMNq4cZYZr OoTfvvZXK5RV0B7akV56ZEDPU4+DUiHYOPjCnoUtOCBWjFI1tLetW50jDMQvNHG/Nth5 MuzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZmdQcdu+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j10-20020a634a4a000000b005533f27a25csi10311920pgl.511.2023.07.25.00.46.30; Tue, 25 Jul 2023 00:46:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZmdQcdu+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232387AbjGYHQz (ORCPT + 99 others); Tue, 25 Jul 2023 03:16:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232340AbjGYHQi (ORCPT ); Tue, 25 Jul 2023 03:16:38 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3840BD; Tue, 25 Jul 2023 00:16:35 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P7205W031496; Tue, 25 Jul 2023 07:16:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=8/LtmSNb13yMzYwKyLuH7zr+LVetrEKVS5tC1j6X0xU=; b=ZmdQcdu+sJVUFo5xAAOLUwl4zvqmBZEQnsi2qcXWYrHUOFrWh8uCLd0Q/Jl4Vavmo6zT VkvVESvAkSjJDkObHe1RJx07/mtmvYWcs3vQwaeikZyUlTHSO9w0WQePlzeaanablz5R TCv5FZVit0mdWj14Z/rFqZg9kEhuQ/vT82M7VyUw8CvFCVse5jxjePTP9ZYS5PpzwF0Q +Sg7XW2UPqpXWTEDCjOTCulrqq98vFjX6N45MTadQn8EAu076F/eo+IDH8n21rM+YxV9 oKnCY/xBabm5Sy0EbVwlUtcfR4uDlWDstNHJLFBL1EZEkiE9c+2bHwN1+lyWYWX7aXeo ow== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s29j5g15j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:25 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7GOwB030033 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:24 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:16:19 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 02/13] dt-bindings: arm: Add support for DSB element size Date: Tue, 25 Jul 2023 15:15:42 +0800 Message-ID: <1690269353-10829-3-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GaVr98-aGZ0lEarl6km_aROLn6X5N5Mp X-Proofpoint-GUID: GaVr98-aGZ0lEarl6km_aROLn6X5N5Mp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 adultscore=0 malwarescore=0 mlxlogscore=927 phishscore=0 clxscore=1015 mlxscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772377818106520483 X-GMAIL-MSGID: 1772377818106520483 Add property "qcom,dsb-elem-size" to support DSB(Discrete Single Bit) element for TPDM. The associated aggregator will read this size before it is enabled. DSB element size currently only supports 32-bit and 64-bit. Signed-off-by: Tao Zhang Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 5c08342..931ee8f 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -44,6 +44,14 @@ properties: minItems: 1 maxItems: 2 + qcom,dsb-element-size: + description: + Specifies the DSB(Discrete Single Bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. DSB element size currently only supports 32-bit and 64-bit. + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [32, 64] + clocks: maxItems: 1 @@ -77,6 +85,8 @@ examples: compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0684c000 0x1000>; + qcom,dsb-element-size = /bits/ 8 <32>; + clocks = <&aoss_qmp>; clock-names = "apb_pclk"; From patchwork Tue Jul 25 07:15:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125363 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2295526vqg; Tue, 25 Jul 2023 00:27:35 -0700 (PDT) X-Google-Smtp-Source: APBJJlHi4KpjkAxbkECifH3yoYqAEOCSFxgAXozVYOoWP0U2DSciA/SGZEwDTiyIwLuDbFNSQaTd X-Received: by 2002:a17:906:7783:b0:994:1eb4:6896 with SMTP id s3-20020a170906778300b009941eb46896mr2071470ejm.25.1690270054078; Tue, 25 Jul 2023 00:27:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690270054; cv=none; d=google.com; s=arc-20160816; b=RlJ2wi9d1lScEUNRr3hXm4QiarBNb/z8xvTw/dzMeP0/83NcIP+LrXKIMg9eQj0WtM BbjHb/iFHUReHWDbQG8r8jA43YwOkGC7BmnKtXvXdipjRWvd2HZg6O3KKLT+ap30L9UB coWlT2jaZV9m7Ho8OUYlmx3jcECUeq1qJVNxO90dQT1NZo+vZLA7gKpRQVsflSYq9NYo GXibjaRmLQD6BxeeFtH6ZmQD5+p30pAe+kV2U5K6Ippxx9TUs2ZZ0beGXCrA73tFrON8 baOLyyl9UVTqF0gz/t+GSQjXfRrvTLvS7yupSUVwR0Av4X0s9wBxTp/M25hJMI4O0kWO YzhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=0PBaaLPc8DhxM4/1AHSr/Qr6PTykK4JIoRGApIYQw/w=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=xHPhkv3n56tdlFdJtbEdx5Msdrnpy0K101kMru3cvVQA2iNKrNbQFr/WLjWrWXwaSm JctAg+5T+kYW3JWs7pj5eDZjnF7dlVyEA3eQY958dDr2mJG/KmV/ZVkZcOXnC/HKJgYw 83uprHFjeODRnb2Pd7plPMgURD4B/b9L35QEkKo2N3STFNURQ6LjwNYtR/7ruLKZ3ZrL TlgQuMtdyzEGU/ZsNbxA78PRi+hn5/DBA9GLlHEWYvviTbaDP6VBTPdz3hVYn4Sqrcpk xakx+Lp3Yq4mhrq/njmi1RDW1tGxXoKHLW5rmFIXglX4EyzyF03NLkZAtTUp27DzYZeA wAiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=iwqNqt4x; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ko20-20020a170907987400b009930e13a56fsi7025933ejc.346.2023.07.25.00.27.09; Tue, 25 Jul 2023 00:27:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=iwqNqt4x; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232447AbjGYHRS (ORCPT + 99 others); Tue, 25 Jul 2023 03:17:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232298AbjGYHRD (ORCPT ); Tue, 25 Jul 2023 03:17:03 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 309571BD2; Tue, 25 Jul 2023 00:16:46 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P5Hl4O022184; Tue, 25 Jul 2023 07:16:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=0PBaaLPc8DhxM4/1AHSr/Qr6PTykK4JIoRGApIYQw/w=; b=iwqNqt4xlfpuB52C6mVyQ53roTPraoQd1gLN9OAn8o9yhP85/e7Rn2LE5DC8jxvpy37i xKzTeVm8uRgiMRgCIENGPNa0mm9CUWjduzhTjX4DaLtEp4NYT1KWRNgVfuyVCUMT1riY 29+EbmiCw+qwdpfJbpnhEsyRg3IOgvl8zeOqB1JSHu6L9Gm/IIsqKjqN1GWwQY0Mmulv /SF12MoXUdKJeHBhORruRkT+ypuTtsRmz5b/Fif2LA2ffe80/2eWDbU0HsjwqagKW2Rq qsbjft8zo1SQE+msJKL9BPmrwNhV3fHN7U2oaikuEg1XgofsmsW8wSXkVGDL+bf+pThb sQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1sr720hg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:31 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7GUwR029445 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:30 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:16:24 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 03/13] coresight-tpdm: Introduce TPDM subtype to TPDM driver Date: Tue, 25 Jul 2023 15:15:43 +0800 Message-ID: <1690269353-10829-4-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LEZncrFHrWIu1SrfchGynz-03tzOYpWe X-Proofpoint-ORIG-GUID: LEZncrFHrWIu1SrfchGynz-03tzOYpWe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 mlxscore=0 clxscore=1011 spamscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=930 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772376612049471898 X-GMAIL-MSGID: 1772376612049471898 Introduce the new subtype of "CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM" for TPDM components in driver. Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-tpdm.c | 2 +- include/linux/coresight.h | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 118fcf2..a8c52aa 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1093,6 +1093,7 @@ static int coresight_validate_source(struct coresight_device *csdev, if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC && subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE && + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM && subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS) { dev_err(&csdev->dev, "wrong device subtype in %s\n", function); return -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index b645612..abaff0b 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -203,7 +203,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) if (!desc.name) return -ENOMEM; desc.type = CORESIGHT_DEV_TYPE_SOURCE; - desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS; + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM; desc.ops = &tpdm_cs_ops; desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index bf70987..dc19a44 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -62,6 +62,7 @@ enum coresight_dev_subtype_source { CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, + CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM, CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, }; From patchwork Tue Jul 25 07:15:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125397 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2310094vqg; Tue, 25 Jul 2023 01:03:02 -0700 (PDT) X-Google-Smtp-Source: APBJJlGZgscpzE6m6a5o0fj8kiZkmO4kjtj0HE+b+bVIyqVpyTrjo3frmFRbOl4az7b1rcZysj9k X-Received: by 2002:a05:6402:1355:b0:51e:22dd:5e90 with SMTP id y21-20020a056402135500b0051e22dd5e90mr9971265edw.4.1690272182564; Tue, 25 Jul 2023 01:03:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690272182; cv=none; d=google.com; s=arc-20160816; b=mQuxiEj38QaRtmj6vshOU2z+9LeHy/RPzGbgryQGzRSnKDpajL1ZEpjh8XHTPGMhIS SjEwLChzIX7w+xrhw30NCU+JRDVQs/rCR7Dt3hL+BFgCdfkP/jsZlMM5V47mI+zy5d5O efCeJPFDU4KpFKb1CC5AGsXrUS5OYVwAGcCjgotz0Rp7DC1L9kN2THKxfA5MhyTV9qD0 t7O+R4E5o/TbsRCaaAT4YCpuurshr7EIC3xDWe4sI3DUjMkmbuPnKT95EblOETsR1Fgv 60dT4qW3P1iGOwDwG+SITzWW/8VNxPE/DYZrgxu9AKTNYp4wohQEMoUY29K7FoiWLt2S qmnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+BKdWwEWwdwCoPZPNCBpNs8qGJS3GBIA2guIKe9oTqs=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=0flEMQTu9o/vMrAE8jqsrBqcuHuVblx15/LTFnD0A1xSqf31q+8xsSJKAwTZORD5ZO +OjpDfuX2T0DGQ7JCqjo7FOPgDtiRPgtZShMuXMfkrNWJkJDHojzZfEeJv+InvVBrvza YJgoJwj+OPVTyOz3dmhjm/A2UyXHtx6voPqiTE53L9NWMTatNM+fTjquI7wZHDe8TH1b KA937UR7zRL0Z5YbjWd/O+rRE7Owpx6b33me2Qo9m7dEzLPP9di78b5jO+4szD+iRKev xEfFbKE6GSLPyCLwXcqejvYR7Sun/ObSclv5ST0PPiYYPfDMxpBKGhbUb2LnNI25fIHA djJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=IYYqln+B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p1-20020a056402074100b0051debfa935asi7977124edy.141.2023.07.25.01.02.38; Tue, 25 Jul 2023 01:03:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=IYYqln+B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232474AbjGYHR2 (ORCPT + 99 others); Tue, 25 Jul 2023 03:17:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232410AbjGYHRK (ORCPT ); Tue, 25 Jul 2023 03:17:10 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 515581FC6; Tue, 25 Jul 2023 00:16:49 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P6Mc1N000308; Tue, 25 Jul 2023 07:16:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=+BKdWwEWwdwCoPZPNCBpNs8qGJS3GBIA2guIKe9oTqs=; b=IYYqln+BfP+4VaJJIaHyYuErTmd9dQdoH1vuo0qTr3Qq3k/ismWGa2RG9wHO1TIph/z9 HJUElKQGySd8JBCinuq8RazxL284YmZ+zAInnUtLy9SV0KjLtp4X5hZbwQMePi5O+V5I LyXoz20oYPSAfgsF+prAZR9Neo9GHOmBgurGHX2lD/K7B4DhgDm0/Wa9cs7C58C3D075 6rb0pjJrSJEch6CeRsB6D2jwuGVHO1TnMCOXbSsb74YoUWH0YGgutLPDRwvxCZlUiAbF Br+t7vGOuAH2AgHvhSXDbiAPTGtuISQaDblWJ6fRsvKcouaU4Jw+ejYyNv5JNZj+aX/i uA== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1r4va79j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:36 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7GZtA014023 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:35 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:16:29 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 04/13] coresight-tpda: Add DSB dataset support Date: Tue, 25 Jul 2023 15:15:44 +0800 Message-ID: <1690269353-10829-5-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VDmtFyusUZEES9ZKUEIM8k85Z7b_6bQf X-Proofpoint-ORIG-GUID: VDmtFyusUZEES9ZKUEIM8k85Z7b_6bQf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 bulkscore=0 mlxscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772378844116132558 X-GMAIL-MSGID: 1772378844116132558 Read the DSB element size from the device tree. Set the register bit that controls the DSB element size of the corresponding port. Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-tpda.c | 96 +++++++++++++++++++++++++--- drivers/hwtracing/coresight/coresight-tpda.h | 4 ++ 2 files changed, 90 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 8d2b9d2..7c71342 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -21,6 +21,58 @@ DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda"); +/* Search and read element data size from the TPDM node in + * the devicetree. Each input port of TPDA is connected to + * a TPDM. Different TPDM supports different types of dataset, + * and some may support more than one type of dataset. + * Parameter "inport" is used to pass in the input port number + * of TPDA, and it is set to 0 in the recursize call. + * Parameter "parent" is used to pass in the original call. + */ +static int tpda_set_element_size(struct tpda_drvdata *drvdata, + struct coresight_device *csdev, int inport, bool match_inport) +{ + static int nr_inport; + int i; + static bool tpdm_found; + struct coresight_device *in_csdev; + + if (inport > (TPDA_MAX_INPORTS - 1)) + return -EINVAL; + + if (match_inport) { + nr_inport = inport; + tpdm_found = false; + } + + for (i = 0; i < csdev->pdata->nr_inconns; i++) { + in_csdev = csdev->pdata->in_conns[i]->src_dev; + if (!in_csdev) + break; + + if (match_inport) + if (csdev->pdata->in_conns[i]->dest_port != inport) + continue; + + if ((in_csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && + (in_csdev->subtype.source_subtype + == CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM)) { + of_property_read_u8(in_csdev->dev.parent->of_node, + "qcom,dsb-element-size", &drvdata->dsb_esize[nr_inport]); + if (!tpdm_found) + tpdm_found = true; + else + dev_warn(drvdata->dev, + "More than one TPDM is mapped to the TPDA input port %d.\n", + nr_inport); + continue; + } + tpda_set_element_size(drvdata, in_csdev, 0, false); + } + + return 0; +} + /* Settings pre enabling port control register */ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) { @@ -32,26 +84,43 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDA_CR); } -static void tpda_enable_port(struct tpda_drvdata *drvdata, int port) +static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) { u32 val; val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + /* + * Configure aggregator port n DSB data set element size + * Set the bit to 0 if the size is 32 + * Set the bit to 1 if the size is 64 + */ + if (drvdata->dsb_esize[port] == 32) + val &= ~TPDA_Pn_CR_DSBSIZE; + else if (drvdata->dsb_esize[port] == 64) + val |= TPDA_Pn_CR_DSBSIZE; + else + return -EINVAL; + /* Enable the port */ val |= TPDA_Pn_CR_ENA; writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); + + return 0; } -static void __tpda_enable(struct tpda_drvdata *drvdata, int port) +static int __tpda_enable(struct tpda_drvdata *drvdata, int port) { + int ret; + CS_UNLOCK(drvdata->base); if (!drvdata->csdev->enable) tpda_enable_pre_port(drvdata); - tpda_enable_port(drvdata, port); - + ret = tpda_enable_port(drvdata, port); CS_LOCK(drvdata->base); + + return ret; } static int tpda_enable(struct coresight_device *csdev, @@ -59,16 +128,23 @@ static int tpda_enable(struct coresight_device *csdev, struct coresight_connection *out) { struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; + + ret = tpda_set_element_size(drvdata, csdev, in->dest_port, true); + if (ret) + return ret; spin_lock(&drvdata->spinlock); - if (atomic_read(&in->dest_refcnt) == 0) - __tpda_enable(drvdata, in->dest_port); + if (atomic_read(&in->dest_refcnt) == 0) { + ret = __tpda_enable(drvdata, in->dest_port); + if (!ret) { + atomic_inc(&in->dest_refcnt); + dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", in->dest_port); + } + } - atomic_inc(&in->dest_refcnt); spin_unlock(&drvdata->spinlock); - - dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", in->dest_port); - return 0; + return ret; } static void __tpda_disable(struct tpda_drvdata *drvdata, int port) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index 0399678..12a1472 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,8 @@ #define TPDA_Pn_CR(n) (0x004 + (n * 4)) /* Aggregator port enable bit */ #define TPDA_Pn_CR_ENA BIT(0) +/* Aggregator port DSB data set element size bit */ +#define TPDA_Pn_CR_DSBSIZE BIT(8) #define TPDA_MAX_INPORTS 32 @@ -23,6 +25,7 @@ * @csdev: component vitals needed by the framework. * @spinlock: lock for the drvdata value. * @enable: enable status of the component. + * @dsb_esize: DSB element size for each inport, it must be 32 or 64. */ struct tpda_drvdata { void __iomem *base; @@ -30,6 +33,7 @@ struct tpda_drvdata { struct coresight_device *csdev; spinlock_t spinlock; u8 atid; + u8 dsb_esize[TPDA_MAX_INPORTS]; }; #endif /* _CORESIGHT_CORESIGHT_TPDA_H */ From patchwork Tue Jul 25 07:15:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125395 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2307071vqg; Tue, 25 Jul 2023 00:57:16 -0700 (PDT) X-Google-Smtp-Source: APBJJlHLy/9vLus2MbUu7OrcaJQmcFLkS7L7knX0Psav9QLy2iE2OU4M24z8TRNg6LvQmZf4G9Gw X-Received: by 2002:a17:907:7784:b0:982:2278:bcef with SMTP id ky4-20020a170907778400b009822278bcefmr11452652ejc.60.1690271836416; Tue, 25 Jul 2023 00:57:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690271836; cv=none; d=google.com; s=arc-20160816; b=uievghFTWg4ebM08x0EsnHh+U1UlOMJc0JW8OCEw2E9gGcuVA+5se1YtE2UMGpxAMZ aX9mqe8xHcs8z5hvT4wxIa2r1fveOPQE1TFF6UMAC91erB2iIUvENvzuuyON2+77cuXg CgH3EY0EWntsqxUwULHWTSCd6CtVe1PE+Nc0gfO2b1NY1LTVzCujsf3FoGyqfE0mR69f 5kBki2zJHz5tCJ4wRxe0dIol13MIstEgNgztkZ4DLe9M8v7Mj1dct7ghiRzA8mTIVURc WN6ONkDH72DJzoZbSyrFtWgfXJ80oPKh8XK0aWy417mkxrxyen3anOi+2G3loKdnyNZE DsaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KNIc+nUsv7BYGi6SdukXxKYIE0hi4LqHfnO0XWDU1Ds=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=NOvLm+q4P7eibcJv6nmCLB0X1JvqKvkcNVULFs1zm3azEiqmcrCEU6UMIE/owAKHxE QqNwKqo1Ay337ZaOGIubHKQgJFAUvQMC5ES1W9Xe5FIHM79pKg6P4mPDRmxg4/9ci4SF /8HuaQk3tnOJBTt+mpDK8RA4JrJ38f6jPQpSYfv3b7xnROaDxRAMOxBk0kYMSO4BZrfG r5WGX0WulA7UF3p9zmpGCjJWYwl0ayjdktVQy93oMvkSOpUJnZyMrf5MBD5LpVG6oOWs WqMfONskB1bBTNadz/TgmTNGk22hMHT3alZqYqtQAFgiBGOiWGneRDxlB4Dv4nU4xlNx PZ9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZP2OlDWO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i17-20020a1709063c5100b00988a75603f5si7702812ejg.235.2023.07.25.00.56.52; Tue, 25 Jul 2023 00:57:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZP2OlDWO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232491AbjGYHRx (ORCPT + 99 others); Tue, 25 Jul 2023 03:17:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232442AbjGYHRS (ORCPT ); Tue, 25 Jul 2023 03:17:18 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 118251FFE; Tue, 25 Jul 2023 00:16:52 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P5sbV7015557; Tue, 25 Jul 2023 07:16:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=KNIc+nUsv7BYGi6SdukXxKYIE0hi4LqHfnO0XWDU1Ds=; b=ZP2OlDWOvbkWlZ2bd/zRNo+VEI46X/2RBAQO3kT2q15JiHiIgD0DRry/YJ62IcVyTwZX AM4N8KzVwtUyfmTu37sX/l3RBoeo5UxBF340h/as3BGYxu1b2Huj/8f6P8VEN8921KkR d+1Fg3IDvbn7efeX4/K1BIU6nBL60LLWie1KGmSyfNYIO65L8t/8an888TqdPS9gaiaz gnlZmRw9WXndnpmtmYvzJS7PS8gYsNHooQMJgftATIGLlFxGZB50igq6HXqX7XB4IO3U oSvpN6bqWG73QQqUsUooSxBxVya8Gp6TjYZYOASXiP1C5z3I4H8zVqX4nzmFBWnFPGQ7 5g== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1sr720hs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:41 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7Gdaj004679 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:39 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:16:34 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 05/13] coresight-tpdm: Initialize DSB subunit configuration Date: Tue, 25 Jul 2023 15:15:45 +0800 Message-ID: <1690269353-10829-6-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: yUdpcXf1YBKe1b1g6bl60T2vfobIbd-g X-Proofpoint-ORIG-GUID: yUdpcXf1YBKe1b1g6bl60T2vfobIbd-g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 mlxscore=0 clxscore=1015 spamscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772378481094638180 X-GMAIL-MSGID: 1772378481094638180 DSB is used for monitoring “events”. Events are something that occurs at some point in time. It could be a state decode, the act of writing/reading a particular address, a FIFO being empty, etc. This decoding of the event desired is done outside TPDM. DSB subunit need to be configured in enablement and disablement. A struct that specifics associated to dsb dataset is needed. It saves the configuration and parameters of the dsb datasets. This change is to add this struct and initialize the configuration of DSB subunit. Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-tpdm.c | 55 ++++++++++++++++++++++++++-- drivers/hwtracing/coresight/coresight-tpdm.h | 18 +++++++++ 2 files changed, 69 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index abaff0b..52aa48a6 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,17 +20,46 @@ DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); +static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) +{ + if (drvdata->datasets & TPDM_PIDR0_DS_DSB) { + memset(drvdata->dsb, 0, sizeof(struct dsb_dataset)); + + drvdata->dsb->trig_ts = true; + drvdata->dsb->trig_type = false; + } +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val; - /* Set the enable bit of DSB control register to 1 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); + /* Set trigger timestamp */ + if (drvdata->dsb->trig_ts) + val |= TPDM_DSB_TIER_XTRIG_TSENAB; + else + val &= ~TPDM_DSB_TIER_XTRIG_TSENAB; + writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + /* Set trigger type */ + if (drvdata->dsb->trig_type) + val |= TPDM_DSB_CR_TRIG_TYPE; + else + val &= ~TPDM_DSB_CR_TRIG_TYPE; + /* Set the enable bit of DSB control register to 1 */ val |= TPDM_DSB_CR_ENA; writel_relaxed(val, drvdata->base + TPDM_DSB_CR); } -/* TPDM enable operations */ +/* TPDM enable operations + * The TPDM or Monitor serves as data collection component for various + * dataset types. It covers Basic Counts(BC), Tenure Counts(TC), + * Continuous Multi-Bit(CMB), Multi-lane CMB(MCMB) and Discrete Single + * Bit(DSB). This function will initialize the configuration according + * to the dataset type supported by the TPDM. + */ static void __tpdm_enable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base); @@ -110,13 +139,24 @@ static const struct coresight_ops tpdm_cs_ops = { .source_ops = &tpdm_source_ops, }; -static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) +static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) { u32 pidr; /* Get the datasets present on the TPDM. */ pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0); + + if (drvdata->datasets & TPDM_PIDR0_DS_DSB) { + if (!drvdata->dsb) { + drvdata->dsb = devm_kzalloc(drvdata->dev, + sizeof(*drvdata->dsb), GFP_KERNEL); + if (!drvdata->dsb) + return -ENOMEM; + } + } + + return 0; } /* @@ -179,6 +219,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) struct coresight_platform_data *pdata; struct tpdm_drvdata *drvdata; struct coresight_desc desc = { 0 }; + int ret; pdata = coresight_get_platform_data(dev); if (IS_ERR(pdata)) @@ -198,6 +239,12 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) drvdata->base = base; + ret = tpdm_datasets_setup(drvdata); + if (ret) + return ret; + + tpdm_reset_datasets(drvdata); + /* Set up coresight component description */ desc.name = coresight_alloc_device_name(&tpdm_devs, dev); if (!desc.name) @@ -214,7 +261,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(drvdata->csdev); spin_lock_init(&drvdata->spinlock); - tpdm_init_default_data(drvdata); + /* Decrease pm refcount when probe is done.*/ pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 5438540..92c34cd 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -11,8 +11,14 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) +#define TPDM_DSB_TIER (0x784) + /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) +/* Enable bit for DSB subunit trigger type */ +#define TPDM_DSB_CR_TRIG_TYPE BIT(12) +/* Enable bit for DSB subunit trigger timestamp */ +#define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1) /* TPDM integration test registers */ #define TPDM_ITATBCNTRL (0xEF0) @@ -41,6 +47,16 @@ #define TPDM_PIDR0_DS_DSB BIT(1) /** + * struct dsb_dataset - specifics associated to dsb dataset + * @trig_ts: Enable/Disable trigger timestamp. + * @trig_type: Enable/Disable trigger type. + */ +struct dsb_dataset { + bool trig_ts; + bool trig_type; +}; + +/** * struct tpdm_drvdata - specifics associated to an TPDM component * @base: memory mapped base address for this component. * @dev: The device entity associated to this component. @@ -48,6 +64,7 @@ * @spinlock: lock for the drvdata value. * @enable: enable status of the component. * @datasets: The datasets types present of the TPDM. + * @dsb Specifics associated to an TPDM component. */ struct tpdm_drvdata { @@ -57,6 +74,7 @@ struct tpdm_drvdata { spinlock_t spinlock; bool enable; unsigned long datasets; + struct dsb_dataset *dsb; }; #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ From patchwork Tue Jul 25 07:15:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125405 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2316481vqg; Tue, 25 Jul 2023 01:16:58 -0700 (PDT) X-Google-Smtp-Source: APBJJlHOWMEEghFN9R91LbgOTjEKp3c8c7Otw4s67myuYfpsf8IPpkdMNcfXfico+NtkMI0noloE X-Received: by 2002:a05:6512:44c:b0:4f4:dbcc:54da with SMTP id y12-20020a056512044c00b004f4dbcc54damr5695811lfk.27.1690273018179; Tue, 25 Jul 2023 01:16:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690273018; cv=none; d=google.com; s=arc-20160816; b=aNAv7iinp2hgvWv/LisJPqsG9kqg5dCfrAHw+nXk27NcfRV3fn1nSjXYnBVXiYrODC gxjA2ZciOVcdDziFBSdJHDOIqCJ9R+I4MPTPE+WMSMqrnQZhgVlV6hBhnVMPIfawvEpW 92KzMw02EUGVyO6Reu6EZjqSbbHTxzt4Ah0IXIRNNJ/smww6HcG0qyx3o5DrvC27ztM1 i5tBmXMHwrFJT9yKPiWlXumelGTuOimbFn0psMa+ei5TwyqZKTXw7ZxUthbOBmlMe1ZR YltQBKdDV+tj6TxpaNRq0Ytfod+POuFRGvOBaOF/SxtI5LBQlFuQ1dUtGKvsFSYGnT7Q Gynw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=jcfc3+ZNk7jCww8lgKXjJoKyRBJfleFcPzEVl0RBPvo=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=e6U1Cx58EiIVjbGcFfRp6E/RLWmHj9p4cwEK5ybV5x+0ZRRrsVGTTK00OsoBDd6oCy LwXpeJ5796hNzfwji6Uxs4QhKsmnNyTVluws4/+4AllJc06Ra3AQEJzxqCHLco9YDTtA ISuPhCDjtZftZHBHP3VKMas7YQyyCe7uwpp/60r5x2UPQNeC7vLJYPGbQ3iXjzGzGT6J FS3ziQp1QnNFa4MzVMnFGEdKfDUFjs3ld+YsuY2GStXYuc62l4ohEG92TdE0H9NSJ3Rn ZQEf5cwW+s7ZjLn+9dHfdYN2/kiSrW8hRKLU6g04uiz+e9jA6R33S6n9RVOq4K98cBSZ BRrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=IOUm47Wq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i11-20020a50fc0b000000b0051e252568besi7489236edr.662.2023.07.25.01.16.34; Tue, 25 Jul 2023 01:16:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=IOUm47Wq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232408AbjGYHSP (ORCPT + 99 others); Tue, 25 Jul 2023 03:18:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232409AbjGYHR1 (ORCPT ); Tue, 25 Jul 2023 03:17:27 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DA1C212D; Tue, 25 Jul 2023 00:16:57 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P4tgM1017364; Tue, 25 Jul 2023 07:16:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=jcfc3+ZNk7jCww8lgKXjJoKyRBJfleFcPzEVl0RBPvo=; b=IOUm47Wq1PsWkYEWY/3N5iGf+uIxNEFPUcsEasXftvlOOOSEhVKH3tmutIxupvDVeBjH auyDBqPJFnPwTxf1T5EnqMxP3O5LxSCYo813UBidY4mGbTAB1qjmwYt5IAuMxOMh1mbL Ox+T1byn71Pc2nGcGXv/aK3C1UVK+mz1uowdodwlaFs//Vdkulq8CIKTbQh04XKFa3nj p7U6CKXvuiKI7k/4hHbFuOWmGoggNgeoBzDtb2l+49f39Kl7VK7xUpjoE50GedrtOIrK avPX3MAYCVVun6vhmgMpH1wNg/XTSby8+CIeokTY/2yBsJYke/nmMXmo4hovaoZ/Dqpb KQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1r4va79s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:45 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7GiGG029540 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:44 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:16:39 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 06/13] coresight-tpdm: Add reset node to TPDM node Date: Tue, 25 Jul 2023 15:15:46 +0800 Message-ID: <1690269353-10829-7-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: kIkKwuHzQ8oygTk2IDYdsJUuh0YdftLH X-Proofpoint-ORIG-GUID: kIkKwuHzQ8oygTk2IDYdsJUuh0YdftLH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 bulkscore=0 mlxscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772379720138861841 X-GMAIL-MSGID: 1772379720138861841 TPDM device need a node to reset the configurations and status of it. This change provides a node to reset the configurations and disable the TPDM if it has been enabled. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 10 ++++++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 22 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 4a58e64..dbc2fbd0 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -11,3 +11,13 @@ Description: Accepts only one of the 2 values - 1 or 2. 1 : Generate 64 bits data 2 : Generate 32 bits data + +What: /sys/bus/coresight/devices//reset +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Reset the dataset of the tpdm, and disable the tpdm. + + Accepts only one value - 1. + 1 : Reset the dataset of the tpdm diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 52aa48a6..acc3eea 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -159,6 +159,27 @@ static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) return 0; } +static ssize_t reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int ret = 0; + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 10, &val); + if (ret || val != 1) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + tpdm_reset_datasets(drvdata); + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_WO(reset); + /* * value 1: 64 bits test data * value 2: 32 bits test data @@ -199,6 +220,7 @@ static ssize_t integration_test_store(struct device *dev, static DEVICE_ATTR_WO(integration_test); static struct attribute *tpdm_attrs[] = { + &dev_attr_reset.attr, &dev_attr_integration_test.attr, NULL, }; From patchwork Tue Jul 25 07:15:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125359 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2295468vqg; Tue, 25 Jul 2023 00:27:27 -0700 (PDT) X-Google-Smtp-Source: APBJJlEubChlP5/4pHZrThzsRxq/k8NYkZVeL4i+vKCliP8t70FJ4YKKrIqZM7r/o7WN1iItU30d X-Received: by 2002:a17:906:3009:b0:992:91ce:4509 with SMTP id 9-20020a170906300900b0099291ce4509mr10323711ejz.57.1690270047697; Tue, 25 Jul 2023 00:27:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690270047; cv=none; d=google.com; s=arc-20160816; b=sTmdONynanGpwLsC9d21MkBEba/SbQ76x8t7OdZda8Br+iOKAHFsObMtOAetTPVdNi biKZXYRjsSG6eqYnP75nY6k0hD4Dj0pyRKBYHOZM5lmIg0UxbhNSOuaNvxt9peWbAfPE VZXsfrV7HJBkl3gpLQARYqSVDodANjntSNp7E6dQPJZ/CRs6Ln+BTrFk5WQ3B3GOMh9P EGGB+InEXrQVkTjOSlOi2wvP/EIAFoXKO+rKB41dC+BQ2S/KdIjQBkPpRs6xIvd35eQg dc8/YuPUoXo1XTjr/Fd7NOD7fH8HUbdZRcNgR9I0tn0lYXSL9vOb5YcamxrHOBHeAylu ziog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=DfyZCmPJgINc2vFaG8QlV7pWGi3oWtmNllEgbtOpkTY=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=NTIPrEjsoK0cR0HiponkuNW1hdYDcv9UC3icEcSODKx57+c3bsXaBhSI/Nypoz6T9D C9nMToIWnS7bgD5/aOwb+UL6b7H6z4+n6gSi7e41VXuXaIaCF3Y8O0BdPlR8qqEMWpvM UD34o/xFeohx42hqgUZ5CTkdpfi7DYn92T/DkeH8RDA9ahDije3OQPbUdM1iOESqBEay 4MxzGz2l1Lwi6+o/gFv84Hehekh9CQkCEYKqY3vc4ZJcpwe3hhdh06/HlHFTPXPbzJHi Hy9MgtfvwxoZ461D00aAdKI+9BBCf6z66G454aIjUx4GoEwD97Tipv3DlDg5sS6zWnKw 9tRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=B+3L3Xju; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s16-20020a170906061000b0099b49300b6asi7964972ejb.158.2023.07.25.00.27.02; Tue, 25 Jul 2023 00:27:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=B+3L3Xju; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232516AbjGYHTD (ORCPT + 99 others); Tue, 25 Jul 2023 03:19:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232462AbjGYHSb (ORCPT ); Tue, 25 Jul 2023 03:18:31 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F60D199F; Tue, 25 Jul 2023 00:17:10 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P5OIZ7030901; Tue, 25 Jul 2023 07:16:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=DfyZCmPJgINc2vFaG8QlV7pWGi3oWtmNllEgbtOpkTY=; b=B+3L3Xju49sCyOFKqFNVDUvVBJ94evDU49uiBq76o868mRvM7HdfazpMxUtf5MsrmTK+ 7wKr0M4cOOKuGyzzAFrPYGrhWhCrgvJoxFjrMiRtxZqiJO6iHNJ3Bqe4hTSCToGYwxZl FaK6lmwjqhEnoVhZIJAZlHyou+v272Pdee3wvhqUrnzCLda4zRtGrz7Lwm9JWSy6BENi ovNcsBBnbm3WK4TcFT4i+6snIGJopFDrRFre9OFeHXmlpV6GcodAgE2E4D3uUKj41GiB n7PkcKfKSjp2xNz0U/lE0q7fG3wEULKJ2eEyV9/PcwnruiKVU71w89YpLtIaiqO9GIPm 4w== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1qasta8p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:57 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7GoWn032112 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:50 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:16:44 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 07/13] coresight-tpdm: Add nodes to set trigger timestamp and type Date: Tue, 25 Jul 2023 15:15:47 +0800 Message-ID: <1690269353-10829-8-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 3E-ucNzOpxBpjPSviRlM8g3fZqjTrMAc X-Proofpoint-GUID: 3E-ucNzOpxBpjPSviRlM8g3fZqjTrMAc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 clxscore=1015 spamscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772376605252329175 X-GMAIL-MSGID: 1772376605252329175 The nodes are needed to set or show the trigger timestamp and trigger type. This change is to add these nodes to achieve these function. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 24 ++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 94 ++++++++++++++++++++++ 2 files changed, 118 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index dbc2fbd0..0b7b4ad 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -21,3 +21,27 @@ Description: Accepts only one value - 1. 1 : Reset the dataset of the tpdm + +What: /sys/bus/coresight/devices//dsb_trig_type +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the trigger type of DSB tpdm. Read the trigger + type of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB trigger type to false + 1 : Set the DSB trigger type to true + +What: /sys/bus/coresight/devices//dsb_trig_ts +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the trigger timestamp of DSB tpdm. Read the + trigger timestamp of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB trigger type to false + 1 : Set the DSB trigger type to true diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index acc3eea..62efc18 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,6 +20,18 @@ DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); +static umode_t tpdm_dsb_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (drvdata && (drvdata->datasets & TPDM_PIDR0_DS_DSB)) + return attr->mode; + + return 0; +} + static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (drvdata->datasets & TPDM_PIDR0_DS_DSB) { @@ -229,8 +241,90 @@ static struct attribute_group tpdm_attr_grp = { .attrs = tpdm_attrs, }; +static ssize_t dsb_trig_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->trig_type); +} + +/* + * Trigger type (boolean): + * false - Disable trigger type. + * true - Enable trigger type. + */ +static ssize_t dsb_trig_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->dsb->trig_type = true; + else + drvdata->dsb->trig_type = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_type); + +static ssize_t dsb_trig_ts_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->trig_ts); +} + +/* + * Trigger timestamp (boolean): + * false - Disable trigger timestamp. + * true - Enable trigger timestamp. + */ +static ssize_t dsb_trig_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->dsb->trig_ts = true; + else + drvdata->dsb->trig_ts = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_ts); + +static struct attribute *tpdm_dsb_attrs[] = { + &dev_attr_dsb_trig_ts.attr, + &dev_attr_dsb_trig_type.attr, + NULL, +}; + +static struct attribute_group tpdm_dsb_attr_grp = { + .attrs = tpdm_dsb_attrs, + .is_visible = tpdm_dsb_is_visible, +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, + &tpdm_dsb_attr_grp, NULL, }; From patchwork Tue Jul 25 07:15:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125374 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2297169vqg; Tue, 25 Jul 2023 00:31:40 -0700 (PDT) X-Google-Smtp-Source: APBJJlHSduDcuo9ZFWr4saop7opj+loMJMo7ZdHDPhOIlYeFQeSpnbaOoKoYZN3h7YeFl7jA+TrH X-Received: by 2002:a17:907:2c41:b0:99b:7297:fbf5 with SMTP id hf1-20020a1709072c4100b0099b7297fbf5mr10085686ejc.61.1690270300575; Tue, 25 Jul 2023 00:31:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690270300; cv=none; d=google.com; s=arc-20160816; b=ERdhPzAWjqUjekxWtvKEfLe+ECQnzOjmWA2+h6pJbv2hvUl+VTrctWLG3ZGE/fCT+x BxVkBb2QGYMwQuWh/mexazq9Z1zvbyNuYFfLkzdtdqaTw2cIx9E+wjklMJS1/2cvi6BH 4RiEqOKuv0h+1rbNX2kweVEFQk1HJtLkB0e1IqiXrTB/lhk+bCMpEaY1qZVBfowwY/je 1VPSssxbYkllt5j+fCy/QoxTOQ3D9ELcBfLlkX4mh/1mdvZV2ET6UYcYxewjPOP2Dnok 6b4MyM5qKlfQFpIz2acaCKFa7L6jtMuiwcqO7gV0Eu3FZYaES7L8/99adoz4ktEHGIKF L07g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=f7KtmMD3x0zsy+mXU47TA2shtj1MOmMQdRqFlm1Gyrk=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=i2+DSlRwYH20PHegI2wUew/uxRctLq+iwIe/dPTOLjAzlDp5hvAj/0504q/iO0byOz XJtdOtXy4SAy+SVSfWYBZvGG/0fz+o+R+cVTGVWYHSoDbPmIL2rU1Kz+fDyCnIAvKOEH c759Y2TKtGnyfBvtQB00/beLk8ib3JEra/NiUqGLY7+MK59cQq0nIL9X1I7HGaf2ESbN uJWysT42GVmx020XtnPcGb8HfvG0uwjWRXX+N084Qbae4TXQlj8XQN8h7Kpjz8PfOZKB g4VTfcmNZa+4zmiq/eldOMmD163XoPSMPRBoYM38U0oP9OLFbCGdbIxO+a7ojhmlfc3l /NaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=KYCPIkDq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o1-20020a170906288100b00965a6d6b536si7602234ejd.335.2023.07.25.00.31.16; Tue, 25 Jul 2023 00:31:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=KYCPIkDq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232505AbjGYHTA (ORCPT + 99 others); Tue, 25 Jul 2023 03:19:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232409AbjGYHST (ORCPT ); Tue, 25 Jul 2023 03:18:19 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC6B4273E; Tue, 25 Jul 2023 00:17:09 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P4fudI005480; Tue, 25 Jul 2023 07:16:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=f7KtmMD3x0zsy+mXU47TA2shtj1MOmMQdRqFlm1Gyrk=; b=KYCPIkDq7Qaxh3t0yP1ITPvE1ogCIrcJmrOgGAVRwNOltcwDpw9Pqv7Zkzpv/H1pCtCr /Tts3W6h9OHzpe2foS8koFC1Dk/PZH2MDnC0CsgG93Z7f0K8n5IDafe0Baot2aKsbr9z W5jISCCqT6qpE2lD28chmU68lreovlIMymmmGwJKGevtxIk0UW0l7SxPWdM/dvaJzuQH nBIsprCJYWYvrOybanKqtjfOBvwV/GH8BMi5Ay5z/vAAY1QAcm4XX5IRiKKOLYn/hE/F hVIOsCjSBiWsvZK3MylZ1A96E15yyEzgr5lq9q7kCAzqJcBL7mMNAtPOEDtRIKgJai5Q 5w== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1qa3t88r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:56 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7GtiO030316 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:16:55 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:16:50 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 08/13] coresight-tpdm: Add node to set dsb programming mode Date: Tue, 25 Jul 2023 15:15:48 +0800 Message-ID: <1690269353-10829-9-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: l039Q7qrlbWExNLatGp0bV8hbxVnYwPw X-Proofpoint-GUID: l039Q7qrlbWExNLatGp0bV8hbxVnYwPw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 malwarescore=0 suspectscore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 mlxscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772376870715886271 X-GMAIL-MSGID: 1772376870715886271 Add node to set and show programming mode for TPDM DSB subunit. Once the DSB programming mode is set, it will be written to the register DSB_CR. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 15 ++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 62 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 16 ++++++ 3 files changed, 93 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 0b7b4ad..2a82cd0 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -45,3 +45,18 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : Set the DSB trigger type to false 1 : Set the DSB trigger type to true + +What: /sys/bus/coresight/devices//dsb_mode +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the mode of DSB tpdm. Read the mode of DSB + tpdm. + + Accepts the value needs to be greater than 0. What data + bits do is listed below. + Bit[0:1] : Test mode control bit for choosing the inputs. + Bit[3] : Set to 0 for low performance mode. + Set to 1 for high performance mode. + Bit[4:8] : Select byte lane for high performance mode. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 62efc18..c38760b 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -42,6 +43,32 @@ static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) } } +static void set_dsb_test_mode(struct tpdm_drvdata *drvdata, u32 *val) +{ + u32 mode; + + mode = TPDM_DSB_MODE_TEST(drvdata->dsb->mode); + *val &= ~TPDM_DSB_TEST_MODE; + *val |= FIELD_PREP(TPDM_DSB_TEST_MODE, mode); +} + +static void set_dsb_hpsel_mode(struct tpdm_drvdata *drvdata, u32 *val) +{ + u32 mode; + + mode = TPDM_DSB_MODE_HPBYTESEL(drvdata->dsb->mode); + *val &= ~TPDM_DSB_HPSEL; + *val |= FIELD_PREP(TPDM_DSB_HPSEL, mode); +} + +static void set_dsb_perf_mode(struct tpdm_drvdata *drvdata, u32 *val) +{ + if (drvdata->dsb->mode & TPDM_DSB_MODE_PERF) + *val |= TPDM_DSB_CR_MODE; + else + *val &= ~TPDM_DSB_CR_MODE; +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val; @@ -55,6 +82,12 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + /* Set the test accurate mode */ + set_dsb_test_mode(drvdata, &val); + /* Set the byte lane for high-performance mode */ + set_dsb_hpsel_mode(drvdata, &val); + /* Set the performance mode */ + set_dsb_perf_mode(drvdata, &val); /* Set trigger type */ if (drvdata->dsb->trig_type) val |= TPDM_DSB_CR_TRIG_TYPE; @@ -241,6 +274,34 @@ static struct attribute_group tpdm_attr_grp = { .attrs = tpdm_attrs, }; +static ssize_t dsb_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%lx\n", + (unsigned long)drvdata->dsb->mode); +} + +static ssize_t dsb_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || val < 0) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->mode = val & TPDM_DSB_MODE_MASK; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_mode); + static ssize_t dsb_trig_type_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -312,6 +373,7 @@ static ssize_t dsb_trig_ts_store(struct device *dev, static DEVICE_ATTR_RW(dsb_trig_ts); static struct attribute *tpdm_dsb_attrs[] = { + &dev_attr_dsb_mode.attr, &dev_attr_dsb_trig_ts.attr, &dev_attr_dsb_trig_type.attr, NULL, diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 92c34cd..49fffb1 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -15,11 +15,25 @@ /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) +/* Enable bit for DSB subunit perfmance mode */ +#define TPDM_DSB_CR_MODE BIT(1) /* Enable bit for DSB subunit trigger type */ #define TPDM_DSB_CR_TRIG_TYPE BIT(12) + /* Enable bit for DSB subunit trigger timestamp */ #define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1) +/* DSB programming modes */ +/* Test mode control bit*/ +#define TPDM_DSB_MODE_TEST(val) (val & GENMASK(1, 0)) +/* Performance mode */ +#define TPDM_DSB_MODE_PERF BIT(3) +/* High performance mode */ +#define TPDM_DSB_MODE_HPBYTESEL(val) (val & GENMASK(8, 4)) +#define TPDM_DSB_MODE_MASK GENMASK(8, 0) +#define TPDM_DSB_TEST_MODE GENMASK(10, 9) +#define TPDM_DSB_HPSEL GENMASK(6, 2) + /* TPDM integration test registers */ #define TPDM_ITATBCNTRL (0xEF0) #define TPDM_ITCNTRL (0xF00) @@ -48,10 +62,12 @@ /** * struct dsb_dataset - specifics associated to dsb dataset + * @mode: DSB programming mode * @trig_ts: Enable/Disable trigger timestamp. * @trig_type: Enable/Disable trigger type. */ struct dsb_dataset { + u32 mode; bool trig_ts; bool trig_type; }; From patchwork Tue Jul 25 07:15:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125404 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2316012vqg; Tue, 25 Jul 2023 01:15:51 -0700 (PDT) X-Google-Smtp-Source: APBJJlGyMozrEnn2s1wADZV/KGZQgJpXETS/uKnjsg/46f6HOz5FI5T8UW5bXyZEY0O2tqHZqdtN X-Received: by 2002:a05:6e02:1313:b0:348:dd48:e9d4 with SMTP id g19-20020a056e02131300b00348dd48e9d4mr2067038ilr.1.1690272950967; Tue, 25 Jul 2023 01:15:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690272950; cv=none; d=google.com; s=arc-20160816; b=iQaTuHUat76Yyhg9HBqyHRvt96UgX4gs8gByAan0uo6uN0HP+WcklQ+k3K9IFwd0n8 qz4k9tTMkUhcIsy4W3j4e8XbriqMFQJCJ8wGzygej/RMxsTj7JLDMUvAighBITMwat9M O+S3aRB+0Zceq1rGN1gbww+BAnEZIElBcCVaUgdarc0+HHg0JxUOOggFWhhGgerBvOGu r6dZGNOse2z1vE1US65JzZqAIidFzPbdVciaBJxpBzN7LqByFOqakcAPzEVV/RfwilXD Si87jA+TF0LyRAuUAtDy8KfwK+ako0W9GK7GDzabg5GRjFekQ2VeVHhyTtOe6L26XK5K mB8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=mXfTZyzndaQ9VVDsG7ANX3/4AdNnFj8gWiGTtvbsQ3g=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=w8y7PchKlRxynx5iCrwOZlw+JZntqK6MUBdu3pg7fo/tSme6O2mHnq2XN2k6e6Pxym MF01V9Kq1Af/QNZoit0ik6qBohSEA+1hRDpA7spAZdgFH+UHqoZ6veHI8taWhC3ZWWnh WJsHRh6FIBUjDLOmWTkgj682w2ca/5j/RlaUfBjiFZTf5JDm4ODX39Eq/kIyZI/Adjlb Sgie7ziCRg3oa3SuMfHM4ImjL3KClOH9h8qVkoVcFVbn+/ADlt8KseeewdYLCRpSOBqz lfbH/+aJpX2zIndM70Sjn7DFE5RzVKXTlHeegYZi6qo6nxsiyHs94Ag5Gs90JUN3hN30 zlrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Q0pJCcpA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bu9-20020a056a00410900b0066a4fe6ad99si10774725pfb.148.2023.07.25.01.15.37; Tue, 25 Jul 2023 01:15:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Q0pJCcpA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232418AbjGYHTR (ORCPT + 99 others); Tue, 25 Jul 2023 03:19:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232416AbjGYHSg (ORCPT ); Tue, 25 Jul 2023 03:18:36 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE28D19BD; Tue, 25 Jul 2023 00:17:13 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P0MVuL008166; Tue, 25 Jul 2023 07:17:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=mXfTZyzndaQ9VVDsG7ANX3/4AdNnFj8gWiGTtvbsQ3g=; b=Q0pJCcpAJ2J8MINXonZglBxC4TQy2M0Kab8SW669s2TUSnVnFzPX86cSRbBFIOqtisbr 7OabxKF3gjW4lN8Gg3ILZRXCNdD/RqVguy9c2FVaosmKu4PlrytQjTv45py07c11HKiU VrsBefXnszlVYVa/qlKvTHBEQyDqrx85QvQLCGmn/5TpcZfKCP709XAm3DWBzGN7mKUj XSg9doffq3tDPQK0gV2zzC9S0IdyPifNHRHFDGyJSPmzSAESSxSmBfhOpjntHxrKrbi5 2vxzBwaXhlovLKRpTF1d2j0oa4x2hN0j6+LQUm1QUo+SjmibbBdF6LETyDg7bnkpq+Jt BQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1s1jt2fb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:17:01 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7H0Ip005253 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:17:00 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:16:55 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 09/13] coresight-tpdm: Add nodes for dsb edge control Date: Tue, 25 Jul 2023 15:15:49 +0800 Message-ID: <1690269353-10829-10-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VvHvVFnWcXHgOd7s00f5jbmiZz4TC3o0 X-Proofpoint-ORIG-GUID: VvHvVFnWcXHgOd7s00f5jbmiZz4TC3o0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 mlxlogscore=999 phishscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 suspectscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250063 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772379649931436594 X-GMAIL-MSGID: 1772379649931436594 Add the nodes to set value for DSB edge control and DSB edge control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. DSB edge detection control 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask. Eight 32 bit registers providing DSB interface edge detection mask control. Add the nodes to configure DSB edge control and DSB edge control mask. Each DSB subunit TPDM maximum of 256 edge detections can be configured. The index and value sysfs files need to be paired and written to order. The index sysfs file is to set the index number of the edge detection which needs to be configured. And the value sysfs file is to set the control or mask for the edge detection. DSB edge detection control should be set as the following values. 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And DSB edge mask should be set as 0 or 1. Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 39 +++++ drivers/hwtracing/coresight/coresight-tpdm.c | 158 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 30 +++- 3 files changed, 223 insertions(+), 4 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 2a82cd0..a4550c5 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -60,3 +60,42 @@ Description: Bit[3] : Set to 0 for low performance mode. Set to 1 for high performance mode. Bit[4:8] : Select byte lane for high performance mode. + +What: /sys/bus/coresight/devices//dsb_edge_ctrl_idx +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read/Write the index number of the edge detection for the DSB + subunit TPDM. Since there are at most 256 edge detections, this + value ranges from 0 to 255. + +What: /sys/bus/coresight/devices//dsb_edge_ctrl_val +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read a set of the edge control registers of the DSB in TPDM. + Write a data to control the edge detection corresponding to + the index number. Before writing data to this sysfs file, + "dsb_edge_ctrl_idx" should be written first to configure the + index number of the edge detection which needs to be controlled. + + Accepts only one of the following values. + 0 - Rising edge detection + 1 - Falling edge detection + 2 - Rising and falling edge detection (toggle detection) + + +What: /sys/bus/coresight/devices//dsb_edge_ctrl_mask +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read a set of the edge control mask registers of the DSB in TPDM. + Write a data to mask the edge detection corresponding to the index + number. Before writing data to this sysfs file, "dsb_edge_ctrl_idx" + should be written first to configure the index number of the edge + detection which needs to be masked. + + Accepts only one of the 2 values - 0 or 1. \ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index c38760b..98fd6ab 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -71,7 +71,14 @@ static void set_dsb_perf_mode(struct tpdm_drvdata *drvdata, u32 *val) static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { - u32 val; + u32 val, i; + + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) + writel_relaxed(drvdata->dsb->edge_ctrl[i], + drvdata->base + TPDM_DSB_EDCR(i)); + for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) + writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], + drvdata->base + TPDM_DSB_EDCMR(i)); val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); /* Set trigger timestamp */ @@ -302,6 +309,152 @@ static ssize_t dsb_mode_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_mode); +static ssize_t dsb_edge_ctrl_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->edge_ctrl_idx); +} + +/* + * The EDCR registers can include up to 16 32-bit registers, and each + * one can be configured to control up to 16 edge detections(2 bits + * control one edge detection). So a total 256 edge detections can be + * configured. This function provides a way to set the index number of + * the edge detection which needs to be configured. + */ +static ssize_t dsb_edge_ctrl_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val >= TPDM_DSB_MAX_LINES)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->edge_ctrl_idx = val; + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_RW(dsb_edge_ctrl_idx); + +static ssize_t dsb_edge_ctrl_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { + bytes = sysfs_emit_at(buf, size, + "Val:0x%x\n", drvdata->dsb->edge_ctrl[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +/* + * This function is used to control the edge detection according + * to the index number that has been set. + * "edge_ctrl" should be one of the following values. + * 0 - Rising edge detection + * 1 - Falling edge detection + * 2 - Rising and falling edge detection (toggle detection) + */ +static ssize_t dsb_edge_ctrl_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val, mask, edge_ctrl; + int reg; + + if ((kstrtoul(buf, 0, &edge_ctrl)) || (edge_ctrl > 0x2)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* + * There are 2 bit per DSB Edge Control line. + * Thus we have 16 lines in a 32bit word. + */ + reg = EDCR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx); + mask = EDCR_TO_WORD_MASK(drvdata->dsb->edge_ctrl_idx); + val = drvdata->dsb->edge_ctrl[reg]; + val &= ~EDCR_TO_WORD_MASK(drvdata->dsb->edge_ctrl_idx); + val |= EDCR_TO_WORD_VAL(edge_ctrl, drvdata->dsb->edge_ctrl_idx); + drvdata->dsb->edge_ctrl[reg] = val; + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_RW(dsb_edge_ctrl_val); + +static ssize_t dsb_edge_ctrl_mask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) { + bytes = sysfs_emit_at(buf, size, + "Val:0x%x\n", drvdata->dsb->edge_ctrl_mask[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +static ssize_t dsb_edge_ctrl_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + u32 set; + int reg; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* + * There is 1 bit per DSB Edge Control Mark line. + * Thus we have 32 lines in a 32bit word. + */ + reg = EDCMR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx); + set = drvdata->dsb->edge_ctrl_mask[reg]; + if (val) + set |= BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx)); + else + set &= ~BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx)); + drvdata->dsb->edge_ctrl_mask[reg] = set; + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_RW(dsb_edge_ctrl_mask); + static ssize_t dsb_trig_type_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -374,6 +527,9 @@ static DEVICE_ATTR_RW(dsb_trig_ts); static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, + &dev_attr_dsb_edge_ctrl_idx.attr, + &dev_attr_dsb_edge_ctrl_val.attr, + &dev_attr_dsb_edge_ctrl_mask.attr, &dev_attr_dsb_trig_ts.attr, &dev_attr_dsb_trig_type.attr, NULL, diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 49fffb1..4afdb29 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) +#define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) +#define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) @@ -34,6 +36,16 @@ #define TPDM_DSB_TEST_MODE GENMASK(10, 9) #define TPDM_DSB_HPSEL GENMASK(6, 2) +#define EDCRS_PER_WORD 16 +#define EDCR_TO_WORD_IDX(r) ((r) / EDCRS_PER_WORD) +#define EDCR_TO_WORD_SHIFT(r) ((r % EDCRS_PER_WORD) * 2) +#define EDCR_TO_WORD_VAL(val, r) (val << EDCR_TO_WORD_SHIFT(r)) +#define EDCR_TO_WORD_MASK(r) EDCR_TO_WORD_VAL(0x3, r) + +#define EDCMRS_PER_WORD 32 +#define EDCMR_TO_WORD_IDX(r) ((r) / EDCMRS_PER_WORD) +#define EDCMR_TO_WORD_SHIFT(r) ((r) % EDCMRS_PER_WORD) + /* TPDM integration test registers */ #define TPDM_ITATBCNTRL (0xEF0) #define TPDM_ITCNTRL (0xF00) @@ -60,14 +72,26 @@ #define TPDM_PIDR0_DS_IMPDEF BIT(0) #define TPDM_PIDR0_DS_DSB BIT(1) +#define TPDM_DSB_MAX_LINES 256 +/* MAX number of EDCR registers */ +#define TPDM_DSB_MAX_EDCR 16 +/* MAX number of EDCMR registers */ +#define TPDM_DSB_MAX_EDCMR 8 + /** * struct dsb_dataset - specifics associated to dsb dataset - * @mode: DSB programming mode - * @trig_ts: Enable/Disable trigger timestamp. - * @trig_type: Enable/Disable trigger type. + * @mode: DSB programming mode + * @edge_ctrl_idx Index number of the edge control + * @edge_ctrl: Save value for edge control + * @edge_ctrl_mask: Save value for edge control mask + * @trig_ts: Enable/Disable trigger timestamp. + * @trig_type: Enable/Disable trigger type. */ struct dsb_dataset { u32 mode; + u32 edge_ctrl_idx; + u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; + u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; bool trig_ts; bool trig_type; }; From patchwork Tue Jul 25 07:15:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125382 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2299225vqg; Tue, 25 Jul 2023 00:36:29 -0700 (PDT) X-Google-Smtp-Source: APBJJlHLMnYEEzsifyrenEUvttBoPnmSlZ5N7AKvPwdW9A5u6AW6XnTkt7qFSng9FUewQY23fqMC X-Received: by 2002:aa7:d1d5:0:b0:522:55bf:21af with SMTP id g21-20020aa7d1d5000000b0052255bf21afmr440043edp.7.1690270589023; Tue, 25 Jul 2023 00:36:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690270589; cv=none; d=google.com; s=arc-20160816; b=KkmbZzPhg6ZGUwzoxFfqqJIzZzwoyI5PEdsCjWeYrcpNLhSLXJLlKmt0xNfhYPovty lj2Pb0tvNums2fczw7XRzF1+CojC0gpBak6J8YeoA+sT3Hja7FSZS5ulEXk3mE088TGo nm7hIx7hoiWbCh2et7An6MlunFtOcvVKnHOz+Y0z0d+st82dHaYoqzYyM/w94h7PB61L hX07rMvmc6OTyczKHiYWiUWRLFk6x9D3vCFTKL/7TbWB1s38KOKOwpgeH+Q6UCC0rmpw LInntlnfWPgdimGSX8gbEXrRn+2UtTI03J1tltP8/MMwEolQZG9CcFOJa3XI8uSZrEav 4WHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=JuxNSZ4L/4+OvCuzDVnh6dKJ5jle+4HKWf7saWivwJE=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=ZFTrwyJM19/G5MVX9nthL9/ZXLeXmERpMftyWakGwTQygOxPdsIvAfN0S67FNYdFdB QiEWAvC5AHxtb4UK4DlMATHG3pI3chpA3ggYWXQe7IKurxYdOqY98pSSImyIh0TLUOL6 t9488JVuPOJEWwmIDR0pfkONKzd7oknLH3YrLHRc8tRjJMLROLKyxLOjGplMe8PBubXP ivisfQEzxXoJvqf3BougsIkPr6nj9GtEpkUHnCtP9wrG/JoSISlpAiRuhouNsDBFVbsD 0ts1KnbMxJ3TkX8fmOMOmHzCmLm05uR0Vt3ASqx1QUf4glwJxjOKllUKxMrUkPXgENKo yQuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=DqgF63v1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t8-20020a05640203c800b0051fde3afeaesi7781461edw.689.2023.07.25.00.36.05; Tue, 25 Jul 2023 00:36:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=DqgF63v1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232533AbjGYHT1 (ORCPT + 99 others); Tue, 25 Jul 2023 03:19:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232421AbjGYHSl (ORCPT ); Tue, 25 Jul 2023 03:18:41 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CC2F19AD; Tue, 25 Jul 2023 00:17:17 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P5SrZH030185; Tue, 25 Jul 2023 07:17:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=JuxNSZ4L/4+OvCuzDVnh6dKJ5jle+4HKWf7saWivwJE=; b=DqgF63v1ZpZvk0BJXt4Q8k+Jf3BSiI1ZsU30fjoIUZRqeJP4KggifkZZ6k4g7MO/UMiu l+F9vGJjej4DQPtMUpf5tWIl7Ys4/N0nsIWvZxuiWBbI8Jl8lNqtYglr3XG4Nesii+7P AyAAGsehpWvQOhHP0lX9Yv997sSg8ykDukBR0MkmMsd9bgOwIAQwdAw2RMser2F1tyLx kfTXvcCTFYPuW14IZNoutKLQ8SG0A/4AP44uac54jC5Isei+olb+RQVku3zlltt5D1I6 9744nbBXikd4+LtYKLqgWqxJcSfyFPuWS3CzKPMLEbIM3bUNqL53VxevYUYQ+hijtFpA ag== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1pfhad4c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:17:05 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7H4Jv032718 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:17:05 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:17:00 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 10/13] coresight-tpdm: Add nodes to configure pattern match output Date: Tue, 25 Jul 2023 15:15:50 +0800 Message-ID: <1690269353-10829-11-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 7RtPWihLlCjUUg9dFMlSfHvH3n8_IKC9 X-Proofpoint-GUID: 7RtPWihLlCjUUg9dFMlSfHvH3n8_IKC9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 phishscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772377173474698217 X-GMAIL-MSGID: 1772377173474698217 Add nodes to configure trigger pattern and trigger pattern mask. Each DSB subunit TPDM has maximum of n(n<7) XPR registers to configure trigger pattern match output. Eight 32 bit registers providing DSB interface trigger output pattern match comparison. And each DSB subunit TPDM has maximum of m(m<7) XPMR registers to configure trigger pattern mask match output. Eight 32 bit registers providing DSB interface trigger output pattern match mask. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 34 +++++- drivers/hwtracing/coresight/coresight-tpdm.c | 118 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 10 ++ 3 files changed, 161 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index a4550c5..66f9582 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -98,4 +98,36 @@ Description: should be written first to configure the index number of the edge detection which needs to be masked. - Accepts only one of the 2 values - 0 or 1. \ No newline at end of file + Accepts only one of the 2 values - 0 or 1. + +What: /sys/bus/coresight/devices//dsb_trig_patt_idx +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read/Write the index number of the trigger pattern value of DSB + tpdm. Since there are at most 8 XPR and XPMR registers for the + trigger parttern, this value ranges from 0 to 7. + +What: /sys/bus/coresight/devices//dsb_trig_patt_val +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read a set of the trigger pattern values of the DSB TPDM. + Write a data to configure the trigger pattern corresponding to + the index number. Before writing data to this sysfs file, + "dsb_trig_patt_idx" should be written first to configure the + index number of the trigger pattern which needs to be configured. + +What: /sys/bus/coresight/devices//dsb_trig_patt_mask +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read a set of the trigger pattern mask of the DSB TPDM. + Write a data to configure the trigger pattern mask corresponding + to the index number. Before writing data to this sysfs file, + "dsb_trig_patt_idx" should be written first to configure the + index number of the trigger pattern mask which needs to be + configured. \ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 98fd6ab..1c32d27 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -80,6 +80,13 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], drvdata->base + TPDM_DSB_EDCMR(i)); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + writel_relaxed(drvdata->dsb->trig_patt[i], + drvdata->base + TPDM_DSB_XPR(i)); + writel_relaxed(drvdata->dsb->trig_patt_mask[i], + drvdata->base + TPDM_DSB_XPMR(i)); + } + val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); /* Set trigger timestamp */ if (drvdata->dsb->trig_ts) @@ -455,6 +462,114 @@ static ssize_t dsb_edge_ctrl_mask_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_edge_ctrl_mask); +static ssize_t dsb_trig_patt_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->trig_patt_idx); +} + +static ssize_t dsb_trig_patt_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index; + + if (kstrtoul(buf, 0, &index)) + return -EINVAL; + if (index >= TPDM_DSB_MAX_PATT) + return -EPERM; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->trig_patt_idx = index; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_patt_idx); + +static ssize_t dsb_trig_patt_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i = 0; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + bytes = sysfs_emit_at(buf, size, + "Value: 0x%x\n", drvdata->dsb->trig_patt[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +static ssize_t dsb_trig_patt_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->trig_patt[drvdata->dsb->trig_patt_idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_patt_val); + +static ssize_t dsb_trig_patt_mask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i = 0; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + bytes = sysfs_emit_at(buf, size, + "Value: 0x%x\n", drvdata->dsb->trig_patt_mask[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +static ssize_t dsb_trig_patt_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->trig_patt_mask[drvdata->dsb->trig_patt_idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_patt_mask); + static ssize_t dsb_trig_type_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -530,6 +645,9 @@ static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_edge_ctrl_idx.attr, &dev_attr_dsb_edge_ctrl_val.attr, &dev_attr_dsb_edge_ctrl_mask.attr, + &dev_attr_dsb_trig_patt_idx.attr, + &dev_attr_dsb_trig_patt_val.attr, + &dev_attr_dsb_trig_patt_mask.attr, &dev_attr_dsb_trig_ts.attr, &dev_attr_dsb_trig_type.attr, NULL, diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 4afdb29..7f688b2 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) +#define TPDM_DSB_XPR(n) (0x7C8 + (n * 4)) +#define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) #define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) @@ -77,21 +79,29 @@ #define TPDM_DSB_MAX_EDCR 16 /* MAX number of EDCMR registers */ #define TPDM_DSB_MAX_EDCMR 8 +/* MAX number of DSB pattern */ +#define TPDM_DSB_MAX_PATT 8 /** * struct dsb_dataset - specifics associated to dsb dataset * @mode: DSB programming mode * @edge_ctrl_idx Index number of the edge control + * @trig_patt_idx Index number of the trigger pattern * @edge_ctrl: Save value for edge control * @edge_ctrl_mask: Save value for edge control mask + * @trig_patt: Save value for trigger pattern + * @trig_patt_mask: Save value for trigger pattern mask * @trig_ts: Enable/Disable trigger timestamp. * @trig_type: Enable/Disable trigger type. */ struct dsb_dataset { u32 mode; u32 edge_ctrl_idx; + u32 trig_patt_idx; u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; + u32 trig_patt[TPDM_DSB_MAX_PATT]; + u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; bool trig_ts; bool trig_type; }; From patchwork Tue Jul 25 07:15:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125370 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2296378vqg; Tue, 25 Jul 2023 00:29:53 -0700 (PDT) X-Google-Smtp-Source: APBJJlEo+g5XVt53gcyF3EHWCjUgRMwcuxHUt3jpNtWmawpceMc3BanDmTLM+z36ysxYbRdY00V+ X-Received: by 2002:a2e:94ca:0:b0:2b6:cd12:24f7 with SMTP id r10-20020a2e94ca000000b002b6cd1224f7mr7629866ljh.44.1690270193218; Tue, 25 Jul 2023 00:29:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690270193; cv=none; d=google.com; s=arc-20160816; b=HgQYpWdO/SkIS0TAU/HOGLTD8dJGMBnljpiwfAUM81pRbNON62KKO+hB2XqkegbxBG udcZlMPX1KjIb1F+4ItZXpBXsf2Iglh+4WmrIih7i+U9glzC8VF8nkwZomqS1Sc6c6zJ p7PYiKdU6yV+Z2z+PA1r0ikvAvZpBfTDPrUe6FvrdCXs+k0NH23Dwu9iylOneWdP5Llw Qlr2LZ2lxEFeLZrZjZGnNWfzOvV3xkG+7/9Ypry+6/2pQK+E99sUETx09gdOzpPsnzq7 2J5OqCBl/T3Uz/M2vIeCKfRf/gWeB1JZJcIoYi59TT6vMiOajgF8hBQ10ViYeRNU1zAR MFfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=QWTgKsVG0x8qetiN9WriXWxj+vVNHTh3tQUv4aE0Y3s=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=Iif/0YAkCG0CT5TBBffCZvg4150wOB+QW9i+PE09vhvfrVR0y6I8EFkfkbPPoHC+Ln bGT3Tusb7b8/XDh9K+vpn/ihaBV0/4kMSCG3LGPqLzwLcjgtVFV2VYbI+xf89CakbJak wIPlDA6FyX2guNFffj6XBxJMnUYlYh85fR7hU8IqeESqSFRWekIzfxxSBHNvEPMTdUpS FVfn0MYDHzPsz7zdGTdas76j8aYobFATTzXEwW1Z6lfv1vtImsBmgUc0AzMaSePty+u/ M8TgiuDNReL8FJolG/Wcig4mOD1M68IWsAkgntFxMB85c7XqeHOse7rUU8bWrfYAGJkU hV+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=XhGMRKqL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p1-20020a17090628c100b0099334262e18si7936142ejd.49.2023.07.25.00.29.26; Tue, 25 Jul 2023 00:29:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=XhGMRKqL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232550AbjGYHTi (ORCPT + 99 others); Tue, 25 Jul 2023 03:19:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232402AbjGYHSv (ORCPT ); Tue, 25 Jul 2023 03:18:51 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 357781BE4; Tue, 25 Jul 2023 00:17:25 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P58Qsp024178; Tue, 25 Jul 2023 07:17:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=QWTgKsVG0x8qetiN9WriXWxj+vVNHTh3tQUv4aE0Y3s=; b=XhGMRKqLHOA8jQcvIlttD+LbgMc9NKhEtTtnuTjqwtaunf1lNuOkncU8jKvZ2Fq3ZL8e IG6ZpGZ/TPpsJ0h9NUx1kEgH33D4Nj1VtPqug9HtIeiT1U2t2N5+1tkdyBuZ1oJAHDpI lbfRAOQeJssgV3PvWgXvpQI2NAmKO8jIJnvMAAaRAEt4/6Rc/dIKyg1AAzeR8d+y4nMO 8xy0C3FNpFNO+wLQDF6om7U5pb/KM8jOAU5xJlyjgr0GdDm91ERpJjO0vP3F76bMR9qe syHGuyRhKQpznQxDzLRna1gLJcPJi6d641gZXUQFHZTSCSlkKoOwCcYNsWeWQwaCXeUZ 7A== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1pfhad4f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:17:12 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7HAKR029913 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:17:10 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:17:05 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 11/13] coresight-tpdm: Add nodes for timestamp request Date: Tue, 25 Jul 2023 15:15:51 +0800 Message-ID: <1690269353-10829-12-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Nm6DnTph5luE-WH-dNjVJGK7zcdaFZHU X-Proofpoint-GUID: Nm6DnTph5luE-WH-dNjVJGK7zcdaFZHU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 phishscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772376758360075262 X-GMAIL-MSGID: 1772376758360075262 Add nodes to configure the timestamp request based on input pattern match. Each TPDM that support DSB subunit has maximum of n(n<7) TPR registers to configure value for timestamp request based on input pattern match. Eight 32 bit registers providing DSB interface timestamp request pattern match comparison. And each TPDM that support DSB subunit has maximum of m(m<7) TPMR registers to configure pattern mask for timestamp request. Eight 32 bit registers providing DSB interface timestamp request pattern match mask generation. Add nodes to enable/disable pattern timestamp and set pattern timestamp type. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 57 +++++- drivers/hwtracing/coresight/coresight-tpdm.c | 205 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 16 ++ 3 files changed, 272 insertions(+), 6 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 66f9582..74a0126 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -130,4 +130,59 @@ Description: to the index number. Before writing data to this sysfs file, "dsb_trig_patt_idx" should be written first to configure the index number of the trigger pattern mask which needs to be - configured. \ No newline at end of file + configured. + +What: /sys/bus/coresight/devices//dsb_patt_idx +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read/Write the index number of the DSB tpdm pattern. Since + there are at most 8 TPR and TPMR registers for the parttern, + this value ranges from 0 to 7. + +What: /sys/bus/coresight/devices//dsb_patt_val +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read a set of the pattern values of the DSB TPDM. Write a data + to configure the pattern corresponding to the index number. + Before writing data to this sysfs file, "dsb_patt_idx" should be + written first to configure the index number of the pattern which + needs to be configured. + +What: /sys/bus/coresight/devices//dsb_patt_mask +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read a set of the pattern mask values of the DSB TPDM. Write a + data to configure the pattern mask corresponding to the index + number. Before writing data to this sysfs file, "dsb_patt_idx" + should be written first to configure the index number of the + pattern mask which needs to be configured. + +What: /sys/bus/coresight/devices//dsb_patt_ts +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the pattern timestamp of DSB tpdm. Read + the pattern timestamp of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Disable DSB pattern timestamp. + 1 : Enable DSB pattern timestamp. + +What: /sys/bus/coresight/devices//dsb_patt_type +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the pattern type of DSB tpdm. Read + the pattern type of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB pattern type to value. + 1 : Set the DSB pattern type to toggle. \ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 1c32d27..f9e5a1d 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -69,6 +69,27 @@ static void set_dsb_perf_mode(struct tpdm_drvdata *drvdata, u32 *val) *val &= ~TPDM_DSB_CR_MODE; } +static void set_dsb_tier(struct tpdm_drvdata *drvdata, u32 *val) +{ + /* Set pattern timestamp type and enablement */ + if (drvdata->dsb->patt_ts) { + *val |= TPDM_DSB_TIER_PATT_TSENAB; + if (drvdata->dsb->patt_type) + *val |= TPDM_DSB_TIER_PATT_TYPE; + else + *val &= ~TPDM_DSB_TIER_PATT_TYPE; + } else { + *val &= ~TPDM_DSB_TIER_PATT_TSENAB; + } + + /* Set trigger timestamp */ + if (drvdata->dsb->trig_ts) + *val |= TPDM_DSB_TIER_XTRIG_TSENAB; + else + *val &= ~TPDM_DSB_TIER_XTRIG_TSENAB; + +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val, i; @@ -81,6 +102,10 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) drvdata->base + TPDM_DSB_EDCMR(i)); for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + writel_relaxed(drvdata->dsb->patt_val[i], + drvdata->base + TPDM_DSB_TPR(i)); + writel_relaxed(drvdata->dsb->patt_mask[i], + drvdata->base + TPDM_DSB_TPMR(i)); writel_relaxed(drvdata->dsb->trig_patt[i], drvdata->base + TPDM_DSB_XPR(i)); writel_relaxed(drvdata->dsb->trig_patt_mask[i], @@ -88,11 +113,7 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) } val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); - /* Set trigger timestamp */ - if (drvdata->dsb->trig_ts) - val |= TPDM_DSB_TIER_XTRIG_TSENAB; - else - val &= ~TPDM_DSB_TIER_XTRIG_TSENAB; + set_dsb_tier(drvdata, &val); writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); val = readl_relaxed(drvdata->base + TPDM_DSB_CR); @@ -462,6 +483,175 @@ static ssize_t dsb_edge_ctrl_mask_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_edge_ctrl_mask); +static ssize_t dsb_patt_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->patt_idx); + +} + +static ssize_t dsb_patt_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index; + + if ((kstrtoul(buf, 0, &index)) || (index >= TPDM_DSB_MAX_PATT)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_idx = index; + spin_unlock(&drvdata->spinlock); + + return size; + +} +static DEVICE_ATTR_RW(dsb_patt_idx); + +static ssize_t dsb_patt_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i = 0; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + bytes = sysfs_emit_at(buf, size, + "Value: 0x%x\n", drvdata->dsb->patt_val[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +static ssize_t dsb_patt_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_val[drvdata->dsb->patt_idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_patt_val); + +static ssize_t dsb_patt_mask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i = 0; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + bytes = sysfs_emit_at(buf, size, + "Value: 0x%x\n", drvdata->dsb->patt_mask[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +static ssize_t dsb_patt_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_mask[drvdata->dsb->patt_idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_patt_mask); + +static ssize_t dsb_patt_ts_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->patt_ts); +} + +/* + * value 1: Enable/Disable DSB pattern timestamp + */ +static ssize_t dsb_patt_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_ts = !!val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_patt_ts); + +static ssize_t dsb_patt_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->patt_type); +} + +/* + * value 1: Set DSB pattern type + */ +static ssize_t dsb_patt_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_type = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_patt_type); + static ssize_t dsb_trig_patt_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -645,6 +835,11 @@ static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_edge_ctrl_idx.attr, &dev_attr_dsb_edge_ctrl_val.attr, &dev_attr_dsb_edge_ctrl_mask.attr, + &dev_attr_dsb_patt_idx.attr, + &dev_attr_dsb_patt_val.attr, + &dev_attr_dsb_patt_mask.attr, + &dev_attr_dsb_patt_ts.attr, + &dev_attr_dsb_patt_type.attr, &dev_attr_dsb_trig_patt_idx.attr, &dev_attr_dsb_trig_patt_val.attr, &dev_attr_dsb_trig_patt_mask.attr, diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 7f688b2..7c52cf4 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) +#define TPDM_DSB_TPR(n) (0x788 + (n * 4)) +#define TPDM_DSB_TPMR(n) (0x7A8 + (n * 4)) #define TPDM_DSB_XPR(n) (0x7C8 + (n * 4)) #define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) @@ -24,8 +26,12 @@ /* Enable bit for DSB subunit trigger type */ #define TPDM_DSB_CR_TRIG_TYPE BIT(12) +/* Enable bit for DSB subunit pattern timestamp */ +#define TPDM_DSB_TIER_PATT_TSENAB BIT(0) /* Enable bit for DSB subunit trigger timestamp */ #define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1) +/* Bit for DSB subunit pattern type */ +#define TPDM_DSB_TIER_PATT_TYPE BIT(2) /* DSB programming modes */ /* Test mode control bit*/ @@ -86,22 +92,32 @@ * struct dsb_dataset - specifics associated to dsb dataset * @mode: DSB programming mode * @edge_ctrl_idx Index number of the edge control + * @patt_idx Index number of pattern * @trig_patt_idx Index number of the trigger pattern * @edge_ctrl: Save value for edge control * @edge_ctrl_mask: Save value for edge control mask + * @patt_val: Save value for pattern + * @patt_mask: Save value for pattern mask * @trig_patt: Save value for trigger pattern * @trig_patt_mask: Save value for trigger pattern mask + * @patt_ts: Enable/Disable pattern timestamp + * @patt_type: Set pattern type * @trig_ts: Enable/Disable trigger timestamp. * @trig_type: Enable/Disable trigger type. */ struct dsb_dataset { u32 mode; u32 edge_ctrl_idx; + u32 patt_idx; u32 trig_patt_idx; u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; + u32 patt_val[TPDM_DSB_MAX_PATT]; + u32 patt_mask[TPDM_DSB_MAX_PATT]; u32 trig_patt[TPDM_DSB_MAX_PATT]; u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; + bool patt_ts; + bool patt_type; bool trig_ts; bool trig_type; }; From patchwork Tue Jul 25 07:15:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125403 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2315845vqg; Tue, 25 Jul 2023 01:15:26 -0700 (PDT) X-Google-Smtp-Source: APBJJlFUlWAa3lOyl6vgkP9q4iierMM9ZjJA9UvFgSC5c3IQaVvnyTAUZdFYBUYqgjYtWY8ajM5N X-Received: by 2002:ae9:f407:0:b0:767:21b7:86e7 with SMTP id y7-20020ae9f407000000b0076721b786e7mr2008112qkl.73.1690272926591; Tue, 25 Jul 2023 01:15:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690272926; cv=none; d=google.com; s=arc-20160816; b=Dq8Ut+sjASGiMwA1LdjXCVWT90ypAArdwVizU6G8PboOkNfKDU68WKxvWA7OA3EuWD 1oPZJY9+572HrgQ7tA7PQspEI/LPGSxhKHTDol6rSmQG66N3JcsFCQX62nnNOzrPgAzc ZAgQF6QsppMCL15VXIksA1IVZFlu5GTxqPq/JZezd/JUjoXKJn3Eb8cvnaO/B1peNL80 dmDnYLXlCqsZdoTuBlqSJzc1G1kATw0xxjD70fwfUb6AIwhu4xLpIcwcQRx+Aj9GkQ8X EUDfdq39w8xMjgp8tigBzdB/N0IY0g9p1g0nx44BHlIX+TdcrhOHVnuLSTu7W488VWc8 hmQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=EwDQ8V1o8aMoce5+y4ZLTI9J03Z8DIY0p5SfAX3XBG4=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=Tbt8dFtndjWMoX+vVcWUXQ9payiYLGEk7fF3WrlUMF0PMY1Zt9s2Hl9YwaB7NX5/Us AWJ96PAtyo3sMRzkDEj8LaqbFr2SM9k2TfkkfGcsgOYQ4JmjwH9PNZe/yQRMvuFcZEK6 q6aVajLd98ZCy//9VXjW+47CEVGnRLfAwJXj9TLq0FXGP4lYLAjHfRVBUJh4/nRpsKaE HrPt9FOvRWzJ9GucAGjCvTn2/+NMR5vqJ5MU2yNUG2D9P2XpZ6+lbXGbRS0z5LaMBEO6 lr50HUdtNJcdJ9tq+RBLNdGaKG8b4kJjATNI8KiD4L0tvb2uyGEeQuXuow2PxrTQPTS/ pNnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=eCWRpju6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c3-20020a17090abf0300b00263f45720besi10795416pjs.169.2023.07.25.01.15.12; Tue, 25 Jul 2023 01:15:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=eCWRpju6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232545AbjGYHTg (ORCPT + 99 others); Tue, 25 Jul 2023 03:19:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232298AbjGYHSu (ORCPT ); Tue, 25 Jul 2023 03:18:50 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 848FA30D0; Tue, 25 Jul 2023 00:17:26 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P5wtlU017895; Tue, 25 Jul 2023 07:17:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=EwDQ8V1o8aMoce5+y4ZLTI9J03Z8DIY0p5SfAX3XBG4=; b=eCWRpju63n0+RHyiJCNtMd7P26SQgbS8XHA77ikzxUFj8uktZxap2DOLrV1TQ6GsCbYZ mGNA8tCW2IV2Or2QwQVw9UJXplzkuZ+hOBjmuU9LEzb5lbjsb3w6IQj0okqlma0iX/le iDGJmwFJGp470H/kTRb7L6RG5PWP73EWDBvukAZFMy9pT+6uUXa1F8js1tnz1D7epdz1 ZwgFW31TPvULAi1u+fN5xypo9gJtCykekflTGatgLHKzRSC0EJsJqKT8rl/72QAnIQQj p8mpzyGfaTgw1YmjO5amt7O1JZmBCWb1F/3rnO/esrCxZ+t4/S3BVv8DyUA5Xn7ramfj JA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1qa3t899-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:17:16 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7HFQc030650 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:17:15 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:17:10 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 12/13] dt-bindings: arm: Add support for DSB MSR register Date: Tue, 25 Jul 2023 15:15:52 +0800 Message-ID: <1690269353-10829-13-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: qbofF1ueMR2PLFMd_7PXOaDIEkEhs99F X-Proofpoint-GUID: qbofF1ueMR2PLFMd_7PXOaDIEkEhs99F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 malwarescore=0 suspectscore=0 clxscore=1015 mlxlogscore=884 priorityscore=1501 mlxscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772379624271401762 X-GMAIL-MSGID: 1772379624271401762 Add property "qcom,dsb-msrs-num" to support DSB(Discrete Single Bit) MSR(mux select register) for TPDM. It specifies the number of MSR registers supported by the DSB TDPM. Signed-off-by: Tao Zhang Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 931ee8f..d1d66bc 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -52,6 +52,15 @@ properties: $ref: /schemas/types.yaml#/definitions/uint8 enum: [32, 64] + qcom,dsb-msrs-num: + description: + Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) + registers supported by the monitor. If this property is not configured + or set to 0, it means this DSB TPDM doesn't support MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + clocks: maxItems: 1 @@ -86,6 +95,7 @@ examples: reg = <0x0684c000 0x1000>; qcom,dsb-element-size = /bits/ 8 <32>; + qcom,dsb-msrs-num = <16>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; From patchwork Tue Jul 25 07:15:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 125379 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2298928vqg; Tue, 25 Jul 2023 00:35:48 -0700 (PDT) X-Google-Smtp-Source: APBJJlEm8zQWcxAcVvIUN8E5m4bV1mtnYGMKBySk1Exk6+P/s0wxWOSd90IoRGyzfgzOhgxxh/34 X-Received: by 2002:a05:6402:712:b0:522:56c1:b334 with SMTP id w18-20020a056402071200b0052256c1b334mr85285edx.23.1690270547778; Tue, 25 Jul 2023 00:35:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690270547; cv=none; d=google.com; s=arc-20160816; b=Yt0T1eiqbuWW6dZDAJ1DvHGTB56d9AaHFTcsizOAaE77zOjRpfVmoLcOgqWdqUB81Q 32ruIZTm3GKmO1JoAc2GzqeUQDCzRj5k3Ryt5rWccg/lZn551dau5ibUB2OiAGE45QdN IeK+LtBt3KA26J5kKV0VRhyPpvjpBAziBOo2RZhPC+4BB6yFNhReatz0pOBmzpk7zv9q o0KB8oQKukQblZ61q5PSI9DjSBAaRCcAcXex5GkpSdUMCy6yyGNbSkUhtdtZkc4qejNS uRPi4C3rtpWi6uV3a4hBhRpZv/dK/isVoXHL6bKb9N+Ht7Qa6/bSY0EsrD832zH1Qub0 Cblg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qq3mgwldR84fvFPQ8IH8tR83mymgCTDsHByFJkWFnHU=; fh=hXfhjPaP7YtK8cx1pDaeyea4542GzczmcrIiOSp/HFc=; b=QFeAvoT8yYvzXoNZeCc9/nq0KfVG0AREZ/iqlYsjVf9dj8UM9jp12s+pizcdosy5PV TkWJva5YjdEi1nxWyVrswc2ok3lCFv3Yf2srjN2JujlS2Lmm+rlJCmKR7e4aFmeN02Pp NaPqnCInNXtpJi313T4V9c1g9xaA1qDTP769aW3hJuChexF0n4yisZdoMHbHkIkcidQj C+Kpg51IskRgsWu1qhrz8uh2bpV/xmXCLCLB+nZJ0mR6JCa9eUSk6j2KJ0LpfmINkNvn dWRy9Dw2MVxoAUeUAnmJ4tEv7L7t1lS96LgluLpyfrdTLMflDM4eY3ukbm8O3PBANIf9 oIZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=DtAYICfv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l1-20020a056402344100b0052228f1f784si3416340edc.148.2023.07.25.00.35.23; Tue, 25 Jul 2023 00:35:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=DtAYICfv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232419AbjGYHUB (ORCPT + 99 others); Tue, 25 Jul 2023 03:20:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232526AbjGYHTR (ORCPT ); Tue, 25 Jul 2023 03:19:17 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 863CE10C7; Tue, 25 Jul 2023 00:17:42 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36P3wqrl013133; Tue, 25 Jul 2023 07:17:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=qq3mgwldR84fvFPQ8IH8tR83mymgCTDsHByFJkWFnHU=; b=DtAYICfvGZVCGu7+2YoGpp8y6YD683tCOcj5gK77v12/3Fm5x8FqS+GEn5XVrAiPQTcN /PFudfpKgLjVyjDrlJCXjbg1G8f/wm7rzv9WA5bwmuU87npKpxNM6s7CAQTyNHPxwqmk YJr2SllLzUcfcrjNdDjE/pHPntQrlt9Tt78SGpLvu/oWstF/HoCi9Uh3xImffRMwn0Km OJGQxga8PQQv48g4Pcgp4TF+ZOxmjfeo3LLZRWBo184WzHgmCrryANy74NGu1YtmBFSV oNjet4WuCRmaoaZJAcJpW5uJRDMJx4cnOJRzXlIBMjrLpEx1tIBMGEO1IM9oMtZys1+N Sw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s1vh8hhc8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:17:21 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36P7HK5I005496 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jul 2023 07:17:20 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 25 Jul 2023 00:17:15 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v7 13/13] coresight-tpdm: Add nodes for dsb msr support Date: Tue, 25 Jul 2023 15:15:53 +0800 Message-ID: <1690269353-10829-14-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> References: <1690269353-10829-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ezmSUYqMWB9opMVd-BLAiF6PUoKXpf-o X-Proofpoint-GUID: ezmSUYqMWB9opMVd-BLAiF6PUoKXpf-o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_02,2023-07-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 impostorscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307250064 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772377129865712382 X-GMAIL-MSGID: 1772377129865712382 Add the nodes for DSB subunit MSR(mux select register) support. The TPDM MSR (mux select register) interface is an optional interface and associated bank of registers per TPDM subunit. The intent of mux select registers is to control muxing structures driving the TPDM’s’ various subunit interfaces. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 19 ++++- drivers/hwtracing/coresight/coresight-tpdm.c | 98 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 7 ++ 3 files changed, 123 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 74a0126..ee41a14 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -185,4 +185,21 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : Set the DSB pattern type to value. - 1 : Set the DSB pattern type to toggle. \ No newline at end of file + 1 : Set the DSB pattern type to toggle. + +What: /sys/bus/coresight/devices//dsb_msr_idx +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read/Write the index number of MSR(mux select register) on DSB + TPDM. This index number should not be greater than the number + of MSR supported by this DSB TPDM. + +What: /sys/bus/coresight/devices//dsb_msr +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the MSR(mux select register) of DSB tpdm. Read + the MSR(mux select register) of DSB tpdm. \ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index f9e5a1d..be7776b 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -90,6 +90,18 @@ static void set_dsb_tier(struct tpdm_drvdata *drvdata, u32 *val) } +static void set_dsb_msr(struct tpdm_drvdata *drvdata) +{ + int i; + + if (drvdata->dsb->msr_num == 0) + return; + + for (i = 0; i < drvdata->dsb->msr_num; i++) + writel_relaxed(drvdata->dsb->msr[i], + drvdata->base + TPDM_DSB_MSR(i)); +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val, i; @@ -116,6 +128,8 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) set_dsb_tier(drvdata, &val); writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); + set_dsb_msr(drvdata); + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); /* Set the test accurate mode */ set_dsb_test_mode(drvdata, &val); @@ -234,6 +248,14 @@ static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) if (!drvdata->dsb) return -ENOMEM; } + if (!of_property_read_u32(drvdata->dev->of_node, + "qcom,dsb_msr_num", &drvdata->dsb->msr_num)) { + drvdata->dsb->msr = devm_kzalloc(drvdata->dev, + (drvdata->dsb->msr_num * sizeof(*drvdata->dsb->msr)), + GFP_KERNEL); + if (!drvdata->dsb->msr) + return -ENOMEM; + } } return 0; @@ -830,6 +852,80 @@ static ssize_t dsb_trig_ts_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_trig_ts); +static ssize_t dsb_msr_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->msr_idx); + +} + +static ssize_t dsb_msr_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index; + + if (kstrtoul(buf, 0, &index)) + return -EINVAL; + if (index >= drvdata->dsb->msr_num) + return -EPERM; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->msr_idx = index; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_msr_idx); + +static ssize_t dsb_msr_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned int i; + unsigned long bytes; + ssize_t size = 0; + + if (drvdata->dsb->msr_num == 0) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < drvdata->dsb->msr_num; i++) { + bytes = sysfs_emit_at(buf, size, + "0x%x\n", drvdata->dsb->msr[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + + return size; +} + +static ssize_t dsb_msr_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->msr[drvdata->dsb->msr_idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_msr); + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_edge_ctrl_idx.attr, @@ -845,6 +941,8 @@ static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_trig_patt_mask.attr, &dev_attr_dsb_trig_ts.attr, &dev_attr_dsb_trig_type.attr, + &dev_attr_dsb_msr_idx.attr, + &dev_attr_dsb_msr.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 7c52cf4..7b70db3 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -18,6 +18,7 @@ #define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) #define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) +#define TPDM_DSB_MSR(n) (0x980 + (n * 4)) /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) @@ -100,6 +101,9 @@ * @patt_mask: Save value for pattern mask * @trig_patt: Save value for trigger pattern * @trig_patt_mask: Save value for trigger pattern mask + * @msr_num Number of MSR supported by DSB TPDM + * @msr_idx Index number of the MSR + * @msr Save value for MSR * @patt_ts: Enable/Disable pattern timestamp * @patt_type: Set pattern type * @trig_ts: Enable/Disable trigger timestamp. @@ -116,6 +120,9 @@ struct dsb_dataset { u32 patt_mask[TPDM_DSB_MAX_PATT]; u32 trig_patt[TPDM_DSB_MAX_PATT]; u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; + u32 msr_num; + u32 msr_idx; + u32 *msr; bool patt_ts; bool patt_type; bool trig_ts;