From patchwork Mon Jul 24 10:10:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 124826 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp1725298vqg; Mon, 24 Jul 2023 04:15:52 -0700 (PDT) X-Google-Smtp-Source: APBJJlF3eoZ1jJiEOCE7/kQTJdwwjCy5uKnOg656q7NZZ5enHEH3fEfDopnoe2nYtCuyFq0wViVN X-Received: by 2002:a17:906:3147:b0:975:63f4:46 with SMTP id e7-20020a170906314700b0097563f40046mr9349955eje.57.1690197352430; Mon, 24 Jul 2023 04:15:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690197352; cv=none; d=google.com; s=arc-20160816; b=Sxn3ndYpEPUMmCDTJk/8Fs18BvH1RFNSWNYKIfYoaFbrZ4ErnsFrsvizqOJiB4CJlm ybIH5yG6JZgV1k4XfXFLnX7m3ya1Dk+vsgzG+qfL7zHQc6XgpGxs9/TpVftucUK8a3Bu 37LyfE12W93hoOXHjOHaph+ZlYoKsE6YRKx7m061Lv03fZSnE0X8YJ+SK2/jjRlHjtx4 /I5iSeTu7cjNfgT2BwRDMldXP3Faulf6CatgVwZ/nepEhSY7Nk5XPSecJASUmSIMb0T7 dgyHGolOEYxDT80+7e+cQE8crMnfGGGutZRDKbPZ3vDy6oi5LIpoKPawgHiN7TL32Rm3 MFaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=JvR6uAO8gSzRwXBZKvRGti9xH8tFyrwQk57/j730c5A=; fh=KMHIlvMyk955GAHEXyGRN89XCb+h1B+4yCIVAgCT/kI=; b=sblZlYDPscD1tofRG1tP10EVqUujNT5Cyt/ZAuZEwF/gFa7b+9vpRlcJOIPPBiJm3N CevI/CKeiDsPJyA4fmP+tdkEaChJR+fvRTBq2axAkinpVF3aimbl6hb1wwO3ENowc3U0 20D7VcQm7cTElzKq1hkPX059EGrna5vn6DYR6373zvjWJQ78EZByh6gvdEUfhi+3wwOW g9HscK+k1XTpi+RBpwiHBswLQ5as4/BUAqXhleAvDPt7ZisA/VPBBVQ0Vx705V9itStq pp0e9vw4QHgjIDAmFu9RNKGft8cYQ3Wdol4oQsDd07u6eTVD00DlHf3U+gQw2cHCV8+P JBFw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y17-20020a17090668d100b00992d6fae2bfsi6381960ejr.953.2023.07.24.04.15.27; Mon, 24 Jul 2023 04:15:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232000AbjGXKT4 convert rfc822-to-8bit (ORCPT + 99 others); Mon, 24 Jul 2023 06:19:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233582AbjGXKSg (ORCPT ); Mon, 24 Jul 2023 06:18:36 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4860593D8; Mon, 24 Jul 2023 03:10:58 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id E691424E350; Mon, 24 Jul 2023 18:10:56 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 24 Jul 2023 18:10:56 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 24 Jul 2023 18:10:55 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Linus Walleij , William Qiu Subject: [PATCH v3 1/2] dt-bindings: spi: add reference file to YAML Date: Mon, 24 Jul 2023 18:10:53 +0800 Message-ID: <20230724101054.25268-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724101054.25268-1-william.qiu@starfivetech.com> References: <20230724101054.25268-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772300378790305092 X-GMAIL-MSGID: 1772300378790305092 In JH7110 SoC, the spi module needs to use "arm,primecell-periphid" to override the h/w ID value to correctly init "spi_dev", so add "primecell.yaml" as the reference file for YAML. Signed-off-by: William Qiu --- Documentation/devicetree/bindings/spi/spi-pl022.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/spi-pl022.yaml b/Documentation/devicetree/bindings/spi/spi-pl022.yaml index 91e540a92faf..5e5a704a766e 100644 --- a/Documentation/devicetree/bindings/spi/spi-pl022.yaml +++ b/Documentation/devicetree/bindings/spi/spi-pl022.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: spi-controller.yaml# + - $ref: /schemas/arm/primecell.yaml# # We need a select here so we don't match all nodes with 'arm,primecell' select: From patchwork Mon Jul 24 10:10:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 124802 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp1721310vqg; Mon, 24 Jul 2023 04:08:24 -0700 (PDT) X-Google-Smtp-Source: APBJJlH9Uzxkfoah7A/kMZFoBRs2+wdedsBguvSG2EaPyycC19/j3KPyrhk1prf0rOEZeFeQKiPf X-Received: by 2002:a05:6512:310f:b0:4fb:7be5:4870 with SMTP id n15-20020a056512310f00b004fb7be54870mr4213071lfb.46.1690196903845; Mon, 24 Jul 2023 04:08:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690196903; cv=none; d=google.com; s=arc-20160816; b=Dm6r/qeG97tTnDxNAChjRISTiwsQt5IISprDzGnpLyUDZKm7m0a+YB0F21peyjQgCu efGkQSGqCn24W9D2S79p2VZhqhs66HewjDHYn1S7utfHh1nwx6Cp3JZnuHqcyOvXc7/V gwruSVDEIFgxmZuxqGJOuwNm8u8VZg5ffqdlUV1r0FCrCn0gfDsQPvIdZXbK/kKnAn/U Ti5CeGMHlxY23wqrDZ9rQ0IJyXJLxzFM6lPBcjNWv+HwmpA0Z7bM1VK7/ynhmGMWrr05 IcXITom2ee7yN9JwIwnFnGf3OL9OeCO3l7ajTaxr7kHI4H7KcKr0U56HxKOw8x/QGRIX hegA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=+6ScLQGb5MJTY4LxzgF8146FwRHBJXm24H+exrp45E4=; fh=KMHIlvMyk955GAHEXyGRN89XCb+h1B+4yCIVAgCT/kI=; b=P1iXE43pg8OFC68rllxWaoV2O3ErFb3GRNQuQPKJcPXgg6/qCnDmXsU4EPWQV0JCwe rygF4AiFWjQh1R2ZR9C/2q3izjZ+9FXoRPA2hc8ukbKa4LB3ij8IOUB5fxJhFzCD62Is PvX1Y85yO215wEu11+yBEnaWW0MOVe0VzRtIG/uhHmamIrI6htx5rwz5+Mmvvv7OvadC 1/y8/ShsBDn0n6wQ4elpAOQk6DmPONiYl4YkxYKItuiWr2EKZV4erubzWJTFE4TQ6Z3d A8lq80dE5cCt0JWPAWneMV046hm49IDID78B1zBEWL+F+8V8Wmaf7pAvkp/AYprIISr0 t95A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w23-20020a50fa97000000b005223d45ef1esi59678edr.692.2023.07.24.04.07.38; Mon, 24 Jul 2023 04:08:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231881AbjGXKTN convert rfc822-to-8bit (ORCPT + 99 others); Mon, 24 Jul 2023 06:19:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233588AbjGXKSi (ORCPT ); Mon, 24 Jul 2023 06:18:38 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63A4993E0; Mon, 24 Jul 2023 03:11:00 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 9E71D7FD6; Mon, 24 Jul 2023 18:10:57 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 24 Jul 2023 18:10:57 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 24 Jul 2023 18:10:56 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Linus Walleij , William Qiu Subject: [PATCH v3 2/2] riscv: dts: starfive: Add spi node and pins configuration Date: Mon, 24 Jul 2023 18:10:54 +0800 Message-ID: <20230724101054.25268-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724101054.25268-1-william.qiu@starfivetech.com> References: <20230724101054.25268-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772299908657162794 X-GMAIL-MSGID: 1772299908657162794 Add StarFive JH7110 SPI controller node and pins configuration on VisionFive 2 board. Signed-off-by: William Qiu Reviewed-by: Krzysztof Kozlowski --- .../jh7110-starfive-visionfive-2.dtsi | 50 +++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 105 ++++++++++++++++++ 2 files changed, 155 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index fa0061eb33a7..9e6ccf460877 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -143,6 +143,18 @@ &i2c6 { status = "okay"; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + spi_dev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins { @@ -200,6 +212,44 @@ GPOEN_SYS_I2C6_DATA, }; }; + spi0_pins: spi0-0 { + mosi-pins { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + miso-pins { + pinmux = ; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + + sck-pins { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + ss-pins { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + }; + uart0_pins: uart0-0 { tx-pins { pinmux = ; + clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>, + <&syscrg JH7110_SYSCLK_SPI0_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI0_APB>; + interrupts = <38>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@10070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>, + <&syscrg JH7110_SYSCLK_SPI1_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI1_APB>; + interrupts = <39>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@10080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10080000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>, + <&syscrg JH7110_SYSCLK_SPI2_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI2_APB>; + interrupts = <40>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; @@ -473,6 +518,66 @@ i2c6: i2c@12060000 { status = "disabled"; }; + spi3: spi@12070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>, + <&syscrg JH7110_SYSCLK_SPI3_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI3_APB>; + interrupts = <52>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@12080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12080000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>, + <&syscrg JH7110_SYSCLK_SPI4_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI4_APB>; + interrupts = <53>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@12090000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12090000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>, + <&syscrg JH7110_SYSCLK_SPI5_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI5_APB>; + interrupts = <54>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@120a0000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x120A0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>, + <&syscrg JH7110_SYSCLK_SPI6_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI6_APB>; + interrupts = <55>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + syscrg: clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x0 0x13020000 0x0 0x10000>;