From patchwork Sun Jul 23 13:54:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 124457 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp1267827vqg; Sun, 23 Jul 2023 06:55:12 -0700 (PDT) X-Google-Smtp-Source: APBJJlHgyy8e3M/5o3uRr3WBb8IFAxI/2Oa2BnLcoMcCt3w5zjvxq2mPPq5Ib8nKhFYnnD0jiGsq X-Received: by 2002:a17:907:7614:b0:997:deb1:ff6a with SMTP id jx20-20020a170907761400b00997deb1ff6amr6568069ejc.22.1690120512201; Sun, 23 Jul 2023 06:55:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690120512; cv=none; d=google.com; s=arc-20160816; b=x93NekJtYauIBHwPFqeL6vDArV+12WWabkK0pAd9VAWWKDpphUhvrBRrvk9NqCUhWk LjoJCPLp+BDIKmvTeFCa4HBOA06dhdYX4FGq/MDZlqo42oUaucV/jOElpoC8LVzRZrBA rRawVq8N/JeNUCmMXEVweq5tEPWjvWLhtbHimAGsSh1W/uyw+Wm6eGN9C9oWHL39CyR3 NjcR4NmGkunqJ3H1JIqn0tPP066+PNLPZLKCrNRMIdxtAxYuY5xCkscEAA4MFllMJA1K 4m5fPGU/YF+6rTdZDx+NbQ4lMcloctQat4bhc2ZyfAluXxFsNPvo2ryeHhQhDPdI82LI imnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=nV4gwo48LxY4GUhoHDWNyGWFieBVlWc/K72volx1PhI=; fh=9EZcvfVI324lLsRm78AR5trG4A9hqVpSpoTtyXFX1N4=; b=Ln4+3oG/jWs2NtNMnz1PlPpx/ATfRh2kQnQbLwsxKUzDEcridj25ecOVxOZHqn/xnE NOulUNJRVSFRlkdvsS742ngNFZPu++vihFihuvlTsSBvYDZhnFEHtaUOeWjgbNh3XQc1 eO/3zMq6bZeK/2W+lPeQQy/sgf8NtZSlLO7PiHFx0yphuCwFkUUJNY8IRGx1+BLrED2D CxbsJi3N6Giq7mR5/bcehSYaz0syU8fhWHl7FDXp3a6reQc9rqlXPHVjtfzH1+x022PJ c7LgPo0EmrdZxRBJNtYkV6ZLrlXzAT3nAN6NizXJo3/imps6HC//DezI59hwYqiYDyOL wk9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=uW3Sel4o; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id c20-20020a170906341400b0099363f18293si4555329ejb.124.2023.07.23.06.55.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Jul 2023 06:55:12 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=uW3Sel4o; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DF6B33858431 for ; Sun, 23 Jul 2023 13:55:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DF6B33858431 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690120510; bh=nV4gwo48LxY4GUhoHDWNyGWFieBVlWc/K72volx1PhI=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=uW3Sel4oVFKy++LO/r3GqhCXIAv1KwksolQEjJDtuxkT3Jdpv3p43X5RXfRWo40BM H78KXmzaZ8H1XE38YqCOgd77oho+9221W9NvbMEXAWbkfEmW6U9qAtKbWsYk/WNRHo qOV2+YtzLTjm99vYe7I0vzDztInyAXTr4zpZGZmk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id D9EBF3858D28 for ; Sun, 23 Jul 2023 13:54:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D9EBF3858D28 X-IronPort-AV: E=McAfee;i="6600,9927,10780"; a="431076467" X-IronPort-AV: E=Sophos;i="6.01,226,1684825200"; d="scan'208";a="431076467" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2023 06:54:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10780"; a="971967400" X-IronPort-AV: E=Sophos;i="6.01,226,1684825200"; d="scan'208";a="971967400" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga006.fm.intel.com with ESMTP; 23 Jul 2023 06:54:22 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 255FB10080C8; Sun, 23 Jul 2023 21:54:22 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix for allowing incorrect dyn for static rounding Date: Sun, 23 Jul 2023 21:54:21 +0800 Message-Id: <20230723135421.3723462-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772219806119901680 X-GMAIL-MSGID: 1772219806119901680 From: Pan Li According to the spec, dyn rounding mode is invalid for RVV floating-point, this patch would like to fix this. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_frm_def): Take range check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-error.c: Update cases. * gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: Removed. Signed-off-by: Pan Li --- .../riscv/riscv-vector-builtins-shapes.cc | 3 +- .../riscv/rvv/base/float-point-frm-error.c | 6 ++-- .../riscv/rvv/base/float-point-frm-insert-6.c | 33 ------------------- 3 files changed, 4 insertions(+), 38 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 69a67106418..22b5fe256df 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -285,8 +285,7 @@ struct alu_frm_def : public build_base { unsigned int frm_num = c.arg_num () - 2; - return c.require_immediate_range_or (frm_num, FRM_STATIC_MIN, - FRM_STATIC_MAX, FRM_DYN); + return c.require_immediate (frm_num, FRM_STATIC_MIN, FRM_STATIC_MAX); } return true; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c index 4ebaa15ab0b..01d82d4e661 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c @@ -7,9 +7,9 @@ typedef float float32_t; void test_float_point_frm_error (float32_t *out, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { - vfloat32m1_t v1 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg-error {passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ - vfloat32m1_t v2 = __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg-error {passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ - vfloat32m1_t v3 = __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg-error {passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ + vfloat32m1_t v1 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg-error {passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\]} } */ + vfloat32m1_t v2 = __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg-error {passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\]} } */ + vfloat32m1_t v3 = __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg-error {passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\]} } */ __riscv_vse32_v_f32m1 (out, v3, vl); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c deleted file mode 100644 index 1ef0e015d8f..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c +++ /dev/null @@ -1,33 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ - -#include "riscv_vector.h" - -typedef float float32_t; - -vfloat32m1_t -test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { - return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, - size_t vl) { - return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) { - return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, - size_t vl) { - return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl); -} - -/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ -/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */ -/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */ -/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */