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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id v4-20020adff684000000b0031431fb40fasm6694886wrp.89.2023.07.22.04.35.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Jul 2023 04:35:03 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrew Jones , Conor Dooley , Sunil V L , Song Shuai , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Atish Patra Subject: [PATCH v5 1/3] Documentation: arm: Add bootargs to the table of added DT parameters Date: Sat, 22 Jul 2023 13:34:43 +0200 Message-Id: <20230722113445.630714-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772121474484168803 X-GMAIL-MSGID: 1772121474484168803 The bootargs node is also added by the EFI stub in the function update_fdt(), so add it to the table. Signed-off-by: Alexandre Ghiti Reviewed-by: Atish Patra Reviewed-by: Song Shuai --- - Changes in v5: * Rebase on top of docs-next Documentation/arch/arm/uefi.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/arm/uefi.rst b/Documentation/arch/arm/uefi.rst index baebe688a006..2b7ad9bd7cd2 100644 --- a/Documentation/arch/arm/uefi.rst +++ b/Documentation/arch/arm/uefi.rst @@ -50,7 +50,7 @@ The stub populates the FDT /chosen node with (and the kernel scans for) the following parameters: ========================== ====== =========================================== -Name Size Description +Name Type Description ========================== ====== =========================================== linux,uefi-system-table 64-bit Physical address of the UEFI System Table. @@ -67,4 +67,6 @@ linux,uefi-mmap-desc-ver 32-bit Version of the mmap descriptor format. kaslr-seed 64-bit Entropy used to randomize the kernel image base address location. + +bootargs String Kernel command line ========================== ====== =========================================== From patchwork Sat Jul 22 11:34:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 124305 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp779105vqg; Sat, 22 Jul 2023 05:35:55 -0700 (PDT) X-Google-Smtp-Source: APBJJlGs5tj+WxgZMTgPXksqWp7lJvFuNrvm8OxYlAaHoSFaMARihNY0NcPB7cX1RrImjSVmOAZK X-Received: by 2002:a17:903:24c:b0:1bb:2ccc:c321 with SMTP id j12-20020a170903024c00b001bb2cccc321mr4844803plh.48.1690029355531; Sat, 22 Jul 2023 05:35:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690029355; cv=none; d=google.com; s=arc-20160816; b=PAlM1gzg4e4WBBZ7a+ulA0sygYIMLVaT6PNKQRdErDiOVqSP7WhrFKBZsScxD6RkFf wFWoZaHt2VAud0e6sjBusDjSjOEYNhYrNkO27pJjlB+9hcAtN/eyXRg53sZNSMs8X4/F zzoDdTxPhxnBvd0Zd7Im8faHH1NRNjuaJYKI8xpZxHIB+si+4Gy/EM8jhW+8fXYrrDg3 iLdUYOySP/52M5CCCfM13BvbVwrJr4ULEYUofoKORl6w8X2CZ1wPqftL8N2epWRoE5gS ypYIc7f+IIouI5Z5xttkq4+5WYOb0yS7aODfI1DYaOsFE1wUCw+AcHt9WzJ2pze+I2eH /euw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tClH+/vlnZHyJoQAaBUK6IjRTXTlSAczbSsv8EGYQts=; fh=nDyOn/teIaAVQOEx7JEYWBOtI5npDjLN+wDsbKWewe4=; b=IShMeBDws3j7aDvTzpUeUFKIQ93UIeeiPU7GFdAYDRKJycqgx3JS/rdDNyoWUPeJY0 JIMSv3RhvEwot8jFIDRbo7aTA3C4jObUj+3VQ9YIVf297sb3FGCJNuCyyDxgHHpVOEe4 m6q4RChCqtHkLMh8y1/8fHFGCjwBFpA3jmbTR3J1Vhu0Y9Jlet40rGaNKgNvDK/KhyJE 7jVmz6blnUw2j6HlgMV4xfVozNTx4J0aZetCznjncE7cpckPssScX4W8y1g1KhAR7nop xSvqoW9J9sFzaHxE4didv13/4t9UuYyjRhu3YIkFFYssPF+XIGxRVu/F0Ax4xuo3ma/6 eVyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=g2gAh8Sy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id e22-20020a5d5956000000b003063db8f45bsm6715616wri.23.2023.07.22.04.36.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Jul 2023 04:36:04 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrew Jones , Conor Dooley , Sunil V L , Song Shuai , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Palmer Dabbelt , Atish Patra Subject: [PATCH v5 2/3] Documentation: riscv: Add early boot document Date: Sat, 22 Jul 2023 13:34:44 +0200 Message-Id: <20230722113445.630714-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230722113445.630714-1-alexghiti@rivosinc.com> References: <20230722113445.630714-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772124221334337284 X-GMAIL-MSGID: 1772124221334337284 This document describes the constraints and requirements of the early boot process in a RISC-V kernel. Signed-off-by: Alexandre Ghiti Reviewed-by: Björn Töpel Reviewed-by: Conor Dooley Reviewed-by: Sunil V L Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt Reviewed-by: Atish Patra Reviewed-by: Song Shuai Acked-by: Palmer Dabbelt Reviewed-by: Randy Dunlap --- - Changes in v5: * Rebase on top of docs-next Documentation/riscv/boot-image-header.rst | 3 - Documentation/riscv/boot.rst | 169 ++++++++++++++++++++++ Documentation/riscv/index.rst | 1 + 3 files changed, 170 insertions(+), 3 deletions(-) create mode 100644 Documentation/riscv/boot.rst diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/riscv/boot-image-header.rst index d7752533865f..a4a45310c4c4 100644 --- a/Documentation/riscv/boot-image-header.rst +++ b/Documentation/riscv/boot-image-header.rst @@ -7,9 +7,6 @@ Boot image header in RISC-V Linux This document only describes the boot image header details for RISC-V Linux. -TODO: - Write a complete booting guide. - The following 64-byte header is present in decompressed Linux kernel image:: u32 code0; /* Executable code */ diff --git a/Documentation/riscv/boot.rst b/Documentation/riscv/boot.rst new file mode 100644 index 000000000000..f890ac442c91 --- /dev/null +++ b/Documentation/riscv/boot.rst @@ -0,0 +1,169 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=============================================== +RISC-V Kernel Boot Requirements and Constraints +=============================================== + +:Author: Alexandre Ghiti +:Date: 23 May 2023 + +This document describes what the RISC-V kernel expects from bootloaders and +firmware, but also the constraints that any developer must have in mind when +touching the early boot process. For the purposes of this document, the +``early boot process`` refers to any code that runs before the final virtual +mapping is set up. + +Pre-kernel Requirements and Constraints +======================================= + +The RISC-V kernel expects the following of bootloaders and platform firmware: + +Register state +-------------- + +The RISC-V kernel expects: + + * ``$a0`` to contain the hartid of the current core. + * ``$a1`` to contain the address of the devicetree in memory. + +CSR state +--------- + +The RISC-V kernel expects: + + * ``$satp = 0``: the MMU, if present, must be disabled. + +Reserved memory for resident firmware +------------------------------------- + +The RISC-V kernel must not map any resident memory, or memory protected with +PMPs, in the direct mapping, so the firmware must correctly mark those regions +as per the devicetree specification and/or the UEFI specification. + +Kernel location +--------------- + +The RISC-V kernel expects to be placed at a PMD boundary (2MB aligned for rv64 +and 4MB aligned for rv32). Note that the EFI stub will physically relocate the +kernel if that's not the case. + +Hardware description +-------------------- + +The firmware can pass either a devicetree or ACPI tables to the RISC-V kernel. + +The devicetree is either passed directly to the kernel from the previous stage +using the ``$a1`` register, or when booting with UEFI, it can be passed using the +EFI configuration table. + +The ACPI tables are passed to the kernel using the EFI configuration table. In +this case, a tiny devicetree is still created by the EFI stub. Please refer to +"EFI stub and devicetree" section below for details about this devicetree. + +Kernel entrance +--------------- + +On SMP systems, there are 2 methods to enter the kernel: + +- ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart + wins a lottery and executes the early boot code while the other harts are + parked waiting for the initialization to finish. This method is mostly used to + support older firmwares without SBI HSM extension and M-mode RISC-V kernel. +- ``Ordered booting``: the firmware releases only one hart that will execute the + initialization phase and then will start all other harts using the SBI HSM + extension. The ordered booting method is the preferred booting method for + booting the RISC-V kernel because it can support cpu hotplug and kexec. + +UEFI +---- + +UEFI memory map +~~~~~~~~~~~~~~~ + +When booting with UEFI, the RISC-V kernel will use only the EFI memory map to +populate the system memory. + +The UEFI firmware must parse the subnodes of the ``/reserved-memory`` devicetree +node and abide by the devicetree specification to convert the attributes of +those subnodes (``no-map`` and ``reusable``) into their correct EFI equivalent +(refer to section "3.5.4 /reserved-memory and UEFI" of the devicetree +specification v0.4-rc1). + +RISCV_EFI_BOOT_PROTOCOL +~~~~~~~~~~~~~~~~~~~~~~~ + +When booting with UEFI, the EFI stub requires the boot hartid in order to pass +it to the RISC-V kernel in ``$a1``. The EFI stub retrieves the boot hartid using +one of the following methods: + +- ``RISCV_EFI_BOOT_PROTOCOL`` (**preferred**). +- ``boot-hartid`` devicetree subnode (**deprecated**). + +Any new firmware must implement ``RISCV_EFI_BOOT_PROTOCOL`` as the devicetree +based approach is deprecated now. + +Early Boot Requirements and Constraints +======================================= + +The RISC-V kernel's early boot process operates under the following constraints: + +EFI stub and devicetree +----------------------- + +When booting with UEFI, the devicetree is supplemented (or created) by the EFI +stub with the same parameters as arm64 which are described at the paragraph +"UEFI kernel support on ARM" in Documentation/arm/uefi.rst. + +Virtual mapping installation +---------------------------- + +The installation of the virtual mapping is done in 2 steps in the RISC-V kernel: + +1. ``setup_vm()`` installs a temporary kernel mapping in ``early_pg_dir`` which + allows discovery of the system memory. Only the kernel text/data are mapped + at this point. When establishing this mapping, no allocation can be done + (since the system memory is not known yet), so ``early_pg_dir`` page table is + statically allocated (using only one table for each level). + +2. ``setup_vm_final()`` creates the final kernel mapping in ``swapper_pg_dir`` + and takes advantage of the discovered system memory to create the linear + mapping. When establishing this mapping, the kernel can allocate memory but + cannot access it directly (since the direct mapping is not present yet), so + it uses temporary mappings in the fixmap region to be able to access the + newly allocated page table levels. + +For ``virt_to_phys()`` and ``phys_to_virt()`` to be able to correctly convert +direct mapping addresses to physical addresses, they need to know the start of +the DRAM. This happens after step 1, right before step 2 installs the direct +mapping (see ``setup_bootmem()`` function in arch/riscv/mm/init.c). Any usage of +those macros before the final virtual mapping is installed must be carefully +examined. + +Devicetree mapping via fixmap +----------------------------- + +As the ``reserved_mem`` array is initialized with virtual addresses established +by ``setup_vm()``, and used with the mapping established by +``setup_vm_final()``, the RISC-V kernel uses the fixmap region to map the +devicetree. This ensures that the devicetree remains accessible by both virtual +mappings. + +Pre-MMU execution +----------------- + +A few pieces of code need to run before even the first virtual mapping is +established. These are the installation of the first virtual mapping itself, +patching of early alternatives and the early parsing of the kernel command line. +That code must be very carefully compiled as: + +- ``-fno-pie``: This is needed for relocatable kernels which use ``-fPIE``, + since otherwise, any access to a global symbol would go through the GOT which + is only relocated virtually. +- ``-mcmodel=medany``: Any access to a global symbol must be PC-relative to + avoid any relocations to happen before the MMU is setup. +- *all* instrumentation must also be disabled (that includes KASAN, ftrace and + others). + +As using a symbol from a different compilation unit requires this unit to be +compiled with those flags, we advise, as much as possible, not to use external +symbols. diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst index 81cf6e616476..4dab0cb4b900 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/riscv/index.rst @@ -6,6 +6,7 @@ RISC-V architecture :maxdepth: 1 acpi + boot boot-image-header vm-layout hwprobe From patchwork Sat Jul 22 11:34:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 124287 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp767238vqg; Sat, 22 Jul 2023 05:10:09 -0700 (PDT) X-Google-Smtp-Source: APBJJlHgb18Dop5VadkPbANIXpBC0KM71IlCQ7/a7zfkC6unA/G8Cw4T9z+0I7cteh0nlXcwQ0bu X-Received: by 2002:a05:6a20:4411:b0:137:514a:9835 with SMTP id ce17-20020a056a20441100b00137514a9835mr4104311pzb.9.1690027808813; Sat, 22 Jul 2023 05:10:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690027808; cv=none; d=google.com; s=arc-20160816; b=r8teHPAReiclVWM9MRpP4rLPOI0rzH8kI59Ale0fuLk3lNGVRL3vA047H4QYTLAGKG e+1d8eUs/+hjSzhQvgJPbhypBNH/K46tjicpaylyrjtChxQeXU9AU/oLnUQeIj5aevIG 65fi/+0X48A/9m38bX16itFb6zncPyGehD4K04fcTZ0Rc6/YSnGCCN0fJp57z5toBlBX MHNxS/79rrr0lYCgvAzw0SIQAroon/EGTpMH0tOwDiCylD1WToGvlUGRtfbqym/Me4Uq 0tcOPqMT/8mE6sCXgrwVpP0pGuYMqyk02Xc/ozRdjejW1hX4N+Rd5UoIgMYhPJvAe1Rc 3MYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dia79abijhqNuyOI1X7cuUqq5ei10OSh1lyxFY8ZqEI=; fh=Clb7LPnjuTHOVWIvadS5v7u+8I+/lQAzizaZjL19cCc=; b=j3KHgK5fRaujGa+IZ5tA16UVqyqL2lZ9KeVIMq4vrKFrA2DZCiHNHMYYQYzNLzlh1m SKk68Pu3ndWR12X9ZNIeHTKOlX/F3eNlpfriOe1VLGZznzRTvEBPgGPMVw4ZAkjn2K/8 EC2ckG0Q7Z6G8e7BcQ+fDymwyN1kP/F20Xa+yPDxR8KeJKLMdwNnwjrHnep6GIo1D0U9 mZPpbvzu1pN+0V+SNPfyGU98bT+TFKEde+wH25apyigJ1qXU3WTDFczjKHdIVYNtesh4 TuOoJkN2Ob3XxcbBM3fnmY0u7cGujPreC0A7JfZgqtm6kSySMbl9AXkNOUMfoQH7yGY4 7Y8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=gFee1fF2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id c16-20020adfe750000000b0030fb828511csm6728788wrn.100.2023.07.22.04.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Jul 2023 04:37:05 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrew Jones , Conor Dooley , Sunil V L , Song Shuai , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Atish Patra , Palmer Dabbelt Subject: [PATCH v5 3/3] Documentation: riscv: Update boot image header since EFI stub is supported Date: Sat, 22 Jul 2023 13:34:45 +0200 Message-Id: <20230722113445.630714-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230722113445.630714-1-alexghiti@rivosinc.com> References: <20230722113445.630714-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772122599643999758 X-GMAIL-MSGID: 1772122599643999758 The EFI stub is supported on RISC-V so update the documentation that explains how the boot image header was reused to support it. Signed-off-by: Alexandre Ghiti Reviewed-by: Atish Patra Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- - Changes in v5: * Rebase on top of docs-next Documentation/riscv/boot-image-header.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/riscv/boot-image-header.rst index a4a45310c4c4..df2ffc173e80 100644 --- a/Documentation/riscv/boot-image-header.rst +++ b/Documentation/riscv/boot-image-header.rst @@ -28,11 +28,11 @@ header in future. Notes ===== -- This header can also be reused to support EFI stub for RISC-V in future. EFI - specification needs PE/COFF image header in the beginning of the kernel image - in order to load it as an EFI application. In order to support EFI stub, - code0 should be replaced with "MZ" magic string and res3(at offset 0x3c) should - point to the rest of the PE/COFF header. +- This header is also reused to support EFI stub for RISC-V. EFI specification + needs PE/COFF image header in the beginning of the kernel image in order to + load it as an EFI application. In order to support EFI stub, code0 is replaced + with "MZ" magic string and res3(at offset 0x3c) points to the rest of the + PE/COFF header. - version field indicate header version number