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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id x9-20020ac259c9000000b004fbf5242e8bsm1107034lfn.231.2023.07.22.01.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Jul 2023 01:52:53 -0700 (PDT) From: Konrad Dybcio Date: Sat, 22 Jul 2023 10:52:45 +0200 Subject: [PATCH 1/3] dt-bindings: pinctrl: qcom,sm6115-lpass-lpi: add SM6115 LPASS TLMM MIME-Version: 1.0 Message-Id: <20230722-topic-6115_lpasstlmm-v1-1-32d1643d8774@linaro.org> References: <20230722-topic-6115_lpasstlmm-v1-0-32d1643d8774@linaro.org> In-Reply-To: <20230722-topic-6115_lpasstlmm-v1-0-32d1643d8774@linaro.org> To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Catalin Marinas , Will Deacon Cc: Marijn Suijten , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690015971; l=4326; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=c43yKRy0X3J5bR0oJzd2QzC0RF8oja+5GuFLw0rnLyM=; b=iVWBp23i34c79z8+M30T/6QTmi7ZvcvfJOz4DOcbFsetM4DlLtYcHMx7GHiGwEO/BEDqUfTHf da1bCH1Q/V+D3poxjeyBpMA0fOkaE/ObabBdbVr0EHNNcQ1T3CliTtQ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772112262736176309 X-GMAIL-MSGID: 1772112262736176309 Add bindings for pin controller in SM6115 Low Power Audio SubSystem LPASS). Signed-off-by: Konrad Dybcio --- .../pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml | 135 +++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..1fe876e6bd66 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 SoC LPASS LPI TLMM + +maintainers: + - Konrad Dybcio + - Srinivas Kandagatla + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM6115 SoC. + +properties: + compatible: + const: qcom,sm6115-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Audio voting clock + + clock-names: + items: + - const: audio + + gpio-controller: true + + "#gpio-cells": + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6115-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6115-lpass-state" + additionalProperties: false + +$defs: + qcom-sm6115-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ dmic01_clk, dmic01_data, dmic23_clk, dmic23_data, gpio, i2s1_clk, + i2s1_data, i2s1_ws, i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, + i2s3_data, i2s3_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_mclk ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-bus-hold: true + bias-pull-down: true + bias-pull-up: true + bias-disable: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + + lpass_tlmm: pinctrl@a7c0000 { + compatible = "qcom,sm6115-lpass-lpi-pinctrl"; + reg = <0x0a7c0000 0x20000>, + <0x0a950000 0x10000>; + clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + }; From patchwork Sat Jul 22 08:52:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 124251 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp706023vqg; Sat, 22 Jul 2023 02:21:36 -0700 (PDT) X-Google-Smtp-Source: APBJJlGz+qbWLGCb0qkQLMxjngXWHQ+3V7oYV9VrnxrMbAUzRmZpiilLR6A5552UUwM5IxbIJhlT X-Received: by 2002:a05:6808:10d1:b0:3a4:2829:326d with SMTP id s17-20020a05680810d100b003a42829326dmr6933575ois.14.1690017696726; Sat, 22 Jul 2023 02:21:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690017696; cv=none; d=google.com; s=arc-20160816; b=gYPuEav0lQB6t/NQYIFFLVM1L+J+zD1MwFsmU33/ke7KJIjLvfVQs6lNLL/cn4mNn3 cYR/BQeYsXbvFo5oB10VjI1fQjWVmt/TS8BGGoJG5Lrg9cfkNBp8AW3V7Ll6CYZ8XKSZ uYfUMFTd+l+8VByhynpxqfooTCwcm9Vwa17e9AULex5akfAOy2jMpbhdQrnYtbleOcaH ZPUz5gOnI+CQbr8W+a6ACqAkILag6+9spRmpB5YDw3THe/qbOkqFHVUw/ZVv6xsxew7A OBtMjNM7bIRRRar0N+428OJGi1TrXdKsOBA86ed+swTWdR/9+b2KcgK5Hy3p+G/E8Lns yUPQ== ARC-Message-Signature: i=1; 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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id x9-20020ac259c9000000b004fbf5242e8bsm1107034lfn.231.2023.07.22.01.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Jul 2023 01:52:55 -0700 (PDT) From: Konrad Dybcio Date: Sat, 22 Jul 2023 10:52:46 +0200 Subject: [PATCH 2/3] pinctrl: qcom: Introduce SM6115 LPI pinctrl driver MIME-Version: 1.0 Message-Id: <20230722-topic-6115_lpasstlmm-v1-2-32d1643d8774@linaro.org> References: <20230722-topic-6115_lpasstlmm-v1-0-32d1643d8774@linaro.org> In-Reply-To: <20230722-topic-6115_lpasstlmm-v1-0-32d1643d8774@linaro.org> To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Catalin Marinas , Will Deacon Cc: Marijn Suijten , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690015971; l=8437; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=dUlMVDn4FZ150DyZa1NExE/bjgAU68qgmu4DlhznUvU=; b=d75pp8MQv1q3z00d0F6/TjnrQmSkBQ9xWd+nml643W1bEH74VwcCLYegiefljSTAHoEmRIao7 TA9GDkbunWuB7u0wMLxIJp4Jnh1AUHP8ThzRC9ghREd7igGtjxh0sXK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772111996027440402 X-GMAIL-MSGID: 1772111996027440402 Add support for the pin controller block on SM6115's Low Power Island. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- drivers/pinctrl/qcom/Kconfig | 9 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 175 ++++++++++++++++++++++++ 3 files changed, 185 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 634c75336983..c6ef38032c05 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,15 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform. +config PINCTRL_SM6115_LPASS_LPI + tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform. + config PINCTRL_SM8250_LPASS_LPI tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 426ddbf35f32..d1179d8b2c42 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c new file mode 100644 index 000000000000..2b09bf171a2c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, 2023 Linaro Ltd. + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic01_clk, + LPI_MUX_dmic01_data, + LPI_MUX_dmic23_clk, + LPI_MUX_dmic23_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_mclk, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; +static int gpio15_pins[] = { 15 }; +static int gpio16_pins[] = { 16 }; +static int gpio17_pins[] = { 17 }; +static int gpio18_pins[] = { 18 }; + +static const struct pinctrl_pin_desc sm6115_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), +}; + +static const char * const dmic01_clk_groups[] = { "gpio6" }; +static const char * const dmic01_data_groups[] = { "gpio7" }; +static const char * const dmic23_clk_groups[] = { "gpio8" }; +static const char * const dmic23_data_groups[] = { "gpio9" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const i2s3_clk_groups[] = { "gpio14" }; +static const char * const i2s3_data_groups[] = { "gpio16", "gpio17" }; +static const char * const i2s3_ws_groups[] = { "gpio15" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2" }; +static const char * const wsa_mclk_groups[] = { "gpio18" }; + +static const struct lpi_pingroup sm6115_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, _, _), + LPI_PINGROUP(10, LPI_NO_SLEW, i2s2_clk, _, _, _), + LPI_PINGROUP(11, LPI_NO_SLEW, i2s2_ws, _, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(18, 14, wsa_mclk, _, _, _), +}; + +static const struct lpi_function sm6115_functions[] = { + LPI_FUNCTION(dmic01_clk), + LPI_FUNCTION(dmic01_data), + LPI_FUNCTION(dmic23_clk), + LPI_FUNCTION(dmic23_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_mclk), +}; + +static const struct lpi_pinctrl_variant_data sm6115_lpi_data = { + .pins = sm6115_lpi_pins, + .npins = ARRAY_SIZE(sm6115_lpi_pins), + .groups = sm6115_groups, + .ngroups = ARRAY_SIZE(sm6115_groups), + .functions = sm6115_functions, + .nfunctions = ARRAY_SIZE(sm6115_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { .compatible = "qcom,sm6115-lpass-lpi-pinctrl", .data = &sm6115_lpi_data }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm6115-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM6115 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); From patchwork Sat Jul 22 08:52:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 124257 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp710776vqg; Sat, 22 Jul 2023 02:37:28 -0700 (PDT) X-Google-Smtp-Source: APBJJlEiZU14ZOAaspnh0Vj9TKCwFR6hQE5D9XigH2Bz290uvc/QWEVJ+cUQGRU6O941UTCI7Vx8 X-Received: by 2002:a05:6808:1a26:b0:3a4:8251:5f43 with SMTP id bk38-20020a0568081a2600b003a482515f43mr5877560oib.40.1690018648263; Sat, 22 Jul 2023 02:37:28 -0700 (PDT) ARC-Seal: i=1; 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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id x9-20020ac259c9000000b004fbf5242e8bsm1107034lfn.231.2023.07.22.01.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Jul 2023 01:52:56 -0700 (PDT) From: Konrad Dybcio Date: Sat, 22 Jul 2023 10:52:47 +0200 Subject: [PATCH 3/3] arm64: defconfig: enable Qualcomm SM6115 LPASS pinctrl MIME-Version: 1.0 Message-Id: <20230722-topic-6115_lpasstlmm-v1-3-32d1643d8774@linaro.org> References: <20230722-topic-6115_lpasstlmm-v1-0-32d1643d8774@linaro.org> In-Reply-To: <20230722-topic-6115_lpasstlmm-v1-0-32d1643d8774@linaro.org> To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Catalin Marinas , Will Deacon Cc: Marijn Suijten , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690015971; l=718; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=3c7z5lg3GdcTEBcbEgugsr8/arhScheGCYc9FCflb+g=; b=iaV0Oo8qCRBQGYyEEEkhvqpIZMrYxKbgTwYDTKy7dp0vjQox3xllLm87sbnc5qQUJaSeIEeLa Yk6uRWOKKDJAFcRmgo6eMSuEL3MR5RHiz9PS08SFeSkezXHmNgeNWNF X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772112869442533176 X-GMAIL-MSGID: 1772112994077759788 Enable the Qualcomm SM6115 LPASS TLMM pin controller driver for providing GPIOs/pins for audio block on SM6115 based boards (e.g. QTI RB2). Signed-off-by: Konrad Dybcio --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6cbf6eb59378..6911101db09e 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -587,6 +587,7 @@ CONFIG_PINCTRL_SDM660=y CONFIG_PINCTRL_SDM670=y CONFIG_PINCTRL_SDM845=y CONFIG_PINCTRL_SM6115=y +CONFIG_PINCTRL_SM6115_LPASS_LPI=m CONFIG_PINCTRL_SM6125=y CONFIG_PINCTRL_SM6350=y CONFIG_PINCTRL_SM6375=y