From patchwork Fri Jul 21 21:20:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 124129 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp487580vqg; Fri, 21 Jul 2023 15:02:03 -0700 (PDT) X-Google-Smtp-Source: APBJJlHFz/c2rG1zwQ5tSj/kTfou6mBU5CCsAxmJNyN7CQrsgFdTj8TV+2q9LS7uPCiRCyY4z+4q X-Received: by 2002:a17:902:8b81:b0:1bb:7a73:6b59 with SMTP id ay1-20020a1709028b8100b001bb7a736b59mr910161plb.32.1689976923479; Fri, 21 Jul 2023 15:02:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689976923; cv=none; d=google.com; s=arc-20160816; b=eC53upTeOn4Ny3COlxMq+E5Ene2mtA05C09HsYQsjrL7Wxydb7uHYv3VaPl/t71JoM w3zp6aan66ehyYBVy0k0B8WbJe826s4LnXVkXZBsitzmGfYcxIi3HkOeE2zK9P/kjMXL LsB9cuY3+xthHeAuW6deqNKBqszyK2Zirhmc0pMxlg6QMRF2318T0rNaxjy5sa9/I4EB Fm05r4A2xregY17rW++2e6CskWz5HTMmJoIGaOCMmQE8Igx4UKIMzokiluwLw3OGz6oK BwkehAEDs8C1SkG8HZL5Y4mMh3ybSlW3aVvdg9y2xYFSwzhP7RH0KwwrhrZyg+XI19Qq X6zQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:to:from:dkim-signature; bh=v4nK1wM9bJnFLBK8DYB5LMkXWzyI0R0NAUVPmfiJkQk=; fh=cXYsyN8veLmFVTNsy36SiG+f6UWeiPuuALASZIO6gAk=; b=u3Kh4GAEYZ75IPPkwmeVWoMesKmg5WWrjRqDAdcJ5t2wyN+n4aRscqOzn+lU8xhK6G Br75ybVgA+vH8599/S0QhiGAmCTKKc8lHHKgTzqS/aOcwxacmLHW1JRWXZt2dfs5IMTc GgJ60ANtkoViQUOZ4BgSnyxElitT1JWF1dU95Yl5/DE+hUa4Ju4tC/doERIQczlXPwj7 ekeaQiactlrApqxTqEv94DR6hSunrl7bk00cFxov7kayLyYfrjk2iLCg3d5laV7sHog4 mfiTeuPyegBXPnh+p3SI8IPro7srr4IPlsHa9V6cVqyYgmRHiHbU9qtzsrOgk6hsX3T+ KpAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=WorVO4mL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=hpe.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d13-20020a170903230d00b001b9736814b6si4247272plh.309.2023.07.21.15.01.45; Fri, 21 Jul 2023 15:02:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=WorVO4mL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=hpe.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230082AbjGUVYm (ORCPT + 99 others); Fri, 21 Jul 2023 17:24:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229644AbjGUVYl (ORCPT ); Fri, 21 Jul 2023 17:24:41 -0400 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4331030D0; Fri, 21 Jul 2023 14:24:40 -0700 (PDT) Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36LLF4Yg009348; Fri, 21 Jul 2023 21:24:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version; s=pps0720; bh=v4nK1wM9bJnFLBK8DYB5LMkXWzyI0R0NAUVPmfiJkQk=; b=WorVO4mLoGIc1skC+BcSfJQhf3hlLM870S/p439/jXNBOVrrIR4FBSIR1U9wD8j6bdKX 8XAJboA1eNW4e3pW1Ar+MnUFrB+eZxcNB2lMdCqoWIWrRh+IFmo1z8qi49ZfK7Ys+2Jj nmHkCoGBQOVG2teBRMvlrFqvHh6cVXHxUjQPxt4Olk7xutgBLXon+Ld4MOC65vChc1qb O7tAaTaJpSdghN2ALFD9/BOR4u731yt1vBBbVR7MP6XVHJreIFUs6+L+TCHAHJb12DBL R3z6UdYD91roIZBd4f6kLDuCIAcCGjfIIuDE7ooqXcJg2/+xt2jazozj/Jvvaclsvzsa 9Q== Received: from p1lg14881.it.hpe.com (p1lg14881.it.hpe.com [16.230.97.202]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3ryuq4329b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jul 2023 21:24:28 +0000 Received: from p1lg14885.dc01.its.hpecorp.net (unknown [10.119.18.236]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14881.it.hpe.com (Postfix) with ESMTPS id 5EA5E804DFE; Fri, 21 Jul 2023 21:24:27 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14885.dc01.its.hpecorp.net (Postfix) with ESMTP id D53A2809E78; Fri, 21 Jul 2023 21:24:26 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/5] dt-bindings: net: Add HPE GXP UMAC MDIO Date: Fri, 21 Jul 2023 16:20:40 -0500 Message-Id: <20230721212044.59666-2-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230721212044.59666-1-nick.hawkins@hpe.com> References: <20230721212044.59666-1-nick.hawkins@hpe.com> X-Proofpoint-ORIG-GUID: O2Xjkxt5WkgSovZXZ8ZDNUwXRFXYpXlJ X-Proofpoint-GUID: O2Xjkxt5WkgSovZXZ8ZDNUwXRFXYpXlJ X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_12,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 impostorscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210189 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772069242564529540 X-GMAIL-MSGID: 1772069242564529540 From: Nick Hawkins Provide access to the register regions and interrupt for Universal MAC(UMAC). The driver under the hpe,gxp-umac-mdio will provide an interface for managing both the internal and external PHYs. Signed-off-by: Nick Hawkins Reviewed-by: Conor Dooley --- .../bindings/net/hpe,gxp-umac-mdio.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/hpe,gxp-umac-mdio.yaml diff --git a/Documentation/devicetree/bindings/net/hpe,gxp-umac-mdio.yaml b/Documentation/devicetree/bindings/net/hpe,gxp-umac-mdio.yaml new file mode 100644 index 000000000000..bb0db1bb67b1 --- /dev/null +++ b/Documentation/devicetree/bindings/net/hpe,gxp-umac-mdio.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/hpe,gxp-umac-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HPE GXP UMAC MDIO Controller + +maintainers: + - Nicholas Hawkins + +description: |+ + The HPE GXP Unversal MAC (UMAC) MDIO controller provides a configuration + path for both external PHY's and SERDES connected PHY's. + +allOf: + - $ref: mdio.yaml# + +properties: + compatible: + const: hpe,gxp-umac-mdio + + reg: + maxItems: 1 + description: The register range of the MDIO controller instance + + resets: + maxItems: 1 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + mdio0: mdio@4080 { + compatible = "hpe,gxp-umac-mdio"; + reg = <0x4080 0x10>; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + phy-mode = "sgmii"; + reg = <0>; + }; + }; From patchwork Fri Jul 21 21:20:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 124119 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp477605vqg; Fri, 21 Jul 2023 14:35:15 -0700 (PDT) X-Google-Smtp-Source: APBJJlGVQkbMu2/3xan3V+eDsWymuAvxNuyNyBw6hF9l0lRqA71d02l07ZshfTXShTpqTNpW6gDZ X-Received: by 2002:a05:6358:341d:b0:132:7a01:32ac with SMTP id h29-20020a056358341d00b001327a0132acmr1118261rwd.16.1689975315174; Fri, 21 Jul 2023 14:35:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689975315; cv=none; d=google.com; s=arc-20160816; b=s7q1RM5zOBw+sU8K5/VsyU6nVB8Y9qbz9tIY8ryMJSxuTl31TalowAIJScGq4qbsJY w3qd3CsjKz9MxIbp8c/v8XMYlwX7LqyLyqK90I7jnA9S04L4MlTO8IuWKPxM8TvaK+NJ TRmsCFIxdsaILpsNAl26xriks7Qo0t3m3cZxYaBsLUvMxEn5lqxdV3378r5ZmKGr6kaE ByuQNCxYkr53E5mfpuulYY7Vd2kXdRY79z4xw6yn4EN7doeD4uPGgyXsvBbmh8Oi2usZ BSe7vjO81ddYlSv7Z1j/RG2MhAG+YQC1uxCsM3c1kv/0THWP8pJCm4Iqkz6u0lmTC0cw I1qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :to:from:dkim-signature; bh=m/rcipiFDUFTVVTI3gLfC3rThRMIiIy72tAvIjWPOYo=; fh=cXYsyN8veLmFVTNsy36SiG+f6UWeiPuuALASZIO6gAk=; b=zqAoWa8+QuLE77JWIhX7h6RgCQzedXy7xoN5CjyD+3jVlJXOp2YiyAG4GBnVSvLFRK 1sCyY/BL8eWPMDGtpQpBWotCOg9zPnYzHyW3JQA/tT6iyGWOrhIZBL2wq9yp8ccKSvfF y3NhgwgoeucbZUSKWZvoyFK7V1qHKDCgfFY4TZArg2t3k37xuoEdbJiSmIaANV+2Ug46 0h3jk3vv/pyD4LHJwPi3sRun96AwICSMkMVjwoqdxG7I+p0Mo/SSzDwXgO+mYC81vHKb U/k9SsUQF/25vm6Nh4nK2NIFqoJL2fW4wxDIsUE7Iac7zgJGcF4HUCMBydFy3Zb5X6fq TwfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=Ru3o7Pmc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=hpe.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l23-20020a637017000000b0055bc1f0be88si3933704pgc.219.2023.07.21.14.35.01; Fri, 21 Jul 2023 14:35:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=Ru3o7Pmc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=hpe.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230215AbjGUVZw (ORCPT + 99 others); Fri, 21 Jul 2023 17:25:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230322AbjGUVZU (ORCPT ); Fri, 21 Jul 2023 17:25:20 -0400 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86DF23A94; Fri, 21 Jul 2023 14:24:59 -0700 (PDT) Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36LIH3d0007369; Fri, 21 Jul 2023 21:24:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : subject : date : message-id : in-reply-to : references; s=pps0720; bh=m/rcipiFDUFTVVTI3gLfC3rThRMIiIy72tAvIjWPOYo=; b=Ru3o7PmcEdq8eACyf5YBOXD+Yrnu08wlyp0Q9DNQphOG7y1vdZfcS4iYO6WykIV0pBuC BgJMfA41ukwffTa8L0MpFd4Cppw3N9mwWDpreD/It0pkrzgCaws0GSzVdCTyteZPixqX 1tdZkPkSwL9nW3ylexErpf9JxpCCII6GQGFKPlpnbOlri1OePNPR8seWN+knTfWHbkdo 7mvBjtVOKK19eQC6ouY8ukWCkuxUA7weBQVlTvqnc/SK9/goAg/IIoyC2xN3fpJu5IAu cRiaT46IT8KXoYw+C6lOjydv2tSAzRpaH7iftncH/tY3E+GxQOK8z/TmUgdEpFHecphI Fg== Received: from p1lg14879.it.hpe.com (p1lg14879.it.hpe.com [16.230.97.200]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3ryrxa4mp6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jul 2023 21:24:44 +0000 Received: from p1lg14885.dc01.its.hpecorp.net (unknown [10.119.18.236]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14879.it.hpe.com (Postfix) with ESMTPS id 1D01FD2C6; Fri, 21 Jul 2023 21:24:28 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14885.dc01.its.hpecorp.net (Postfix) with ESMTP id 6753880A555; Fri, 21 Jul 2023 21:24:27 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/5] net: hpe: Add GXP UMAC MDIO Date: Fri, 21 Jul 2023 16:20:41 -0500 Message-Id: <20230721212044.59666-3-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230721212044.59666-1-nick.hawkins@hpe.com> References: <20230721212044.59666-1-nick.hawkins@hpe.com> X-Proofpoint-ORIG-GUID: 65nR56lbpxoCbusJez4V8tEt5Z-hZHWI X-Proofpoint-GUID: 65nR56lbpxoCbusJez4V8tEt5Z-hZHWI X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_12,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 phishscore=0 spamscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210189 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772067556373914627 X-GMAIL-MSGID: 1772067556373914627 From: Nick Hawkins The GXP contains two Universal Ethernet MACs that can be connected externally to several physical devices. From an external interface perspective the BMC provides two SERDES interface connections capable of either SGMII or 1000Base-X operation. The BMC also provides a RMII interface for sideband connections to external Ethernet controllers. The primary MAC (umac0) can be mapped to either SGMII/1000-BaseX SERDES interface. The secondary MAC (umac1) can be mapped to only the second SGMII/1000-Base X Serdes interface or it can be mapped for RMII sideband. The MDIO(mdio0) interface from the primary MAC (umac0) is used for external PHY status and configuration. The MDIO(mdio1) interface from the secondary MAC (umac1) is routed to the SGMII/100Base-X IP blocks on the two SERDES interface connections. Signed-off-by: Nick Hawkins --- drivers/net/ethernet/Kconfig | 1 + drivers/net/ethernet/Makefile | 1 + drivers/net/ethernet/hpe/Kconfig | 28 ++++ drivers/net/ethernet/hpe/Makefile | 1 + drivers/net/ethernet/hpe/gxp-umac-mdio.c | 158 +++++++++++++++++++++++ 5 files changed, 189 insertions(+) create mode 100644 drivers/net/ethernet/hpe/Kconfig create mode 100644 drivers/net/ethernet/hpe/Makefile create mode 100644 drivers/net/ethernet/hpe/gxp-umac-mdio.c diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index 5a274b99f299..b4921b84be51 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -80,6 +80,7 @@ source "drivers/net/ethernet/fujitsu/Kconfig" source "drivers/net/ethernet/fungible/Kconfig" source "drivers/net/ethernet/google/Kconfig" source "drivers/net/ethernet/hisilicon/Kconfig" +source "drivers/net/ethernet/hpe/Kconfig" source "drivers/net/ethernet/huawei/Kconfig" source "drivers/net/ethernet/i825xx/Kconfig" source "drivers/net/ethernet/ibm/Kconfig" diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index 0d872d4efcd1..2e3cae9dbe97 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_NET_VENDOR_FREESCALE) += freescale/ obj-$(CONFIG_NET_VENDOR_FUJITSU) += fujitsu/ obj-$(CONFIG_NET_VENDOR_FUNGIBLE) += fungible/ obj-$(CONFIG_NET_VENDOR_GOOGLE) += google/ +obj-$(CONFIG_NET_VENDOR_HPE) += hpe/ obj-$(CONFIG_NET_VENDOR_HISILICON) += hisilicon/ obj-$(CONFIG_NET_VENDOR_HUAWEI) += huawei/ obj-$(CONFIG_NET_VENDOR_IBM) += ibm/ diff --git a/drivers/net/ethernet/hpe/Kconfig b/drivers/net/ethernet/hpe/Kconfig new file mode 100644 index 000000000000..461aa15ace34 --- /dev/null +++ b/drivers/net/ethernet/hpe/Kconfig @@ -0,0 +1,28 @@ +config NET_VENDOR_HPE + bool "HPE device" + default y + depends on ARCH_HPE + help + Say y here to support the HPE network devices. + The GXP contains two Ethernet MACs that can be + connected externally to several physical devices. + From an external interface perspective the BMC + provides two SERDES interface connections capable + of either SGMII or 1000Base-X operation. The BMC + also provides a RMII interface for sideband + connections to external Ethernet controllers. + +if NET_VENDOR_HPE + +config GXP_UMAC_MDIO + tristate "GXP UMAC mdio support" + depends on ARCH_HPE + help + Say y here to support the GXP UMAC MDIO bus. The + MDIO(mdio0) interface from the primary MAC (umac0) + is used for external PHY status and configuration. + The MDIO(mdio1) interface from the secondary MAC + (umac1) is routed to the SGMII/100Base-X IP blocks + on the two SERDES interface connections. + +endif diff --git a/drivers/net/ethernet/hpe/Makefile b/drivers/net/ethernet/hpe/Makefile new file mode 100644 index 000000000000..e84c8786ba04 --- /dev/null +++ b/drivers/net/ethernet/hpe/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_GXP_UMAC_MDIO) += gxp-umac-mdio.o diff --git a/drivers/net/ethernet/hpe/gxp-umac-mdio.c b/drivers/net/ethernet/hpe/gxp-umac-mdio.c new file mode 100644 index 000000000000..763e59185409 --- /dev/null +++ b/drivers/net/ethernet/hpe/gxp-umac-mdio.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2023 Hewlett-Packard Development Company, L.P. */ + +#include +#include +#include +#include +#include +#include + +#define UMAC_MII 0x00 /* R/W MII Register */ +#define UMAC_MII_PHY_ADDR_MASK 0x001F0000 +#define UMAC_MII_PHY_ADDR_SHIFT 16 +#define UMAC_MII_MOWNER 0x00000200 +#define UMAC_MII_MRNW 0x00000100 +#define UMAC_MII_REG_ADDR_MASK 0x0000001F +#define UMAC_MII_DATA 0x04 /* R/W MII Data Register */ + +struct umac_mdio_priv { + void __iomem *base; +}; + +static int umac_mdio_read(struct mii_bus *bus, int phy_id, int reg) +{ + struct umac_mdio_priv *umac_mdio = bus->priv; + unsigned int value; + unsigned int status; + int ret; + + status = __raw_readl(umac_mdio->base + UMAC_MII); + + status &= ~(UMAC_MII_PHY_ADDR_MASK | UMAC_MII_REG_ADDR_MASK); + status |= ((phy_id << UMAC_MII_PHY_ADDR_SHIFT) & + UMAC_MII_PHY_ADDR_MASK); + status |= (reg & UMAC_MII_REG_ADDR_MASK); + status |= UMAC_MII_MRNW; /* set bit for read mode */ + __raw_writel(status, umac_mdio->base + UMAC_MII); + + status |= UMAC_MII_MOWNER; /* set bit to activate mii transfer */ + __raw_writel(status, umac_mdio->base + UMAC_MII); + + ret = readl_poll_timeout(umac_mdio->base + UMAC_MII, status, + !(status & UMAC_MII_MOWNER), 1000, 100000); + if (ret) { + dev_err(bus->parent, "mdio read time out\n"); + return -ETIMEDOUT; + } + + value = __raw_readl(umac_mdio->base + UMAC_MII_DATA); + return value; +} + +static int umac_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 value) +{ + struct umac_mdio_priv *umac_mdio = bus->priv; + unsigned int status; + int ret; + + __raw_writel(value, umac_mdio->base + UMAC_MII_DATA); + + status = __raw_readl(umac_mdio->base + UMAC_MII); + + status &= ~(UMAC_MII_PHY_ADDR_MASK | UMAC_MII_REG_ADDR_MASK); + status |= ((phy_id << UMAC_MII_PHY_ADDR_SHIFT) & + UMAC_MII_PHY_ADDR_MASK); + status |= (reg & UMAC_MII_REG_ADDR_MASK); + status &= ~UMAC_MII_MRNW; /* clear bit for write mode */ + __raw_writel(status, umac_mdio->base + UMAC_MII); + + status |= UMAC_MII_MOWNER; /* set bit to activate mii transfer */ + __raw_writel(status, umac_mdio->base + UMAC_MII); + + ret = readl_poll_timeout(umac_mdio->base + UMAC_MII, status, + !(status & UMAC_MII_MOWNER), 1000, 100000); + if (ret) { + dev_err(bus->parent, "mdio read time out\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int umac_mdio_probe(struct platform_device *pdev) +{ + struct resource *res; + struct mii_bus *bus; + struct umac_mdio_priv *umac_mdio; + + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "fail to get resource\n"); + return -ENODEV; + } + + bus = devm_mdiobus_alloc_size(&pdev->dev, + sizeof(struct umac_mdio_priv)); + if (!bus) { + dev_err(&pdev->dev, "failed to alloc mii bus\n"); + return -ENOMEM; + } + + snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); + + bus->name = dev_name(&pdev->dev); + bus->read = umac_mdio_read, + bus->write = umac_mdio_write, + bus->parent = &pdev->dev; + umac_mdio = bus->priv; + umac_mdio->base = devm_ioremap_resource(&pdev->dev, res); + if (!umac_mdio->base) { + dev_err(&pdev->dev, "failed to do ioremap\n"); + return -ENODEV; + } + + platform_set_drvdata(pdev, umac_mdio); + + ret = of_mdiobus_register(bus, pdev->dev.of_node); + + if (ret < 0) { + dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret); + return ret; + } + + return 0; +} + +static int umac_mdio_remove(struct platform_device *pdev) +{ + struct mii_bus *bus = platform_get_drvdata(pdev); + + if (bus) + mdiobus_unregister(bus); + + return 0; +} + +static const struct of_device_id umac_mdio_of_matches[] = { + { .compatible = "hpe,gxp-umac-mdio", }, + {}, +}; +MODULE_DEVICE_TABLE(of, umac_mdio_of_matches); + +static struct platform_driver umac_driver = { + .driver = { + .name = "gxp-umac-mdio", + .of_match_table = of_match_ptr(umac_mdio_of_matches), + }, + .probe = umac_mdio_probe, + .remove = umac_mdio_remove, +}; + +module_platform_driver(umac_driver); + +MODULE_AUTHOR("Nick Hawkins "); +MODULE_DESCRIPTION("HPE GXP UMAC MDIO driver"); +MODULE_LICENSE("GPL"); From patchwork Fri Jul 21 21:20:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 124133 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp492098vqg; Fri, 21 Jul 2023 15:10:56 -0700 (PDT) X-Google-Smtp-Source: APBJJlGHU03X62QmPu7IZ0ZJMq7tVussQFI9UZbxkp/xFJIrnfBTLIJKWrAlgJwyM5U04Vas3MVW X-Received: by 2002:a2e:6a10:0:b0:2b7:1005:931b with SMTP id f16-20020a2e6a10000000b002b71005931bmr2171995ljc.0.1689977456530; Fri, 21 Jul 2023 15:10:56 -0700 (PDT) ARC-Seal: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i9-20020a170906090900b009827e17b069si2855201ejd.1029.2023.07.21.15.10.31; Fri, 21 Jul 2023 15:10:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=TziHYlpZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=hpe.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230330AbjGUVZ4 (ORCPT + 99 others); Fri, 21 Jul 2023 17:25:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230037AbjGUVZW (ORCPT ); Fri, 21 Jul 2023 17:25:22 -0400 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C615E3A8F; Fri, 21 Jul 2023 14:25:00 -0700 (PDT) Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36LK8aev026761; Fri, 21 Jul 2023 21:24:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version; s=pps0720; bh=iRlorkov3huiTBrRF5aHfpBB+eam/ZCgsrAc5IIrWq8=; b=TziHYlpZO6AU9reDDGzkF3KOI5m/BNS+R4Kom6ATxoAPqZF6xeuiPh2JYBd9m0EgfnzN jhqtIJzfwQtmRZH/yjZNCRtube7P3LyR5BmXzoNDsdmzSaXH8391rEYiQu6Lawz3Mq6S MOyXqqr9GFbj0ceuyn/X7zOf/ZztBeXcmAZael02C9Il6p0aEPlLJ3JJxGgNpF6ooTR+ BRS4rr4XtanNs9nnPpdy+0dZBWYp35Z6C5MFtPGdo7aKClz6c26ATxfRa+lFYhcocUSl Qm0JRyvmLI7j8y6TYV3IaeGPzI5wjc91V1fn7GCdJ5kQz2RmQb8rWbZ5GQzOxHX0aUiw zA== Received: from p1lg14881.it.hpe.com (p1lg14881.it.hpe.com [16.230.97.202]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3ryd8b9ywq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jul 2023 21:24:53 +0000 Received: from p1lg14885.dc01.its.hpecorp.net (unknown [10.119.18.236]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14881.it.hpe.com (Postfix) with ESMTPS id 9C2AA804DF9; Fri, 21 Jul 2023 21:24:28 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14885.dc01.its.hpecorp.net (Postfix) with ESMTP id 15CE080A540; Fri, 21 Jul 2023 21:24:28 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/5] dt-bindings: net: Add HPE GXP UMAC Date: Fri, 21 Jul 2023 16:20:42 -0500 Message-Id: <20230721212044.59666-4-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230721212044.59666-1-nick.hawkins@hpe.com> References: <20230721212044.59666-1-nick.hawkins@hpe.com> X-Proofpoint-GUID: ZzxqsRzLTQy19jOxfQcenbfm7Vr8U2BV X-Proofpoint-ORIG-GUID: ZzxqsRzLTQy19jOxfQcenbfm7Vr8U2BV X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_12,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 mlxlogscore=952 lowpriorityscore=0 impostorscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210189 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772069801145808010 X-GMAIL-MSGID: 1772069801145808010 From: Nick Hawkins Provide access to the register regions and interrupt for Universal MAC(UMAC). The driver under the hpe,gxp-umac binding will provide an interface for sending and receiving networking data from both of the UMACs on the system. Signed-off-by: Nick Hawkins --- .../devicetree/bindings/net/hpe,gxp-umac.yaml | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/hpe,gxp-umac.yaml diff --git a/Documentation/devicetree/bindings/net/hpe,gxp-umac.yaml b/Documentation/devicetree/bindings/net/hpe,gxp-umac.yaml new file mode 100644 index 000000000000..c3b68c4ba7f2 --- /dev/null +++ b/Documentation/devicetree/bindings/net/hpe,gxp-umac.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/hpe,gxp-umac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HPE GXP Unified MAC Controller + +maintainers: + - Nick Hawkins + +description: | + HPE GXP 802.3 10/100/1000T Ethernet Unifed MAC controller. + Device node of the controller has following properties. + +properties: + compatible: + const: hpe,gxp-umac + + use-ncsi: + type: boolean + description: | + Indicates if the device should use NCSI (Network Controlled + Sideband Interface). + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + mac-address: true + + ethernet-ports: + type: object + additionalProperties: false + description: Ethernet ports to PHY + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^port@[0-1]$": + type: object + additionalProperties: false + description: Port to PHY + + properties: + reg: + minimum: 0 + maximum: 1 + + phy-handle: + maxItems: 1 + + required: + - reg + - phy-handle + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - ethernet-ports + +examples: + - | + ethernet@4000 { + compatible = "hpe,gxp-umac"; + reg = <0x4000 0x80>; + interrupts = <22>; + mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-handle = <ð_phy0>; + }; + + port@1 { + reg = <1>; + phy-handle = <ð_phy1>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@0 { + reg = <0>; + }; + + eth_phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; +... 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From an external interface perspective the BMC provides two SERDES interface connections capable of either SGMII or 1000Base-X operation. The BMC also provides a RMII interface for sideband connections to external Ethernet controllers. The primary MAC (umac0) can be mapped to either SGMII/1000-BaseX SERDES interface. The secondary MAC (umac1) can be mapped to only the second SGMII/1000-Base X Serdes interface or it can be mapped for RMII sideband. The MDIO(mdio0) interface from the primary MAC (umac0) is used for external PHY status and configuration. The MDIO(mdio1) interface from the secondary MAC (umac1) is routed to the SGMII/100Base-X IP blocks on the two SERDES interface connections. Signed-off-by: Nick Hawkins --- drivers/net/ethernet/hpe/Kconfig | 15 + drivers/net/ethernet/hpe/Makefile | 1 + drivers/net/ethernet/hpe/gxp-umac.c | 911 ++++++++++++++++++++++++++++ drivers/net/ethernet/hpe/gxp-umac.h | 89 +++ 4 files changed, 1016 insertions(+) create mode 100644 drivers/net/ethernet/hpe/gxp-umac.c create mode 100644 drivers/net/ethernet/hpe/gxp-umac.h diff --git a/drivers/net/ethernet/hpe/Kconfig b/drivers/net/ethernet/hpe/Kconfig index 461aa15ace34..cc269558b707 100644 --- a/drivers/net/ethernet/hpe/Kconfig +++ b/drivers/net/ethernet/hpe/Kconfig @@ -14,6 +14,21 @@ config NET_VENDOR_HPE if NET_VENDOR_HPE +config GXP_UMAC + tristate "GXP UMAC support" + depends on ARCH_HPE + select CRC32 + select MII + select PHYLIB + select GXP_UMAC_MDIO + help + Say y here to support the GXP UMACs interface. The + primary MAC (umac0) can be mapped to either + SGMII/1000-BaseX SERDES interface. The secondary MAC + (umac1) can be mapped to only the second + SGMII/1000-Base X Serdes interface or it can be + mapped for RMII sideband. + config GXP_UMAC_MDIO tristate "GXP UMAC mdio support" depends on ARCH_HPE diff --git a/drivers/net/ethernet/hpe/Makefile b/drivers/net/ethernet/hpe/Makefile index e84c8786ba04..5c2c3bcde532 100644 --- a/drivers/net/ethernet/hpe/Makefile +++ b/drivers/net/ethernet/hpe/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_GXP_UMAC_MDIO) += gxp-umac-mdio.o +obj-$(CONFIG_GXP_UMAC) += gxp-umac.o diff --git a/drivers/net/ethernet/hpe/gxp-umac.c b/drivers/net/ethernet/hpe/gxp-umac.c new file mode 100644 index 000000000000..a4fe3eb9f68f --- /dev/null +++ b/drivers/net/ethernet/hpe/gxp-umac.c @@ -0,0 +1,911 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2023 Hewlett-Packard Enterprise Development Company, L.P. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gxp-umac.h" + +#define PHY_88E1514_COPPER_CONTROL_REG 0 +#define PHY_88E1514_PAGE_ADDRESS 22 + +#define PHY_88E1514_GENERAL_CONTROL_REG1 20 + +#define DRV_MODULE_NAME "gxp-umac" +#define DRV_MODULE_VERSION "0.1" + +#define NUMBER_OF_PORTS 2 +#define EXTERNAL_PORT 1 +#define INTERNAL_PORT 0 + +struct umac_priv { + void __iomem *base; + int irq; + struct platform_device *pdev; + struct umac_tx_descs *tx_descs; + struct umac_rx_descs *rx_descs; + dma_addr_t tx_descs_dma_addr; + dma_addr_t rx_descs_dma_addr; + unsigned int tx_cur; + unsigned int tx_done; + unsigned int rx_cur; + struct napi_struct napi; + struct net_device *ndev; + struct phy_device *phy_dev; + struct phy_device *int_phy_dev; + struct ncsi_dev *ncsidev; + bool use_ncsi; +}; + +static void umac_get_drvinfo(struct net_device *ndev, + struct ethtool_drvinfo *info) +{ + strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); + strscpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); +} + +static int umac_get_link_ksettings(struct net_device *ndev, + struct ethtool_link_ksettings *cmd) +{ + phy_ethtool_ksettings_get(ndev->phydev, cmd); + return 0; +} + +static int umac_set_link_ksettings(struct net_device *ndev, + const struct ethtool_link_ksettings *cmd) +{ + return phy_ethtool_ksettings_set(ndev->phydev, cmd); +} + +static int umac_nway_reset(struct net_device *ndev) +{ + return genphy_restart_aneg(ndev->phydev); +} + +static u32 umac_get_link(struct net_device *ndev) +{ + int err; + + err = genphy_update_link(ndev->phydev); + if (err) + return ethtool_op_get_link(ndev); + + return ndev->phydev->link; +} + +static struct net_device_stats *umac_get_stats(struct net_device *ndev) +{ + return &ndev->stats; +} + +static int umac_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) +{ + if (!netif_running(ndev)) + return -EINVAL; + + if (!ndev->phydev) + return -ENODEV; + + return phy_mii_ioctl(ndev->phydev, ifr, cmd); +} + +static void umac_set_mac_address(struct net_device *ndev, void *p_addr) +{ + struct umac_priv *umac = netdev_priv(ndev); + char *addr = (char *)p_addr; + unsigned int value; + + /* update address to register */ + value = addr[0] << 8 | addr[1]; + writel(value, umac->base + UMAC_MAC_ADDR_HI); + value = addr[2] << 8 | addr[3]; + writel(value, umac->base + UMAC_MAC_ADDR_MID); + value = addr[4] << 8 | addr[5]; + writel(value, umac->base + UMAC_MAC_ADDR_LO); +} + +static int umac_eth_mac_addr(struct net_device *ndev, void *p) +{ + int ret; + struct sockaddr *addr = p; + + ret = eth_prepare_mac_addr_change(ndev, p); + if (ret < 0) + return ret; + + eth_commit_mac_addr_change(ndev, p); + umac_set_mac_address(ndev, addr->sa_data); + + return 0; +} + +static void umac_channel_enable(struct umac_priv *umac) +{ + unsigned int value; + + value = readl(umac->base + UMAC_CONFIG_STATUS); + value |= UMAC_CFG_TXEN | UMAC_CFG_RXEN; + writel(value, umac->base + UMAC_CONFIG_STATUS); + + /* start processing by writing the ring prompt register */ + writel(0, umac->base + UMAC_RING_PROMPT); +} + +static void umac_channel_disable(struct umac_priv *umac) +{ + writel(0, umac->base + UMAC_CONFIG_STATUS); +} + +static int umac_init_ring_discriptor(struct net_device *ndev) +{ + struct umac_priv *umac = netdev_priv(ndev); + struct platform_device *pdev = umac->pdev; + + struct umac_tx_desc_entry *ptxdesc; + struct umac_rx_desc_entry *prxdesc; + + unsigned int i; + + if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { + netdev_err(ndev, "No suitable DMA available\n"); + return -ENOMEM; + } + + umac->tx_descs = dma_alloc_coherent(&pdev->dev, + sizeof(struct umac_tx_descs), + &umac->tx_descs_dma_addr, GFP_KERNEL); + if (!umac->tx_descs) + return -ENOMEM; + + umac->rx_descs = dma_alloc_coherent(&pdev->dev, + sizeof(struct umac_rx_descs), + &umac->rx_descs_dma_addr, GFP_KERNEL); + if (!umac->rx_descs) { + dma_free_coherent(&pdev->dev, sizeof(struct umac_tx_descs), + umac->tx_descs, + umac->tx_descs_dma_addr); + return -ENOMEM; + } + + for (i = 0; i < UMAC_MAX_TX_DESC_ENTRIES; i++) { + ptxdesc = &umac->tx_descs->entrylist[i]; + ptxdesc->dmaaddress = cpu_to_le32(umac->tx_descs_dma_addr + + offsetof(struct umac_tx_descs, + framelist[i][0])); + } + + for (i = 0; i < UMAC_MAX_RX_DESC_ENTRIES; i++) { + prxdesc = &umac->rx_descs->entrylist[i]; + prxdesc->dmaaddress = cpu_to_le32(umac->rx_descs_dma_addr + + offsetof(struct umac_rx_descs, + framelist[i][0])); + prxdesc->status = UMAC_RING_ENTRY_HW_OWN; + prxdesc->count = UMAC_MAX_RX_FRAME_SIZE; + } + + umac->tx_cur = 0; + umac->tx_done = 0; + umac->rx_cur = 0; + + return 0; +} + +static int umac_int_phy_init(struct umac_priv *umac) +{ + struct phy_device *phy_dev = umac->int_phy_dev; + unsigned int value; + + value = phy_read(phy_dev, 0); + if (value & 0x4000) + pr_info("Internal PHY loopback is enabled - clearing\n"); + + value &= ~0x4000; /* disable loopback */ + phy_write(phy_dev, 0, value); + + value = phy_read(phy_dev, 0); + value |= 0x1000; /* set aneg enable */ + value |= 0x8000; /* SW reset */ + phy_write(phy_dev, 0, value); + + do { + value = phy_read(phy_dev, 0); + } while (value & 0x8000); + + return 0; +} + +static int umac_phy_fixup(struct phy_device *phy_dev) +{ + unsigned int value; + + /* set phy mode to SGMII to copper */ + /* set page to 18 by writing 18 to register 22 */ + phy_write(phy_dev, PHY_88E1514_PAGE_ADDRESS, 18); + value = phy_read(phy_dev, PHY_88E1514_GENERAL_CONTROL_REG1); + value &= ~0x07; + value |= 0x01; + phy_write(phy_dev, PHY_88E1514_GENERAL_CONTROL_REG1, value); + + /* perform mode reset by setting bit 15 in general_control_reg1 */ + phy_write(phy_dev, PHY_88E1514_GENERAL_CONTROL_REG1, value | 0x8000); + + do { + value = phy_read(phy_dev, PHY_88E1514_GENERAL_CONTROL_REG1); + } while (value & 0x8000); + + /* after setting the mode, must perform a SW reset */ + phy_write(phy_dev, PHY_88E1514_PAGE_ADDRESS, 0); /* set page to 0 */ + + value = phy_read(phy_dev, PHY_88E1514_COPPER_CONTROL_REG); + value |= 0x8000; + phy_write(phy_dev, PHY_88E1514_COPPER_CONTROL_REG, value); + + do { + value = phy_read(phy_dev, PHY_88E1514_COPPER_CONTROL_REG); + } while (value & 0x8000); + + return 0; +} + +static int umac_init_hw(struct net_device *ndev) +{ + struct umac_priv *umac = netdev_priv(ndev); + unsigned int value; + + /* initialize tx and rx rings to first entry */ + writel(0, umac->base + UMAC_RING_PTR); + + /* clear the missed bit */ + writel(0, umac->base + UMAC_CLEAR_STATUS); + + /* disable checksum generation */ + writel(0, umac->base + UMAC_CKSUM_CONFIG); + + /* write the ring size register */ + value = ((UMAC_RING_SIZE_256 << UMAC_TX_RING_SIZE_SHIFT) & + UMAC_TX_RING_SIZE_MASK) | + ((UMAC_RING_SIZE_256 << UMAC_RX_RING_SIZE_SHIFT) & + UMAC_RX_RING_SIZE_MASK); + writel(value, umac->base + UMAC_RING_SIZE); + + /* write rx ring base address */ + writel(cpu_to_le32(umac->rx_descs_dma_addr), + umac->base + UMAC_RX_RING_ADDR); + + /* write tx ring base address */ + writel(cpu_to_le32(umac->tx_descs_dma_addr), + umac->base + UMAC_TX_RING_ADDR); + + /* write burst size */ + writel(0x22, umac->base + UMAC_DMA_CONFIG); + + umac_channel_disable(umac); + + /* disable clocks and gigabit mode (leave channels disabled) */ + value = readl(umac->base + UMAC_CONFIG_STATUS); + value &= 0xfffff9ff; + writel(value, umac->base + UMAC_CONFIG_STATUS); + udelay(2); + + if (umac->use_ncsi) { + /* set correct tx clock */ + value &= UMAC_CFG_TX_CLK_EN; + value &= ~UMAC_CFG_GTX_CLK_EN; + value &= ~UMAC_CFG_GIGABIT_MODE; /* RMII mode */ + value |= UMAC_CFG_FULL_DUPLEX; /* full duplex */ + } else { + if (ndev->phydev->duplex) + value |= UMAC_CFG_FULL_DUPLEX; + else + value &= ~UMAC_CFG_FULL_DUPLEX; + + if (ndev->phydev->speed == SPEED_1000) { + value &= ~UMAC_CFG_TX_CLK_EN; + value |= UMAC_CFG_GTX_CLK_EN; + value |= UMAC_CFG_GIGABIT_MODE; + } else { + value |= UMAC_CFG_TX_CLK_EN; + value &= ~UMAC_CFG_GTX_CLK_EN; + value &= ~UMAC_CFG_GIGABIT_MODE; + } + } + writel(value, umac->base + UMAC_CONFIG_STATUS); + udelay(2); + + umac_channel_enable(umac); + + return 0; +} + +static int umac_start_xmit(struct sk_buff *skb, struct net_device *ndev) +{ + struct umac_priv *umac = netdev_priv(ndev); + struct umac_tx_desc_entry *ptxdesc; + u8 *pframe; + unsigned int length; + + ptxdesc = &umac->tx_descs->entrylist[umac->tx_cur]; + pframe = umac->tx_descs->framelist[umac->tx_cur]; + + length = skb->len; + if (length > 1514) { + netdev_err(ndev, "send data %d bytes > 1514, clamp it to 1514\n", + skb->len); + length = 1514; + } + + memset(pframe, 0, UMAC_MAX_FRAME_SIZE); + memcpy(pframe, skb->data, length); + + if (length < ETH_ZLEN) + length = ETH_ZLEN; /* minimum tx byte */ + + ptxdesc->count = length; + ptxdesc->status = UMAC_RING_ENTRY_HW_OWN; + ptxdesc->cksumoffset = 0; /* disable checksum generation */ + + umac->tx_cur++; + if (umac->tx_cur >= UMAC_MAX_TX_DESC_ENTRIES) + umac->tx_cur = 0; + + /* if current tx ring buffer is full, stop the queue */ + ptxdesc = &umac->tx_descs->entrylist[umac->tx_cur]; + if (ptxdesc->status & UMAC_RING_ENTRY_HW_OWN) + netif_stop_queue(ndev); + + /* start processing by writing the ring prompt register */ + writel(0, umac->base + UMAC_RING_PROMPT); + dev_kfree_skb(skb); + + return NETDEV_TX_OK; +} + +static int umac_rx(struct net_device *ndev, int budget) +{ + struct umac_priv *umac = netdev_priv(ndev); + + struct umac_rx_desc_entry *prxdesc; + struct sk_buff *skb; + + unsigned int rxlength; + int rxpktcount = 0; + u8 *pframe; + u8 *skb_buf; + + prxdesc = &umac->rx_descs->entrylist[umac->rx_cur]; + pframe = umac->rx_descs->framelist[umac->rx_cur]; + + while (!(prxdesc->status & UMAC_RING_ENTRY_HW_OWN)) { + rxlength = prxdesc->count; + skb = netdev_alloc_skb(ndev, rxlength); + if (!skb) { + /* run out of memory */ + ndev->stats.rx_dropped++; + return rxpktcount; + } + + /* make 16 bytes aligned for 14 bytes ethernet header */ + skb_buf = skb_put(skb, rxlength); + memcpy(skb_buf, pframe, rxlength); + + skb->protocol = eth_type_trans(skb, ndev); + netif_receive_skb(skb); + rxpktcount++; + + prxdesc->status = UMAC_RING_ENTRY_HW_OWN; + prxdesc->count = UMAC_MAX_FRAME_SIZE; + + ndev->stats.rx_packets++; + ndev->stats.rx_bytes += rxlength; + + /* move to next buffer */ + umac->rx_cur++; + if (umac->rx_cur >= UMAC_MAX_RX_DESC_ENTRIES) + umac->rx_cur = 0; + + if (rxpktcount >= budget) + break; + + prxdesc = &umac->rx_descs->entrylist[umac->rx_cur]; + pframe = umac->rx_descs->framelist[umac->rx_cur]; + } + /* start processing by writing the ring prompt register */ + writel(0, umac->base + UMAC_RING_PROMPT); + + return rxpktcount; +} + +static void umac_tx_done(struct net_device *ndev) +{ + struct umac_priv *umac = netdev_priv(ndev); + + unsigned int txptr; + unsigned int value; + struct umac_tx_desc_entry *ptxdesc; + + value = readl(umac->base + UMAC_RING_PTR); + txptr = (value & UMAC_TX_RING_PTR_MASK) >> UMAC_TX_RING_PTR_SHIFT; + + ptxdesc = &umac->tx_descs->entrylist[umac->tx_done]; + + while (!(ptxdesc->status & UMAC_RING_ENTRY_HW_OWN)) { + if (umac->tx_done == txptr) + break; + + ndev->stats.tx_packets++; + ndev->stats.tx_bytes += ptxdesc->count; + + umac->tx_done++; + if (umac->tx_done >= UMAC_MAX_TX_DESC_ENTRIES) + umac->tx_done = 0; + ptxdesc = &umac->tx_descs->entrylist[umac->tx_done]; + } + + /* clear tx interrupt */ + value = readl(umac->base + UMAC_INTERRUPT); + value &= ~UMAC_TX_INT; + writel(value, umac->base + UMAC_INTERRUPT); + + if (netif_queue_stopped(ndev)) + netif_wake_queue(ndev); +} + +static void umac_irq_enable(struct umac_priv *umac) +{ + unsigned int value; + + /* enable interrupt */ + value = readl(umac->base + UMAC_INTERRUPT); + value |= (UMAC_RX_INTEN | UMAC_TX_INTEN); + writel(value, umac->base + UMAC_INTERRUPT); +} + +static void umac_irq_disable(struct umac_priv *umac) +{ + unsigned int value; + + /* clear and disable interrupt */ + value = readl(umac->base + UMAC_INTERRUPT); + value |= (UMAC_RX_INT | UMAC_TX_INT); + value &= ~(UMAC_RX_INTEN | UMAC_TX_INTEN); + writel(value, umac->base + UMAC_INTERRUPT); +} + +static irqreturn_t umac_interrupt(int irq, void *p_ndev) +{ + struct net_device *ndev = (struct net_device *)p_ndev; + struct umac_priv *umac = netdev_priv(ndev); + + if (umac->use_ncsi || netif_running(ndev)) { + umac_irq_disable(umac); + napi_schedule(&umac->napi); + } + + return IRQ_HANDLED; +} + +static int umac_poll(struct napi_struct *napi, int budget) +{ + struct umac_priv *umac = container_of(napi, struct umac_priv, napi); + struct net_device *ndev = umac->ndev; + unsigned int value; + int rx_done = 0; + + umac_tx_done(ndev); + + rx_done = umac_rx(ndev, budget); + + if (rx_done < budget) { + napi_complete_done(napi, rx_done); + /* clear rx interrupt */ + value = readl(umac->base + UMAC_INTERRUPT); + value &= ~UMAC_RX_INT; + writel(value, umac->base + UMAC_INTERRUPT); + + /* enable interrupt */ + umac_irq_enable(umac); + } + + return rx_done; +} + +static int umac_open(struct net_device *ndev) +{ + struct umac_priv *umac = netdev_priv(ndev); + int err; + + if (request_irq(ndev->irq, umac_interrupt, 0x0, ndev->name, ndev)) { + netdev_err(ndev, "failed to register irq\n"); + return -EAGAIN; + } + + umac_init_ring_discriptor(ndev); + umac_init_hw(ndev); + + if (umac->use_ncsi) + netif_carrier_on(ndev); + else + phy_start(ndev->phydev); + + napi_enable(&umac->napi); + netif_start_queue(ndev); + umac_irq_enable(umac); + + if (umac->use_ncsi) { + err = ncsi_start_dev(umac->ncsidev); + if (err) { + netdev_err(ndev, "failed to start ncsi\n"); + free_irq(ndev->irq, ndev); + return err; + } + } + + netdev_info(ndev, "%s is OPENED\n", ndev->name); + return 0; +} + +static int umac_stop(struct net_device *ndev) +{ + struct umac_priv *umac = netdev_priv(ndev); + struct platform_device *pdev = umac->pdev; + + dma_free_coherent(&pdev->dev, sizeof(struct umac_tx_descs), + umac->tx_descs, umac->tx_descs_dma_addr); + dma_free_coherent(&pdev->dev, sizeof(struct umac_rx_descs), + umac->rx_descs, umac->rx_descs_dma_addr); + netif_stop_queue(ndev); + + if (umac->use_ncsi) + ncsi_stop_dev(umac->ncsidev); + else + phy_stop(ndev->phydev); + umac_irq_disable(umac); + umac_channel_disable(umac); + napi_disable(&umac->napi); + + free_irq(ndev->irq, ndev); + + return 0; +} + +static const struct ethtool_ops umac_ethtool_ops = { + .get_ts_info = ethtool_op_get_ts_info, + .get_link_ksettings = umac_get_link_ksettings, + .set_link_ksettings = umac_set_link_ksettings, + .get_drvinfo = umac_get_drvinfo, + .nway_reset = umac_nway_reset, + .get_link = umac_get_link, +}; + +static const struct net_device_ops umac_netdev_ops = { + .ndo_open = umac_open, + .ndo_stop = umac_stop, + .ndo_start_xmit = umac_start_xmit, + .ndo_get_stats = umac_get_stats, + .ndo_do_ioctl = umac_ioctl, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_mac_address = umac_eth_mac_addr, +}; + +static int umac_init_mac_address(struct net_device *ndev) +{ + struct umac_priv *umac = netdev_priv(ndev); + struct platform_device *pdev = umac->pdev; + char addr[ETH_ALEN]; + int err; + + err = of_get_mac_address(pdev->dev.of_node, addr); + if (err) + netdev_err(ndev, "Failed to get address from device-tree: %d\n", + err); + + if (is_valid_ether_addr(addr)) { + dev_addr_set(ndev, addr); + netdev_info(ndev, + "Read MAC address %pM from DTB\n", ndev->dev_addr); + } else { + eth_hw_addr_random(ndev); + netdev_info(ndev, "Generated random MAC address %pM\n", + ndev->dev_addr); + } + + dev_addr_set(ndev, addr); + umac_set_mac_address(ndev, addr); + + return 0; +} + +static void umac_ncsi_handler(struct ncsi_dev *ncsidev) +{ + if (unlikely(ncsidev->state != ncsi_dev_state_functional)) + return; + + netdev_info(ncsidev->dev, "NCSI interface %s\n", + ncsidev->link_up ? "up" : "down"); +} + +static void umac_adjust_link(struct net_device *ndev) +{ + struct umac_priv *umac = netdev_priv(ndev); + int value; + + if (ndev->phydev->link) { + /* disable both clock */ + value = readl(umac->base + UMAC_CONFIG_STATUS); + value &= 0xfffff9ff; + writel(value, umac->base + UMAC_CONFIG_STATUS); + udelay(2); + + if (ndev->phydev->duplex) + value |= UMAC_CFG_FULL_DUPLEX; + else + value &= ~UMAC_CFG_FULL_DUPLEX; + + switch (ndev->phydev->speed) { + case SPEED_1000: + value &= ~UMAC_CFG_TX_CLK_EN; + value |= UMAC_CFG_GTX_CLK_EN; + value |= UMAC_CFG_GIGABIT_MODE; + break; + case SPEED_100: + value |= UMAC_CFG_TX_CLK_EN; + value &= ~UMAC_CFG_GTX_CLK_EN; + value &= ~UMAC_CFG_GIGABIT_MODE; + break; + } + /* update duplex and gigabit_mode to umac */ + writel(value, umac->base + UMAC_CONFIG_STATUS); + udelay(2); + + netif_carrier_on(ndev); + } else { + /* disable both clock */ + value = readl(umac->base + UMAC_CONFIG_STATUS); + value &= 0xfffff9ff; + writel(value, umac->base + UMAC_CONFIG_STATUS); + udelay(2); + + value &= ~UMAC_CFG_FULL_DUPLEX; + value &= ~UMAC_CFG_GTX_CLK_EN; + value &= ~UMAC_CFG_GIGABIT_MODE; + value |= UMAC_CFG_TX_CLK_EN; + writel(value, umac->base + UMAC_CONFIG_STATUS); + udelay(2); + + netif_carrier_off(ndev); + } +} + +static struct device_node *gxp_umac_get_eth_child_node(struct device_node *ether_np, int id) +{ + struct device_node *port_np; + int port_id; + + for_each_child_of_node(ether_np, port_np) { + /* It is not a 'port' node, continue. */ + if (strcmp(port_np->name, "port")) + continue; + if (of_property_read_u32(port_np, "reg", &port_id) < 0) + continue; + + if (port_id == id) + return port_np; + } + + /* Not found! */ + return NULL; +} + +static int umac_setup_phy(struct net_device *ndev) +{ + struct umac_priv *umac = netdev_priv(ndev); + struct platform_device *pdev = umac->pdev; + struct device_node *phy_handle; + phy_interface_t interface; + struct device_node *eth_ports_np; + struct device_node *port_np; + int ret; + int err; + int i; + + /* Get child node ethernet-ports. */ + eth_ports_np = of_get_child_by_name(pdev->dev.of_node, "ethernet-ports"); + if (!eth_ports_np) { + dev_err(&pdev->dev, "No ethernet-ports child node found!\n"); + return -ENODEV; + } + + for (i = 0; i < NUMBER_OF_PORTS; i++) { + /* Get port@i of node ethernet-ports */ + port_np = gxp_umac_get_eth_child_node(eth_ports_np, i); + if (!port_np) + break; + + if (i == INTERNAL_PORT) { + phy_handle = of_parse_phandle(port_np, "phy-handle", 0); + if (phy_handle) { + umac->int_phy_dev = of_phy_find_device(phy_handle); + if (!umac->int_phy_dev) + return -ENODEV; + + umac_int_phy_init(umac); + } else { + return dev_err_probe(&pdev->dev, PTR_ERR(phy_handle), + "Failed to map phy-handle for port %d", i); + } + } + + if (i == EXTERNAL_PORT) { + phy_handle = of_parse_phandle(port_np, "phy-handle", 0); + if (phy_handle) { + /* register the phy board fixup */ + ret = phy_register_fixup_for_uid(0x01410dd1, 0xffffffff, + umac_phy_fixup); + if (ret) + dev_err(&pdev->dev, "cannot register phy board fixup\n"); + + err = of_get_phy_mode(phy_handle, &interface); + if (err) + interface = PHY_INTERFACE_MODE_NA; + + umac->phy_dev = of_phy_connect(ndev, phy_handle, + &umac_adjust_link, + 0, interface); + + if (!umac->phy_dev) + return -ENODEV; + + /* If the specified phy-handle has a fixed-link declaration, use the + * fixed-link properties to set the configuration for the PHY + */ + if (of_phy_is_fixed_link(phy_handle)) { + struct device_node *fixed_link_node = + of_get_child_by_name(phy_handle, + "fixed-link"); + + if (of_property_read_u32(fixed_link_node, "speed", + &umac->phy_dev->speed)) { + netdev_err(ndev, "Invalid fixed-link specified.\n"); + return -EINVAL; + } + umac->phy_dev->duplex = + of_property_read_bool(fixed_link_node, + "full-duplex"); + umac->phy_dev->pause = + of_property_read_bool(fixed_link_node, + "pause"); + umac->phy_dev->asym_pause = + of_property_read_bool(fixed_link_node, + "asym-pause"); + umac->phy_dev->autoneg = AUTONEG_DISABLE; + __clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, + umac->phy_dev->advertising); + } + } else { + return dev_err_probe(&pdev->dev, PTR_ERR(phy_handle), + "Failed to map phy-handle for port %d", i); + } + } + } + + return 0; +} + +static int umac_probe(struct platform_device *pdev) +{ + struct umac_priv *umac; + struct net_device *ndev; + struct resource *res; + int ret = 0; + + ndev = alloc_etherdev(sizeof(*umac)); + if (!ndev) + return -ENOMEM; + + SET_NETDEV_DEV(ndev, &pdev->dev); + + umac = netdev_priv(ndev); + umac->pdev = pdev; + umac->ndev = ndev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + netdev_err(ndev, "failed to get I/O memory\n"); + free_netdev(ndev); + return -ENXIO; + } + + umac->base = devm_ioremap_resource(&pdev->dev, res); + if (!umac->base) { + netdev_err(ndev, "failed to remap I/O memory\n"); + free_netdev(ndev); + return -EBUSY; + } + + ndev->irq = platform_get_irq(pdev, 0); + if (ndev->irq < 0) { + netdev_err(ndev, "failed to get irq\n"); + free_netdev(ndev); + return -ENXIO; + } + + platform_set_drvdata(pdev, ndev); + + ndev->netdev_ops = &umac_netdev_ops; + ndev->ethtool_ops = &umac_ethtool_ops; + + umac_init_mac_address(ndev); + umac_channel_disable(umac); + ret = umac_setup_phy(ndev); + if (ret != 0) { + netdev_err(ndev, "failed to setup phy ret=%d\n", ret); + return -ENODEV; + } + + umac->use_ncsi = false; + if (of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) { + if (!IS_ENABLED(CONFIG_NET_NCSI)) { + netdev_err(ndev, "NCSI stack not enabled\n"); + free_netdev(ndev); + return 0; + } + + dev_info(&pdev->dev, "Using NCSI interface\n"); + umac->use_ncsi = true; + umac->ncsidev = ncsi_register_dev(ndev, umac_ncsi_handler); + if (!umac->ncsidev) { + free_netdev(ndev); + return -ENODEV; + } + } + + netif_napi_add(ndev, &umac->napi, umac_poll); + ret = register_netdev(ndev); + if (ret != 0) { + netdev_err(ndev, "failed to register UMAC ret=%d\n", ret); + netif_napi_del(&umac->napi); + free_netdev(ndev); + return -ENODEV; + } + + return ret; +} + +static int umac_remove(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct umac_priv *umac = netdev_priv(ndev); + + unregister_netdev(ndev); + iounmap(umac->base); + free_netdev(ndev); + return 0; +} + +static const struct of_device_id umac_of_matches[] = { + { .compatible = "hpe, gxp-umac", }, + {}, +}; +MODULE_DEVICE_TABLE(of, umac_of_matches); + +static struct platform_driver umac_driver = { + .driver = { + .name = "gxp-umac", + .of_match_table = of_match_ptr(umac_of_matches), + }, + .probe = umac_probe, + .remove = umac_remove, +}; + +module_platform_driver(umac_driver); + +MODULE_AUTHOR("Nick Hawkins X-Patchwork-Id: 124118 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp477512vqg; Fri, 21 Jul 2023 14:35:02 -0700 (PDT) X-Google-Smtp-Source: APBJJlH6EShCFSAeWRGWg1crNPb0SzUORyadR7YdU4axEzPRpacHun6wTVC7C5UK+8BgLQr7FfwY X-Received: by 2002:a9d:65c8:0:b0:6b9:c51c:f4d5 with SMTP id z8-20020a9d65c8000000b006b9c51cf4d5mr1349682oth.10.1689975302148; Fri, 21 Jul 2023 14:35:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689975302; cv=none; d=google.com; s=arc-20160816; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v24-20020a63f218000000b005578994f212si3710467pgh.425.2023.07.21.14.34.48; Fri, 21 Jul 2023 14:35:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=Bkb1a2zC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=hpe.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230252AbjGUVYr (ORCPT + 99 others); Fri, 21 Jul 2023 17:24:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229644AbjGUVYn (ORCPT ); Fri, 21 Jul 2023 17:24:43 -0400 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07B6130D0; Fri, 21 Jul 2023 14:24:42 -0700 (PDT) Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36LJ1s2Y031028; Fri, 21 Jul 2023 21:24:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : subject : date : message-id : in-reply-to : references; s=pps0720; bh=3qFbs7ny735Se8n+zekA1xfETEDp1cFK+SaOIyzWAhg=; b=Bkb1a2zCHDwf/8Exym+IiFrKI87IrgZAEuW7hE4+2qRcwQOrj2wG6YMBxaTW7hrqihLr 2ZB6wcWkdqhMfDDrE758r8lKXq0ZhdlLKX9xhwg0bYBlv6cXcQkRxOh4+MfyuCQWCpFN WLGkS3e4DuyHnqh3nnoY5zjoQr6iO6/JefPzWBLyv7lj4xao2XcchcOecBQwmG2D2RKJ YSsC/5DUyKBuu3oF5+oaZZbxSm4Cv8qNudxH4aKAHNL+DI+c08KUizSnFjeFnvxYxecD YGMGIIGhYh1W9ocorfQuxHrTu3AsooZ1H+RhQqLpdq3qGVeOF84YZvCty6Z3CChuTyRC GQ== Received: from p1lg14878.it.hpe.com (p1lg14878.it.hpe.com [16.230.97.204]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3ryacpbwwt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jul 2023 21:24:30 +0000 Received: from p1lg14885.dc01.its.hpecorp.net (unknown [10.119.18.236]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14878.it.hpe.com (Postfix) with ESMTPS id E604AD2D2; Fri, 21 Jul 2023 21:24:29 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14885.dc01.its.hpecorp.net (Postfix) with ESMTP id 41FEA809FDC; Fri, 21 Jul 2023 21:24:29 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/5] MAINTAINERS: HPE: Add GXP UMAC Networking Files Date: Fri, 21 Jul 2023 16:20:44 -0500 Message-Id: <20230721212044.59666-6-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230721212044.59666-1-nick.hawkins@hpe.com> References: <20230721212044.59666-1-nick.hawkins@hpe.com> X-Proofpoint-ORIG-GUID: OcWqRi7nCqDrzVPQvsG7gQUKHY1vudSp X-Proofpoint-GUID: OcWqRi7nCqDrzVPQvsG7gQUKHY1vudSp X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_12,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 spamscore=0 malwarescore=0 adultscore=0 phishscore=0 mlxlogscore=932 impostorscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210189 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772067542256801485 X-GMAIL-MSGID: 1772067542256801485 From: Nick Hawkins List the files added for supporting the UMAC networking on GXP. Signed-off-by: Nick Hawkins --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 27ef11624748..4f1c3fa27f7f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2243,6 +2243,8 @@ S: Maintained F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml F: Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml F: Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml +F: Documentation/devicetree/bindings/net/hpe,gxp-umac-mdio.yaml +F: Documentation/devicetree/bindings/net/hpe,gxp-umac.yaml F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml F: Documentation/hwmon/gxp-fan-ctrl.rst @@ -2252,6 +2254,7 @@ F: arch/arm/mach-hpe/ F: drivers/clocksource/timer-gxp.c F: drivers/hwmon/gxp-fan-ctrl.c F: drivers/i2c/busses/i2c-gxp.c +F: drivers/net/ethernet/hpe/ F: drivers/spi/spi-gxp.c F: drivers/watchdog/gxp-wdt.c