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Fri, 21 Jul 2023 17:24:47 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36LHOiQn023756; Fri, 21 Jul 2023 17:24:44 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3rumhknepf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 21 Jul 2023 17:24:44 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36LHOi6i023745; Fri, 21 Jul 2023 17:24:44 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 36LHOhsa023744; Fri, 21 Jul 2023 17:24:44 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 1811C32C9; Fri, 21 Jul 2023 22:54:43 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, Mrinmay Sarkar , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] dt-bindings: PCI: qcom: Add sa8775p compatible Date: Fri, 21 Jul 2023 22:54:32 +0530 Message-Id: <1689960276-29266-2-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689960276-29266-1-git-send-email-quic_msarkar@quicinc.com> References: <1689960276-29266-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: X5AusCD69MkcwNt_90B0Pn4Gw7Fj_lsN X-Proofpoint-ORIG-GUID: X5AusCD69MkcwNt_90B0Pn4Gw7Fj_lsN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_10,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 spamscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxlogscore=999 impostorscore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210153 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772053376357747989 X-GMAIL-MSGID: 1772053376357747989 Add sa8775p platform to the binding. Signed-off-by: Mrinmay Sarkar Reviewed-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie.yaml | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 81971be4..eadba38 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -29,6 +29,7 @@ properties: - qcom,pcie-msm8996 - qcom,pcie-qcs404 - qcom,pcie-sa8540p + - qcom,pcie-sa8775p - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sc8280xp @@ -211,6 +212,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-sa8775p - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sc8280xp @@ -748,7 +750,32 @@ allOf: compatible: contains: enum: + - qcom,pcie-sa8775p + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: - qcom,pcie-sa8540p + - qcom,pcie-sa8775p - qcom,pcie-sc8280xp then: required: @@ -790,6 +817,7 @@ allOf: contains: enum: - qcom,pcie-msm8996 + - qcom,pcie-sa8775p - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sdm845 From patchwork Fri Jul 21 17:24:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 124042 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp369986vqg; Fri, 21 Jul 2023 10:49:52 -0700 (PDT) X-Google-Smtp-Source: APBJJlG3RWVaDv6FMsljSOS/Y5J2Lq67M0A1V/SfVrk2IXHcPn6QO9/dekgKA7Je69VtHiyb/aCJ X-Received: by 2002:a17:902:d505:b0:1b6:76ee:190b with SMTP id b5-20020a170902d50500b001b676ee190bmr2888899plg.35.1689961792530; Fri, 21 Jul 2023 10:49:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689961792; cv=none; d=google.com; s=arc-20160816; b=wTWj6FOHbui/F0+2kM2HmqmUhWULMLgyDE3+Detw/xfP2UbpB/Pou0Cml7MGZ+OPZb 0LB832NjxmnnBKgJF+lJQQPYB+PTFkE4rIIohDlZvX5dDv2sTqio88JMTuyeYb2WPFxI IzNmJMDJLl2t1zfOQuW8FkAQwfSUZIt5fFmbcD4iC5q3mLssqqL8CU7xBcsCuJ0DwpSB 6YZkeNeWaCA7o5WhqhjfSGGy9va+zrElmn6YVvX7kwzMXTF31AT6K1GvSx+e6J9MYsaY WbzX+v+xS2tIquopX3lBwnMaj2Y1kyHYp641aUaXEekjtH9tUkl6VVFyp5ubZYpJEc/Q PeVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=kAzD23HxFnLQVkojbJgEB4UEjXzhftCnufIVR1nhpu8=; fh=fa3AiaE4KLv2j4FY3Qgg7xWWvU+TpRVNhCr9/l8NBoA=; b=Q6LhT1H6C/3dJTGq/CQaVr05V4ek1vow9pfoPCYx7D1vIv0nHyCn6uN3glrguqhucx Tic6xia77PsloSayeKWe1c1PKprxhfMb8XHJFq1KXUMeJiFoVTqViLOd3FMHDaca/0RA 8OBHdsr8K+LbvLVcgCn+9xRgMj3qdq5N4GdOuY8ScZ10TYrBUGPYkCXUg0xkQ3j/wMo5 ZmOzjmYGzRAV8dZWgczbf8A9S0B6c4CxFrNgUJu+txu3cWovek5c66gy2kygtR+SIdcf WZmFQJSPr+x1CYd6lRqMkqI2IiL0PqcqRZ92w5d2Rkx8w3Q9sJWFyIZDFRbnS61D5/jI ralw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="eo1/kXPM"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Fri, 21 Jul 2023 17:24:49 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36LHOgsc023733; Fri, 21 Jul 2023 17:24:45 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3rumhknepm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 21 Jul 2023 17:24:45 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36LHOjM1023763; Fri, 21 Jul 2023 17:24:45 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 36LHOjaH023762; Fri, 21 Jul 2023 17:24:45 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id B01FA32C9; Fri, 21 Jul 2023 22:54:44 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, Mrinmay Sarkar , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] PCI: qcom: Add support for sa8775p SoC Date: Fri, 21 Jul 2023 22:54:33 +0530 Message-Id: <1689960276-29266-3-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689960276-29266-1-git-send-email-quic_msarkar@quicinc.com> References: <1689960276-29266-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GwxYWPrONmwjXIHUa4nnSirwly1VYmFo X-Proofpoint-ORIG-GUID: GwxYWPrONmwjXIHUa4nnSirwly1VYmFo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_10,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 phishscore=0 mlxlogscore=997 impostorscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 adultscore=0 malwarescore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210151 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772053376192715481 X-GMAIL-MSGID: 1772053376192715481 Add support for sa8775p SoC that uses controller version 5.90 reusing the 1.9.0 config. Signed-off-by: Mrinmay Sarkar Reviewed-by: Bjorn Andersson Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index cee4e40..e2f2940 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1613,6 +1613,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_9_0}, { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, From patchwork Fri Jul 21 17:24:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 124036 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp360250vqg; Fri, 21 Jul 2023 10:31:00 -0700 (PDT) X-Google-Smtp-Source: APBJJlEjjMaD7D7n6J7t3cmRKVTM4LqxEmmEaENuMPJbQ9K8YclzI3CtDlqNTqiDZJDJZJZQtNq8 X-Received: by 2002:aa7:d80f:0:b0:51d:955f:9e17 with SMTP id v15-20020aa7d80f000000b0051d955f9e17mr2034296edq.16.1689960659985; Fri, 21 Jul 2023 10:30:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689960659; cv=none; d=google.com; s=arc-20160816; b=PALmSnE58dlVvDMCOQFip5fTzcopnFtdNtS+UN70DbfmcqH6CJcgIi+EUZk1A4dieu TcRmxerXHUwzJcKyergFfNWn+yL/SG1iOgsFSOT3FMkLuC3+U17drqdlk6FtCablNQ+P xYod0NkjBJR8ALdk+0RedIaIK6BWgFa023dpIuasvFj2paI3phnbOJef1YvZ0ce5VOT0 4XYqpMEfIFuco5E5govVyWW/n0fdRRY8hD19ojGErjrYTAuJdHmUXbiHTMAn1F6FQmgi 5y9s40E/DorT3qQZFVUGXt2jn9t2l49g2HiYdcMUnGX436RorWagtVPcAYAapsFTmjsU KkOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=85UC/4/Geciipqr3eLRLQLu1VtLSki/byJNTttdKQ+U=; fh=fa3AiaE4KLv2j4FY3Qgg7xWWvU+TpRVNhCr9/l8NBoA=; b=OQuyXmMEFLPUc89D3xLd91ebyPgVwFXBeIdRJxZqJtUpbd/71+B7nrtyyr3RLUhEis Z5n7alfpRiO4HBNO/9WbPrFf9e+2guZpUDV+v4qX1LPH02leNFajpXQimFVBt/QINYwo BvVN92ORLrdRaqmdJNeNr4/BeQ+SVBCb+TTs5We988EM8H+P5aE8LHwyv0s4Ar3XLf0g BD3Y4NaUnpSKPIxunaEXH8s3vzqwj3vC3edTe0wB0bVRPJFqQH0PwCZvBFvxWFISDTQw rWejfKYSWvp9vHCkm8hYVO8me1IQTYsg2YwserQXwLYqjluXgG+OP/IpJLUvJmPMhyzu yu2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=BQctjkdw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Fri, 21 Jul 2023 17:24:50 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36LHOlin023788; Fri, 21 Jul 2023 17:24:47 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3rumhknepr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 21 Jul 2023 17:24:47 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36LHOlED023783; Fri, 21 Jul 2023 17:24:47 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 36LHOkmQ023782; Fri, 21 Jul 2023 17:24:47 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 55CE632C9; Fri, 21 Jul 2023 22:54:46 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, Mrinmay Sarkar , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes Date: Fri, 21 Jul 2023 22:54:34 +0530 Message-Id: <1689960276-29266-4-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689960276-29266-1-git-send-email-quic_msarkar@quicinc.com> References: <1689960276-29266-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Buy7lTc0HZpSzw2aToXtieGhuNufd8cX X-Proofpoint-GUID: Buy7lTc0HZpSzw2aToXtieGhuNufd8cX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_10,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 phishscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 mlxscore=0 bulkscore=0 spamscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210151 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772052189509658815 X-GMAIL-MSGID: 1772052189509658815 Add pcie dtsi nodes for two controllers found on sa8775p platform. Signed-off-by: Mrinmay Sarkar --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 204 +++++++++++++++++++++++++++++++++- 1 file changed, 202 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 59eedfc..7b55cb7 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -481,8 +481,8 @@ <0>, <0>, <0>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>, <0>; @@ -2357,4 +2357,204 @@ , ; }; + + pcie0: pci@1c00000{ + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <2>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy@1c04000 { + compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x1c04000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, + <&gcc GCC_PCIE_0_PHY_AUX_CLK>; + + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", + "pipediv2", "phy_aux"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pci@1c10000{ + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <1>; + num-lanes = <4>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy@1c14000 { + compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg = <0x0 0x1c14000 0x0 0x4000>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, + <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", + "pipediv2", "phy_aux"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; }; From patchwork Fri Jul 21 17:24:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 124040 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp369328vqg; Fri, 21 Jul 2023 10:48:27 -0700 (PDT) X-Google-Smtp-Source: APBJJlGNQ7gE2AmB3/WwjG1olPjQadJ8EhJ6TYs1cJNumFs+rQc5JM0lNSeQSnGp3CC6gEf1YYMY X-Received: by 2002:a05:6a20:6a28:b0:135:26ad:124 with SMTP id p40-20020a056a206a2800b0013526ad0124mr2605661pzk.5.1689961706736; Fri, 21 Jul 2023 10:48:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689961706; cv=none; d=google.com; s=arc-20160816; b=drTXMGpo493eO0q/Uf9LGOwHtbcKiw7pTpPxo4LJz/lop/ye2nuStYkUthIHgo5lJ/ b3dNEEnI5BTJRynHHXPET1Mgop87mFVjqsTZWmJg4TlAXkr3wpY4ZZyrLuxoKq9PcV3K MgN+ylV8usxMr/AEcoW1+IyOh6oFGRMp/Zz/FuaIqfu4a6b2lgYrLr30Juqr+IpTODZz a5DG1SeMjRs+w+39JwMNePnDnzlVYc1AQx5UEYjy+acUcz9yzvJtEZgK+T3rEZ0U2hl/ e3unrjlNxaA1n5S3tTQCvv8AXHcmodTqUbnoEGasSEmxmaJVpfYRhK2Lu3NPRFFkYMgC kZTg== ARC-Message-Signature: i=1; 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Signed-off-by: Mrinmay Sarkar --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 80 +++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 8c2890b..ed76680 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -552,6 +552,86 @@ bias-pull-down; }; }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio4"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio3"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&pcie0 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; }; &uart10 {