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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n28-20020a056402515c00b0051ddf3cc9e1si1827338edd.609.2023.07.20.23.02.52; Thu, 20 Jul 2023 23:03:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Ys0T9+zL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229679AbjGUFrC (ORCPT + 99 others); Fri, 21 Jul 2023 01:47:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229601AbjGUFq7 (ORCPT ); Fri, 21 Jul 2023 01:46:59 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83B7619B3; Thu, 20 Jul 2023 22:46:57 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36L4TBuT015616; Fri, 21 Jul 2023 05:46:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=4+h6/F8Aj0WysnxgCaBtRIUpva2wYuJ/9mYqckG1fRI=; b=Ys0T9+zLmIuA5RPlNtCr19Whrk8ZYLZjG9eE68G8nafYfFNf+1gcmOsYbSIku3qOxpNx ulLQxIdH0Ke657XSxIOqNQ2h1loGQRDfcisI+TQOzCKOiCp1ZA+pV7AyYXbk3Xhfipt3 BzhgW+2WRIZAY2VIDvgyDmgWi+YOlWvKATMqYDJbnJacV6ULDR/ai9WVG9GVS4p7Xpa8 RkkpH/doFKCn5wRswfXCefsvrM7BGdVIVUkmdjHpH2Ce76pLHxq9eBnXzXGpFIi41Yis Q4+8qq0XqL2zMQuPfE75WqlkyobtVRJzuhTywWyiKTy74kiiCtyWqVnoXmzu79IFFAxp LQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rxxqv2wm6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jul 2023 05:46:51 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36L5ko5j003452 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jul 2023 05:46:50 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 20 Jul 2023 22:46:44 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH v5 1/5] thermal/drivers/tsens: Add TSENS enable and calibration support for V2 Date: Fri, 21 Jul 2023 11:16:15 +0530 Message-ID: <20230721054619.2366510-2-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721054619.2366510-1-quic_ipkumar@quicinc.com> References: <20230721054619.2366510-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WAhgKN-xzaGDScBCnMLQdvrhiJgyjh63 X-Proofpoint-GUID: WAhgKN-xzaGDScBCnMLQdvrhiJgyjh63 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_02,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210052 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772008921092858384 X-GMAIL-MSGID: 1772008921092858384 SoCs without RPM have to enable sensors and calibrate from the kernel. Though TSENS IP supports 16 sensors, not all are used. So used hw_id to enable the relevant sensors. Added new calibration function for V2 as the tsens.c calib function only supports V1. Signed-off-by: Praveenkumar I --- [v5]: Added bitfield.h to fix build error reported by kernel test robot. error: implicit declaration of function 'FIELD_PREP' is invalid in C99 [v4]: Named the values used inside the init_tsens_v2_no_rpm(), used FIELD_PREP() to get the Sn_CONVERSION data and some minor changes in the function variable order and array size. [v3]: Renamed the init function and removed version check in it. Corrected the if check in init_common() at tsens.c [v2]: Added separate init function for tsens v2 which calls init_common and initialize the remaining fields. Reformatted calibrate function and used hw_ids for sensors to enable. drivers/thermal/qcom/tsens-v2.c | 149 ++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 2 +- drivers/thermal/qcom/tsens.h | 3 + 3 files changed, 153 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 29a61d2d6ca3..7190e477b173 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -4,13 +4,32 @@ * Copyright (c) 2018, Linaro Limited */ +#include #include #include +#include #include "tsens.h" /* ----- SROT ------ */ #define SROT_HW_VER_OFF 0x0000 #define SROT_CTRL_OFF 0x0004 +#define SROT_MEASURE_PERIOD 0x0008 +#define SROT_Sn_CONVERSION 0x0060 +#define V2_SHIFT_DEFAULT 0x0003 +#define V2_SLOPE_DEFAULT 0x0cd0 +#define V2_CZERO_DEFAULT 0x016a +#define ONE_PT_SLOPE 0x0cd0 +#define TWO_PT_SHIFTED_GAIN 921600 +#define ONE_PT_CZERO_CONST 94 +#define SW_RST_DEASSERT 0x0 +#define SW_RST_ASSERT 0x1 +#define MEASURE_PERIOD_2mSEC 0x1 +#define RSEULT_FORMAT_TEMP 0x1 +#define TSENS_ENABLE 0x1 +#define SENSOR_CONVERSION(n) (((n) * 4) + SROT_Sn_CONVERSION) +#define CONVERSION_SHIFT_MASK GENMASK(24, 23) +#define CONVERSION_SLOPE_MASK GENMASK(22, 10) +#define CONVERSION_CZERO_MASK GENMASK(9, 0) /* ----- TM ------ */ #define TM_INT_EN_OFF 0x0004 @@ -59,6 +78,11 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* CTRL_OFF */ [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0), [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1), + [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 18), + [CODE_OR_TEMP] = REG_FIELD(SROT_CTRL_OFF, 21, 21), + + /* MAIN_MEASURE_PERIOD */ + [MAIN_MEASURE_PERIOD] = REG_FIELD(SROT_MEASURE_PERIOD, 0, 7), /* ----- TM ------ */ /* INTERRUPT ENABLE */ @@ -104,6 +128,131 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static int tsens_v2_calibrate_sensor(struct device *dev, struct tsens_sensor *sensor, + struct regmap *map, u32 mode, u32 base0, u32 base1) +{ + u32 slope, czero, val; + char name[8]; + int ret; + + /* Read offset value */ + ret = snprintf(name, sizeof(name), "s%d", sensor->hw_id); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(dev, name, &sensor->offset); + if (ret) + return ret; + + /* Based on calib mode, program SHIFT, SLOPE and CZERO */ + switch (mode) { + case TWO_PT_CALIB: + slope = (TWO_PT_SHIFTED_GAIN / (base1 - base0)); + + czero = (base0 + sensor->offset - ((base1 - base0) / 3)); + + val = FIELD_PREP(CONVERSION_SHIFT_MASK, V2_SHIFT_DEFAULT) | + FIELD_PREP(CONVERSION_SLOPE_MASK, slope) | + FIELD_PREP(CONVERSION_CZERO_MASK, czero); + + fallthrough; + case ONE_PT_CALIB2: + czero = base0 + sensor->offset - ONE_PT_CZERO_CONST; + + val = FIELD_PREP(CONVERSION_SHIFT_MASK, V2_SHIFT_DEFAULT) | + FIELD_PREP(CONVERSION_SLOPE_MASK, ONE_PT_SLOPE) | + FIELD_PREP(CONVERSION_CZERO_MASK, czero); + + break; + default: + dev_dbg(dev, "calibrationless mode\n"); + + val = FIELD_PREP(CONVERSION_SHIFT_MASK, V2_SHIFT_DEFAULT) | + FIELD_PREP(CONVERSION_SLOPE_MASK, V2_SLOPE_DEFAULT) | + FIELD_PREP(CONVERSION_CZERO_MASK, V2_CZERO_DEFAULT); + } + + regmap_write(map, SENSOR_CONVERSION(sensor->hw_id), val); + + return 0; +} + +static int tsens_v2_calibration(struct tsens_priv *priv) +{ + struct device *dev = priv->dev; + u32 mode, base0, base1; + int i, ret; + + if (priv->num_sensors > MAX_SENSORS) + return -EINVAL; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "mode", &mode); + if (ret == -ENOENT) + dev_warn(priv->dev, "Calibration data not present in DT\n"); + if (ret < 0) + return ret; + + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base0", &base0); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base1", &base1); + if (ret < 0) + return ret; + + /* Calibrate each sensor */ + for (i = 0; i < priv->num_sensors; i++) { + ret = tsens_v2_calibrate_sensor(dev, &priv->sensor[i], priv->srot_map, + mode, base0, base1); + if (ret < 0) + return ret; + } + + return 0; +} + +static int __init init_tsens_v2_no_rpm(struct tsens_priv *priv) +{ + struct device *dev = priv->dev; + int i, ret; + u32 val = 0; + + ret = init_common(priv); + if (ret < 0) + return ret; + + priv->rf[CODE_OR_TEMP] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[CODE_OR_TEMP]); + if (IS_ERR(priv->rf[CODE_OR_TEMP])) + return PTR_ERR(priv->rf[CODE_OR_TEMP]); + + priv->rf[MAIN_MEASURE_PERIOD] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[MAIN_MEASURE_PERIOD]); + if (IS_ERR(priv->rf[MAIN_MEASURE_PERIOD])) + return PTR_ERR(priv->rf[MAIN_MEASURE_PERIOD]); + + regmap_field_write(priv->rf[TSENS_SW_RST], SW_RST_ASSERT); + + regmap_field_write(priv->rf[MAIN_MEASURE_PERIOD], MEASURE_PERIOD_2mSEC); + + /* Enable available sensors */ + for (i = 0; i < priv->num_sensors; i++) + val |= 1 << priv->sensor[i].hw_id; + + regmap_field_write(priv->rf[SENSOR_EN], val); + + /* Select temperature format, unit is deci-Celsius */ + regmap_field_write(priv->rf[CODE_OR_TEMP], RSEULT_FORMAT_TEMP); + + regmap_field_write(priv->rf[TSENS_SW_RST], SW_RST_DEASSERT); + + regmap_field_write(priv->rf[TSENS_EN], TSENS_ENABLE); + + return 0; +} + static const struct tsens_ops ops_generic_v2 = { .init = init_common, .get_temp = get_temp_tsens_valid, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 98c356acfe98..9dc0c2150948 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -974,7 +974,7 @@ int __init init_common(struct tsens_priv *priv) ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); if (ret) goto err_put_device; - if (!enabled) { + if (!enabled && (tsens_version(priv) != VER_2_X_NO_RPM)) { dev_err(dev, "%s: device not enabled\n", __func__); ret = -ENODEV; goto err_put_device; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 2805de1c6827..b2e8f0f2b466 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -35,6 +35,7 @@ enum tsens_ver { VER_0_1, VER_1_X, VER_2_X, + VER_2_X_NO_RPM, }; enum tsens_irq_type { @@ -168,6 +169,8 @@ enum regfield_ids { TSENS_SW_RST, SENSOR_EN, CODE_OR_TEMP, + /* MEASURE_PERIOD */ + MAIN_MEASURE_PERIOD, /* ----- TM ------ */ /* TRDY */ From patchwork Fri Jul 21 05:46:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 123583 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp5820vqg; Thu, 20 Jul 2023 23:30:14 -0700 (PDT) X-Google-Smtp-Source: APBJJlH3YTc7HZSe4J24qHNBMf5xI0PIpIg8LqVDppcJS4qfzgiDKg9Gm/lFhjivImf89awDFVsZ X-Received: by 2002:aa7:c902:0:b0:521:6275:c9af with SMTP id b2-20020aa7c902000000b005216275c9afmr1085309edt.7.1689921014530; Thu, 20 Jul 2023 23:30:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689921014; cv=none; d=google.com; s=arc-20160816; b=exjhu3OShleoBRK+2I+nfP74Q1/s7BfAb2aUDWmMDeK6nOiMe9Z/BG6WSgEKMN8OAd d6YkK2b4GUHR1L/yq72TPzI/PzfIU4JCFiHt0pdpRUoNPWPBSMzPj8LZD2U5SKlzPvuc u6LswCWbwlbP3Q0PcejSIu2mEVJMkcTsyKZM1/jwzt0M0curKXSgsp5B3D6qozEPSad1 tjVUGae7yLziBrqt6IPhgQXEoDjOBH8yrGc4SRYTiU3DmF3JAbWPX1QLNlnbZK8oEsoo JVOMdDNZtrcewk7I+efHIC4OmHUJMDTOdlsBxgxM4xL1xOo7Y23srOV01F3oa9rRNZ84 TE4Q== ARC-Message-Signature: i=1; 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RPM is not available in the SoC, hence adding new compatible to have the sensor enablement and calibration function. This patch also adds nvmem-cell-names for ipq5332 Reviewed-by: Krzysztof Kozlowski Signed-off-by: Praveenkumar I --- [v5]: No changes. [v4]: Pick up R-b tag [v3]: No changes. [v2]: Followed the order for ipq5332 and added nvmem-cell-names. .../devicetree/bindings/thermal/qcom-tsens.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 27e9e16e6455..cca115906762 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -69,6 +69,7 @@ properties: - description: v2 of TSENS with combined interrupt enum: + - qcom,ipq5332-tsens - qcom,ipq8074-tsens - description: v2 of TSENS with combined interrupt @@ -205,6 +206,15 @@ properties: - const: s9_p2_backup - const: s10_p1_backup - const: s10_p2_backup + - items: + - const: mode + - const: base0 + - const: base1 + - pattern: '^s[0-9]+$' + - pattern: '^s[0-9]+$' + - pattern: '^s[0-9]+$' + - pattern: '^s[0-9]+$' + - pattern: '^s[0-9]+$' "#qcom,sensors": description: @@ -266,6 +276,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-tsens - qcom,ipq8074-tsens then: properties: @@ -281,6 +292,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-tsens - qcom,ipq8074-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 From patchwork Fri Jul 21 05:46:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 123568 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3586131vqt; Thu, 20 Jul 2023 23:05:11 -0700 (PDT) X-Google-Smtp-Source: APBJJlHTawLh+piPGzs2B7BPWxlH6T2/6icqEkg5WzrFt/ywtaukzsi6lzDJm6dzu2WWMPtlQ1Eo X-Received: by 2002:a17:902:bc83:b0:1b8:9551:a705 with SMTP id bb3-20020a170902bc8300b001b89551a705mr707399plb.55.1689919511464; Thu, 20 Jul 2023 23:05:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689919511; cv=none; d=google.com; s=arc-20160816; b=U1JmU3h43iycAWHCiLfnoxqpepvSLeedVXE17WWCVYcRWiwGgQauNRaTCJd0QsDF0l T/yh45UwEaXrV95c5DBVhL2fvTAE1DY6/sXLQqq7Tmr9kl/bVSXhhyZBoWx6GEAAAWLC sNqbyCACvKCEf44cXeDkItqA0D8CMhvReFS+Qkd/rQfJSXAklppfVAY01UhcC1hQyBtz S06/KIyBKZmJklcby+QC7zyD+l+4lCtOl/QnScI8Kk2np4v9S0oHecPRqkaZ6wY74xmF KUl70YXxdAtUjJhAFCukHXR3MoqRQp8q1L4KoFRe6TW/xIvsXvMu0fowtnxBmHXj9+XL p9zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=71CbpnNRMkXI1Pos5VsiU4h+wLSJfDujY+eq0Ik/wD8=; fh=X4rJ+cR0B+d5Oa7pFIBp3MHYxg8a+8b0Sx0w3zuICOE=; b=ECoPrGoP9+0DDsw923lWGqTpzaV0S/PcQQUc0/n0/MzpXGjGZfATqB8K+gso2VF9jH llB3nTFodsQ7hd0vAUxDbiUZHqymTFKp7MH7Z2g9J2/HQG2aQyAkfkkUoFLAnMcaWHdu 0vrYvVQs2+1j8SYN2rIya75vehkgbClB48jSC4bksfYTZTwwKSqD+LnZAUTjR1+FgPSr mZf4ZVHsZW+rdEyXjxuL1BfA9A/wKVjSu1KNs//BeTYzl34/hpZXBfKip6LTdJiBJhuZ HMBCrP1kMYDMjX1U6KmjcnNQQpIso3GHm5jlK6xjhhjJ+jbirMcFu3JQ3DwSMobHDoU0 LDug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=hVg4wU7e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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This patch adds the tsense node with nvmem cells for calibration data. Signed-off-by: Praveenkumar I --- [v5]: No changes. [v4]: No changes. [v3]: Reordered device nodes according to the address. [v2]: Included qfprom nodes only for available sensors and removed the offset suffix. arch/arm64/boot/dts/qcom/ipq5332.dtsi | 66 +++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db44624..026f99fda00c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -150,6 +150,46 @@ qfprom: efuse@a4000 { reg = <0x000a4000 0x721>; #address-cells = <1>; #size-cells = <1>; + + s11: s11@3a5 { + reg = <0x3a5 0x1>; + bits = <4 4>; + }; + + s12: s12@3a6 { + reg = <0x3a6 0x1>; + bits = <0 4>; + }; + + s13: s13@3a6 { + reg = <0x3a6 0x1>; + bits = <4 4>; + }; + + s14: s14@3ad { + reg = <0x3ad 0x2>; + bits = <7 4>; + }; + + s15: s15@3ae { + reg = <0x3ae 0x1>; + bits = <3 4>; + }; + + tsens_mode: mode@3e1 { + reg = <0x3e1 0x1>; + bits = <0 3>; + }; + + tsens_base0: base0@3e1 { + reg = <0x3e1 0x2>; + bits = <3 10>; + }; + + tsens_base1: base1@3e2 { + reg = <0x3e2 0x2>; + bits = <5 10>; + }; }; rng: rng@e3000 { @@ -159,6 +199,32 @@ rng: rng@e3000 { clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5332-tsens"; + reg = <0x4a9000 0x1000>, + <0x4a8000 0x1000>; + nvmem-cells = <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&s11>, + <&s12>, + <&s13>, + <&s14>, + <&s15>; + nvmem-cell-names = "mode", + "base0", + "base1", + "s11", + "s12", + "s13", + "s14", + "s15"; + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5332-tlmm"; reg = <0x01000000 0x300000>; From patchwork Fri Jul 21 05:46:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 123570 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3586563vqt; Thu, 20 Jul 2023 23:06:04 -0700 (PDT) X-Google-Smtp-Source: APBJJlEM5vlcdDbwX8EVdwI6xfKhlSC1AZQYgyDqsutU7xuV6ehXA5niQ4hqBUbK2ByV/rv2u5rH X-Received: by 2002:a0d:ca84:0:b0:577:3ad5:54de with SMTP id m126-20020a0dca84000000b005773ad554demr1206160ywd.38.1689919564082; Thu, 20 Jul 2023 23:06:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689919564; cv=none; d=google.com; s=arc-20160816; b=ZXbigKet8KTaPfPny8jAy3mgCO5ApQSQRpXDGp787C3Fi56pM6hUZS4OquLB7iBTeN ZofugrYuM85fQL5WxZWMM2nzfspigAhDKNEk46ye1yaF19eImutCOKVgyKqT0AGk97NT QVAlKNe/9c7VdV2gOEwQldTelBFofq7r2mnuSF2mnKNiEGZ+dcv68Pa0hG9IXROBsZJA U5uN59AuvSkKO6WfXuqLbvFU05ZHZO6r/0SYJK2+iK/FtqMzgrssQdOtEOVSmy4AwdUP ah6AHyd4o9uAzwuwIo+dcRZ2JgdK6paey8yCK27R/TXEumxOLgHzk3R2fwQ0jRl3/bN2 ix6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=D4BQkjsQEb/XBcfxrn1viqb6mvOgEbyrf+okFWbI5XM=; fh=X4rJ+cR0B+d5Oa7pFIBp3MHYxg8a+8b0Sx0w3zuICOE=; b=sxEc2f7OUoB9VOp8C9Q6kDd9CmHmEPfodwZDaKGsQyKTyLxcx+bI8x1GN9IXEFso0A IknosHJiZml70kyuaUWDv33SlLzKQpyHNALp9sT9j/n7uCIRPkpHWvJccVZ75ZT4uAgA sM9a39WFmN4WmoYdDorjQogmRhWwZacFnh13BuBt5XLBwEwq8f84eGc+dGdF6g12U5UB 9OQDb77QC7wIzJV50H3M4vuOdkdkWxzeC5ZiLs2fA29XoPuzk9MEpiUADCNxOiIbiv8y F3Oa4U9gzUNMWCr/TAX9a10MaHcyTYxLlV/bUtmmApD4Rr5CGeiZJAgY6iAP5Qs2XX4E dctA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=pgDIccmw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Praveenkumar I --- [v5]: No changes. [v4]: No changes. [v3]: Pick up R-b tag [v2]: Added passive trips and alignment change. arch/arm64/boot/dts/qcom/ipq5332.dtsi | 78 +++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 026f99fda00c..fe9f0fdd44ee 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -480,4 +480,82 @@ timer { , ; }; + + thermal-zones { + rfa-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 11>; + + trips { + rfa-0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + rfa-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 12>; + + trips { + rfa-1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + misc-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 13>; + + trips { + misc-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 14>; + + trips { + cpu-top-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu-passive { + temperature = <105000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + top-glue-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 15>; + + trips { + top-glue-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; }; From patchwork Fri Jul 21 05:46:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 123596 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp9939vqg; Thu, 20 Jul 2023 23:39:34 -0700 (PDT) X-Google-Smtp-Source: APBJJlGNp5SYXziNmK4JZSpVC7O4+rYjm3OpFxPsWhMExP411dpzXu8t/VTKaCAO1xr31K7kv7bk X-Received: by 2002:a05:6358:528f:b0:135:a10e:1ed0 with SMTP id g15-20020a056358528f00b00135a10e1ed0mr1033821rwa.23.1689921573769; Thu, 20 Jul 2023 23:39:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689921573; cv=none; d=google.com; s=arc-20160816; b=Fm3+bCIO+Sxa7sA91bcWZh3YtyFP2sCLfz/CTkXBP+meO+HVdg1AyZ0RGakL86e1VZ RK+zfaDeMJsmY7ccE4PxMhhNpVc1M50SgzlXqt6jQxogl9DnYcMr66KTnxAaAngPMkQ+ DHM6dclJ2eccjoKnPHMRXjEkdfDgmn9GQhesD3OU8kg8gSnL8pqxTH6BHlvedWkrYIaq C3CJCoF+M/QZVMr5I/3yUwOtEksVuvgXiQB3AjMRD3pKjr1YwHPOJ48nQwsRMVHEe5zc CTl9UtQnCZF5PqAPVPTsjIArjnzu6OCKI0JNzALYaTI4F+VYb0GZINLvSVzm3o3j/zdz etZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aDrEGWzK5xW/XLzPrRNTbcEJP+wW9LlOvmNV/qztgfg=; fh=X4rJ+cR0B+d5Oa7pFIBp3MHYxg8a+8b0Sx0w3zuICOE=; b=hySXQzzhhSyJALtXrjPvzkRBRdQVyKP9OAF9kqMpTKY9zWnIXap7rjRqo5xDCOp0Iz Q6mhS5tOcL0k2dqqjpt3J4MlTTHDBb2k7hKYKgqqso12MdG/gbPZJUPz2afoV85S0ofu PP1IwUEtMpA43amVR/QZLLvYwnEls3PsRWnfDxK3f+m54qaV/MmeFBI8Vpmm2X/Dnbt8 VULvCn/lbDFB2mWCYuLokoY+9htnMEfmbZUL8ctvIDrvJbG0+kUdQV6mtzVRvYY0mDOL L0nher7eUx5XhJZIZBRcXAWW2z51Tkfnm93Z57B/Xkqq76OMniNGJFv2QTpfW0s3QuW4 k+UQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=PsKykelV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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It does not have RPM and kernel needs to take care of sensor enablement, calibration. Hence introduced new feature_config, ops and data for IPQ5332. Signed-off-by: Praveenkumar I --- [v5]: No changes. [v4]: No changes. [v3]: No changes. [v2]: Added tsens_features for ipq5332 with VER_2_X_NO_RPM. Used hw_ids to mention the available sensors. Dropped v2 in ops_ipq5332. drivers/thermal/qcom/tsens-v2.c | 25 +++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 7190e477b173..512839597ac6 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -69,6 +69,17 @@ static struct tsens_features ipq8074_feat = { .trip_max_temp = 204000, }; +static struct tsens_features ipq5332_feat = { + .ver_major = VER_2_X_NO_RPM, + .crit_int = 1, + .combo_int = 1, + .adc = 0, + .srot_split = 1, + .max_sensors = 16, + .trip_min_temp = 0, + .trip_max_temp = 204000, +}; + static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* ----- SROT ------ */ /* VERSION */ @@ -270,6 +281,20 @@ struct tsens_plat_data data_ipq8074 = { .fields = tsens_v2_regfields, }; +static const struct tsens_ops ops_ipq5332 = { + .init = init_tsens_v2_no_rpm, + .get_temp = get_temp_tsens_valid, + .calibrate = tsens_v2_calibration, +}; + +struct tsens_plat_data data_ipq5332 = { + .num_sensors = 5, + .ops = &ops_ipq5332, + .hw_ids = (unsigned int []){11, 12, 13, 14, 15}, + .feat = &ipq5332_feat, + .fields = tsens_v2_regfields, +}; + /* Kept around for backward compatibility with old msm8996.dtsi */ struct tsens_plat_data data_8996 = { .num_sensors = 13, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 9dc0c2150948..af58a94628a8 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -1106,6 +1106,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,ipq8074-tsens", .data = &data_ipq8074, + }, { + .compatible = "qcom,ipq5332-tsens", + .data = &data_ipq5332, }, { .compatible = "qcom,mdm9607-tsens", .data = &data_9607, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index b2e8f0f2b466..1dde363914cd 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -648,6 +648,6 @@ extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8 extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; /* TSENS v2 targets */ -extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; +extern struct tsens_plat_data data_8996, data_ipq8074, data_ipq5332, data_tsens_v2; #endif /* __QCOM_TSENS_H__ */