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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 7-20020a630007000000b00553836cb761si2017110pga.717.2023.07.20.20.20.58; Thu, 20 Jul 2023 20:21:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=Z62fCUfh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229731AbjGUCmJ (ORCPT + 99 others); Thu, 20 Jul 2023 22:42:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229534AbjGUCmE (ORCPT ); Thu, 20 Jul 2023 22:42:04 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 810F7268E; Thu, 20 Jul 2023 19:41:57 -0700 (PDT) X-UUID: 2534e7b4277011ee9cb5633481061a41-20230721 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=0GTgfHZrkSs0xnUZ/LSuab61h/gYO3SBlbVog4q7hk8=; b=Z62fCUfh1fOj6pjKtKMeL5+IbqVdsWICr0II1gO0DEiVXvTmA8XXcOkbxr9KU1bg2389S4wyeaHn+eMGkKb2MzZbM4MZQaaLiHY9JOXEQ5ZWIeixJuLB7DRIGSoBs4Y8luAXHBkByoBbpu179snKDlBOZzFdF3r2X+EQTjm9NqE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:c0cac047-093c-4f6f-9490-7af227363221,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:176cd25,CLOUDID:6c8df44c-06c1-468b-847d-5b62d44dbb9b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 2534e7b4277011ee9cb5633481061a41-20230721 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1602522252; Fri, 21 Jul 2023 10:41:50 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 21 Jul 2023 10:41:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 21 Jul 2023 10:41:49 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v15 01/13] dt-bindings: remoteproc: mediatek: Improve the rpmsg subnode definition Date: Fri, 21 Jul 2023 10:41:20 +0800 Message-ID: <20230721024132.6548-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230721024132.6548-1-tinghan.shen@mediatek.com> References: <20230721024132.6548-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771998724332985783 X-GMAIL-MSGID: 1771998724332985783 Improve the definition of the rpmsg subnode by assigning a distinct node name and adding the definition source of node properties. Signed-off-by: Tinghan Shen Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/remoteproc/mtk,scp.yaml | 31 +++++++++---------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 895415772d1d..271081df0e46 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -58,6 +58,18 @@ properties: memory-region: maxItems: 1 + cros-ec-rpmsg: + $ref: /schemas/mfd/google,cros-ec.yaml + description: + This subnode represents the rpmsg device. The properties + of this node are defined by the individual bindings for + the rpmsg devices. + + required: + - mediatek,rpmsg-name + + unevaluatedProperties: false + required: - compatible - reg @@ -89,21 +101,7 @@ allOf: reg-names: maxItems: 2 -additionalProperties: - type: object - description: - Subnodes of the SCP represent rpmsg devices. The names of the devices - are not important. The properties of these nodes are defined by the - individual bindings for the rpmsg devices. - properties: - mediatek,rpmsg-name: - $ref: /schemas/types.yaml#/definitions/string-array - description: - Contains the name for the rpmsg device. Used to match - the subnode to rpmsg device announced by SCP. - - required: - - mediatek,rpmsg-name +additionalProperties: false examples: - | @@ -118,7 +116,8 @@ examples: clocks = <&infracfg CLK_INFRA_SCPSYS>; clock-names = "main"; - cros_ec { + cros-ec-rpmsg { + compatible = "google,cros-ec-rpmsg"; mediatek,rpmsg-name = "cros-ec-rpmsg"; }; }; From patchwork Fri Jul 21 02:41:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 123526 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3522043vqt; Thu, 20 Jul 2023 20:07:40 -0700 (PDT) X-Google-Smtp-Source: APBJJlG2qA/gmeJxKSM+tLM0LQiJxVvJl4p/iz9GglzzivLa7nE+zsgjqW4DVyIdGTJArrLy3tLS X-Received: by 2002:a17:907:271a:b0:993:ffcb:ad4e with SMTP id w26-20020a170907271a00b00993ffcbad4emr504303ejk.13.1689908860042; Thu, 20 Jul 2023 20:07:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689908860; cv=none; d=google.com; s=arc-20160816; b=Py3cJ3PoHCBG0jvwo0zq63y06Oyd4A9gYi5jsjdSUUBP51C+rIbjemGR0Ia/70idhk ELArrEGeTCrU/fSt7c7/L0gW80TXuNWNbbJ3sgqrD7AyAf0e9wT+5j3aejG19rW2A6sq 0HRC89lKx4VHfjJi2GWPVgvt3Q/WoD+9cyE3hB2R7u5LX2KqAvFt/fAX+2jnYo3dAnAJ P/ZxnCjqp8i/2b3kO5sfcZyHA7B7mE1SFGHOMX5g/0WgbRQWeRLSY3g1oFiTd7ZVSfwP Is6loHKX71T0+JcY2ycGQfiF/d6IjKDSnPqllh35O8jN/wU5t4sjoPCEeTF6Yw8uIVTV 2YIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=0v1sHSdRL6Qx9RsSEfvIFRQuGdYV7Ul8S2vCf20EzFw=; fh=fiUFlTmdXAnPLHH0bIyIc4brKi/t2/OmtpRJQ8s00Ug=; b=Lf44mZuKCan2rP3Ct6AOwPaY1BtX5xXUH6oPKe20AgVB5r/FMJM+v6b7N6q2RlckO8 n0B0Wsrr1sEI8blrY/sC2RgJ7UMMFVpZ0aHtbatN9UM98djAvkJrWAAoxN0Fj9ZqhHbo gVQ8A7WRFv1/++0KEcZJaDXxH7vbP7g6jZM4Z9bkJtid8eQfNxk9TX/by00djaUTedcS fyW774zHL/ZXruYwG47ljL74qXkxoTb9UIM01u0sLEXakqMkdQhEWyNgny3XrSbhU/h1 HM4YX3hYlOCt20HI4h8dsptZEc1lRTzXOKb4BiJYwixbZDLehwASXLb5Y56WgJsRqSl7 MT1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=tUMpiC0R; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Acked-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 6ce16a265e05..34076ba28fd0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -831,7 +831,7 @@ pinctrl-names = "default"; pinctrl-0 = <&scp_pins>; - cros_ec { + cros-ec-rpmsg { compatible = "google,cros-ec-rpmsg"; mediatek,rpmsg-name = "cros-ec-rpmsg"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 0e8b34117090..1bbc994bc109 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1284,7 +1284,7 @@ pinctrl-names = "default"; pinctrl-0 = <&scp_pins>; - cros-ec { + cros-ec-rpmsg { compatible = "google,cros-ec-rpmsg"; mediatek,rpmsg-name = "cros-ec-rpmsg"; }; From patchwork Fri Jul 21 02:41:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 123531 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3527620vqt; Thu, 20 Jul 2023 20:23:54 -0700 (PDT) X-Google-Smtp-Source: APBJJlGSyXtKZIl8gRBwUzlo3pURyDbBC3kQXnzOt20o31dKQ62TkVcoMO/X5ubwQ3iIA69tdgzm X-Received: by 2002:a17:903:2445:b0:1b8:a7ec:38c5 with SMTP id l5-20020a170903244500b001b8a7ec38c5mr753891pls.57.1689909833757; Thu, 20 Jul 2023 20:23:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689909833; cv=none; d=google.com; s=arc-20160816; b=D6ThDu8CdtX5h/mxWvaKQjeyTIJXnc8trJ3+AL69BAdJKF2yHaeOo4dqBMltWFaxs0 Q/PTCRbqBscJuhNuR9BvnlSUC4oR0i2kblpbOjqY4Nfi0SlHnm5gNSJGW9MgfdMIk9X4 K/ap6Bx0ugQuqZCuNLhv/vFJYLHfcfNp787RuQphEbXKQFXE7eimye7BWJsk0XDPn2O5 po4Jv94CZvS7NPK3tX2102+A5bJU5YNIcVpsGUgDgwCuZldIUJZG548C0RivkYJRvC9s YNjmKbZswfGC0FTmVv7v4OpP4HWoEMvGg4EvxfL56JRlaWA8v+IXCk69bdeeIibSrC+7 COZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=mHZvfrM0o5UaIt01vL+X0Xi78aCQjddfdApBpcmPqT8=; fh=fiUFlTmdXAnPLHH0bIyIc4brKi/t2/OmtpRJQ8s00Ug=; b=zyclcydahiSp3gXgszOvVebj2K+w/ZTl8ayKpF/eZdromnUzbEacqmkMjp1zPxr8bb GJHFIhyFIvfMoGybJ5Wcl0911Zc7s7WNd5UZw4myJsRposnawKiH/tMj6rvGWAcTX4uG mG/OIUzfMtVd/8bwa2Zm8j7rk2JHI0WcZK5PgIIHSDaoNIsM+em4H+y2qO6KTgwQrRBy lB7U+xdYD6H0Ub/h4aRMDodreV62U7c+XptovvJAOLrwgDIiHFQRlkcjtZUjc7XKiI8c mCmsZ4tLu2EfSnNSvYEcIy9dJsyeK1sLhUKKRHTSt5XkpOaliu5DgeeDTOzpCRrk0Y5z yUSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="k3a3feZ/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Under different applications, the MT8195 SCP can be used as single-core or dual-core. This change keeps the single-core definitions and adds new definitions for the dual-core use case. Signed-off-by: Tinghan Shen Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/remoteproc/mtk,scp.yaml | 145 +++++++++++++++++- 1 file changed, 141 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 271081df0e46..09102dda4942 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt8188-scp - mediatek,mt8192-scp - mediatek,mt8195-scp + - mediatek,mt8195-scp-dual reg: description: @@ -31,10 +32,7 @@ properties: reg-names: minItems: 2 - items: - - const: sram - - const: cfg - - const: l1tcm + maxItems: 3 clocks: description: @@ -70,6 +68,81 @@ properties: unevaluatedProperties: false + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: + description: + Standard ranges definition providing address translations for + local SCP SRAM address spaces to bus addresses. + +patternProperties: + "^scp@[a-f0-9]+$": + type: object + description: + The MediaTek SCP integrated to SoC might be a multi-core version. + The other cores are represented as child nodes of the boot core. + There are some integration differences for the IP like the usage of + address translator for translating SoC bus addresses into address space + for the processor. + + Each SCP core has own cache memory. The SRAM and L1TCM are shared by + cores. The power of cache, SRAM and L1TCM power should be enabled + before booting SCP cores. The size of cache, SRAM, and L1TCM are varied + on differnt SoCs. + + The SCP cores do not use an MMU, but has a set of registers to + control the translations between 32-bit CPU addresses into system bus + addresses. Cache and memory access settings are provided through a + Memory Protection Unit (MPU), programmable only from the SCP. + + properties: + compatible: + enum: + - mediatek,scp-core + + reg: + description: The base address and size of SRAM. + maxItems: 1 + + reg-names: + const: sram + + interrupts: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + If present, name (or relative path) of the file within the + firmware search path containing the firmware image used when + initializing sub cores of multi-core SCP. + + memory-region: + maxItems: 1 + + cros-ec-rpmsg: + $ref: /schemas/mfd/google,cros-ec.yaml + description: + This subnode represents the rpmsg device. The properties + of this node are defined by the individual bindings for + the rpmsg devices. + + required: + - mediatek,rpmsg-name + + unevaluatedProperties: false + + required: + - compatible + - reg + - reg-names + + additionalProperties: false + required: - compatible - reg @@ -99,7 +172,37 @@ allOf: reg: maxItems: 2 reg-names: + items: + - const: sram + - const: cfg + - if: + properties: + compatible: + enum: + - mediatek,mt8192-scp + - mediatek,mt8195-scp + then: + properties: + reg: + maxItems: 3 + reg-names: + items: + - const: sram + - const: cfg + - const: l1tcm + - if: + properties: + compatible: + enum: + - mediatek,mt8195-scp-dual + then: + properties: + reg: maxItems: 2 + reg-names: + items: + - const: cfg + - const: l1tcm additionalProperties: false @@ -121,3 +224,37 @@ examples: mediatek,rpmsg-name = "cros-ec-rpmsg"; }; }; + + - | + scp@10500000 { + compatible = "mediatek,mt8195-scp-dual"; + reg = <0x10720000 0xe0000>, + <0x10700000 0x8000>; + reg-names = "cfg", "l1tcm"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10500000 0x100000>; + + scp@0 { + compatible = "mediatek,scp-core"; + reg = <0x0 0xa0000>; + reg-names = "sram"; + + cros-ec-rpmsg { + compatible = "google,cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; + }; + + scp@a0000 { + compatible = "mediatek,scp-core"; + reg = <0xa0000 0x20000>; + reg-names = "sram"; + + cros-ec-rpmsg { + compatible = "google,cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; + }; + }; From patchwork Fri Jul 21 02:41:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 123528 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3526293vqt; Thu, 20 Jul 2023 20:20:03 -0700 (PDT) X-Google-Smtp-Source: APBJJlGDqOyWJPkejqkWFyv+AgA7alBm7GYHG4k2kFXFcBEcYrJokoq70LPFeZ9NyaAb3ibglg3c X-Received: by 2002:a05:6808:15a1:b0:3a4:6691:9340 with SMTP id t33-20020a05680815a100b003a466919340mr912962oiw.41.1689909603228; Thu, 20 Jul 2023 20:20:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689909603; cv=none; d=google.com; s=arc-20160816; b=bhK9MnII6IkBqZynwDWOJibPrKr9/S8HM/g+KeEAQOH36n1Vy2Ckhvk2owLa53UsBz BSuY0mWyy4Arj57VlV0PJ0ZLyLNYyW+woKviYvFPZOXg103aoNoDvnn+q3HalLNH9DIq 3EFBycAiKNrKJVABotnFZdtdDzkeQ/z7OdO+4jugfTw66Cj8Jdbb8tDcfrT0pjOwO1Zg Jkgji7cDD3yCT3O88ZncbZubX8dCRMavEHYLG16U7I26KXLI7BP9oZGNv7PiqdtdDGMw 6gIstdol8huoGFJPfY11DKhrf+Z3IbTXirO2hjcoV6CfPmVZtXZNhg5AVWfCbyvcjW+G QJEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=j+QYraQbzb9ohLMzNn/JclhKPYuqSnCdv9f3/SYy3Jw=; fh=fiUFlTmdXAnPLHH0bIyIc4brKi/t2/OmtpRJQ8s00Ug=; b=F4IJI5sRHHpn/a5vCW+b1pn4+uXYplBL2YhFk8YBxFtbSDMgNaUbGlsxDnUPh+XFcC BHk6HQDec3yFedSIFIFjmQ31aJcWvo5qXn7dD8wVjSl0S7FH+t7OHWZes3OTYiKroKQ4 wnkeES6D5V9XKDXUebDZ0dETqZpizRMkiaRP7rSVZrr0c58aUEqsgsvpTerGE14/T9d1 /niZKiFXkvcvKLOXserloT2vfDYDKa+7qfoJk/UQibnSqLwc1JTU7Su5ByBEgcV2NTOU yuVFdzOkoINwIDJqJlrJXKk6PFIfvsUD/mvQFVUAk3YZnWIQds9qfxKImhVnWcDqRuzT vtWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=PgHz3Qn8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r20-20020a6560d4000000b0055764ab00d4si1945519pgv.877.2023.07.20.20.19.49; Thu, 20 Jul 2023 20:20:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=PgHz3Qn8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229818AbjGUCmY (ORCPT + 99 others); Thu, 20 Jul 2023 22:42:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229655AbjGUCmG (ORCPT ); Thu, 20 Jul 2023 22:42:06 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8220D271E; Thu, 20 Jul 2023 19:42:00 -0700 (PDT) X-UUID: 255501e8277011ee9cb5633481061a41-20230721 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=j+QYraQbzb9ohLMzNn/JclhKPYuqSnCdv9f3/SYy3Jw=; b=PgHz3Qn8NEclIsBdn8B7LRZWnV4yt8/i+stttZyyOOSFRPe3yLLadhxd0LRzInhWXYnvLPof25X25ZadBiWi8VcGwZ4dJtOuSPIr79I77l1YvCB1gv1yWlPIRWx1IZGJuWxgdaFWBm3J3hlvQ2+FW40gLKDw0D07kWqHnr7Xeg8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:62d7bf88-590e-4100-bcd0-3836a7034e3c,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:176cd25,CLOUDID:6d8df44c-06c1-468b-847d-5b62d44dbb9b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 255501e8277011ee9cb5633481061a41-20230721 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1271037973; Fri, 21 Jul 2023 10:41:51 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 21 Jul 2023 10:41:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 21 Jul 2023 10:41:50 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v15 04/13] remoteproc: mediatek: Add MT8195 SCP core 1 operations Date: Fri, 21 Jul 2023 10:41:23 +0800 Message-ID: <20230721024132.6548-5-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230721024132.6548-1-tinghan.shen@mediatek.com> References: <20230721024132.6548-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771998652200334072 X-GMAIL-MSGID: 1771998652200334072 The SCP rproc driver has a set of chip dependent callbacks for boot sequence and IRQ handling. Implement these callbacks for MT8195 SCP core 1. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- drivers/remoteproc/mtk_common.h | 9 ++++++ drivers/remoteproc/mtk_scp.c | 55 +++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index ea6fa1100a00..c0905aec3b4b 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -47,6 +47,7 @@ #define MT8192_SCP2SPM_IPC_CLR 0x4094 #define MT8192_GIPC_IN_SET 0x4098 #define MT8192_HOST_IPC_INT_BIT BIT(0) +#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) #define MT8192_CORE0_SW_RSTN_CLR 0x10000 #define MT8192_CORE0_SW_RSTN_SET 0x10004 @@ -56,6 +57,14 @@ #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) +#define MT8195_CPU1_SRAM_PD 0x1084 +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 +#define MT8195_CORE1_SW_RSTN_SET 0x20004 +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_CFG 0x20034 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index dcc94ee2458d..48e759c2d486 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -176,6 +176,16 @@ static void mt8192_scp_reset_deassert(struct mtk_scp *scp) writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); } +static void mt8195_scp_c1_reset_assert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_SET); +} + +static void mt8195_scp_c1_reset_deassert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_CLR); +} + static void mt8183_scp_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -212,6 +222,18 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->reg_base + MT8195_SSHUB2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) + scp_ipi_handler(scp); + + writel(scp_to_host, scp->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); +} + static irqreturn_t scp_irq_handler(int irq, void *priv) { struct mtk_scp *scp = priv; @@ -453,6 +475,18 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) return 0; } +static int mt8195_scp_c1_before_load(struct mtk_scp *scp) +{ + scp->data->scp_reset_assert(scp); + + scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* enable MPU for all memory regions */ + writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + + return 0; +} + static int scp_load(struct rproc *rproc, const struct firmware *fw) { struct mtk_scp *scp = rproc->priv; @@ -625,6 +659,15 @@ static void mt8195_scp_stop(struct mtk_scp *scp) writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); } +static void mt8195_scp_c1_stop(struct mtk_scp *scp) +{ + /* Power off CPU SRAM */ + scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* Disable SCP watchdog */ + writel(0, scp->reg_base + MT8195_CORE1_WDT_CFG); +} + static int scp_stop(struct rproc *rproc) { struct mtk_scp *scp = rproc->priv; @@ -989,6 +1032,18 @@ static const struct mtk_scp_of_data mt8195_of_data = { .host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT, }; +static const struct mtk_scp_of_data mt8195_of_data_c1 = { + .scp_clk_get = mt8195_scp_clk_get, + .scp_before_load = mt8195_scp_c1_before_load, + .scp_irq_handler = mt8195_scp_c1_irq_handler, + .scp_reset_assert = mt8195_scp_c1_reset_assert, + .scp_reset_deassert = mt8195_scp_c1_reset_deassert, + .scp_stop = mt8195_scp_c1_stop, + .scp_da_to_va = mt8192_scp_da_to_va, + .host_to_scp_reg = MT8192_GIPC_IN_SET, + .host_to_scp_int_bit = MT8195_CORE1_HOST_IPC_INT_BIT, +}; + static const struct of_device_id mtk_scp_of_match[] = { { .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data }, { .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data }, From patchwork Fri Jul 21 02:41:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 123536 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3531455vqt; Thu, 20 Jul 2023 20:35:53 -0700 (PDT) X-Google-Smtp-Source: APBJJlHqWdgogaD2nMCph8bCsCwXmlWcYKqHybIMc3MqzFAe5nK7/2aFU1tPWwaOrgHiMPwh9xDQ X-Received: by 2002:a17:907:7625:b0:99b:4d3c:d7e4 with SMTP id jy5-20020a170907762500b0099b4d3cd7e4mr542686ejc.63.1689910553477; Thu, 20 Jul 2023 20:35:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689910553; cv=none; d=google.com; s=arc-20160816; b=ZZQ7cbVF87+KsIeZn8A3yRBz6uumeXZTjsDhW9bhaQp5S4Fd5vCWCorJ8HiovCAQFL KVkj3wYWsnlMLkrqwvaIxWhM6Rws917C/cjhvhgjbqryIiCvrFfIjO8qpjhwIrp8PUpK PL5uNmSJqAI1TKkEKeTCYoTjdTAkLA4t3ToNZL+jFqen/Pb1/AGPRF1EXuH+CYhKaAIK tGds+3aIYud7hMcekAMb1NznYQSx3dK5ly4oYONPqCXH1AX1YU1y+lVY4IAetbkcg7ii nLCDK+X+y8ca7vsykVbJNMkp8qqK6pYzeeq0i7bQ5/PH+dhv3b0kQ8RtQTAbs+CIdCdb PaMQ== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z10-20020a1709063a0a00b00991df86ac08si1629982eje.256.2023.07.20.20.35.29; Thu, 20 Jul 2023 20:35:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=aqUZUKqM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230028AbjGUCmk (ORCPT + 99 others); Thu, 20 Jul 2023 22:42:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229690AbjGUCmH (ORCPT ); Thu, 20 Jul 2023 22:42:07 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80A062727; Thu, 20 Jul 2023 19:42:01 -0700 (PDT) X-UUID: 258b3268277011ee9cb5633481061a41-20230721 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=xqe4y7akWk4vh9DHQ2bMXFCj7hfb7W/6pohIRXHZLEY=; b=aqUZUKqMSNcOgEzqzObWBsxKi7B9a+563dp3rI2UVRE02eQTo4rCwjQr9+cHKtka4SUjc/67Dm47W7mnWTu1SkaBlYur8d/7dGTSEZl0OATYIdWsHrOonzt7R/ACSygvVtbvpUXeJQMqi2/hqyE/spTkxTZNtwr1LDsxMNgEo+M=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:d7fb089e-e4f8-4f57-b6c8-49afd5fd92e6,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.28,REQID:d7fb089e-e4f8-4f57-b6c8-49afd5fd92e6,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:176cd25,CLOUDID:dbf1e88e-7caa-48c2-8dbb-206f0389473c,B ulkID:230721104152KQQFPAH6,BulkQuantity:0,Recheck:0,SF:17|19|48|38|29|28,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_FSD,TF_CID_SPAM_SNR,TF_CID_SPAM_SDM,TF_CID_SPAM_ASC, TF_CID_SPAM_FAS X-UUID: 258b3268277011ee9cb5633481061a41-20230721 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 631241489; Fri, 21 Jul 2023 10:41:51 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 21 Jul 2023 10:41:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 21 Jul 2023 10:41:50 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Tinghan Shen" CC: , , , , , Subject: [PATCH v15 05/13] remoteproc: mediatek: Extract SCP common registers Date: Fri, 21 Jul 2023 10:41:24 +0800 Message-ID: <20230721024132.6548-6-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230721024132.6548-1-tinghan.shen@mediatek.com> References: <20230721024132.6548-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771999648522547657 X-GMAIL-MSGID: 1771999648522547657 This is the 1st preliminary steps for probing multi-core SCP. The registers of config and l1tcm are common on single-core SCP and multi-core SCP. Extract these registers out to reduce duplicated fields in mtk_scp when probing multi-core SCP. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 13 +- drivers/remoteproc/mtk_scp.c | 201 +++++++++++++++++-------------- drivers/remoteproc/mtk_scp_ipi.c | 4 +- 3 files changed, 122 insertions(+), 96 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index c0905aec3b4b..b04d71277c1f 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -100,17 +100,20 @@ struct mtk_scp_of_data { size_t ipi_buf_offset; }; +struct mtk_scp_of_cluster { + void __iomem *reg_base; + void __iomem *l1tcm_base; + size_t l1tcm_size; + phys_addr_t l1tcm_phys; +}; + struct mtk_scp { struct device *dev; struct rproc *rproc; struct clk *clk; - void __iomem *reg_base; void __iomem *sram_base; size_t sram_size; phys_addr_t sram_phys; - void __iomem *l1tcm_base; - size_t l1tcm_size; - phys_addr_t l1tcm_phys; const struct mtk_scp_of_data *data; @@ -128,6 +131,8 @@ struct mtk_scp { size_t dram_size; struct rproc_subdev *rpmsg_subdev; + + struct mtk_scp_of_cluster *cluster; }; /** diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 48e759c2d486..9486f5020946 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -152,45 +152,45 @@ static void mt8183_scp_reset_assert(struct mtk_scp *scp) { u32 val; - val = readl(scp->reg_base + MT8183_SW_RSTN); + val = readl(scp->cluster->reg_base + MT8183_SW_RSTN); val &= ~MT8183_SW_RSTN_BIT; - writel(val, scp->reg_base + MT8183_SW_RSTN); + writel(val, scp->cluster->reg_base + MT8183_SW_RSTN); } static void mt8183_scp_reset_deassert(struct mtk_scp *scp) { u32 val; - val = readl(scp->reg_base + MT8183_SW_RSTN); + val = readl(scp->cluster->reg_base + MT8183_SW_RSTN); val |= MT8183_SW_RSTN_BIT; - writel(val, scp->reg_base + MT8183_SW_RSTN); + writel(val, scp->cluster->reg_base + MT8183_SW_RSTN); } static void mt8192_scp_reset_assert(struct mtk_scp *scp) { - writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET); + writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); } static void mt8192_scp_reset_deassert(struct mtk_scp *scp) { - writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); + writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_CLR); } static void mt8195_scp_c1_reset_assert(struct mtk_scp *scp) { - writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_SET); + writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_SET); } static void mt8195_scp_c1_reset_deassert(struct mtk_scp *scp) { - writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_CLR); + writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_CLR); } static void mt8183_scp_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; - scp_to_host = readl(scp->reg_base + MT8183_SCP_TO_HOST); + scp_to_host = readl(scp->cluster->reg_base + MT8183_SCP_TO_HOST); if (scp_to_host & MT8183_SCP_IPC_INT_BIT) scp_ipi_handler(scp); else @@ -198,14 +198,14 @@ static void mt8183_scp_irq_handler(struct mtk_scp *scp) /* SCP won't send another interrupt until we set SCP_TO_HOST to 0. */ writel(MT8183_SCP_IPC_INT_BIT | MT8183_SCP_WDT_INT_BIT, - scp->reg_base + MT8183_SCP_TO_HOST); + scp->cluster->reg_base + MT8183_SCP_TO_HOST); } static void mt8192_scp_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; - scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); + scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET); if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { scp_ipi_handler(scp); @@ -215,10 +215,10 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) * MT8192_SCP2APMCU_IPC. */ writel(MT8192_SCP_IPC_INT_BIT, - scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); + scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR); } else { scp_wdt_handler(scp, scp_to_host); - writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); + writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ); } } @@ -226,12 +226,12 @@ static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; - scp_to_host = readl(scp->reg_base + MT8195_SSHUB2APMCU_IPC_SET); + scp_to_host = readl(scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_SET); if (scp_to_host & MT8192_SCP_IPC_INT_BIT) scp_ipi_handler(scp); - writel(scp_to_host, scp->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); + writel(scp_to_host, scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); } static irqreturn_t scp_irq_handler(int irq, void *priv) @@ -363,26 +363,26 @@ static int mt8195_scp_clk_get(struct mtk_scp *scp) static int mt8183_scp_before_load(struct mtk_scp *scp) { /* Clear SCP to host interrupt */ - writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST); + writel(MT8183_SCP_IPC_INT_BIT, scp->cluster->reg_base + MT8183_SCP_TO_HOST); /* Reset clocks before loading FW */ - writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL); - writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_SW_SEL); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_DIV_SEL); /* Initialize TCM before loading FW. */ - writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD); - writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_L1_SRAM_PD); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD); /* Turn on the power of SCP's SRAM before using it. */ - writel(0x0, scp->reg_base + MT8183_SCP_SRAM_PDN); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_SRAM_PDN); /* * Set I-cache and D-cache size before loading SCP FW. * SCP SRAM logical address may change when cache size setting differs. */ writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB, - scp->reg_base + MT8183_SCP_CACHE_CON); - writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON); + scp->cluster->reg_base + MT8183_SCP_CACHE_CON); + writel(MT8183_SCP_CACHESIZE_8KB, scp->cluster->reg_base + MT8183_SCP_DCACHE_CON); return 0; } @@ -408,28 +408,28 @@ static void scp_sram_power_off(void __iomem *addr, u32 reserved_mask) static int mt8186_scp_before_load(struct mtk_scp *scp) { /* Clear SCP to host interrupt */ - writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST); + writel(MT8183_SCP_IPC_INT_BIT, scp->cluster->reg_base + MT8183_SCP_TO_HOST); /* Reset clocks before loading FW */ - writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL); - writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_SW_SEL); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_DIV_SEL); /* Turn on the power of SCP's SRAM before using it. Enable 1 block per time*/ - scp_sram_power_on(scp->reg_base + MT8183_SCP_SRAM_PDN, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8183_SCP_SRAM_PDN, 0); /* Initialize TCM before loading FW. */ - writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD); - writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD); - writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1); - writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_L1_SRAM_PD); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD); + writel(0x0, scp->cluster->reg_base + MT8186_SCP_L1_SRAM_PD_P1); + writel(0x0, scp->cluster->reg_base + MT8186_SCP_L1_SRAM_PD_p2); /* * Set I-cache and D-cache size before loading SCP FW. * SCP SRAM logical address may change when cache size setting differs. */ writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB, - scp->reg_base + MT8183_SCP_CACHE_CON); - writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON); + scp->cluster->reg_base + MT8183_SCP_CACHE_CON); + writel(MT8183_SCP_CACHESIZE_8KB, scp->cluster->reg_base + MT8183_SCP_DCACHE_CON); return 0; } @@ -437,19 +437,19 @@ static int mt8186_scp_before_load(struct mtk_scp *scp) static int mt8192_scp_before_load(struct mtk_scp *scp) { /* clear SPM interrupt, SCP2SPM_IPC_CLR */ - writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR); + writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); - writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET); + writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); /* enable SRAM clock */ - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0); - scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); /* enable MPU for all memory regions */ - writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); + writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); return 0; } @@ -457,20 +457,20 @@ static int mt8192_scp_before_load(struct mtk_scp *scp) static int mt8195_scp_before_load(struct mtk_scp *scp) { /* clear SPM interrupt, SCP2SPM_IPC_CLR */ - writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR); + writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); - writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET); + writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); /* enable SRAM clock */ - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN, + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); - scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); /* enable MPU for all memory regions */ - writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); + writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); return 0; } @@ -479,10 +479,10 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *scp) { scp->data->scp_reset_assert(scp); - scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); /* enable MPU for all memory regions */ - writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); return 0; } @@ -601,11 +601,11 @@ static void *mt8192_scp_da_to_va(struct mtk_scp *scp, u64 da, size_t len) } /* optional memory region */ - if (scp->l1tcm_size && - da >= scp->l1tcm_phys && - (da + len) <= scp->l1tcm_phys + scp->l1tcm_size) { - offset = da - scp->l1tcm_phys; - return (void __force *)scp->l1tcm_base + offset; + if (scp->cluster->l1tcm_size && + da >= scp->cluster->l1tcm_phys && + (da + len) <= scp->cluster->l1tcm_phys + scp->cluster->l1tcm_size) { + offset = da - scp->cluster->l1tcm_phys; + return (void __force *)scp->cluster->l1tcm_base + offset; } /* optional memory region */ @@ -629,43 +629,43 @@ static void *scp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iome static void mt8183_scp_stop(struct mtk_scp *scp) { /* Disable SCP watchdog */ - writel(0, scp->reg_base + MT8183_WDT_CFG); + writel(0, scp->cluster->reg_base + MT8183_WDT_CFG); } static void mt8192_scp_stop(struct mtk_scp *scp) { /* Disable SRAM clock */ - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0); - scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); /* Disable SCP watchdog */ - writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); + writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG); } static void mt8195_scp_stop(struct mtk_scp *scp) { /* Disable SRAM clock */ - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN, + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); - scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); /* Disable SCP watchdog */ - writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); + writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG); } static void mt8195_scp_c1_stop(struct mtk_scp *scp) { /* Power off CPU SRAM */ - scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); /* Disable SCP watchdog */ - writel(0, scp->reg_base + MT8195_CORE1_WDT_CFG); + writel(0, scp->cluster->reg_base + MT8195_CORE1_WDT_CFG); } static int scp_stop(struct rproc *rproc) @@ -854,7 +854,8 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *scp) } } -static int scp_probe(struct platform_device *pdev) +static int scp_cluster_init(struct platform_device *pdev, + struct mtk_scp_of_cluster *scp_cluster) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; @@ -876,6 +877,7 @@ static int scp_probe(struct platform_device *pdev) scp->rproc = rproc; scp->dev = dev; scp->data = of_device_get_match_data(dev); + scp->cluster = scp_cluster; platform_set_drvdata(pdev, scp); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); @@ -887,24 +889,6 @@ static int scp_probe(struct platform_device *pdev) scp->sram_size = resource_size(res); scp->sram_phys = res->start; - /* l1tcm is an optional memory region */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm"); - scp->l1tcm_base = devm_ioremap_resource(dev, res); - if (IS_ERR(scp->l1tcm_base)) { - ret = PTR_ERR(scp->l1tcm_base); - if (ret != -EINVAL) { - return dev_err_probe(dev, ret, "Failed to map l1tcm memory\n"); - } - } else { - scp->l1tcm_size = resource_size(res); - scp->l1tcm_phys = res->start; - } - - scp->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg"); - if (IS_ERR(scp->reg_base)) - return dev_err_probe(dev, PTR_ERR(scp->reg_base), - "Failed to parse and map cfg memory\n"); - ret = scp->data->scp_clk_get(scp); if (ret) return ret; @@ -956,6 +940,43 @@ static int scp_probe(struct platform_device *pdev) return ret; } +static int scp_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_scp_of_cluster *scp_cluster; + struct resource *res; + int ret; + + scp_cluster = devm_kzalloc(dev, sizeof(*scp_cluster), GFP_KERNEL); + if (!scp_cluster) + return -ENOMEM; + + scp_cluster->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg"); + if (IS_ERR(scp_cluster->reg_base)) + return dev_err_probe(dev, PTR_ERR(scp_cluster->reg_base), + "Failed to parse and map cfg memory\n"); + + /* l1tcm is an optional memory region */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm"); + scp_cluster->l1tcm_base = devm_ioremap_resource(dev, res); + if (IS_ERR(scp_cluster->l1tcm_base)) { + ret = PTR_ERR(scp_cluster->l1tcm_base); + if (ret != -EINVAL) + return dev_err_probe(dev, ret, "Failed to map l1tcm memory\n"); + + scp_cluster->l1tcm_base = NULL; + } else { + scp_cluster->l1tcm_size = resource_size(res); + scp_cluster->l1tcm_phys = res->start; + } + + ret = scp_cluster_init(pdev, scp_cluster); + if (ret) + return ret; + + return 0; +} + static void scp_remove(struct platform_device *pdev) { struct mtk_scp *scp = platform_get_drvdata(pdev); diff --git a/drivers/remoteproc/mtk_scp_ipi.c b/drivers/remoteproc/mtk_scp_ipi.c index 9c7c17b9d181..cd0b60106ec2 100644 --- a/drivers/remoteproc/mtk_scp_ipi.c +++ b/drivers/remoteproc/mtk_scp_ipi.c @@ -177,7 +177,7 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len, mutex_lock(&scp->send_lock); /* Wait until SCP receives the last command */ - ret = readl_poll_timeout_atomic(scp->reg_base + scp->data->host_to_scp_reg, + ret = readl_poll_timeout_atomic(scp->cluster->reg_base + scp->data->host_to_scp_reg, val, !val, 0, SCP_TIMEOUT_US); if (ret) { dev_err(scp->dev, "%s: IPI timeout!\n", __func__); @@ -192,7 +192,7 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len, scp->ipi_id_ack[id] = false; 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The initialization procedure for remoteproc is similar for both single-core and multi-core architectures and is reusing to avoid redundant code. Rewrite the probing flow of single-core SCP to adapt with the 'cluster' concept needed by the multi-core SCP. The SCP core object(s) is maintained at the cluster list. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 2 + drivers/remoteproc/mtk_scp.c | 84 +++++++++++++++++++++++---------- 2 files changed, 62 insertions(+), 24 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index b04d71277c1f..1438159ae736 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -105,6 +105,7 @@ struct mtk_scp_of_cluster { void __iomem *l1tcm_base; size_t l1tcm_size; phys_addr_t l1tcm_phys; + struct list_head mtk_scp_list; }; struct mtk_scp { @@ -132,6 +133,7 @@ struct mtk_scp { struct rproc_subdev *rpmsg_subdev; + struct list_head elem; struct mtk_scp_of_cluster *cluster; }; diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 9486f5020946..d67dcabdab9e 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -854,8 +854,8 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *scp) } } -static int scp_cluster_init(struct platform_device *pdev, - struct mtk_scp_of_cluster *scp_cluster) +static struct mtk_scp *scp_rproc_init(struct platform_device *pdev, + struct mtk_scp_of_cluster *scp_cluster) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; @@ -867,11 +867,13 @@ static int scp_cluster_init(struct platform_device *pdev, ret = rproc_of_parse_firmware(dev, 0, &fw_name); if (ret < 0 && ret != -EINVAL) - return ret; + return ERR_PTR(ret); rproc = devm_rproc_alloc(dev, np->name, &scp_ops, fw_name, sizeof(*scp)); - if (!rproc) - return dev_err_probe(dev, -ENOMEM, "unable to allocate remoteproc\n"); + if (!rproc) { + dev_err(dev, "unable to allocate remoteproc\n"); + return ERR_PTR(-ENOMEM); + } scp = rproc->priv; scp->rproc = rproc; @@ -882,20 +884,21 @@ static int scp_cluster_init(struct platform_device *pdev, res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); scp->sram_base = devm_ioremap_resource(dev, res); - if (IS_ERR(scp->sram_base)) - return dev_err_probe(dev, PTR_ERR(scp->sram_base), - "Failed to parse and map sram memory\n"); + if (IS_ERR(scp->sram_base)) { + dev_err(dev, "Failed to parse and map sram memory\n"); + return ERR_CAST(scp->sram_base); + } scp->sram_size = resource_size(res); scp->sram_phys = res->start; ret = scp->data->scp_clk_get(scp); if (ret) - return ret; + return ERR_PTR(ret); ret = scp_map_memory_region(scp); if (ret) - return ret; + return ERR_PTR(ret); mutex_init(&scp->send_lock); for (i = 0; i < SCP_IPI_MAX; i++) @@ -922,11 +925,7 @@ static int scp_cluster_init(struct platform_device *pdev, goto remove_subdev; } - ret = rproc_add(rproc); - if (ret) - goto remove_subdev; - - return 0; + return scp; remove_subdev: scp_remove_rpmsg_subdev(scp); @@ -937,7 +936,43 @@ static int scp_cluster_init(struct platform_device *pdev, mutex_destroy(&scp->ipi_desc[i].lock); mutex_destroy(&scp->send_lock); - return ret; + return ERR_PTR(ret); +} + +static void scp_free(struct mtk_scp *scp) +{ + int i; + + scp_remove_rpmsg_subdev(scp); + scp_ipi_unregister(scp, SCP_IPI_INIT); + scp_unmap_memory_region(scp); + for (i = 0; i < SCP_IPI_MAX; i++) + mutex_destroy(&scp->ipi_desc[i].lock); + mutex_destroy(&scp->send_lock); +} + +static int scp_cluster_init(struct platform_device *pdev, + struct mtk_scp_of_cluster *scp_cluster) +{ + struct device *dev = &pdev->dev; + struct list_head *scp_list = &scp_cluster->mtk_scp_list; + struct mtk_scp *scp; + int ret; + + scp = scp_rproc_init(pdev, scp_cluster); + if (IS_ERR(scp)) + return PTR_ERR(scp); + + ret = rproc_add(scp->rproc); + if (ret) { + dev_err(dev, "Failed to add rproc\n"); + scp_free(scp); + return ret; + } + + list_add_tail(&scp->elem, scp_list); + + return 0; } static int scp_probe(struct platform_device *pdev) @@ -970,6 +1005,8 @@ static int scp_probe(struct platform_device *pdev) scp_cluster->l1tcm_phys = res->start; } + INIT_LIST_HEAD(&scp_cluster->mtk_scp_list); + ret = scp_cluster_init(pdev, scp_cluster); if (ret) return ret; @@ -980,15 +1017,14 @@ static int scp_probe(struct platform_device *pdev) static void scp_remove(struct platform_device *pdev) { struct mtk_scp *scp = platform_get_drvdata(pdev); - int i; + struct mtk_scp_of_cluster *scp_cluster = scp->cluster; + struct mtk_scp *temp; - rproc_del(scp->rproc); - scp_remove_rpmsg_subdev(scp); - scp_ipi_unregister(scp, SCP_IPI_INIT); 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The SCP driver populates the platform device and checks the child nodes to identify whether it's a single-core SCP or a multi-core SCP. Add the remoteproc instances of multi-core SCP to the SCP cluster list. When the SCP driver is removed, it cleanup resources by walking through the cluster list. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_scp.c | 118 +++++++++++++++++++++++++++++++++-- 1 file changed, 113 insertions(+), 5 deletions(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index d67dcabdab9e..34095a461e15 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -855,7 +855,8 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *scp) } static struct mtk_scp *scp_rproc_init(struct platform_device *pdev, - struct mtk_scp_of_cluster *scp_cluster) + struct mtk_scp_of_cluster *scp_cluster, + const struct mtk_scp_of_data *of_data) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; @@ -878,7 +879,7 @@ static struct mtk_scp *scp_rproc_init(struct platform_device *pdev, scp = rproc->priv; scp->rproc = rproc; scp->dev = dev; - scp->data = of_device_get_match_data(dev); + scp->data = of_data; scp->cluster = scp_cluster; platform_set_drvdata(pdev, scp); @@ -951,15 +952,15 @@ static void scp_free(struct mtk_scp *scp) mutex_destroy(&scp->send_lock); } -static int scp_cluster_init(struct platform_device *pdev, - struct mtk_scp_of_cluster *scp_cluster) +static int scp_add_single_core(struct platform_device *pdev, + struct mtk_scp_of_cluster *scp_cluster) { struct device *dev = &pdev->dev; struct list_head *scp_list = &scp_cluster->mtk_scp_list; struct mtk_scp *scp; int ret; - scp = scp_rproc_init(pdev, scp_cluster); + scp = scp_rproc_init(pdev, scp_cluster, of_device_get_match_data(dev)); if (IS_ERR(scp)) return PTR_ERR(scp); @@ -975,6 +976,102 @@ static int scp_cluster_init(struct platform_device *pdev, return 0; } +static int scp_add_multi_core(struct platform_device *pdev, + struct mtk_scp_of_cluster *scp_cluster) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev_of_node(dev); + struct platform_device *cpdev; + struct device_node *child; + struct list_head *scp_list = &scp_cluster->mtk_scp_list; + const struct mtk_scp_of_data **cluster_of_data; + struct mtk_scp *scp, *temp; + int core_id = 0; + int ret; + + cluster_of_data = (const struct mtk_scp_of_data **)of_device_get_match_data(dev); + + for_each_available_child_of_node(np, child) { + if (!cluster_of_data[core_id]) { + ret = -EINVAL; + dev_err(dev, "Not support core %d\n", core_id); + of_node_put(child); + goto init_fail; + } + + cpdev = of_find_device_by_node(child); + if (!cpdev) { + ret = -ENODEV; + dev_err(dev, "Not found platform device for core %d\n", core_id); + of_node_put(child); + goto init_fail; + } + + scp = scp_rproc_init(cpdev, scp_cluster, cluster_of_data[core_id]); + put_device(&cpdev->dev); + if (IS_ERR(scp)) { + ret = PTR_ERR(scp); + dev_err(dev, "Failed to initialize core %d rproc\n", core_id); + of_node_put(child); + goto init_fail; + } + + ret = rproc_add(scp->rproc); + if (ret) { + dev_err(dev, "Failed to add rproc of core %d\n", core_id); + of_node_put(child); + scp_free(scp); + goto init_fail; + } + + list_add_tail(&scp->elem, scp_list); + core_id++; + } + + platform_set_drvdata(pdev, list_first_entry(scp_list, struct mtk_scp, elem)); + + return 0; + +init_fail: + list_for_each_entry_safe_reverse(scp, temp, scp_list, elem) { + list_del(&scp->elem); + rproc_del(scp->rproc); + scp_free(scp); + } + + return ret; +} + +static int scp_is_single_core(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev_of_node(dev); + struct device_node *child; + + child = of_get_next_available_child(np, NULL); + if (!child) + return dev_err_probe(dev, -ENODEV, "No child node\n"); + + of_node_put(child); + return of_node_name_eq(child, "cros-ec-rpmsg"); +} + +static int scp_cluster_init(struct platform_device *pdev, struct mtk_scp_of_cluster *scp_cluster) +{ + int ret; + + ret = scp_is_single_core(pdev); + if (ret < 0) + return ret; + + if (ret) + ret = scp_add_single_core(pdev, scp_cluster); + else + ret = scp_add_multi_core(pdev, scp_cluster); + + return ret; +} + static int scp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1007,6 +1104,10 @@ static int scp_probe(struct platform_device *pdev) INIT_LIST_HEAD(&scp_cluster->mtk_scp_list); + ret = devm_of_platform_populate(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to populate platform devices\n"); + ret = scp_cluster_init(pdev, scp_cluster); if (ret) return ret; @@ -1101,12 +1202,19 @@ static const struct mtk_scp_of_data mt8195_of_data_c1 = { .host_to_scp_int_bit = MT8195_CORE1_HOST_IPC_INT_BIT, }; +static const struct mtk_scp_of_data *mt8195_of_data_cores[] = { + &mt8195_of_data, + &mt8195_of_data_c1, + NULL +}; + static const struct of_device_id mtk_scp_of_match[] = { { .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data }, { .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data }, { .compatible = "mediatek,mt8188-scp", .data = &mt8188_of_data }, { .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data }, { .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data }, + { .compatible = "mediatek,mt8195-scp-dual", .data = &mt8195_of_data_cores }, {}, }; MODULE_DEVICE_TABLE(of, mtk_scp_of_match); From patchwork Fri Jul 21 02:41:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 123522 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3513882vqt; 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To address this constraint, extracted the power control flow of L2TCM and made it shared between both cores, enabling support of arbitrary boot order. The flow for controlling L2TCM power has been incorporated into the mt8195_scp_before_load() and mt8195_scp_stop() APIs, which are respectively invoked during the rproc->ops->start() and rproc->ops->stop() operations. These APIs effectively serve the same purpose as the rproc prepare()/unprepare() APIs." Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 3 ++ drivers/remoteproc/mtk_scp.c | 71 ++++++++++++++++++++++++++------- 2 files changed, 59 insertions(+), 15 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 1438159ae736..fea05bbba9aa 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -106,6 +106,9 @@ struct mtk_scp_of_cluster { size_t l1tcm_size; phys_addr_t l1tcm_phys; struct list_head mtk_scp_list; + /* Prevent concurrent operations of this structure and L2TCM power control. */ + struct mutex cluster_lock; + u32 l2tcm_refcnt; }; struct mtk_scp { diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 34095a461e15..c624f9c3db17 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -454,19 +454,37 @@ static int mt8192_scp_before_load(struct mtk_scp *scp) return 0; } -static int mt8195_scp_before_load(struct mtk_scp *scp) +static int mt8195_scp_l2tcm_on(struct mtk_scp *scp) { - /* clear SPM interrupt, SCP2SPM_IPC_CLR */ - writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); + struct mtk_scp_of_cluster *scp_cluster = scp->cluster; + + mutex_lock(&scp_cluster->cluster_lock); + + if (scp_cluster->l2tcm_refcnt == 0) { + /* clear SPM interrupt, SCP2SPM_IPC_CLR */ + writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); + + /* Power on L2TCM */ + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, + MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + } + + scp_cluster->l2tcm_refcnt += 1; + mutex_unlock(&scp_cluster->cluster_lock); + + return 0; +} + +static int mt8195_scp_before_load(struct mtk_scp *scp) +{ writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); - /* enable SRAM clock */ - scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, - MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + mt8195_scp_l2tcm_on(scp); + scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); /* enable MPU for all memory regions */ @@ -479,6 +497,8 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *scp) { scp->data->scp_reset_assert(scp); + mt8195_scp_l2tcm_on(scp); + scp_sram_power_on(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); /* enable MPU for all memory regions */ @@ -645,14 +665,31 @@ static void mt8192_scp_stop(struct mtk_scp *scp) writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG); } +static void mt8195_scp_l2tcm_off(struct mtk_scp *scp) +{ + struct mtk_scp_of_cluster *scp_cluster = scp->cluster; + + mutex_lock(&scp_cluster->cluster_lock); + + if (scp_cluster->l2tcm_refcnt > 0) + scp_cluster->l2tcm_refcnt -= 1; + + if (scp_cluster->l2tcm_refcnt == 0) { + /* Power off L2TCM */ + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, + MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + } + + mutex_unlock(&scp_cluster->cluster_lock); +} + static void mt8195_scp_stop(struct mtk_scp *scp) { - /* Disable SRAM clock */ - scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, - MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + mt8195_scp_l2tcm_off(scp); + scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); /* Disable SCP watchdog */ @@ -661,6 +698,8 @@ static void mt8195_scp_stop(struct mtk_scp *scp) static void mt8195_scp_c1_stop(struct mtk_scp *scp) { + mt8195_scp_l2tcm_off(scp); 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d9-20020a50fb09000000b005218239ce17si1730477edq.216.2023.07.20.19.43.59; Thu, 20 Jul 2023 19:44:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=W1dzhOKU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229941AbjGUCmT (ORCPT + 99 others); Thu, 20 Jul 2023 22:42:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229635AbjGUCmF (ORCPT ); Thu, 20 Jul 2023 22:42:05 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBA83271C; Thu, 20 Jul 2023 19:41:59 -0700 (PDT) X-UUID: 263be0ea277011eeb20a276fd37b9834-20230721 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=yJpPZnIfqbjbl1UOtIUv6D8T7S7CPLpi9wfN1Bi61F0=; b=W1dzhOKUFjlPim+NU/ikO2o3lP67C0Nj/3g1zFcPdtmPmT6rdMkC45i6VEDqkxxmT+nywKd9IH1e5pQgwNwxT5+oh6o1EAXMynUwweq3Oul/P26Ne0IDNALv9gOtTBbDwXwNPuHHWsLY9XE+IKtVJBCRDKqwZCQO16cM6d8lx5o=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:4f339582-5989-4e1b-a8e1-dfa7bda46caa,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:176cd25,CLOUDID:c311de87-44fb-401c-8de7-6a5572f1f5d5,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 263be0ea277011eeb20a276fd37b9834-20230721 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1603218869; Fri, 21 Jul 2023 10:41:52 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 21 Jul 2023 10:41:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 21 Jul 2023 10:41:51 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v15 09/13] remoteproc: mediatek: Setup MT8195 SCP core 1 SRAM offset Date: Fri, 21 Jul 2023 10:41:28 +0800 Message-ID: <20230721024132.6548-10-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230721024132.6548-1-tinghan.shen@mediatek.com> References: <20230721024132.6548-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771996408077872117 X-GMAIL-MSGID: 1771996408077872117 Because MT8195 SCP core 0 and core 1 both boot from head of SRAM and have the same viewpoint of SRAM, SCP has a "core 1 SRAM offset" configuration to control the access destination of SCP core 1 to boot core 1 from different SRAM location. The "core 1 SRAM offset" configuration is composed by a range and an offset. It works like a simple memory mapped mechanism. When SCP core 1 accesses a SRAM address located in the range, the SCP bus adds the configured offset to the address to shift the physical destination address on SCP SRAM. This shifting is transparent to the software running on SCP core 1. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 7 +++++++ drivers/remoteproc/mtk_scp.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index fea05bbba9aa..3d6b53b9f374 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -65,6 +65,13 @@ #define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 #define MT8195_CORE1_WDT_CFG 0x20034 +#define MT8195_SEC_CTRL 0x85000 +#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) +#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) +#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 +#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 +#define MT8195_L2TCM_OFFSET 0x850d0 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index c624f9c3db17..d1d0d7fb574c 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -495,6 +495,10 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) static int mt8195_scp_c1_before_load(struct mtk_scp *scp) { + u32 sec_ctrl; + struct mtk_scp *scp_c0; + struct mtk_scp_of_cluster *scp_cluster = scp->cluster; + scp->data->scp_reset_assert(scp); mt8195_scp_l2tcm_on(scp); @@ -504,6 +508,30 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *scp) /* enable MPU for all memory regions */ writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + /* + * The L2TCM_OFFSET_RANGE and L2TCM_OFFSET shift the destination address + * on SRAM when SCP core 1 accesses SRAM. + * + * This configuration solves booting the SCP core 0 and core 1 from + * different SRAM address because core 0 and core 1 both boot from + * the head of SRAM by default. this must be configured before boot SCP core 1. + * + * The value of L2TCM_OFFSET_RANGE is from the viewpoint of SCP core 1. + * When SCP core 1 issues address within the range (L2TCM_OFFSET_RANGE), + * the address will be added with a fixed offset (L2TCM_OFFSET) on the bus. + * The shift action is tranparent to software. + */ + writel(0, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW); + writel(scp->sram_size, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH); + + scp_c0 = list_first_entry(&scp_cluster->mtk_scp_list, struct mtk_scp, elem); + writel(scp->sram_phys - scp_c0->sram_phys, scp->cluster->reg_base + MT8195_L2TCM_OFFSET); + + /* enable SRAM offset when fetching instruction and data */ + sec_ctrl = readl(scp->cluster->reg_base + MT8195_SEC_CTRL); + sec_ctrl |= MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D; + writel(sec_ctrl, scp->cluster->reg_base + MT8195_SEC_CTRL); + return 0; } From patchwork Fri Jul 21 02:41:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 123520 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3513589vqt; Thu, 20 Jul 2023 19:44:00 -0700 (PDT) X-Google-Smtp-Source: APBJJlE2nbyESMQm0nUAQ4/QGr5aJN027q8wUY+UtT3zpzWmLiKlF3h8j+UDUptlQrsVlZL0Kzz3 X-Received: by 2002:a2e:960b:0:b0:2b7:65:fca2 with SMTP id v11-20020a2e960b000000b002b70065fca2mr475367ljh.49.1689907439890; Thu, 20 Jul 2023 19:43:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689907439; cv=none; d=google.com; s=arc-20160816; b=W2b/mE94fzZSIFRtwL2QAspHDWV1WnyfOUlNLLac28xGO0lxrBRDlgL0+86Gpjj2uz UDvcmNhvRYVpoVNU98tSNNYe8tJn2BLmK1Mzn9K/TetY0aYnFMlNlVgX9D9iQFrptT4x VkelwMt/VUthcZADDJ0LC9BXOgOnCuUzNb1OqnjYHH1e87vwQfQuNNH74PFJhO2SiEkT euCVxeHs18DWe8UdNcEer2gAwql+FGS0LNa6B0ywfN08/6ulrkHeZ1f3NCsGXxkYyrgD +TNQ6CzKsVkSNgl0tUTtL2266fmgPL9uvJRH6ykWfLlBdF/+FJ4kfGpp84gk91m1w/bM /a8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=1roPG2mTGR+MAEAjiL8RQveUZJI6YanudT+wZMHG6FU=; fh=h2/vjUCGtNC+BMuYkewKR/IrgUI087y/plyyI4iel/0=; b=CzRc3qjwQNeGQsuWfbP/srdylMHpLqL17Kw4kqjcNWhwgWifyqVMd/hbOpmPsy/iDN aI0IjPxc5U5DuTuIns/y+gjoZ7DRh06xElKraBrUT1eXa4JcNECqI3VU7I9X04kpNfNM tgdChsxfl/b277LgNJFQOz0ejbShOntwja1K0t1wkiNd/242hwGSf2G1tNGFFSgrbDJF ADh1IDkndhs4EdhDm1LBzQTKGWgr4VErIf6BiY/9evlXM616FRsVAsk2+FR5w730Mg0i RKPyIg3sKbqk69xiHUmRkMSGLTd61oh7FJQmkoIWd/zzmmJiESxs/CBTAn7u2RFEDbLQ OrLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=KZrcN7I4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r10-20020a170906364a00b0098dd0341f27si1517962ejb.225.2023.07.20.19.43.36; Thu, 20 Jul 2023 19:43:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=KZrcN7I4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229826AbjGUCmL (ORCPT + 99 others); Thu, 20 Jul 2023 22:42:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229604AbjGUCmF (ORCPT ); Thu, 20 Jul 2023 22:42:05 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D19082691; Thu, 20 Jul 2023 19:41:58 -0700 (PDT) X-UUID: 263c55fc277011eeb20a276fd37b9834-20230721 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=1roPG2mTGR+MAEAjiL8RQveUZJI6YanudT+wZMHG6FU=; b=KZrcN7I4wz0NCMIwiu7OrubchNOWTVAnejuLqebmSJmGTZkgZLGqIV6cH6ZB7WPgzKNCOMYnPdjtUCawvpkV6jDNmBn+0fdkvE9W36RJM6ipGUQSJjruUEPJ1PeWMuiqCpAF3l7pX1H4PPOd78sIKVKNv2K32tDYIyDfPuN7/WY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:4959aecc-245a-4fc4-91e5-9cd04d399a35,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:176cd25,CLOUDID:c211de87-44fb-401c-8de7-6a5572f1f5d5,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 263c55fc277011eeb20a276fd37b9834-20230721 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2048987741; Fri, 21 Jul 2023 10:41:52 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 21 Jul 2023 10:41:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 21 Jul 2023 10:41:51 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Tinghan Shen" CC: , , , , , Subject: [PATCH v15 10/13] remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout Date: Fri, 21 Jul 2023 10:41:29 +0800 Message-ID: <20230721024132.6548-11-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230721024132.6548-1-tinghan.shen@mediatek.com> References: <20230721024132.6548-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771996383640693905 X-GMAIL-MSGID: 1771996383640693905 The MT8195 SCP core 1 watchdog timeout needs to be handled in the SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout IRQ is wired on the same IRQ entry for core 0 watchdog timeout. MT8195 SCP has a watchdog status register to identify the watchdog timeout source when IRQ triggered. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 5 +++++ drivers/remoteproc/mtk_scp.c | 25 ++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 3d6b53b9f374..6d7736a031f7 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -55,6 +55,10 @@ #define MT8192_CORE0_WDT_IRQ 0x10030 #define MT8192_CORE0_WDT_CFG 0x10034 +#define MT8195_SYS_STATUS 0x4004 +#define MT8195_CORE0_WDT BIT(16) +#define MT8195_CORE1_WDT BIT(17) + #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) #define MT8195_CPU1_SRAM_PD 0x1084 @@ -63,6 +67,7 @@ #define MT8195_CORE1_SW_RSTN_CLR 0x20000 #define MT8195_CORE1_SW_RSTN_SET 0x20004 #define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_IRQ 0x20030 #define MT8195_CORE1_WDT_CFG 0x20034 #define MT8195_SEC_CTRL 0x85000 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index d1d0d7fb574c..fcd1dd9b3580 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -222,6 +222,29 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + } else { + u32 reason = readl(scp->cluster->reg_base + MT8195_SYS_STATUS); + + if (reason & MT8195_CORE0_WDT) + writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ); + + if (reason & MT8195_CORE1_WDT) + writel(1, scp->cluster->reg_base + MT8195_CORE1_WDT_IRQ); + + scp_wdt_handler(scp, reason); + } + + writel(scp_to_host, scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR); +} + static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -1250,7 +1273,7 @@ static const struct mtk_scp_of_data mt8192_of_data = { static const struct mtk_scp_of_data mt8195_of_data = { .scp_clk_get = mt8195_scp_clk_get, .scp_before_load = mt8195_scp_before_load, - .scp_irq_handler = mt8192_scp_irq_handler, + .scp_irq_handler = mt8195_scp_irq_handler, .scp_reset_assert = mt8192_scp_reset_assert, .scp_reset_deassert = mt8192_scp_reset_deassert, .scp_stop = mt8195_scp_stop, From patchwork Fri Jul 21 02:41:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 123524 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3518355vqt; Thu, 20 Jul 2023 19:58:36 -0700 (PDT) X-Google-Smtp-Source: APBJJlGRxAO5ae8nU0zkloIA6711ilJnqpqcEStLu7vcqPYbgFPaQnRu30BY/9NMO1AJJW+plCYk X-Received: by 2002:a05:6a20:948f:b0:134:a4e2:4ac8 with SMTP id hs15-20020a056a20948f00b00134a4e24ac8mr473029pzb.39.1689908316633; Thu, 20 Jul 2023 19:58:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689908316; cv=none; d=google.com; s=arc-20160816; b=Z8WaVZynTnR0r3EkL0C9g9bEDac/9vs9PNiLA6LvGQt1pyY+GURPIuIGlCpY9gXIS4 HZZ+APoIc0GYhcUH0g4smB4GMFyHk7Jnw3Ku3RG11yJS2X56BnduEfdVHK35Julx2A2P JQRVPV6hqQjuEbWHL97hZuqsPhYphWX2DcxaxPCbxx/nfFzTf0GkftVlT47jqLjfY5Af EovCoWHuz1xH2viHOofS9y/TajNe7c7HShhkDeSDRBCngPHP1ujqG4bXZ94Gne4iB5ew dX4aCWQHD0WmUQqFSnVUQfBaPCwyp8WhA7NLFaABq1gos6LUeowMzN4BROT+K16lgD5a OEyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=i634ZhMfSzfCWgqPzYo892EfK/lf78npMnhCjtYSpK4=; fh=fiUFlTmdXAnPLHH0bIyIc4brKi/t2/OmtpRJQ8s00Ug=; b=cTBfjLC7CSwYDdWQRp2bcjhsA6UIPEKEzWDfun7B9qGdVPn0OwVsptvdVJHsHDrARt mV6Da6sfmCXTdWdkip+M+ttrhgXJkw/647fqNv0cNR3an4YKxbzMgB6Kf7xy3qbvcJPp 2Vaq4Cp8tdBZGVnUNpyKa9zFYInrPKx1G8q7ncYOK5bID/bZWkKdW4PIRIopVcs9OC9G eyrR7uVd/De2QNrLOEPbw7Xu53BIcUVtEp6XkL3pz98EBohl3FbM+KImjBxjTGXV9B6i 0yus5y80n9izEkav9MTzoI/ZSKog2ImV/WsxRX1DGAUHBZJeDPmZUO/Imm4aqv/hKm7a TVPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=G8CsWhZn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Triggering the rproc recovery flow on all instances will ensure proper recovery of the SCP sub-system. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_scp.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index fcd1dd9b3580..9ed2e18e36ba 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -68,8 +68,14 @@ EXPORT_SYMBOL_GPL(scp_put); static void scp_wdt_handler(struct mtk_scp *scp, u32 scp_to_host) { + struct mtk_scp_of_cluster *scp_cluster = scp->cluster; + struct mtk_scp *scp_node; + dev_err(scp->dev, "SCP watchdog timeout! 0x%x", scp_to_host); - rproc_report_crash(scp->rproc, RPROC_WATCHDOG); + + /* report watchdog timeout to all cores */ + list_for_each_entry(scp_node, &scp_cluster->mtk_scp_list, elem) + rproc_report_crash(scp_node->rproc, RPROC_WATCHDOG); } static void scp_init_ipi_handler(void *data, unsigned int len, void *priv) From patchwork Fri Jul 21 02:41:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 123533 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3529977vqt; Thu, 20 Jul 2023 20:31:19 -0700 (PDT) X-Google-Smtp-Source: APBJJlH39DuDfbJLhwaVTatA0S6hA91PIGJxk4VjjHeSolEHg8MJT1ARAdBS1a+Aseb9ETu0xcgO X-Received: by 2002:a17:907:7784:b0:982:2278:bcef with SMTP id ky4-20020a170907778400b009822278bcefmr586827ejc.60.1689910278878; Thu, 20 Jul 2023 20:31:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689910278; cv=none; d=google.com; s=arc-20160816; b=Eph1kjA7C94hG4gZy4xV9EvsTS7YvCEQ9/gyV+5zn8ase6AanvenK1YypB0HenBWb1 +jT1ZUCvpzD8UuDv8fLjOksHXOQmHD+OvfCPHX2JrpdcBR9HffiRPg5ZBuQ7DxGI20Wn mDa1eOzz9s6oGaf+4L1L8mbMfXnBuaxHz5+69PzgiXDnfSkZDpcnWeCfgon4bUMK3LVe gndhChiyU/CSOX5dBL5oiruIxZbUl39IalTF8aZ7mIK8lHQLgSLpbJvvgsV3SPmtp2r+ n8tT5kt1ClltIE38MnJY7eACut0UJnh2HL5IiJERLz5z0TnnDrWfCSHmUS3Tf3Zqi0Kq Y2lA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=oGLyNnZHkQKJzdQWL3F5sD5WDsZNC4/1QM0HlBGFsG0=; fh=fiUFlTmdXAnPLHH0bIyIc4brKi/t2/OmtpRJQ8s00Ug=; b=WDtJSlT8+HXKkPa9EccpqhlF0krt4HQzLOsggboaF1FFoZFyQFzzs74kBXjw9+f1eM 1Ej3G6RoSw4tavaaxlPxuj+1lJEut8FiMGP9gqnJXVvWL/Bdb7DHuJLwB0CF06ySNdvV 0js+u0GU2v9xJy3mUfOfRNWRmewLJV5IRGiCinbTTlDR56HPtG1Yq11wRLOlsB0L9+pL UlJx0tum7xUtb+xyPzUZqoCn7LeSQ1/jqqJiCNotjw/BAysBsPGMOpnbTHsNu/BQNuXh 2XRdvD5kPtQwOAOJO1nMoC4zMSiswM09XEgXJKrMt4sBHjh6B17FtA9gUCcj5m/Qj2qe 3wRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=O1XcbrID; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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The error is due to a handler not being found, not an invalid IPI ID. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_scp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 9ed2e18e36ba..38fb85dd6fb6 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -112,7 +112,7 @@ static void scp_ipi_handler(struct mtk_scp *scp) scp_ipi_lock(scp, id); handler = ipi_desc[id].handler; if (!handler) { - dev_err(scp->dev, "No such ipi id = %d\n", id); + dev_err(scp->dev, "No handler for ipi id = %d\n", id); scp_ipi_unlock(scp, id); return; } From patchwork Fri Jul 21 02:41:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 123527 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3522214vqt; Thu, 20 Jul 2023 20:08:14 -0700 (PDT) X-Google-Smtp-Source: APBJJlGTBVwmKDsEk4Sz3NY0h1/XPGlpVjVFv7/fmBk7IqZIDicS+ZQqf5TG+62BxJY21zCmh3X+ X-Received: by 2002:a05:6808:1998:b0:3a4:2412:f9c3 with SMTP id bj24-20020a056808199800b003a42412f9c3mr1091457oib.27.1689908894618; Thu, 20 Jul 2023 20:08:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689908894; cv=none; d=google.com; s=arc-20160816; b=Hqd/Ic21cZtz9uq96fRBbmyAeZOFTETleSoNqYP0V0NFloMi0iCjMU9bH/q1RrNT8I 7+ZWyqlMN2RLclAvkTcPjVYFerltHOfIqkt7BpCy35NFacK5ii8UXj3dMD8SEJjobAj7 9OLOIVosMB2oDxsvWXeZA85c/rDsxyET0HgO78Ffkr5GqSXWqCgBBFx4L90qeT6jCNFe MaEwUs2+mA9/l2LAAYNn4NjJyVkMCA3DcD5YqXQzg/GwcImsU5Gu83PNcxF3OMMh7pUO t0LYT5CBR5D/eONW6mmlGvQup2wlvyf+eXsiqDA3QPtBSt8OhxI7LHZIM7/EjnZ5MBxm KY5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=EgTVB8/wFgscxLDYs3qg9WMPyo6Fp8L2xH8FV1ZxS8Y=; fh=fiUFlTmdXAnPLHH0bIyIc4brKi/t2/OmtpRJQ8s00Ug=; b=1Gp5MGv3PSOh542WYZ+XCS2cO3xmp8XKj0A3K/PMSJKK+6oUjmS8nk0EUh3CTs/MPj S6sKUGx+xDH1cCCzujh3vfkZpOvVU0GqxNZIwJnstOL4GIqJZbGgcqQ6hLxXekzGp54c BLqR2TVGDpOYiYoKLqtx3nRPSuOR1ZRhkzY8LQ7oPQfCJeEvXmoJJzIXno9uqg8CIEjN lqbbg+YHT+n65QhN99K+NPfEZHJIW1Sj+/vjs06OjKWT/oBqhI0s4qn6245dlTeWZky4 ngUTICFK928UmVE4tnPGtzyho2ck+9I3/4CUmOgNM6dT5BrzK3meU4J9ROk6njG8DGkL f8ng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=stjO2kSr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Since the SCP device node is changed to multi-core structure, enable SCP cluster to enable probing SCP core 0. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 6 +++- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 34 ++++++++++++++----- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 37a3e9de90ff..4584077d3a4c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -991,7 +991,11 @@ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; -&scp { +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { status = "okay"; firmware-name = "mediatek/mt8195/scp.img"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 48b72b3645e1..7809118f74fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -922,14 +922,30 @@ clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; }; - scp: scp@10500000 { - compatible = "mediatek,mt8195-scp"; - reg = <0 0x10500000 0 0x100000>, - <0 0x10720000 0 0xe0000>, - <0 0x10700000 0 0x8000>; - reg-names = "sram", "cfg", "l1tcm"; - interrupts = ; + scp_cluster: scp@10500000 { + compatible = "mediatek,mt8195-scp-dual"; + reg = <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>; + reg-names = "cfg", "l1tcm"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x10500000 0x100000>; status = "disabled"; + + scp_c0: scp@0 { + compatible = "mediatek,scp-core"; + reg = <0x0 0xa0000>; + reg-names = "sram"; + interrupts = ; + status = "disabled"; + }; + + scp_c1: scp@a0000 { + compatible = "mediatek,scp-core"; + reg = <0xa0000 0x20000>; + reg-names = "sram"; + interrupts = ; + status = "disabled"; + }; }; scp_adsp: clock-controller@10720000 { @@ -2374,7 +2390,7 @@ video-codec@18000000 { compatible = "mediatek,mt8195-vcodec-dec"; - mediatek,scp = <&scp>; + mediatek,scp = <&scp_c0>; iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; #address-cells = <2>; #size-cells = <2>; @@ -2540,7 +2556,7 @@ <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; interrupts = ; - mediatek,scp = <&scp>; + mediatek,scp = <&scp_c0>; clocks = <&vencsys CLK_VENC_VENC>; clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC>;